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1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
2 | * |
3 | * This program is free software; you can redistribute it and/or modify |
4 | * it under the terms of the GNU General Public License version 2 and |
5 | * only version 2 as published by the Free Software Foundation. |
6 | * |
7 | * This program is distributed in the hope that it will be useful, |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
10 | * GNU General Public License for more details. |
11 | */ |
12 | |
13 | #include <linux/module.h> |
14 | #include <linux/init.h> |
15 | #include <linux/rtc.h> |
16 | #include <linux/pm.h> |
17 | #include <linux/slab.h> |
18 | #include <linux/spinlock.h> |
19 | |
20 | #include <linux/mfd/pm8xxx/core.h> |
21 | #include <linux/mfd/pm8xxx/rtc.h> |
22 | |
23 | |
24 | /* RTC Register offsets from RTC CTRL REG */ |
25 | #define PM8XXX_ALARM_CTRL_OFFSET 0x01 |
26 | #define PM8XXX_RTC_WRITE_OFFSET 0x02 |
27 | #define PM8XXX_RTC_READ_OFFSET 0x06 |
28 | #define PM8XXX_ALARM_RW_OFFSET 0x0A |
29 | |
30 | /* RTC_CTRL register bit fields */ |
31 | #define PM8xxx_RTC_ENABLE BIT(7) |
32 | #define PM8xxx_RTC_ALARM_ENABLE BIT(1) |
33 | #define PM8xxx_RTC_ALARM_CLEAR BIT(0) |
34 | |
35 | #define NUM_8_BIT_RTC_REGS 0x4 |
36 | |
37 | /** |
38 | * struct pm8xxx_rtc - rtc driver internal structure |
39 | * @rtc: rtc device for this driver. |
40 | * @rtc_alarm_irq: rtc alarm irq number. |
41 | * @rtc_base: address of rtc control register. |
42 | * @rtc_read_base: base address of read registers. |
43 | * @rtc_write_base: base address of write registers. |
44 | * @alarm_rw_base: base address of alarm registers. |
45 | * @ctrl_reg: rtc control register. |
46 | * @rtc_dev: device structure. |
47 | * @ctrl_reg_lock: spinlock protecting access to ctrl_reg. |
48 | */ |
49 | struct pm8xxx_rtc { |
50 | struct rtc_device *rtc; |
51 | int rtc_alarm_irq; |
52 | int rtc_base; |
53 | int rtc_read_base; |
54 | int rtc_write_base; |
55 | int alarm_rw_base; |
56 | u8 ctrl_reg; |
57 | struct device *rtc_dev; |
58 | spinlock_t ctrl_reg_lock; |
59 | }; |
60 | |
61 | /* |
62 | * The RTC registers need to be read/written one byte at a time. This is a |
63 | * hardware limitation. |
64 | */ |
65 | static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val, |
66 | int base, int count) |
67 | { |
68 | int i, rc; |
69 | struct device *parent = rtc_dd->rtc_dev->parent; |
70 | |
71 | for (i = 0; i < count; i++) { |
72 | rc = pm8xxx_readb(parent, base + i, &rtc_val[i]); |
73 | if (rc < 0) { |
74 | dev_err(rtc_dd->rtc_dev, "PMIC read failed\n"); |
75 | return rc; |
76 | } |
77 | } |
78 | |
79 | return 0; |
80 | } |
81 | |
82 | static int pm8xxx_write_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val, |
83 | int base, int count) |
84 | { |
85 | int i, rc; |
86 | struct device *parent = rtc_dd->rtc_dev->parent; |
87 | |
88 | for (i = 0; i < count; i++) { |
89 | rc = pm8xxx_writeb(parent, base + i, rtc_val[i]); |
90 | if (rc < 0) { |
91 | dev_err(rtc_dd->rtc_dev, "PMIC write failed\n"); |
92 | return rc; |
93 | } |
94 | } |
95 | |
96 | return 0; |
97 | } |
98 | |
99 | /* |
100 | * Steps to write the RTC registers. |
101 | * 1. Disable alarm if enabled. |
102 | * 2. Write 0x00 to LSB. |
103 | * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0]. |
104 | * 4. Enable alarm if disabled in step 1. |
105 | */ |
106 | static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm) |
107 | { |
108 | int rc, i; |
109 | unsigned long secs, irq_flags; |
110 | u8 value[NUM_8_BIT_RTC_REGS], reg = 0, alarm_enabled = 0, ctrl_reg; |
111 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
112 | |
113 | rtc_tm_to_time(tm, &secs); |
114 | |
115 | for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { |
116 | value[i] = secs & 0xFF; |
117 | secs >>= 8; |
118 | } |
119 | |
120 | dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs); |
121 | |
122 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); |
123 | ctrl_reg = rtc_dd->ctrl_reg; |
124 | |
125 | if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) { |
126 | alarm_enabled = 1; |
127 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; |
128 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, |
129 | 1); |
130 | if (rc < 0) { |
131 | dev_err(dev, "Write to RTC control register " |
132 | "failed\n"); |
133 | goto rtc_rw_fail; |
134 | } |
135 | rtc_dd->ctrl_reg = ctrl_reg; |
136 | } else |
137 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
138 | |
139 | /* Write 0 to Byte[0] */ |
140 | reg = 0; |
141 | rc = pm8xxx_write_wrapper(rtc_dd, ®, rtc_dd->rtc_write_base, 1); |
142 | if (rc < 0) { |
143 | dev_err(dev, "Write to RTC write data register failed\n"); |
144 | goto rtc_rw_fail; |
145 | } |
146 | |
147 | /* Write Byte[1], Byte[2], Byte[3] */ |
148 | rc = pm8xxx_write_wrapper(rtc_dd, value + 1, |
149 | rtc_dd->rtc_write_base + 1, 3); |
150 | if (rc < 0) { |
151 | dev_err(dev, "Write to RTC write data register failed\n"); |
152 | goto rtc_rw_fail; |
153 | } |
154 | |
155 | /* Write Byte[0] */ |
156 | rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->rtc_write_base, 1); |
157 | if (rc < 0) { |
158 | dev_err(dev, "Write to RTC write data register failed\n"); |
159 | goto rtc_rw_fail; |
160 | } |
161 | |
162 | if (alarm_enabled) { |
163 | ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE; |
164 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, |
165 | 1); |
166 | if (rc < 0) { |
167 | dev_err(dev, "Write to RTC control register " |
168 | "failed\n"); |
169 | goto rtc_rw_fail; |
170 | } |
171 | rtc_dd->ctrl_reg = ctrl_reg; |
172 | } |
173 | |
174 | rtc_rw_fail: |
175 | if (alarm_enabled) |
176 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
177 | |
178 | return rc; |
179 | } |
180 | |
181 | static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm) |
182 | { |
183 | int rc; |
184 | u8 value[NUM_8_BIT_RTC_REGS], reg; |
185 | unsigned long secs; |
186 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
187 | |
188 | rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->rtc_read_base, |
189 | NUM_8_BIT_RTC_REGS); |
190 | if (rc < 0) { |
191 | dev_err(dev, "RTC read data register failed\n"); |
192 | return rc; |
193 | } |
194 | |
195 | /* |
196 | * Read the LSB again and check if there has been a carry over. |
197 | * If there is, redo the read operation. |
198 | */ |
199 | rc = pm8xxx_read_wrapper(rtc_dd, ®, rtc_dd->rtc_read_base, 1); |
200 | if (rc < 0) { |
201 | dev_err(dev, "RTC read data register failed\n"); |
202 | return rc; |
203 | } |
204 | |
205 | if (unlikely(reg < value[0])) { |
206 | rc = pm8xxx_read_wrapper(rtc_dd, value, |
207 | rtc_dd->rtc_read_base, NUM_8_BIT_RTC_REGS); |
208 | if (rc < 0) { |
209 | dev_err(dev, "RTC read data register failed\n"); |
210 | return rc; |
211 | } |
212 | } |
213 | |
214 | secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24); |
215 | |
216 | rtc_time_to_tm(secs, tm); |
217 | |
218 | rc = rtc_valid_tm(tm); |
219 | if (rc < 0) { |
220 | dev_err(dev, "Invalid time read from RTC\n"); |
221 | return rc; |
222 | } |
223 | |
224 | dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n", |
225 | secs, tm->tm_hour, tm->tm_min, tm->tm_sec, |
226 | tm->tm_mday, tm->tm_mon, tm->tm_year); |
227 | |
228 | return 0; |
229 | } |
230 | |
231 | static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
232 | { |
233 | int rc, i; |
234 | u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg; |
235 | unsigned long secs, irq_flags; |
236 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
237 | |
238 | rtc_tm_to_time(&alarm->time, &secs); |
239 | |
240 | for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { |
241 | value[i] = secs & 0xFF; |
242 | secs >>= 8; |
243 | } |
244 | |
245 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); |
246 | |
247 | rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base, |
248 | NUM_8_BIT_RTC_REGS); |
249 | if (rc < 0) { |
250 | dev_err(dev, "Write to RTC ALARM register failed\n"); |
251 | goto rtc_rw_fail; |
252 | } |
253 | |
254 | ctrl_reg = rtc_dd->ctrl_reg; |
255 | ctrl_reg = alarm->enabled ? (ctrl_reg | PM8xxx_RTC_ALARM_ENABLE) : |
256 | (ctrl_reg & ~PM8xxx_RTC_ALARM_ENABLE); |
257 | |
258 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); |
259 | if (rc < 0) { |
260 | dev_err(dev, "Write to RTC control register failed\n"); |
261 | goto rtc_rw_fail; |
262 | } |
263 | |
264 | rtc_dd->ctrl_reg = ctrl_reg; |
265 | |
266 | dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", |
267 | alarm->time.tm_hour, alarm->time.tm_min, |
268 | alarm->time.tm_sec, alarm->time.tm_mday, |
269 | alarm->time.tm_mon, alarm->time.tm_year); |
270 | rtc_rw_fail: |
271 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
272 | return rc; |
273 | } |
274 | |
275 | static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
276 | { |
277 | int rc; |
278 | u8 value[NUM_8_BIT_RTC_REGS]; |
279 | unsigned long secs; |
280 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
281 | |
282 | rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base, |
283 | NUM_8_BIT_RTC_REGS); |
284 | if (rc < 0) { |
285 | dev_err(dev, "RTC alarm time read failed\n"); |
286 | return rc; |
287 | } |
288 | |
289 | secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24); |
290 | |
291 | rtc_time_to_tm(secs, &alarm->time); |
292 | |
293 | rc = rtc_valid_tm(&alarm->time); |
294 | if (rc < 0) { |
295 | dev_err(dev, "Invalid alarm time read from RTC\n"); |
296 | return rc; |
297 | } |
298 | |
299 | dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", |
300 | alarm->time.tm_hour, alarm->time.tm_min, |
301 | alarm->time.tm_sec, alarm->time.tm_mday, |
302 | alarm->time.tm_mon, alarm->time.tm_year); |
303 | |
304 | return 0; |
305 | } |
306 | |
307 | static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) |
308 | { |
309 | int rc; |
310 | unsigned long irq_flags; |
311 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
312 | u8 ctrl_reg; |
313 | |
314 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); |
315 | ctrl_reg = rtc_dd->ctrl_reg; |
316 | ctrl_reg = (enable) ? (ctrl_reg | PM8xxx_RTC_ALARM_ENABLE) : |
317 | (ctrl_reg & ~PM8xxx_RTC_ALARM_ENABLE); |
318 | |
319 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); |
320 | if (rc < 0) { |
321 | dev_err(dev, "Write to RTC control register failed\n"); |
322 | goto rtc_rw_fail; |
323 | } |
324 | |
325 | rtc_dd->ctrl_reg = ctrl_reg; |
326 | |
327 | rtc_rw_fail: |
328 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
329 | return rc; |
330 | } |
331 | |
332 | static struct rtc_class_ops pm8xxx_rtc_ops = { |
333 | .read_time = pm8xxx_rtc_read_time, |
334 | .set_alarm = pm8xxx_rtc_set_alarm, |
335 | .read_alarm = pm8xxx_rtc_read_alarm, |
336 | .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable, |
337 | }; |
338 | |
339 | static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) |
340 | { |
341 | struct pm8xxx_rtc *rtc_dd = dev_id; |
342 | u8 ctrl_reg; |
343 | int rc; |
344 | unsigned long irq_flags; |
345 | |
346 | rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF); |
347 | |
348 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); |
349 | |
350 | /* Clear the alarm enable bit */ |
351 | ctrl_reg = rtc_dd->ctrl_reg; |
352 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; |
353 | |
354 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); |
355 | if (rc < 0) { |
356 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
357 | dev_err(rtc_dd->rtc_dev, "Write to RTC control register " |
358 | "failed\n"); |
359 | goto rtc_alarm_handled; |
360 | } |
361 | |
362 | rtc_dd->ctrl_reg = ctrl_reg; |
363 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
364 | |
365 | /* Clear RTC alarm register */ |
366 | rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base + |
367 | PM8XXX_ALARM_CTRL_OFFSET, 1); |
368 | if (rc < 0) { |
369 | dev_err(rtc_dd->rtc_dev, "RTC Alarm control register read " |
370 | "failed\n"); |
371 | goto rtc_alarm_handled; |
372 | } |
373 | |
374 | ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR; |
375 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base + |
376 | PM8XXX_ALARM_CTRL_OFFSET, 1); |
377 | if (rc < 0) |
378 | dev_err(rtc_dd->rtc_dev, "Write to RTC Alarm control register" |
379 | " failed\n"); |
380 | |
381 | rtc_alarm_handled: |
382 | return IRQ_HANDLED; |
383 | } |
384 | |
385 | static int pm8xxx_rtc_probe(struct platform_device *pdev) |
386 | { |
387 | int rc; |
388 | u8 ctrl_reg; |
389 | bool rtc_write_enable = false; |
390 | struct pm8xxx_rtc *rtc_dd; |
391 | struct resource *rtc_resource; |
392 | const struct pm8xxx_rtc_platform_data *pdata = |
393 | dev_get_platdata(&pdev->dev); |
394 | |
395 | if (pdata != NULL) |
396 | rtc_write_enable = pdata->rtc_write_enable; |
397 | |
398 | rtc_dd = kzalloc(sizeof(*rtc_dd), GFP_KERNEL); |
399 | if (rtc_dd == NULL) { |
400 | dev_err(&pdev->dev, "Unable to allocate memory!\n"); |
401 | return -ENOMEM; |
402 | } |
403 | |
404 | /* Initialise spinlock to protect RTC control register */ |
405 | spin_lock_init(&rtc_dd->ctrl_reg_lock); |
406 | |
407 | rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0); |
408 | if (rtc_dd->rtc_alarm_irq < 0) { |
409 | dev_err(&pdev->dev, "Alarm IRQ resource absent!\n"); |
410 | rc = -ENXIO; |
411 | goto fail_rtc_enable; |
412 | } |
413 | |
414 | rtc_resource = platform_get_resource_byname(pdev, IORESOURCE_IO, |
415 | "pmic_rtc_base"); |
416 | if (!(rtc_resource && rtc_resource->start)) { |
417 | dev_err(&pdev->dev, "RTC IO resource absent!\n"); |
418 | rc = -ENXIO; |
419 | goto fail_rtc_enable; |
420 | } |
421 | |
422 | rtc_dd->rtc_base = rtc_resource->start; |
423 | |
424 | /* Setup RTC register addresses */ |
425 | rtc_dd->rtc_write_base = rtc_dd->rtc_base + PM8XXX_RTC_WRITE_OFFSET; |
426 | rtc_dd->rtc_read_base = rtc_dd->rtc_base + PM8XXX_RTC_READ_OFFSET; |
427 | rtc_dd->alarm_rw_base = rtc_dd->rtc_base + PM8XXX_ALARM_RW_OFFSET; |
428 | |
429 | rtc_dd->rtc_dev = &pdev->dev; |
430 | |
431 | /* Check if the RTC is on, else turn it on */ |
432 | rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); |
433 | if (rc < 0) { |
434 | dev_err(&pdev->dev, "RTC control register read failed!\n"); |
435 | goto fail_rtc_enable; |
436 | } |
437 | |
438 | if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) { |
439 | ctrl_reg |= PM8xxx_RTC_ENABLE; |
440 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, |
441 | 1); |
442 | if (rc < 0) { |
443 | dev_err(&pdev->dev, "Write to RTC control register " |
444 | "failed\n"); |
445 | goto fail_rtc_enable; |
446 | } |
447 | } |
448 | |
449 | rtc_dd->ctrl_reg = ctrl_reg; |
450 | if (rtc_write_enable == true) |
451 | pm8xxx_rtc_ops.set_time = pm8xxx_rtc_set_time; |
452 | |
453 | platform_set_drvdata(pdev, rtc_dd); |
454 | |
455 | /* Register the RTC device */ |
456 | rtc_dd->rtc = rtc_device_register("pm8xxx_rtc", &pdev->dev, |
457 | &pm8xxx_rtc_ops, THIS_MODULE); |
458 | if (IS_ERR(rtc_dd->rtc)) { |
459 | dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n", |
460 | __func__, PTR_ERR(rtc_dd->rtc)); |
461 | rc = PTR_ERR(rtc_dd->rtc); |
462 | goto fail_rtc_enable; |
463 | } |
464 | |
465 | /* Request the alarm IRQ */ |
466 | rc = request_any_context_irq(rtc_dd->rtc_alarm_irq, |
467 | pm8xxx_alarm_trigger, IRQF_TRIGGER_RISING, |
468 | "pm8xxx_rtc_alarm", rtc_dd); |
469 | if (rc < 0) { |
470 | dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc); |
471 | goto fail_req_irq; |
472 | } |
473 | |
474 | device_init_wakeup(&pdev->dev, 1); |
475 | |
476 | dev_dbg(&pdev->dev, "Probe success !!\n"); |
477 | |
478 | return 0; |
479 | |
480 | fail_req_irq: |
481 | rtc_device_unregister(rtc_dd->rtc); |
482 | fail_rtc_enable: |
483 | platform_set_drvdata(pdev, NULL); |
484 | kfree(rtc_dd); |
485 | return rc; |
486 | } |
487 | |
488 | static int pm8xxx_rtc_remove(struct platform_device *pdev) |
489 | { |
490 | struct pm8xxx_rtc *rtc_dd = platform_get_drvdata(pdev); |
491 | |
492 | device_init_wakeup(&pdev->dev, 0); |
493 | free_irq(rtc_dd->rtc_alarm_irq, rtc_dd); |
494 | rtc_device_unregister(rtc_dd->rtc); |
495 | platform_set_drvdata(pdev, NULL); |
496 | kfree(rtc_dd); |
497 | |
498 | return 0; |
499 | } |
500 | |
501 | #ifdef CONFIG_PM_SLEEP |
502 | static int pm8xxx_rtc_resume(struct device *dev) |
503 | { |
504 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
505 | |
506 | if (device_may_wakeup(dev)) |
507 | disable_irq_wake(rtc_dd->rtc_alarm_irq); |
508 | |
509 | return 0; |
510 | } |
511 | |
512 | static int pm8xxx_rtc_suspend(struct device *dev) |
513 | { |
514 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
515 | |
516 | if (device_may_wakeup(dev)) |
517 | enable_irq_wake(rtc_dd->rtc_alarm_irq); |
518 | |
519 | return 0; |
520 | } |
521 | #endif |
522 | |
523 | static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops, pm8xxx_rtc_suspend, pm8xxx_rtc_resume); |
524 | |
525 | static struct platform_driver pm8xxx_rtc_driver = { |
526 | .probe = pm8xxx_rtc_probe, |
527 | .remove = pm8xxx_rtc_remove, |
528 | .driver = { |
529 | .name = PM8XXX_RTC_DEV_NAME, |
530 | .owner = THIS_MODULE, |
531 | .pm = &pm8xxx_rtc_pm_ops, |
532 | }, |
533 | }; |
534 | |
535 | module_platform_driver(pm8xxx_rtc_driver); |
536 | |
537 | MODULE_ALIAS("platform:rtc-pm8xxx"); |
538 | MODULE_DESCRIPTION("PMIC8xxx RTC driver"); |
539 | MODULE_LICENSE("GPL v2"); |
540 | MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>"); |
541 |
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