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1 | /* |
2 | * drivers/char/watchdog/sp805-wdt.c |
3 | * |
4 | * Watchdog driver for ARM SP805 watchdog module |
5 | * |
6 | * Copyright (C) 2010 ST Microelectronics |
7 | * Viresh Kumar <viresh.linux@gmail.com> |
8 | * |
9 | * This file is licensed under the terms of the GNU General Public |
10 | * License version 2 or later. This program is licensed "as is" without any |
11 | * warranty of any kind, whether express or implied. |
12 | */ |
13 | |
14 | #include <linux/device.h> |
15 | #include <linux/resource.h> |
16 | #include <linux/amba/bus.h> |
17 | #include <linux/bitops.h> |
18 | #include <linux/clk.h> |
19 | #include <linux/init.h> |
20 | #include <linux/io.h> |
21 | #include <linux/ioport.h> |
22 | #include <linux/kernel.h> |
23 | #include <linux/math64.h> |
24 | #include <linux/module.h> |
25 | #include <linux/moduleparam.h> |
26 | #include <linux/pm.h> |
27 | #include <linux/slab.h> |
28 | #include <linux/spinlock.h> |
29 | #include <linux/types.h> |
30 | #include <linux/watchdog.h> |
31 | |
32 | /* default timeout in seconds */ |
33 | #define DEFAULT_TIMEOUT 60 |
34 | |
35 | #define MODULE_NAME "sp805-wdt" |
36 | |
37 | /* watchdog register offsets and masks */ |
38 | #define WDTLOAD 0x000 |
39 | #define LOAD_MIN 0x00000001 |
40 | #define LOAD_MAX 0xFFFFFFFF |
41 | #define WDTVALUE 0x004 |
42 | #define WDTCONTROL 0x008 |
43 | /* control register masks */ |
44 | #define INT_ENABLE (1 << 0) |
45 | #define RESET_ENABLE (1 << 1) |
46 | #define WDTINTCLR 0x00C |
47 | #define WDTRIS 0x010 |
48 | #define WDTMIS 0x014 |
49 | #define INT_MASK (1 << 0) |
50 | #define WDTLOCK 0xC00 |
51 | #define UNLOCK 0x1ACCE551 |
52 | #define LOCK 0x00000001 |
53 | |
54 | /** |
55 | * struct sp805_wdt: sp805 wdt device structure |
56 | * @wdd: instance of struct watchdog_device |
57 | * @lock: spin lock protecting dev structure and io access |
58 | * @base: base address of wdt |
59 | * @clk: clock structure of wdt |
60 | * @adev: amba device structure of wdt |
61 | * @status: current status of wdt |
62 | * @load_val: load value to be set for current timeout |
63 | * @timeout: current programmed timeout |
64 | */ |
65 | struct sp805_wdt { |
66 | struct watchdog_device wdd; |
67 | spinlock_t lock; |
68 | void __iomem *base; |
69 | struct clk *clk; |
70 | struct amba_device *adev; |
71 | unsigned int load_val; |
72 | unsigned int timeout; |
73 | }; |
74 | |
75 | static bool nowayout = WATCHDOG_NOWAYOUT; |
76 | module_param(nowayout, bool, 0); |
77 | MODULE_PARM_DESC(nowayout, |
78 | "Set to 1 to keep watchdog running after device release"); |
79 | |
80 | /* This routine finds load value that will reset system in required timout */ |
81 | static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout) |
82 | { |
83 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
84 | u64 load, rate; |
85 | |
86 | rate = clk_get_rate(wdt->clk); |
87 | |
88 | /* |
89 | * sp805 runs counter with given value twice, after the end of first |
90 | * counter it gives an interrupt and then starts counter again. If |
91 | * interrupt already occurred then it resets the system. This is why |
92 | * load is half of what should be required. |
93 | */ |
94 | load = div_u64(rate, 2) * timeout - 1; |
95 | |
96 | load = (load > LOAD_MAX) ? LOAD_MAX : load; |
97 | load = (load < LOAD_MIN) ? LOAD_MIN : load; |
98 | |
99 | spin_lock(&wdt->lock); |
100 | wdt->load_val = load; |
101 | /* roundup timeout to closest positive integer value */ |
102 | wdt->timeout = div_u64((load + 1) * 2 + (rate / 2), rate); |
103 | spin_unlock(&wdt->lock); |
104 | |
105 | return 0; |
106 | } |
107 | |
108 | /* returns number of seconds left for reset to occur */ |
109 | static unsigned int wdt_timeleft(struct watchdog_device *wdd) |
110 | { |
111 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
112 | u64 load, rate; |
113 | |
114 | rate = clk_get_rate(wdt->clk); |
115 | |
116 | spin_lock(&wdt->lock); |
117 | load = readl_relaxed(wdt->base + WDTVALUE); |
118 | |
119 | /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */ |
120 | if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK)) |
121 | load += wdt->load_val + 1; |
122 | spin_unlock(&wdt->lock); |
123 | |
124 | return div_u64(load, rate); |
125 | } |
126 | |
127 | static int wdt_config(struct watchdog_device *wdd, bool ping) |
128 | { |
129 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
130 | int ret; |
131 | |
132 | if (!ping) { |
133 | |
134 | ret = clk_prepare_enable(wdt->clk); |
135 | if (ret) { |
136 | dev_err(&wdt->adev->dev, "clock enable fail"); |
137 | return ret; |
138 | } |
139 | } |
140 | |
141 | spin_lock(&wdt->lock); |
142 | |
143 | writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
144 | writel_relaxed(wdt->load_val, wdt->base + WDTLOAD); |
145 | |
146 | if (!ping) { |
147 | writel_relaxed(INT_MASK, wdt->base + WDTINTCLR); |
148 | writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + |
149 | WDTCONTROL); |
150 | } |
151 | |
152 | writel_relaxed(LOCK, wdt->base + WDTLOCK); |
153 | |
154 | /* Flush posted writes. */ |
155 | readl_relaxed(wdt->base + WDTLOCK); |
156 | spin_unlock(&wdt->lock); |
157 | |
158 | return 0; |
159 | } |
160 | |
161 | static int wdt_ping(struct watchdog_device *wdd) |
162 | { |
163 | return wdt_config(wdd, true); |
164 | } |
165 | |
166 | /* enables watchdog timers reset */ |
167 | static int wdt_enable(struct watchdog_device *wdd) |
168 | { |
169 | return wdt_config(wdd, false); |
170 | } |
171 | |
172 | /* disables watchdog timers reset */ |
173 | static int wdt_disable(struct watchdog_device *wdd) |
174 | { |
175 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
176 | |
177 | spin_lock(&wdt->lock); |
178 | |
179 | writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
180 | writel_relaxed(0, wdt->base + WDTCONTROL); |
181 | writel_relaxed(LOCK, wdt->base + WDTLOCK); |
182 | |
183 | /* Flush posted writes. */ |
184 | readl_relaxed(wdt->base + WDTLOCK); |
185 | spin_unlock(&wdt->lock); |
186 | |
187 | clk_disable_unprepare(wdt->clk); |
188 | |
189 | return 0; |
190 | } |
191 | |
192 | static const struct watchdog_info wdt_info = { |
193 | .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
194 | .identity = MODULE_NAME, |
195 | }; |
196 | |
197 | static const struct watchdog_ops wdt_ops = { |
198 | .owner = THIS_MODULE, |
199 | .start = wdt_enable, |
200 | .stop = wdt_disable, |
201 | .ping = wdt_ping, |
202 | .set_timeout = wdt_setload, |
203 | .get_timeleft = wdt_timeleft, |
204 | }; |
205 | |
206 | static int |
207 | sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id) |
208 | { |
209 | struct sp805_wdt *wdt; |
210 | int ret = 0; |
211 | |
212 | if (!devm_request_mem_region(&adev->dev, adev->res.start, |
213 | resource_size(&adev->res), "sp805_wdt")) { |
214 | dev_warn(&adev->dev, "Failed to get memory region resource\n"); |
215 | ret = -ENOENT; |
216 | goto err; |
217 | } |
218 | |
219 | wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL); |
220 | if (!wdt) { |
221 | dev_warn(&adev->dev, "Kzalloc failed\n"); |
222 | ret = -ENOMEM; |
223 | goto err; |
224 | } |
225 | |
226 | wdt->base = devm_ioremap(&adev->dev, adev->res.start, |
227 | resource_size(&adev->res)); |
228 | if (!wdt->base) { |
229 | ret = -ENOMEM; |
230 | dev_warn(&adev->dev, "ioremap fail\n"); |
231 | goto err; |
232 | } |
233 | |
234 | wdt->clk = clk_get(&adev->dev, NULL); |
235 | if (IS_ERR(wdt->clk)) { |
236 | dev_warn(&adev->dev, "Clock not found\n"); |
237 | ret = PTR_ERR(wdt->clk); |
238 | goto err; |
239 | } |
240 | |
241 | wdt->adev = adev; |
242 | wdt->wdd.info = &wdt_info; |
243 | wdt->wdd.ops = &wdt_ops; |
244 | |
245 | spin_lock_init(&wdt->lock); |
246 | watchdog_set_nowayout(&wdt->wdd, nowayout); |
247 | watchdog_set_drvdata(&wdt->wdd, wdt); |
248 | wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT); |
249 | |
250 | ret = watchdog_register_device(&wdt->wdd); |
251 | if (ret) { |
252 | dev_err(&adev->dev, "watchdog_register_device() failed: %d\n", |
253 | ret); |
254 | goto err_register; |
255 | } |
256 | amba_set_drvdata(adev, wdt); |
257 | |
258 | dev_info(&adev->dev, "registration successful\n"); |
259 | return 0; |
260 | |
261 | err_register: |
262 | clk_put(wdt->clk); |
263 | err: |
264 | dev_err(&adev->dev, "Probe Failed!!!\n"); |
265 | return ret; |
266 | } |
267 | |
268 | static int sp805_wdt_remove(struct amba_device *adev) |
269 | { |
270 | struct sp805_wdt *wdt = amba_get_drvdata(adev); |
271 | |
272 | watchdog_unregister_device(&wdt->wdd); |
273 | amba_set_drvdata(adev, NULL); |
274 | watchdog_set_drvdata(&wdt->wdd, NULL); |
275 | clk_put(wdt->clk); |
276 | |
277 | return 0; |
278 | } |
279 | |
280 | static int __maybe_unused sp805_wdt_suspend(struct device *dev) |
281 | { |
282 | struct sp805_wdt *wdt = dev_get_drvdata(dev); |
283 | |
284 | if (watchdog_active(&wdt->wdd)) |
285 | return wdt_disable(&wdt->wdd); |
286 | |
287 | return 0; |
288 | } |
289 | |
290 | static int __maybe_unused sp805_wdt_resume(struct device *dev) |
291 | { |
292 | struct sp805_wdt *wdt = dev_get_drvdata(dev); |
293 | |
294 | if (watchdog_active(&wdt->wdd)) |
295 | return wdt_enable(&wdt->wdd); |
296 | |
297 | return 0; |
298 | } |
299 | |
300 | static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend, |
301 | sp805_wdt_resume); |
302 | |
303 | static struct amba_id sp805_wdt_ids[] = { |
304 | { |
305 | .id = 0x00141805, |
306 | .mask = 0x00ffffff, |
307 | }, |
308 | { 0, 0 }, |
309 | }; |
310 | |
311 | MODULE_DEVICE_TABLE(amba, sp805_wdt_ids); |
312 | |
313 | static struct amba_driver sp805_wdt_driver = { |
314 | .drv = { |
315 | .name = MODULE_NAME, |
316 | .pm = &sp805_wdt_dev_pm_ops, |
317 | }, |
318 | .id_table = sp805_wdt_ids, |
319 | .probe = sp805_wdt_probe, |
320 | .remove = sp805_wdt_remove, |
321 | }; |
322 | |
323 | module_amba_driver(sp805_wdt_driver); |
324 | |
325 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |
326 | MODULE_DESCRIPTION("ARM SP805 Watchdog Driver"); |
327 | MODULE_LICENSE("GPL"); |
328 |
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