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1 | /* drivers/devfreq/exynos4210_memorybus.c |
2 | * |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com/ |
5 | * MyungJoo Ham <myungjoo.ham@samsung.com> |
6 | * |
7 | * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework |
8 | * This version supports EXYNOS4210 only. This changes bus frequencies |
9 | * and vddint voltages. Exynos4412/4212 should be able to be supported |
10 | * with minor modifications. |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as |
14 | * published by the Free Software Foundation. |
15 | * |
16 | */ |
17 | |
18 | #include <linux/io.h> |
19 | #include <linux/slab.h> |
20 | #include <linux/mutex.h> |
21 | #include <linux/suspend.h> |
22 | #include <linux/opp.h> |
23 | #include <linux/devfreq.h> |
24 | #include <linux/platform_device.h> |
25 | #include <linux/regulator/consumer.h> |
26 | #include <linux/module.h> |
27 | |
28 | /* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */ |
29 | #ifdef CONFIG_EXYNOS_ASV |
30 | extern unsigned int exynos_result_of_asv; |
31 | #endif |
32 | |
33 | #include <mach/regs-clock.h> |
34 | |
35 | #include <plat/map-s5p.h> |
36 | |
37 | #define MAX_SAFEVOLT 1200000 /* 1.2V */ |
38 | |
39 | enum exynos4_busf_type { |
40 | TYPE_BUSF_EXYNOS4210, |
41 | TYPE_BUSF_EXYNOS4x12, |
42 | }; |
43 | |
44 | /* Assume that the bus is saturated if the utilization is 40% */ |
45 | #define BUS_SATURATION_RATIO 40 |
46 | |
47 | enum ppmu_counter { |
48 | PPMU_PMNCNT0 = 0, |
49 | PPMU_PMCCNT1, |
50 | PPMU_PMNCNT2, |
51 | PPMU_PMNCNT3, |
52 | PPMU_PMNCNT_MAX, |
53 | }; |
54 | struct exynos4_ppmu { |
55 | void __iomem *hw_base; |
56 | unsigned int ccnt; |
57 | unsigned int event; |
58 | unsigned int count[PPMU_PMNCNT_MAX]; |
59 | bool ccnt_overflow; |
60 | bool count_overflow[PPMU_PMNCNT_MAX]; |
61 | }; |
62 | |
63 | enum busclk_level_idx { |
64 | LV_0 = 0, |
65 | LV_1, |
66 | LV_2, |
67 | LV_3, |
68 | LV_4, |
69 | _LV_END |
70 | }; |
71 | #define EX4210_LV_MAX LV_2 |
72 | #define EX4x12_LV_MAX LV_4 |
73 | #define EX4210_LV_NUM (LV_2 + 1) |
74 | #define EX4x12_LV_NUM (LV_4 + 1) |
75 | |
76 | /** |
77 | * struct busfreq_opp_info - opp information for bus |
78 | * @rate: Frequency in hertz |
79 | * @volt: Voltage in microvolts corresponding to this OPP |
80 | */ |
81 | struct busfreq_opp_info { |
82 | unsigned long rate; |
83 | unsigned long volt; |
84 | }; |
85 | |
86 | struct busfreq_data { |
87 | enum exynos4_busf_type type; |
88 | struct device *dev; |
89 | struct devfreq *devfreq; |
90 | bool disabled; |
91 | struct regulator *vdd_int; |
92 | struct regulator *vdd_mif; /* Exynos4412/4212 only */ |
93 | struct busfreq_opp_info curr_oppinfo; |
94 | struct exynos4_ppmu dmc[2]; |
95 | |
96 | struct notifier_block pm_notifier; |
97 | struct mutex lock; |
98 | |
99 | /* Dividers calculated at boot/probe-time */ |
100 | unsigned int dmc_divtable[_LV_END]; /* DMC0 */ |
101 | unsigned int top_divtable[_LV_END]; |
102 | }; |
103 | |
104 | struct bus_opp_table { |
105 | unsigned int idx; |
106 | unsigned long clk; |
107 | unsigned long volt; |
108 | }; |
109 | |
110 | /* 4210 controls clock of mif and voltage of int */ |
111 | static struct bus_opp_table exynos4210_busclk_table[] = { |
112 | {LV_0, 400000, 1150000}, |
113 | {LV_1, 267000, 1050000}, |
114 | {LV_2, 133000, 1025000}, |
115 | {0, 0, 0}, |
116 | }; |
117 | |
118 | /* |
119 | * MIF is the main control knob clock for exynox4x12 MIF/INT |
120 | * clock and voltage of both mif/int are controlled. |
121 | */ |
122 | static struct bus_opp_table exynos4x12_mifclk_table[] = { |
123 | {LV_0, 400000, 1100000}, |
124 | {LV_1, 267000, 1000000}, |
125 | {LV_2, 160000, 950000}, |
126 | {LV_3, 133000, 950000}, |
127 | {LV_4, 100000, 950000}, |
128 | {0, 0, 0}, |
129 | }; |
130 | |
131 | /* |
132 | * INT is not the control knob of 4x12. LV_x is not meant to represent |
133 | * the current performance. (MIF does) |
134 | */ |
135 | static struct bus_opp_table exynos4x12_intclk_table[] = { |
136 | {LV_0, 200000, 1000000}, |
137 | {LV_1, 160000, 950000}, |
138 | {LV_2, 133000, 925000}, |
139 | {LV_3, 100000, 900000}, |
140 | {0, 0, 0}, |
141 | }; |
142 | |
143 | /* TODO: asv volt definitions are "__initdata"? */ |
144 | /* Some chips have different operating voltages */ |
145 | static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = { |
146 | {1150000, 1050000, 1050000}, |
147 | {1125000, 1025000, 1025000}, |
148 | {1100000, 1000000, 1000000}, |
149 | {1075000, 975000, 975000}, |
150 | {1050000, 950000, 950000}, |
151 | }; |
152 | |
153 | static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = { |
154 | /* 400 267 160 133 100 */ |
155 | {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */ |
156 | {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */ |
157 | {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */ |
158 | {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */ |
159 | {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */ |
160 | {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */ |
161 | {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */ |
162 | {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */ |
163 | {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */ |
164 | }; |
165 | |
166 | static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = { |
167 | /* 200 160 133 100 */ |
168 | {1000000, 950000, 925000, 900000}, /* ASV0 */ |
169 | {975000, 925000, 925000, 900000}, /* ASV1 */ |
170 | {950000, 925000, 900000, 875000}, /* ASV2 */ |
171 | {950000, 900000, 900000, 875000}, /* ASV3 */ |
172 | {925000, 875000, 875000, 875000}, /* ASV4 */ |
173 | {900000, 850000, 850000, 850000}, /* ASV5 */ |
174 | {900000, 850000, 850000, 850000}, /* ASV6 */ |
175 | {900000, 850000, 850000, 850000}, /* ASV7 */ |
176 | {900000, 850000, 850000, 850000}, /* ASV8 */ |
177 | }; |
178 | |
179 | /*** Clock Divider Data for Exynos4210 ***/ |
180 | static unsigned int exynos4210_clkdiv_dmc0[][8] = { |
181 | /* |
182 | * Clock divider value for following |
183 | * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD |
184 | * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS } |
185 | */ |
186 | |
187 | /* DMC L0: 400MHz */ |
188 | { 3, 1, 1, 1, 1, 1, 3, 1 }, |
189 | /* DMC L1: 266.7MHz */ |
190 | { 4, 1, 1, 2, 1, 1, 3, 1 }, |
191 | /* DMC L2: 133MHz */ |
192 | { 5, 1, 1, 5, 1, 1, 3, 1 }, |
193 | }; |
194 | static unsigned int exynos4210_clkdiv_top[][5] = { |
195 | /* |
196 | * Clock divider value for following |
197 | * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND } |
198 | */ |
199 | /* ACLK200 L0: 200MHz */ |
200 | { 3, 7, 4, 5, 1 }, |
201 | /* ACLK200 L1: 160MHz */ |
202 | { 4, 7, 5, 6, 1 }, |
203 | /* ACLK200 L2: 133MHz */ |
204 | { 5, 7, 7, 7, 1 }, |
205 | }; |
206 | static unsigned int exynos4210_clkdiv_lr_bus[][2] = { |
207 | /* |
208 | * Clock divider value for following |
209 | * { DIVGDL/R, DIVGPL/R } |
210 | */ |
211 | /* ACLK_GDL/R L1: 200MHz */ |
212 | { 3, 1 }, |
213 | /* ACLK_GDL/R L2: 160MHz */ |
214 | { 4, 1 }, |
215 | /* ACLK_GDL/R L3: 133MHz */ |
216 | { 5, 1 }, |
217 | }; |
218 | |
219 | /*** Clock Divider Data for Exynos4212/4412 ***/ |
220 | static unsigned int exynos4x12_clkdiv_dmc0[][6] = { |
221 | /* |
222 | * Clock divider value for following |
223 | * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD |
224 | * DIVDMCP} |
225 | */ |
226 | |
227 | /* DMC L0: 400MHz */ |
228 | {3, 1, 1, 1, 1, 1}, |
229 | /* DMC L1: 266.7MHz */ |
230 | {4, 1, 1, 2, 1, 1}, |
231 | /* DMC L2: 160MHz */ |
232 | {5, 1, 1, 4, 1, 1}, |
233 | /* DMC L3: 133MHz */ |
234 | {5, 1, 1, 5, 1, 1}, |
235 | /* DMC L4: 100MHz */ |
236 | {7, 1, 1, 7, 1, 1}, |
237 | }; |
238 | static unsigned int exynos4x12_clkdiv_dmc1[][6] = { |
239 | /* |
240 | * Clock divider value for following |
241 | * { G2DACP, DIVC2C, DIVC2C_ACLK } |
242 | */ |
243 | |
244 | /* DMC L0: 400MHz */ |
245 | {3, 1, 1}, |
246 | /* DMC L1: 266.7MHz */ |
247 | {4, 2, 1}, |
248 | /* DMC L2: 160MHz */ |
249 | {5, 4, 1}, |
250 | /* DMC L3: 133MHz */ |
251 | {5, 5, 1}, |
252 | /* DMC L4: 100MHz */ |
253 | {7, 7, 1}, |
254 | }; |
255 | static unsigned int exynos4x12_clkdiv_top[][5] = { |
256 | /* |
257 | * Clock divider value for following |
258 | * { DIVACLK266_GPS, DIVACLK100, DIVACLK160, |
259 | DIVACLK133, DIVONENAND } |
260 | */ |
261 | |
262 | /* ACLK_GDL/R L0: 200MHz */ |
263 | {2, 7, 4, 5, 1}, |
264 | /* ACLK_GDL/R L1: 200MHz */ |
265 | {2, 7, 4, 5, 1}, |
266 | /* ACLK_GDL/R L2: 160MHz */ |
267 | {4, 7, 5, 7, 1}, |
268 | /* ACLK_GDL/R L3: 133MHz */ |
269 | {4, 7, 5, 7, 1}, |
270 | /* ACLK_GDL/R L4: 100MHz */ |
271 | {7, 7, 7, 7, 1}, |
272 | }; |
273 | static unsigned int exynos4x12_clkdiv_lr_bus[][2] = { |
274 | /* |
275 | * Clock divider value for following |
276 | * { DIVGDL/R, DIVGPL/R } |
277 | */ |
278 | |
279 | /* ACLK_GDL/R L0: 200MHz */ |
280 | {3, 1}, |
281 | /* ACLK_GDL/R L1: 200MHz */ |
282 | {3, 1}, |
283 | /* ACLK_GDL/R L2: 160MHz */ |
284 | {4, 1}, |
285 | /* ACLK_GDL/R L3: 133MHz */ |
286 | {5, 1}, |
287 | /* ACLK_GDL/R L4: 100MHz */ |
288 | {7, 1}, |
289 | }; |
290 | static unsigned int exynos4x12_clkdiv_sclkip[][3] = { |
291 | /* |
292 | * Clock divider value for following |
293 | * { DIVMFC, DIVJPEG, DIVFIMC0~3} |
294 | */ |
295 | |
296 | /* SCLK_MFC: 200MHz */ |
297 | {3, 3, 4}, |
298 | /* SCLK_MFC: 200MHz */ |
299 | {3, 3, 4}, |
300 | /* SCLK_MFC: 160MHz */ |
301 | {4, 4, 5}, |
302 | /* SCLK_MFC: 133MHz */ |
303 | {5, 5, 5}, |
304 | /* SCLK_MFC: 100MHz */ |
305 | {7, 7, 7}, |
306 | }; |
307 | |
308 | |
309 | static int exynos4210_set_busclk(struct busfreq_data *data, |
310 | struct busfreq_opp_info *oppi) |
311 | { |
312 | unsigned int index; |
313 | unsigned int tmp; |
314 | |
315 | for (index = LV_0; index < EX4210_LV_NUM; index++) |
316 | if (oppi->rate == exynos4210_busclk_table[index].clk) |
317 | break; |
318 | |
319 | if (index == EX4210_LV_NUM) |
320 | return -EINVAL; |
321 | |
322 | /* Change Divider - DMC0 */ |
323 | tmp = data->dmc_divtable[index]; |
324 | |
325 | __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); |
326 | |
327 | do { |
328 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); |
329 | } while (tmp & 0x11111111); |
330 | |
331 | /* Change Divider - TOP */ |
332 | tmp = data->top_divtable[index]; |
333 | |
334 | __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); |
335 | |
336 | do { |
337 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); |
338 | } while (tmp & 0x11111); |
339 | |
340 | /* Change Divider - LEFTBUS */ |
341 | tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); |
342 | |
343 | tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); |
344 | |
345 | tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << |
346 | EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | |
347 | (exynos4210_clkdiv_lr_bus[index][1] << |
348 | EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); |
349 | |
350 | __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); |
351 | |
352 | do { |
353 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); |
354 | } while (tmp & 0x11); |
355 | |
356 | /* Change Divider - RIGHTBUS */ |
357 | tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); |
358 | |
359 | tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); |
360 | |
361 | tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << |
362 | EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | |
363 | (exynos4210_clkdiv_lr_bus[index][1] << |
364 | EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); |
365 | |
366 | __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); |
367 | |
368 | do { |
369 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); |
370 | } while (tmp & 0x11); |
371 | |
372 | return 0; |
373 | } |
374 | |
375 | static int exynos4x12_set_busclk(struct busfreq_data *data, |
376 | struct busfreq_opp_info *oppi) |
377 | { |
378 | unsigned int index; |
379 | unsigned int tmp; |
380 | |
381 | for (index = LV_0; index < EX4x12_LV_NUM; index++) |
382 | if (oppi->rate == exynos4x12_mifclk_table[index].clk) |
383 | break; |
384 | |
385 | if (index == EX4x12_LV_NUM) |
386 | return -EINVAL; |
387 | |
388 | /* Change Divider - DMC0 */ |
389 | tmp = data->dmc_divtable[index]; |
390 | |
391 | __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); |
392 | |
393 | do { |
394 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); |
395 | } while (tmp & 0x11111111); |
396 | |
397 | /* Change Divider - DMC1 */ |
398 | tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1); |
399 | |
400 | tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK | |
401 | EXYNOS4_CLKDIV_DMC1_C2C_MASK | |
402 | EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK); |
403 | |
404 | tmp |= ((exynos4x12_clkdiv_dmc1[index][0] << |
405 | EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) | |
406 | (exynos4x12_clkdiv_dmc1[index][1] << |
407 | EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) | |
408 | (exynos4x12_clkdiv_dmc1[index][2] << |
409 | EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)); |
410 | |
411 | __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1); |
412 | |
413 | do { |
414 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1); |
415 | } while (tmp & 0x111111); |
416 | |
417 | /* Change Divider - TOP */ |
418 | tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); |
419 | |
420 | tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK | |
421 | EXYNOS4_CLKDIV_TOP_ACLK100_MASK | |
422 | EXYNOS4_CLKDIV_TOP_ACLK160_MASK | |
423 | EXYNOS4_CLKDIV_TOP_ACLK133_MASK | |
424 | EXYNOS4_CLKDIV_TOP_ONENAND_MASK); |
425 | |
426 | tmp |= ((exynos4x12_clkdiv_top[index][0] << |
427 | EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) | |
428 | (exynos4x12_clkdiv_top[index][1] << |
429 | EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | |
430 | (exynos4x12_clkdiv_top[index][2] << |
431 | EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | |
432 | (exynos4x12_clkdiv_top[index][3] << |
433 | EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | |
434 | (exynos4x12_clkdiv_top[index][4] << |
435 | EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); |
436 | |
437 | __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); |
438 | |
439 | do { |
440 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); |
441 | } while (tmp & 0x11111); |
442 | |
443 | /* Change Divider - LEFTBUS */ |
444 | tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); |
445 | |
446 | tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); |
447 | |
448 | tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << |
449 | EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | |
450 | (exynos4x12_clkdiv_lr_bus[index][1] << |
451 | EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); |
452 | |
453 | __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); |
454 | |
455 | do { |
456 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); |
457 | } while (tmp & 0x11); |
458 | |
459 | /* Change Divider - RIGHTBUS */ |
460 | tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); |
461 | |
462 | tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); |
463 | |
464 | tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << |
465 | EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | |
466 | (exynos4x12_clkdiv_lr_bus[index][1] << |
467 | EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); |
468 | |
469 | __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); |
470 | |
471 | do { |
472 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); |
473 | } while (tmp & 0x11); |
474 | |
475 | /* Change Divider - MFC */ |
476 | tmp = __raw_readl(EXYNOS4_CLKDIV_MFC); |
477 | |
478 | tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK); |
479 | |
480 | tmp |= ((exynos4x12_clkdiv_sclkip[index][0] << |
481 | EXYNOS4_CLKDIV_MFC_SHIFT)); |
482 | |
483 | __raw_writel(tmp, EXYNOS4_CLKDIV_MFC); |
484 | |
485 | do { |
486 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC); |
487 | } while (tmp & 0x1); |
488 | |
489 | /* Change Divider - JPEG */ |
490 | tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1); |
491 | |
492 | tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK); |
493 | |
494 | tmp |= ((exynos4x12_clkdiv_sclkip[index][1] << |
495 | EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)); |
496 | |
497 | __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1); |
498 | |
499 | do { |
500 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); |
501 | } while (tmp & 0x1); |
502 | |
503 | /* Change Divider - FIMC0~3 */ |
504 | tmp = __raw_readl(EXYNOS4_CLKDIV_CAM); |
505 | |
506 | tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK | |
507 | EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK); |
508 | |
509 | tmp |= ((exynos4x12_clkdiv_sclkip[index][2] << |
510 | EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) | |
511 | (exynos4x12_clkdiv_sclkip[index][2] << |
512 | EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) | |
513 | (exynos4x12_clkdiv_sclkip[index][2] << |
514 | EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) | |
515 | (exynos4x12_clkdiv_sclkip[index][2] << |
516 | EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)); |
517 | |
518 | __raw_writel(tmp, EXYNOS4_CLKDIV_CAM); |
519 | |
520 | do { |
521 | tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); |
522 | } while (tmp & 0x1111); |
523 | |
524 | return 0; |
525 | } |
526 | |
527 | |
528 | static void busfreq_mon_reset(struct busfreq_data *data) |
529 | { |
530 | unsigned int i; |
531 | |
532 | for (i = 0; i < 2; i++) { |
533 | void __iomem *ppmu_base = data->dmc[i].hw_base; |
534 | |
535 | /* Reset PPMU */ |
536 | __raw_writel(0x8000000f, ppmu_base + 0xf010); |
537 | __raw_writel(0x8000000f, ppmu_base + 0xf050); |
538 | __raw_writel(0x6, ppmu_base + 0xf000); |
539 | __raw_writel(0x0, ppmu_base + 0xf100); |
540 | |
541 | /* Set PPMU Event */ |
542 | data->dmc[i].event = 0x6; |
543 | __raw_writel(((data->dmc[i].event << 12) | 0x1), |
544 | ppmu_base + 0xfc); |
545 | |
546 | /* Start PPMU */ |
547 | __raw_writel(0x1, ppmu_base + 0xf000); |
548 | } |
549 | } |
550 | |
551 | static void exynos4_read_ppmu(struct busfreq_data *data) |
552 | { |
553 | int i, j; |
554 | |
555 | for (i = 0; i < 2; i++) { |
556 | void __iomem *ppmu_base = data->dmc[i].hw_base; |
557 | u32 overflow; |
558 | |
559 | /* Stop PPMU */ |
560 | __raw_writel(0x0, ppmu_base + 0xf000); |
561 | |
562 | /* Update local data from PPMU */ |
563 | overflow = __raw_readl(ppmu_base + 0xf050); |
564 | |
565 | data->dmc[i].ccnt = __raw_readl(ppmu_base + 0xf100); |
566 | data->dmc[i].ccnt_overflow = overflow & (1 << 31); |
567 | |
568 | for (j = 0; j < PPMU_PMNCNT_MAX; j++) { |
569 | data->dmc[i].count[j] = __raw_readl( |
570 | ppmu_base + (0xf110 + (0x10 * j))); |
571 | data->dmc[i].count_overflow[j] = overflow & (1 << j); |
572 | } |
573 | } |
574 | |
575 | busfreq_mon_reset(data); |
576 | } |
577 | |
578 | static int exynos4x12_get_intspec(unsigned long mifclk) |
579 | { |
580 | int i = 0; |
581 | |
582 | while (exynos4x12_intclk_table[i].clk) { |
583 | if (exynos4x12_intclk_table[i].clk <= mifclk) |
584 | return i; |
585 | i++; |
586 | } |
587 | |
588 | return -EINVAL; |
589 | } |
590 | |
591 | static int exynos4_bus_setvolt(struct busfreq_data *data, |
592 | struct busfreq_opp_info *oppi, |
593 | struct busfreq_opp_info *oldoppi) |
594 | { |
595 | int err = 0, tmp; |
596 | unsigned long volt = oppi->volt; |
597 | |
598 | switch (data->type) { |
599 | case TYPE_BUSF_EXYNOS4210: |
600 | /* OPP represents DMC clock + INT voltage */ |
601 | err = regulator_set_voltage(data->vdd_int, volt, |
602 | MAX_SAFEVOLT); |
603 | break; |
604 | case TYPE_BUSF_EXYNOS4x12: |
605 | /* OPP represents MIF clock + MIF voltage */ |
606 | err = regulator_set_voltage(data->vdd_mif, volt, |
607 | MAX_SAFEVOLT); |
608 | if (err) |
609 | break; |
610 | |
611 | tmp = exynos4x12_get_intspec(oppi->rate); |
612 | if (tmp < 0) { |
613 | err = tmp; |
614 | regulator_set_voltage(data->vdd_mif, |
615 | oldoppi->volt, |
616 | MAX_SAFEVOLT); |
617 | break; |
618 | } |
619 | err = regulator_set_voltage(data->vdd_int, |
620 | exynos4x12_intclk_table[tmp].volt, |
621 | MAX_SAFEVOLT); |
622 | /* Try to recover */ |
623 | if (err) |
624 | regulator_set_voltage(data->vdd_mif, |
625 | oldoppi->volt, |
626 | MAX_SAFEVOLT); |
627 | break; |
628 | default: |
629 | err = -EINVAL; |
630 | } |
631 | |
632 | return err; |
633 | } |
634 | |
635 | static int exynos4_bus_target(struct device *dev, unsigned long *_freq, |
636 | u32 flags) |
637 | { |
638 | int err = 0; |
639 | struct platform_device *pdev = container_of(dev, struct platform_device, |
640 | dev); |
641 | struct busfreq_data *data = platform_get_drvdata(pdev); |
642 | struct opp *opp; |
643 | unsigned long freq; |
644 | unsigned long old_freq = data->curr_oppinfo.rate; |
645 | struct busfreq_opp_info new_oppinfo; |
646 | |
647 | rcu_read_lock(); |
648 | opp = devfreq_recommended_opp(dev, _freq, flags); |
649 | if (IS_ERR(opp)) { |
650 | rcu_read_unlock(); |
651 | return PTR_ERR(opp); |
652 | } |
653 | new_oppinfo.rate = opp_get_freq(opp); |
654 | new_oppinfo.volt = opp_get_voltage(opp); |
655 | rcu_read_unlock(); |
656 | freq = new_oppinfo.rate; |
657 | |
658 | if (old_freq == freq) |
659 | return 0; |
660 | |
661 | dev_dbg(dev, "targeting %lukHz %luuV\n", freq, new_oppinfo.volt); |
662 | |
663 | mutex_lock(&data->lock); |
664 | |
665 | if (data->disabled) |
666 | goto out; |
667 | |
668 | if (old_freq < freq) |
669 | err = exynos4_bus_setvolt(data, &new_oppinfo, |
670 | &data->curr_oppinfo); |
671 | if (err) |
672 | goto out; |
673 | |
674 | if (old_freq != freq) { |
675 | switch (data->type) { |
676 | case TYPE_BUSF_EXYNOS4210: |
677 | err = exynos4210_set_busclk(data, &new_oppinfo); |
678 | break; |
679 | case TYPE_BUSF_EXYNOS4x12: |
680 | err = exynos4x12_set_busclk(data, &new_oppinfo); |
681 | break; |
682 | default: |
683 | err = -EINVAL; |
684 | } |
685 | } |
686 | if (err) |
687 | goto out; |
688 | |
689 | if (old_freq > freq) |
690 | err = exynos4_bus_setvolt(data, &new_oppinfo, |
691 | &data->curr_oppinfo); |
692 | if (err) |
693 | goto out; |
694 | |
695 | data->curr_oppinfo = new_oppinfo; |
696 | out: |
697 | mutex_unlock(&data->lock); |
698 | return err; |
699 | } |
700 | |
701 | static int exynos4_get_busier_dmc(struct busfreq_data *data) |
702 | { |
703 | u64 p0 = data->dmc[0].count[0]; |
704 | u64 p1 = data->dmc[1].count[0]; |
705 | |
706 | p0 *= data->dmc[1].ccnt; |
707 | p1 *= data->dmc[0].ccnt; |
708 | |
709 | if (data->dmc[1].ccnt == 0) |
710 | return 0; |
711 | |
712 | if (p0 > p1) |
713 | return 0; |
714 | return 1; |
715 | } |
716 | |
717 | static int exynos4_bus_get_dev_status(struct device *dev, |
718 | struct devfreq_dev_status *stat) |
719 | { |
720 | struct busfreq_data *data = dev_get_drvdata(dev); |
721 | int busier_dmc; |
722 | int cycles_x2 = 2; /* 2 x cycles */ |
723 | void __iomem *addr; |
724 | u32 timing; |
725 | u32 memctrl; |
726 | |
727 | exynos4_read_ppmu(data); |
728 | busier_dmc = exynos4_get_busier_dmc(data); |
729 | stat->current_frequency = data->curr_oppinfo.rate; |
730 | |
731 | if (busier_dmc) |
732 | addr = S5P_VA_DMC1; |
733 | else |
734 | addr = S5P_VA_DMC0; |
735 | |
736 | memctrl = __raw_readl(addr + 0x04); /* one of DDR2/3/LPDDR2 */ |
737 | timing = __raw_readl(addr + 0x38); /* CL or WL/RL values */ |
738 | |
739 | switch ((memctrl >> 8) & 0xf) { |
740 | case 0x4: /* DDR2 */ |
741 | cycles_x2 = ((timing >> 16) & 0xf) * 2; |
742 | break; |
743 | case 0x5: /* LPDDR2 */ |
744 | case 0x6: /* DDR3 */ |
745 | cycles_x2 = ((timing >> 8) & 0xf) + ((timing >> 0) & 0xf); |
746 | break; |
747 | default: |
748 | pr_err("%s: Unknown Memory Type(%d).\n", __func__, |
749 | (memctrl >> 8) & 0xf); |
750 | return -EINVAL; |
751 | } |
752 | |
753 | /* Number of cycles spent on memory access */ |
754 | stat->busy_time = data->dmc[busier_dmc].count[0] / 2 * (cycles_x2 + 2); |
755 | stat->busy_time *= 100 / BUS_SATURATION_RATIO; |
756 | stat->total_time = data->dmc[busier_dmc].ccnt; |
757 | |
758 | /* If the counters have overflown, retry */ |
759 | if (data->dmc[busier_dmc].ccnt_overflow || |
760 | data->dmc[busier_dmc].count_overflow[0]) |
761 | return -EAGAIN; |
762 | |
763 | return 0; |
764 | } |
765 | |
766 | static void exynos4_bus_exit(struct device *dev) |
767 | { |
768 | struct busfreq_data *data = dev_get_drvdata(dev); |
769 | |
770 | devfreq_unregister_opp_notifier(dev, data->devfreq); |
771 | } |
772 | |
773 | static struct devfreq_dev_profile exynos4_devfreq_profile = { |
774 | .initial_freq = 400000, |
775 | .polling_ms = 50, |
776 | .target = exynos4_bus_target, |
777 | .get_dev_status = exynos4_bus_get_dev_status, |
778 | .exit = exynos4_bus_exit, |
779 | }; |
780 | |
781 | static int exynos4210_init_tables(struct busfreq_data *data) |
782 | { |
783 | u32 tmp; |
784 | int mgrp; |
785 | int i, err = 0; |
786 | |
787 | tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); |
788 | for (i = LV_0; i < EX4210_LV_NUM; i++) { |
789 | tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | |
790 | EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | |
791 | EXYNOS4_CLKDIV_DMC0_DPHY_MASK | |
792 | EXYNOS4_CLKDIV_DMC0_DMC_MASK | |
793 | EXYNOS4_CLKDIV_DMC0_DMCD_MASK | |
794 | EXYNOS4_CLKDIV_DMC0_DMCP_MASK | |
795 | EXYNOS4_CLKDIV_DMC0_COPY2_MASK | |
796 | EXYNOS4_CLKDIV_DMC0_CORETI_MASK); |
797 | |
798 | tmp |= ((exynos4210_clkdiv_dmc0[i][0] << |
799 | EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | |
800 | (exynos4210_clkdiv_dmc0[i][1] << |
801 | EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | |
802 | (exynos4210_clkdiv_dmc0[i][2] << |
803 | EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | |
804 | (exynos4210_clkdiv_dmc0[i][3] << |
805 | EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | |
806 | (exynos4210_clkdiv_dmc0[i][4] << |
807 | EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | |
808 | (exynos4210_clkdiv_dmc0[i][5] << |
809 | EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) | |
810 | (exynos4210_clkdiv_dmc0[i][6] << |
811 | EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) | |
812 | (exynos4210_clkdiv_dmc0[i][7] << |
813 | EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)); |
814 | |
815 | data->dmc_divtable[i] = tmp; |
816 | } |
817 | |
818 | tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); |
819 | for (i = LV_0; i < EX4210_LV_NUM; i++) { |
820 | tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK | |
821 | EXYNOS4_CLKDIV_TOP_ACLK100_MASK | |
822 | EXYNOS4_CLKDIV_TOP_ACLK160_MASK | |
823 | EXYNOS4_CLKDIV_TOP_ACLK133_MASK | |
824 | EXYNOS4_CLKDIV_TOP_ONENAND_MASK); |
825 | |
826 | tmp |= ((exynos4210_clkdiv_top[i][0] << |
827 | EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) | |
828 | (exynos4210_clkdiv_top[i][1] << |
829 | EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | |
830 | (exynos4210_clkdiv_top[i][2] << |
831 | EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | |
832 | (exynos4210_clkdiv_top[i][3] << |
833 | EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | |
834 | (exynos4210_clkdiv_top[i][4] << |
835 | EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); |
836 | |
837 | data->top_divtable[i] = tmp; |
838 | } |
839 | |
840 | #ifdef CONFIG_EXYNOS_ASV |
841 | tmp = exynos4_result_of_asv; |
842 | #else |
843 | tmp = 0; /* Max voltages for the reliability of the unknown */ |
844 | #endif |
845 | |
846 | pr_debug("ASV Group of Exynos4 is %d\n", tmp); |
847 | /* Use merged grouping for voltage */ |
848 | switch (tmp) { |
849 | case 0: |
850 | mgrp = 0; |
851 | break; |
852 | case 1: |
853 | case 2: |
854 | mgrp = 1; |
855 | break; |
856 | case 3: |
857 | case 4: |
858 | mgrp = 2; |
859 | break; |
860 | case 5: |
861 | case 6: |
862 | mgrp = 3; |
863 | break; |
864 | case 7: |
865 | mgrp = 4; |
866 | break; |
867 | default: |
868 | pr_warn("Unknown ASV Group. Use max voltage.\n"); |
869 | mgrp = 0; |
870 | } |
871 | |
872 | for (i = LV_0; i < EX4210_LV_NUM; i++) |
873 | exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i]; |
874 | |
875 | for (i = LV_0; i < EX4210_LV_NUM; i++) { |
876 | err = opp_add(data->dev, exynos4210_busclk_table[i].clk, |
877 | exynos4210_busclk_table[i].volt); |
878 | if (err) { |
879 | dev_err(data->dev, "Cannot add opp entries.\n"); |
880 | return err; |
881 | } |
882 | } |
883 | |
884 | |
885 | return 0; |
886 | } |
887 | |
888 | static int exynos4x12_init_tables(struct busfreq_data *data) |
889 | { |
890 | unsigned int i; |
891 | unsigned int tmp; |
892 | int ret; |
893 | |
894 | /* Enable pause function for DREX2 DVFS */ |
895 | tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL); |
896 | tmp |= EXYNOS4_DMC_PAUSE_ENABLE; |
897 | __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL); |
898 | |
899 | tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); |
900 | |
901 | for (i = 0; i < EX4x12_LV_NUM; i++) { |
902 | tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | |
903 | EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | |
904 | EXYNOS4_CLKDIV_DMC0_DPHY_MASK | |
905 | EXYNOS4_CLKDIV_DMC0_DMC_MASK | |
906 | EXYNOS4_CLKDIV_DMC0_DMCD_MASK | |
907 | EXYNOS4_CLKDIV_DMC0_DMCP_MASK); |
908 | |
909 | tmp |= ((exynos4x12_clkdiv_dmc0[i][0] << |
910 | EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | |
911 | (exynos4x12_clkdiv_dmc0[i][1] << |
912 | EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | |
913 | (exynos4x12_clkdiv_dmc0[i][2] << |
914 | EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | |
915 | (exynos4x12_clkdiv_dmc0[i][3] << |
916 | EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | |
917 | (exynos4x12_clkdiv_dmc0[i][4] << |
918 | EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | |
919 | (exynos4x12_clkdiv_dmc0[i][5] << |
920 | EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)); |
921 | |
922 | data->dmc_divtable[i] = tmp; |
923 | } |
924 | |
925 | #ifdef CONFIG_EXYNOS_ASV |
926 | tmp = exynos4_result_of_asv; |
927 | #else |
928 | tmp = 0; /* Max voltages for the reliability of the unknown */ |
929 | #endif |
930 | |
931 | if (tmp > 8) |
932 | tmp = 0; |
933 | pr_debug("ASV Group of Exynos4x12 is %d\n", tmp); |
934 | |
935 | for (i = 0; i < EX4x12_LV_NUM; i++) { |
936 | exynos4x12_mifclk_table[i].volt = |
937 | exynos4x12_mif_step_50[tmp][i]; |
938 | exynos4x12_intclk_table[i].volt = |
939 | exynos4x12_int_volt[tmp][i]; |
940 | } |
941 | |
942 | for (i = 0; i < EX4x12_LV_NUM; i++) { |
943 | ret = opp_add(data->dev, exynos4x12_mifclk_table[i].clk, |
944 | exynos4x12_mifclk_table[i].volt); |
945 | if (ret) { |
946 | dev_err(data->dev, "Fail to add opp entries.\n"); |
947 | return ret; |
948 | } |
949 | } |
950 | |
951 | return 0; |
952 | } |
953 | |
954 | static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this, |
955 | unsigned long event, void *ptr) |
956 | { |
957 | struct busfreq_data *data = container_of(this, struct busfreq_data, |
958 | pm_notifier); |
959 | struct opp *opp; |
960 | struct busfreq_opp_info new_oppinfo; |
961 | unsigned long maxfreq = ULONG_MAX; |
962 | int err = 0; |
963 | |
964 | switch (event) { |
965 | case PM_SUSPEND_PREPARE: |
966 | /* Set Fastest and Deactivate DVFS */ |
967 | mutex_lock(&data->lock); |
968 | |
969 | data->disabled = true; |
970 | |
971 | rcu_read_lock(); |
972 | opp = opp_find_freq_floor(data->dev, &maxfreq); |
973 | if (IS_ERR(opp)) { |
974 | rcu_read_unlock(); |
975 | dev_err(data->dev, "%s: unable to find a min freq\n", |
976 | __func__); |
977 | return PTR_ERR(opp); |
978 | } |
979 | new_oppinfo.rate = opp_get_freq(opp); |
980 | new_oppinfo.volt = opp_get_voltage(opp); |
981 | rcu_read_unlock(); |
982 | |
983 | err = exynos4_bus_setvolt(data, &new_oppinfo, |
984 | &data->curr_oppinfo); |
985 | if (err) |
986 | goto unlock; |
987 | |
988 | switch (data->type) { |
989 | case TYPE_BUSF_EXYNOS4210: |
990 | err = exynos4210_set_busclk(data, &new_oppinfo); |
991 | break; |
992 | case TYPE_BUSF_EXYNOS4x12: |
993 | err = exynos4x12_set_busclk(data, &new_oppinfo); |
994 | break; |
995 | default: |
996 | err = -EINVAL; |
997 | } |
998 | if (err) |
999 | goto unlock; |
1000 | |
1001 | data->curr_oppinfo = new_oppinfo; |
1002 | unlock: |
1003 | mutex_unlock(&data->lock); |
1004 | if (err) |
1005 | return err; |
1006 | return NOTIFY_OK; |
1007 | case PM_POST_RESTORE: |
1008 | case PM_POST_SUSPEND: |
1009 | /* Reactivate */ |
1010 | mutex_lock(&data->lock); |
1011 | data->disabled = false; |
1012 | mutex_unlock(&data->lock); |
1013 | return NOTIFY_OK; |
1014 | } |
1015 | |
1016 | return NOTIFY_DONE; |
1017 | } |
1018 | |
1019 | static int exynos4_busfreq_probe(struct platform_device *pdev) |
1020 | { |
1021 | struct busfreq_data *data; |
1022 | struct opp *opp; |
1023 | struct device *dev = &pdev->dev; |
1024 | int err = 0; |
1025 | |
1026 | data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data), GFP_KERNEL); |
1027 | if (data == NULL) { |
1028 | dev_err(dev, "Cannot allocate memory.\n"); |
1029 | return -ENOMEM; |
1030 | } |
1031 | |
1032 | data->type = pdev->id_entry->driver_data; |
1033 | data->dmc[0].hw_base = S5P_VA_DMC0; |
1034 | data->dmc[1].hw_base = S5P_VA_DMC1; |
1035 | data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event; |
1036 | data->dev = dev; |
1037 | mutex_init(&data->lock); |
1038 | |
1039 | switch (data->type) { |
1040 | case TYPE_BUSF_EXYNOS4210: |
1041 | err = exynos4210_init_tables(data); |
1042 | break; |
1043 | case TYPE_BUSF_EXYNOS4x12: |
1044 | err = exynos4x12_init_tables(data); |
1045 | break; |
1046 | default: |
1047 | dev_err(dev, "Cannot determine the device id %d\n", data->type); |
1048 | err = -EINVAL; |
1049 | } |
1050 | if (err) |
1051 | return err; |
1052 | |
1053 | data->vdd_int = devm_regulator_get(dev, "vdd_int"); |
1054 | if (IS_ERR(data->vdd_int)) { |
1055 | dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); |
1056 | return PTR_ERR(data->vdd_int); |
1057 | } |
1058 | if (data->type == TYPE_BUSF_EXYNOS4x12) { |
1059 | data->vdd_mif = devm_regulator_get(dev, "vdd_mif"); |
1060 | if (IS_ERR(data->vdd_mif)) { |
1061 | dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n"); |
1062 | return PTR_ERR(data->vdd_mif); |
1063 | } |
1064 | } |
1065 | |
1066 | rcu_read_lock(); |
1067 | opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq); |
1068 | if (IS_ERR(opp)) { |
1069 | rcu_read_unlock(); |
1070 | dev_err(dev, "Invalid initial frequency %lu kHz.\n", |
1071 | exynos4_devfreq_profile.initial_freq); |
1072 | return PTR_ERR(opp); |
1073 | } |
1074 | data->curr_oppinfo.rate = opp_get_freq(opp); |
1075 | data->curr_oppinfo.volt = opp_get_voltage(opp); |
1076 | rcu_read_unlock(); |
1077 | |
1078 | platform_set_drvdata(pdev, data); |
1079 | |
1080 | busfreq_mon_reset(data); |
1081 | |
1082 | data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile, |
1083 | "simple_ondemand", NULL); |
1084 | if (IS_ERR(data->devfreq)) |
1085 | return PTR_ERR(data->devfreq); |
1086 | |
1087 | devfreq_register_opp_notifier(dev, data->devfreq); |
1088 | |
1089 | err = register_pm_notifier(&data->pm_notifier); |
1090 | if (err) { |
1091 | dev_err(dev, "Failed to setup pm notifier\n"); |
1092 | devfreq_remove_device(data->devfreq); |
1093 | return err; |
1094 | } |
1095 | |
1096 | return 0; |
1097 | } |
1098 | |
1099 | static int exynos4_busfreq_remove(struct platform_device *pdev) |
1100 | { |
1101 | struct busfreq_data *data = platform_get_drvdata(pdev); |
1102 | |
1103 | unregister_pm_notifier(&data->pm_notifier); |
1104 | devfreq_remove_device(data->devfreq); |
1105 | |
1106 | return 0; |
1107 | } |
1108 | |
1109 | static int exynos4_busfreq_resume(struct device *dev) |
1110 | { |
1111 | struct busfreq_data *data = dev_get_drvdata(dev); |
1112 | |
1113 | busfreq_mon_reset(data); |
1114 | return 0; |
1115 | } |
1116 | |
1117 | static const struct dev_pm_ops exynos4_busfreq_pm = { |
1118 | .resume = exynos4_busfreq_resume, |
1119 | }; |
1120 | |
1121 | static const struct platform_device_id exynos4_busfreq_id[] = { |
1122 | { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 }, |
1123 | { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 }, |
1124 | { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 }, |
1125 | { }, |
1126 | }; |
1127 | |
1128 | static struct platform_driver exynos4_busfreq_driver = { |
1129 | .probe = exynos4_busfreq_probe, |
1130 | .remove = exynos4_busfreq_remove, |
1131 | .id_table = exynos4_busfreq_id, |
1132 | .driver = { |
1133 | .name = "exynos4-busfreq", |
1134 | .owner = THIS_MODULE, |
1135 | .pm = &exynos4_busfreq_pm, |
1136 | }, |
1137 | }; |
1138 | |
1139 | static int __init exynos4_busfreq_init(void) |
1140 | { |
1141 | return platform_driver_register(&exynos4_busfreq_driver); |
1142 | } |
1143 | late_initcall(exynos4_busfreq_init); |
1144 | |
1145 | static void __exit exynos4_busfreq_exit(void) |
1146 | { |
1147 | platform_driver_unregister(&exynos4_busfreq_driver); |
1148 | } |
1149 | module_exit(exynos4_busfreq_exit); |
1150 | |
1151 | MODULE_LICENSE("GPL"); |
1152 | MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework"); |
1153 | MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>"); |
1154 |
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