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1 | /* |
2 | * Radisys 82600 Embedded chipset Memory Controller kernel module |
3 | * (C) 2005 EADS Astrium |
4 | * This file may be distributed under the terms of the |
5 | * GNU General Public License. |
6 | * |
7 | * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne |
8 | * Harbaugh, Dan Hollis <goemon at anime dot net> and others. |
9 | * |
10 | * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $ |
11 | * |
12 | * Written with reference to 82600 High Integration Dual PCI System |
13 | * Controller Data Book: |
14 | * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf |
15 | * references to this document given in [] |
16 | */ |
17 | |
18 | #include <linux/module.h> |
19 | #include <linux/init.h> |
20 | #include <linux/pci.h> |
21 | #include <linux/pci_ids.h> |
22 | #include <linux/edac.h> |
23 | #include "edac_core.h" |
24 | |
25 | #define R82600_REVISION " Ver: 2.0.2" |
26 | #define EDAC_MOD_STR "r82600_edac" |
27 | |
28 | #define r82600_printk(level, fmt, arg...) \ |
29 | edac_printk(level, "r82600", fmt, ##arg) |
30 | |
31 | #define r82600_mc_printk(mci, level, fmt, arg...) \ |
32 | edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg) |
33 | |
34 | /* Radisys say "The 82600 integrates a main memory SDRAM controller that |
35 | * supports up to four banks of memory. The four banks can support a mix of |
36 | * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, |
37 | * each of which can be any size from 16MB to 512MB. Both registered (control |
38 | * signals buffered) and unbuffered DIMM types are supported. Mixing of |
39 | * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs |
40 | * is not allowed. The 82600 SDRAM interface operates at the same frequency as |
41 | * the CPU bus, 66MHz, 100MHz or 133MHz." |
42 | */ |
43 | |
44 | #define R82600_NR_CSROWS 4 |
45 | #define R82600_NR_CHANS 1 |
46 | #define R82600_NR_DIMMS 4 |
47 | |
48 | #define R82600_BRIDGE_ID 0x8200 |
49 | |
50 | /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */ |
51 | #define R82600_DRAMC 0x57 /* Various SDRAM related control bits |
52 | * all bits are R/W |
53 | * |
54 | * 7 SDRAM ISA Hole Enable |
55 | * 6 Flash Page Mode Enable |
56 | * 5 ECC Enable: 1=ECC 0=noECC |
57 | * 4 DRAM DIMM Type: 1= |
58 | * 3 BIOS Alias Disable |
59 | * 2 SDRAM BIOS Flash Write Enable |
60 | * 1:0 SDRAM Refresh Rate: 00=Disabled |
61 | * 01=7.8usec (256Mbit SDRAMs) |
62 | * 10=15.6us 11=125usec |
63 | */ |
64 | |
65 | #define R82600_SDRAMC 0x76 /* "SDRAM Control Register" |
66 | * More SDRAM related control bits |
67 | * all bits are R/W |
68 | * |
69 | * 15:8 Reserved. |
70 | * |
71 | * 7:5 Special SDRAM Mode Select |
72 | * |
73 | * 4 Force ECC |
74 | * |
75 | * 1=Drive ECC bits to 0 during |
76 | * write cycles (i.e. ECC test mode) |
77 | * |
78 | * 0=Normal ECC functioning |
79 | * |
80 | * 3 Enhanced Paging Enable |
81 | * |
82 | * 2 CAS# Latency 0=3clks 1=2clks |
83 | * |
84 | * 1 RAS# to CAS# Delay 0=3 1=2 |
85 | * |
86 | * 0 RAS# Precharge 0=3 1=2 |
87 | */ |
88 | |
89 | #define R82600_EAP 0x80 /* ECC Error Address Pointer Register |
90 | * |
91 | * 31 Disable Hardware Scrubbing (RW) |
92 | * 0=Scrub on corrected read |
93 | * 1=Don't scrub on corrected read |
94 | * |
95 | * 30:12 Error Address Pointer (RO) |
96 | * Upper 19 bits of error address |
97 | * |
98 | * 11:4 Syndrome Bits (RO) |
99 | * |
100 | * 3 BSERR# on multibit error (RW) |
101 | * 1=enable 0=disable |
102 | * |
103 | * 2 NMI on Single Bit Eror (RW) |
104 | * 1=NMI triggered by SBE n.b. other |
105 | * prerequeists |
106 | * 0=NMI not triggered |
107 | * |
108 | * 1 MBE (R/WC) |
109 | * read 1=MBE at EAP (see above) |
110 | * read 0=no MBE, or SBE occurred first |
111 | * write 1=Clear MBE status (must also |
112 | * clear SBE) |
113 | * write 0=NOP |
114 | * |
115 | * 1 SBE (R/WC) |
116 | * read 1=SBE at EAP (see above) |
117 | * read 0=no SBE, or MBE occurred first |
118 | * write 1=Clear SBE status (must also |
119 | * clear MBE) |
120 | * write 0=NOP |
121 | */ |
122 | |
123 | #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address |
124 | * Registers |
125 | * |
126 | * 7:0 Address lines 30:24 - upper limit of |
127 | * each row [p57] |
128 | */ |
129 | |
130 | struct r82600_error_info { |
131 | u32 eapr; |
132 | }; |
133 | |
134 | static bool disable_hardware_scrub; |
135 | |
136 | static struct edac_pci_ctl_info *r82600_pci; |
137 | |
138 | static void r82600_get_error_info(struct mem_ctl_info *mci, |
139 | struct r82600_error_info *info) |
140 | { |
141 | struct pci_dev *pdev; |
142 | |
143 | pdev = to_pci_dev(mci->pdev); |
144 | pci_read_config_dword(pdev, R82600_EAP, &info->eapr); |
145 | |
146 | if (info->eapr & BIT(0)) |
147 | /* Clear error to allow next error to be reported [p.62] */ |
148 | pci_write_bits32(pdev, R82600_EAP, |
149 | ((u32) BIT(0) & (u32) BIT(1)), |
150 | ((u32) BIT(0) & (u32) BIT(1))); |
151 | |
152 | if (info->eapr & BIT(1)) |
153 | /* Clear error to allow next error to be reported [p.62] */ |
154 | pci_write_bits32(pdev, R82600_EAP, |
155 | ((u32) BIT(0) & (u32) BIT(1)), |
156 | ((u32) BIT(0) & (u32) BIT(1))); |
157 | } |
158 | |
159 | static int r82600_process_error_info(struct mem_ctl_info *mci, |
160 | struct r82600_error_info *info, |
161 | int handle_errors) |
162 | { |
163 | int error_found; |
164 | u32 eapaddr, page; |
165 | u32 syndrome; |
166 | |
167 | error_found = 0; |
168 | |
169 | /* bits 30:12 store the upper 19 bits of the 32 bit error address */ |
170 | eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13; |
171 | /* Syndrome in bits 11:4 [p.62] */ |
172 | syndrome = (info->eapr >> 4) & 0xFF; |
173 | |
174 | /* the R82600 reports at less than page * |
175 | * granularity (upper 19 bits only) */ |
176 | page = eapaddr >> PAGE_SHIFT; |
177 | |
178 | if (info->eapr & BIT(0)) { /* CE? */ |
179 | error_found = 1; |
180 | |
181 | if (handle_errors) |
182 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
183 | page, 0, syndrome, |
184 | edac_mc_find_csrow_by_page(mci, page), |
185 | 0, -1, |
186 | mci->ctl_name, ""); |
187 | } |
188 | |
189 | if (info->eapr & BIT(1)) { /* UE? */ |
190 | error_found = 1; |
191 | |
192 | if (handle_errors) |
193 | /* 82600 doesn't give enough info */ |
194 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
195 | page, 0, 0, |
196 | edac_mc_find_csrow_by_page(mci, page), |
197 | 0, -1, |
198 | mci->ctl_name, ""); |
199 | } |
200 | |
201 | return error_found; |
202 | } |
203 | |
204 | static void r82600_check(struct mem_ctl_info *mci) |
205 | { |
206 | struct r82600_error_info info; |
207 | |
208 | edac_dbg(1, "MC%d\n", mci->mc_idx); |
209 | r82600_get_error_info(mci, &info); |
210 | r82600_process_error_info(mci, &info, 1); |
211 | } |
212 | |
213 | static inline int ecc_enabled(u8 dramcr) |
214 | { |
215 | return dramcr & BIT(5); |
216 | } |
217 | |
218 | static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
219 | u8 dramcr) |
220 | { |
221 | struct csrow_info *csrow; |
222 | struct dimm_info *dimm; |
223 | int index; |
224 | u8 drbar; /* SDRAM Row Boundary Address Register */ |
225 | u32 row_high_limit, row_high_limit_last; |
226 | u32 reg_sdram, ecc_on, row_base; |
227 | |
228 | ecc_on = ecc_enabled(dramcr); |
229 | reg_sdram = dramcr & BIT(4); |
230 | row_high_limit_last = 0; |
231 | |
232 | for (index = 0; index < mci->nr_csrows; index++) { |
233 | csrow = mci->csrows[index]; |
234 | dimm = csrow->channels[0]->dimm; |
235 | |
236 | /* find the DRAM Chip Select Base address and mask */ |
237 | pci_read_config_byte(pdev, R82600_DRBA + index, &drbar); |
238 | |
239 | edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar); |
240 | |
241 | row_high_limit = ((u32) drbar << 24); |
242 | /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ |
243 | |
244 | edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n", |
245 | index, row_high_limit, row_high_limit_last); |
246 | |
247 | /* Empty row [p.57] */ |
248 | if (row_high_limit == row_high_limit_last) |
249 | continue; |
250 | |
251 | row_base = row_high_limit_last; |
252 | |
253 | csrow->first_page = row_base >> PAGE_SHIFT; |
254 | csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; |
255 | |
256 | dimm->nr_pages = csrow->last_page - csrow->first_page + 1; |
257 | /* Error address is top 19 bits - so granularity is * |
258 | * 14 bits */ |
259 | dimm->grain = 1 << 14; |
260 | dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; |
261 | /* FIXME - check that this is unknowable with this chipset */ |
262 | dimm->dtype = DEV_UNKNOWN; |
263 | |
264 | /* Mode is global on 82600 */ |
265 | dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; |
266 | row_high_limit_last = row_high_limit; |
267 | } |
268 | } |
269 | |
270 | static int r82600_probe1(struct pci_dev *pdev, int dev_idx) |
271 | { |
272 | struct mem_ctl_info *mci; |
273 | struct edac_mc_layer layers[2]; |
274 | u8 dramcr; |
275 | u32 eapr; |
276 | u32 scrub_disabled; |
277 | u32 sdram_refresh_rate; |
278 | struct r82600_error_info discard; |
279 | |
280 | edac_dbg(0, "\n"); |
281 | pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); |
282 | pci_read_config_dword(pdev, R82600_EAP, &eapr); |
283 | scrub_disabled = eapr & BIT(31); |
284 | sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); |
285 | edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate); |
286 | edac_dbg(2, "DRAMC register = %#0x\n", dramcr); |
287 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
288 | layers[0].size = R82600_NR_CSROWS; |
289 | layers[0].is_virt_csrow = true; |
290 | layers[1].type = EDAC_MC_LAYER_CHANNEL; |
291 | layers[1].size = R82600_NR_CHANS; |
292 | layers[1].is_virt_csrow = false; |
293 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); |
294 | if (mci == NULL) |
295 | return -ENOMEM; |
296 | |
297 | edac_dbg(0, "mci = %p\n", mci); |
298 | mci->pdev = &pdev->dev; |
299 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; |
300 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
301 | /* FIXME try to work out if the chip leads have been used for COM2 |
302 | * instead on this board? [MA6?] MAYBE: |
303 | */ |
304 | |
305 | /* On the R82600, the pins for memory bits 72:65 - i.e. the * |
306 | * EC bits are shared with the pins for COM2 (!), so if COM2 * |
307 | * is enabled, we assume COM2 is wired up, and thus no EDAC * |
308 | * is possible. */ |
309 | mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
310 | |
311 | if (ecc_enabled(dramcr)) { |
312 | if (scrub_disabled) |
313 | edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n", |
314 | mci, eapr); |
315 | } else |
316 | mci->edac_cap = EDAC_FLAG_NONE; |
317 | |
318 | mci->mod_name = EDAC_MOD_STR; |
319 | mci->mod_ver = R82600_REVISION; |
320 | mci->ctl_name = "R82600"; |
321 | mci->dev_name = pci_name(pdev); |
322 | mci->edac_check = r82600_check; |
323 | mci->ctl_page_to_phys = NULL; |
324 | r82600_init_csrows(mci, pdev, dramcr); |
325 | r82600_get_error_info(mci, &discard); /* clear counters */ |
326 | |
327 | /* Here we assume that we will never see multiple instances of this |
328 | * type of memory controller. The ID is therefore hardcoded to 0. |
329 | */ |
330 | if (edac_mc_add_mc(mci)) { |
331 | edac_dbg(3, "failed edac_mc_add_mc()\n"); |
332 | goto fail; |
333 | } |
334 | |
335 | /* get this far and it's successful */ |
336 | |
337 | if (disable_hardware_scrub) { |
338 | edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n"); |
339 | pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); |
340 | } |
341 | |
342 | /* allocating generic PCI control info */ |
343 | r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); |
344 | if (!r82600_pci) { |
345 | printk(KERN_WARNING |
346 | "%s(): Unable to create PCI control\n", |
347 | __func__); |
348 | printk(KERN_WARNING |
349 | "%s(): PCI error report via EDAC not setup\n", |
350 | __func__); |
351 | } |
352 | |
353 | edac_dbg(3, "success\n"); |
354 | return 0; |
355 | |
356 | fail: |
357 | edac_mc_free(mci); |
358 | return -ENODEV; |
359 | } |
360 | |
361 | /* returns count (>= 0), or negative on error */ |
362 | static int r82600_init_one(struct pci_dev *pdev, |
363 | const struct pci_device_id *ent) |
364 | { |
365 | edac_dbg(0, "\n"); |
366 | |
367 | /* don't need to call pci_enable_device() */ |
368 | return r82600_probe1(pdev, ent->driver_data); |
369 | } |
370 | |
371 | static void r82600_remove_one(struct pci_dev *pdev) |
372 | { |
373 | struct mem_ctl_info *mci; |
374 | |
375 | edac_dbg(0, "\n"); |
376 | |
377 | if (r82600_pci) |
378 | edac_pci_release_generic_ctl(r82600_pci); |
379 | |
380 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
381 | return; |
382 | |
383 | edac_mc_free(mci); |
384 | } |
385 | |
386 | static DEFINE_PCI_DEVICE_TABLE(r82600_pci_tbl) = { |
387 | { |
388 | PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID) |
389 | }, |
390 | { |
391 | 0, |
392 | } /* 0 terminated list. */ |
393 | }; |
394 | |
395 | MODULE_DEVICE_TABLE(pci, r82600_pci_tbl); |
396 | |
397 | static struct pci_driver r82600_driver = { |
398 | .name = EDAC_MOD_STR, |
399 | .probe = r82600_init_one, |
400 | .remove = r82600_remove_one, |
401 | .id_table = r82600_pci_tbl, |
402 | }; |
403 | |
404 | static int __init r82600_init(void) |
405 | { |
406 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
407 | opstate_init(); |
408 | |
409 | return pci_register_driver(&r82600_driver); |
410 | } |
411 | |
412 | static void __exit r82600_exit(void) |
413 | { |
414 | pci_unregister_driver(&r82600_driver); |
415 | } |
416 | |
417 | module_init(r82600_init); |
418 | module_exit(r82600_exit); |
419 | |
420 | MODULE_LICENSE("GPL"); |
421 | MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. " |
422 | "on behalf of EADS Astrium"); |
423 | MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers"); |
424 | |
425 | module_param(disable_hardware_scrub, bool, 0644); |
426 | MODULE_PARM_DESC(disable_hardware_scrub, |
427 | "If set, disable the chipset's automatic scrub for CEs"); |
428 | |
429 | module_param(edac_op_state, int, 0444); |
430 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |
431 |
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