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1 | /* |
2 | * linux/arch/arm/plat-pxa/gpio.c |
3 | * |
4 | * Generic PXA GPIO handling |
5 | * |
6 | * Author: Nicolas Pitre |
7 | * Created: Jun 15, 2001 |
8 | * Copyright: MontaVista Software Inc. |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as |
12 | * published by the Free Software Foundation. |
13 | */ |
14 | #include <linux/module.h> |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> |
18 | #include <linux/gpio-pxa.h> |
19 | #include <linux/init.h> |
20 | #include <linux/irq.h> |
21 | #include <linux/irqdomain.h> |
22 | #include <linux/io.h> |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> |
25 | #include <linux/platform_device.h> |
26 | #include <linux/syscore_ops.h> |
27 | #include <linux/slab.h> |
28 | |
29 | #include <asm/mach/irq.h> |
30 | |
31 | #include <mach/irqs.h> |
32 | |
33 | /* |
34 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with |
35 | * one set of registers. The register offsets are organized below: |
36 | * |
37 | * GPLR GPDR GPSR GPCR GRER GFER GEDR |
38 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 |
39 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C |
40 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 |
41 | * |
42 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 |
43 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C |
44 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 |
45 | * |
46 | * NOTE: |
47 | * BANK 3 is only available on PXA27x and later processors. |
48 | * BANK 4 and 5 are only available on PXA935 |
49 | */ |
50 | |
51 | #define GPLR_OFFSET 0x00 |
52 | #define GPDR_OFFSET 0x0C |
53 | #define GPSR_OFFSET 0x18 |
54 | #define GPCR_OFFSET 0x24 |
55 | #define GRER_OFFSET 0x30 |
56 | #define GFER_OFFSET 0x3C |
57 | #define GEDR_OFFSET 0x48 |
58 | #define GAFR_OFFSET 0x54 |
59 | #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ |
60 | |
61 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) |
62 | |
63 | int pxa_last_gpio; |
64 | static int irq_base; |
65 | |
66 | #ifdef CONFIG_OF |
67 | static struct irq_domain *domain; |
68 | static struct device_node *pxa_gpio_of_node; |
69 | #endif |
70 | |
71 | struct pxa_gpio_chip { |
72 | struct gpio_chip chip; |
73 | void __iomem *regbase; |
74 | char label[10]; |
75 | |
76 | unsigned long irq_mask; |
77 | unsigned long irq_edge_rise; |
78 | unsigned long irq_edge_fall; |
79 | int (*set_wake)(unsigned int gpio, unsigned int on); |
80 | |
81 | #ifdef CONFIG_PM |
82 | unsigned long saved_gplr; |
83 | unsigned long saved_gpdr; |
84 | unsigned long saved_grer; |
85 | unsigned long saved_gfer; |
86 | #endif |
87 | }; |
88 | |
89 | enum { |
90 | PXA25X_GPIO = 0, |
91 | PXA26X_GPIO, |
92 | PXA27X_GPIO, |
93 | PXA3XX_GPIO, |
94 | PXA93X_GPIO, |
95 | MMP_GPIO = 0x10, |
96 | }; |
97 | |
98 | static DEFINE_SPINLOCK(gpio_lock); |
99 | static struct pxa_gpio_chip *pxa_gpio_chips; |
100 | static int gpio_type; |
101 | static void __iomem *gpio_reg_base; |
102 | |
103 | #define for_each_gpio_chip(i, c) \ |
104 | for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) |
105 | |
106 | static inline void __iomem *gpio_chip_base(struct gpio_chip *c) |
107 | { |
108 | return container_of(c, struct pxa_gpio_chip, chip)->regbase; |
109 | } |
110 | |
111 | static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) |
112 | { |
113 | return &pxa_gpio_chips[gpio_to_bank(gpio)]; |
114 | } |
115 | |
116 | static inline int gpio_is_pxa_type(int type) |
117 | { |
118 | return (type & MMP_GPIO) == 0; |
119 | } |
120 | |
121 | static inline int gpio_is_mmp_type(int type) |
122 | { |
123 | return (type & MMP_GPIO) != 0; |
124 | } |
125 | |
126 | /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, |
127 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. |
128 | */ |
129 | static inline int __gpio_is_inverted(int gpio) |
130 | { |
131 | if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) |
132 | return 1; |
133 | return 0; |
134 | } |
135 | |
136 | /* |
137 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate |
138 | * function of a GPIO, and GPDRx cannot be altered once configured. It |
139 | * is attributed as "occupied" here (I know this terminology isn't |
140 | * accurate, you are welcome to propose a better one :-) |
141 | */ |
142 | static inline int __gpio_is_occupied(unsigned gpio) |
143 | { |
144 | struct pxa_gpio_chip *pxachip; |
145 | void __iomem *base; |
146 | unsigned long gafr = 0, gpdr = 0; |
147 | int ret, af = 0, dir = 0; |
148 | |
149 | pxachip = gpio_to_pxachip(gpio); |
150 | base = gpio_chip_base(&pxachip->chip); |
151 | gpdr = readl_relaxed(base + GPDR_OFFSET); |
152 | |
153 | switch (gpio_type) { |
154 | case PXA25X_GPIO: |
155 | case PXA26X_GPIO: |
156 | case PXA27X_GPIO: |
157 | gafr = readl_relaxed(base + GAFR_OFFSET); |
158 | af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; |
159 | dir = gpdr & GPIO_bit(gpio); |
160 | |
161 | if (__gpio_is_inverted(gpio)) |
162 | ret = (af != 1) || (dir == 0); |
163 | else |
164 | ret = (af != 0) || (dir != 0); |
165 | break; |
166 | default: |
167 | ret = gpdr & GPIO_bit(gpio); |
168 | break; |
169 | } |
170 | return ret; |
171 | } |
172 | |
173 | static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
174 | { |
175 | return chip->base + offset + irq_base; |
176 | } |
177 | |
178 | int pxa_irq_to_gpio(int irq) |
179 | { |
180 | return irq - irq_base; |
181 | } |
182 | |
183 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
184 | { |
185 | void __iomem *base = gpio_chip_base(chip); |
186 | uint32_t value, mask = 1 << offset; |
187 | unsigned long flags; |
188 | |
189 | spin_lock_irqsave(&gpio_lock, flags); |
190 | |
191 | value = readl_relaxed(base + GPDR_OFFSET); |
192 | if (__gpio_is_inverted(chip->base + offset)) |
193 | value |= mask; |
194 | else |
195 | value &= ~mask; |
196 | writel_relaxed(value, base + GPDR_OFFSET); |
197 | |
198 | spin_unlock_irqrestore(&gpio_lock, flags); |
199 | return 0; |
200 | } |
201 | |
202 | static int pxa_gpio_direction_output(struct gpio_chip *chip, |
203 | unsigned offset, int value) |
204 | { |
205 | void __iomem *base = gpio_chip_base(chip); |
206 | uint32_t tmp, mask = 1 << offset; |
207 | unsigned long flags; |
208 | |
209 | writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
210 | |
211 | spin_lock_irqsave(&gpio_lock, flags); |
212 | |
213 | tmp = readl_relaxed(base + GPDR_OFFSET); |
214 | if (__gpio_is_inverted(chip->base + offset)) |
215 | tmp &= ~mask; |
216 | else |
217 | tmp |= mask; |
218 | writel_relaxed(tmp, base + GPDR_OFFSET); |
219 | |
220 | spin_unlock_irqrestore(&gpio_lock, flags); |
221 | return 0; |
222 | } |
223 | |
224 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
225 | { |
226 | return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); |
227 | } |
228 | |
229 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
230 | { |
231 | writel_relaxed(1 << offset, gpio_chip_base(chip) + |
232 | (value ? GPSR_OFFSET : GPCR_OFFSET)); |
233 | } |
234 | |
235 | #ifdef CONFIG_OF_GPIO |
236 | static int pxa_gpio_of_xlate(struct gpio_chip *gc, |
237 | const struct of_phandle_args *gpiospec, |
238 | u32 *flags) |
239 | { |
240 | if (gpiospec->args[0] > pxa_last_gpio) |
241 | return -EINVAL; |
242 | |
243 | if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip) |
244 | return -EINVAL; |
245 | |
246 | if (flags) |
247 | *flags = gpiospec->args[1]; |
248 | |
249 | return gpiospec->args[0] % 32; |
250 | } |
251 | #endif |
252 | |
253 | static int pxa_init_gpio_chip(int gpio_end, |
254 | int (*set_wake)(unsigned int, unsigned int)) |
255 | { |
256 | int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; |
257 | struct pxa_gpio_chip *chips; |
258 | |
259 | chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL); |
260 | if (chips == NULL) { |
261 | pr_err("%s: failed to allocate GPIO chips\n", __func__); |
262 | return -ENOMEM; |
263 | } |
264 | |
265 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { |
266 | struct gpio_chip *c = &chips[i].chip; |
267 | |
268 | sprintf(chips[i].label, "gpio-%d", i); |
269 | chips[i].regbase = gpio_reg_base + BANK_OFF(i); |
270 | chips[i].set_wake = set_wake; |
271 | |
272 | c->base = gpio; |
273 | c->label = chips[i].label; |
274 | |
275 | c->direction_input = pxa_gpio_direction_input; |
276 | c->direction_output = pxa_gpio_direction_output; |
277 | c->get = pxa_gpio_get; |
278 | c->set = pxa_gpio_set; |
279 | c->to_irq = pxa_gpio_to_irq; |
280 | #ifdef CONFIG_OF_GPIO |
281 | c->of_node = pxa_gpio_of_node; |
282 | c->of_xlate = pxa_gpio_of_xlate; |
283 | c->of_gpio_n_cells = 2; |
284 | #endif |
285 | |
286 | /* number of GPIOs on last bank may be less than 32 */ |
287 | c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; |
288 | gpiochip_add(c); |
289 | } |
290 | pxa_gpio_chips = chips; |
291 | return 0; |
292 | } |
293 | |
294 | /* Update only those GRERx and GFERx edge detection register bits if those |
295 | * bits are set in c->irq_mask |
296 | */ |
297 | static inline void update_edge_detect(struct pxa_gpio_chip *c) |
298 | { |
299 | uint32_t grer, gfer; |
300 | |
301 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; |
302 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; |
303 | grer |= c->irq_edge_rise & c->irq_mask; |
304 | gfer |= c->irq_edge_fall & c->irq_mask; |
305 | writel_relaxed(grer, c->regbase + GRER_OFFSET); |
306 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); |
307 | } |
308 | |
309 | static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) |
310 | { |
311 | struct pxa_gpio_chip *c; |
312 | int gpio = pxa_irq_to_gpio(d->irq); |
313 | unsigned long gpdr, mask = GPIO_bit(gpio); |
314 | |
315 | c = gpio_to_pxachip(gpio); |
316 | |
317 | if (type == IRQ_TYPE_PROBE) { |
318 | /* Don't mess with enabled GPIOs using preconfigured edges or |
319 | * GPIOs set to alternate function or to output during probe |
320 | */ |
321 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) |
322 | return 0; |
323 | |
324 | if (__gpio_is_occupied(gpio)) |
325 | return 0; |
326 | |
327 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
328 | } |
329 | |
330 | gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
331 | |
332 | if (__gpio_is_inverted(gpio)) |
333 | writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); |
334 | else |
335 | writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); |
336 | |
337 | if (type & IRQ_TYPE_EDGE_RISING) |
338 | c->irq_edge_rise |= mask; |
339 | else |
340 | c->irq_edge_rise &= ~mask; |
341 | |
342 | if (type & IRQ_TYPE_EDGE_FALLING) |
343 | c->irq_edge_fall |= mask; |
344 | else |
345 | c->irq_edge_fall &= ~mask; |
346 | |
347 | update_edge_detect(c); |
348 | |
349 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, |
350 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
351 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); |
352 | return 0; |
353 | } |
354 | |
355 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) |
356 | { |
357 | struct pxa_gpio_chip *c; |
358 | int loop, gpio, gpio_base, n; |
359 | unsigned long gedr; |
360 | struct irq_chip *chip = irq_desc_get_chip(desc); |
361 | |
362 | chained_irq_enter(chip, desc); |
363 | |
364 | do { |
365 | loop = 0; |
366 | for_each_gpio_chip(gpio, c) { |
367 | gpio_base = c->chip.base; |
368 | |
369 | gedr = readl_relaxed(c->regbase + GEDR_OFFSET); |
370 | gedr = gedr & c->irq_mask; |
371 | writel_relaxed(gedr, c->regbase + GEDR_OFFSET); |
372 | |
373 | for_each_set_bit(n, &gedr, BITS_PER_LONG) { |
374 | loop = 1; |
375 | |
376 | generic_handle_irq(gpio_to_irq(gpio_base + n)); |
377 | } |
378 | } |
379 | } while (loop); |
380 | |
381 | chained_irq_exit(chip, desc); |
382 | } |
383 | |
384 | static void pxa_ack_muxed_gpio(struct irq_data *d) |
385 | { |
386 | int gpio = pxa_irq_to_gpio(d->irq); |
387 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
388 | |
389 | writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); |
390 | } |
391 | |
392 | static void pxa_mask_muxed_gpio(struct irq_data *d) |
393 | { |
394 | int gpio = pxa_irq_to_gpio(d->irq); |
395 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
396 | uint32_t grer, gfer; |
397 | |
398 | c->irq_mask &= ~GPIO_bit(gpio); |
399 | |
400 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); |
401 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); |
402 | writel_relaxed(grer, c->regbase + GRER_OFFSET); |
403 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); |
404 | } |
405 | |
406 | static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) |
407 | { |
408 | int gpio = pxa_irq_to_gpio(d->irq); |
409 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
410 | |
411 | if (c->set_wake) |
412 | return c->set_wake(gpio, on); |
413 | else |
414 | return 0; |
415 | } |
416 | |
417 | static void pxa_unmask_muxed_gpio(struct irq_data *d) |
418 | { |
419 | int gpio = pxa_irq_to_gpio(d->irq); |
420 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
421 | |
422 | c->irq_mask |= GPIO_bit(gpio); |
423 | update_edge_detect(c); |
424 | } |
425 | |
426 | static struct irq_chip pxa_muxed_gpio_chip = { |
427 | .name = "GPIO", |
428 | .irq_ack = pxa_ack_muxed_gpio, |
429 | .irq_mask = pxa_mask_muxed_gpio, |
430 | .irq_unmask = pxa_unmask_muxed_gpio, |
431 | .irq_set_type = pxa_gpio_irq_type, |
432 | .irq_set_wake = pxa_gpio_set_wake, |
433 | }; |
434 | |
435 | static int pxa_gpio_nums(void) |
436 | { |
437 | int count = 0; |
438 | |
439 | #ifdef CONFIG_ARCH_PXA |
440 | if (cpu_is_pxa25x()) { |
441 | #ifdef CONFIG_CPU_PXA26x |
442 | count = 89; |
443 | gpio_type = PXA26X_GPIO; |
444 | #elif defined(CONFIG_PXA25x) |
445 | count = 84; |
446 | gpio_type = PXA26X_GPIO; |
447 | #endif /* CONFIG_CPU_PXA26x */ |
448 | } else if (cpu_is_pxa27x()) { |
449 | count = 120; |
450 | gpio_type = PXA27X_GPIO; |
451 | } else if (cpu_is_pxa93x()) { |
452 | count = 191; |
453 | gpio_type = PXA93X_GPIO; |
454 | } else if (cpu_is_pxa3xx()) { |
455 | count = 127; |
456 | gpio_type = PXA3XX_GPIO; |
457 | } |
458 | #endif /* CONFIG_ARCH_PXA */ |
459 | |
460 | #ifdef CONFIG_ARCH_MMP |
461 | if (cpu_is_pxa168() || cpu_is_pxa910()) { |
462 | count = 127; |
463 | gpio_type = MMP_GPIO; |
464 | } else if (cpu_is_mmp2()) { |
465 | count = 191; |
466 | gpio_type = MMP_GPIO; |
467 | } |
468 | #endif /* CONFIG_ARCH_MMP */ |
469 | return count; |
470 | } |
471 | |
472 | #ifdef CONFIG_OF |
473 | static struct of_device_id pxa_gpio_dt_ids[] = { |
474 | { .compatible = "mrvl,pxa-gpio" }, |
475 | { .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO }, |
476 | {} |
477 | }; |
478 | |
479 | static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, |
480 | irq_hw_number_t hw) |
481 | { |
482 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
483 | handle_edge_irq); |
484 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
485 | return 0; |
486 | } |
487 | |
488 | const struct irq_domain_ops pxa_irq_domain_ops = { |
489 | .map = pxa_irq_domain_map, |
490 | .xlate = irq_domain_xlate_twocell, |
491 | }; |
492 | |
493 | static int pxa_gpio_probe_dt(struct platform_device *pdev) |
494 | { |
495 | int ret, nr_banks, nr_gpios; |
496 | struct device_node *prev, *next, *np = pdev->dev.of_node; |
497 | const struct of_device_id *of_id = |
498 | of_match_device(pxa_gpio_dt_ids, &pdev->dev); |
499 | |
500 | if (!of_id) { |
501 | dev_err(&pdev->dev, "Failed to find gpio controller\n"); |
502 | return -EFAULT; |
503 | } |
504 | gpio_type = (int)of_id->data; |
505 | |
506 | next = of_get_next_child(np, NULL); |
507 | prev = next; |
508 | if (!next) { |
509 | dev_err(&pdev->dev, "Failed to find child gpio node\n"); |
510 | ret = -EINVAL; |
511 | goto err; |
512 | } |
513 | for (nr_banks = 1; ; nr_banks++) { |
514 | next = of_get_next_child(np, prev); |
515 | if (!next) |
516 | break; |
517 | prev = next; |
518 | } |
519 | of_node_put(prev); |
520 | nr_gpios = nr_banks << 5; |
521 | pxa_last_gpio = nr_gpios - 1; |
522 | |
523 | irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); |
524 | if (irq_base < 0) { |
525 | dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); |
526 | goto err; |
527 | } |
528 | domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0, |
529 | &pxa_irq_domain_ops, NULL); |
530 | pxa_gpio_of_node = np; |
531 | return 0; |
532 | err: |
533 | iounmap(gpio_reg_base); |
534 | return ret; |
535 | } |
536 | #else |
537 | #define pxa_gpio_probe_dt(pdev) (-1) |
538 | #endif |
539 | |
540 | static int pxa_gpio_probe(struct platform_device *pdev) |
541 | { |
542 | struct pxa_gpio_chip *c; |
543 | struct resource *res; |
544 | struct clk *clk; |
545 | struct pxa_gpio_platform_data *info; |
546 | int gpio, irq, ret, use_of = 0; |
547 | int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; |
548 | |
549 | ret = pxa_gpio_probe_dt(pdev); |
550 | if (ret < 0) { |
551 | pxa_last_gpio = pxa_gpio_nums(); |
552 | #ifdef CONFIG_ARCH_PXA |
553 | if (gpio_is_pxa_type(gpio_type)) |
554 | irq_base = PXA_GPIO_TO_IRQ(0); |
555 | #endif |
556 | #ifdef CONFIG_ARCH_MMP |
557 | if (gpio_is_mmp_type(gpio_type)) |
558 | irq_base = MMP_GPIO_TO_IRQ(0); |
559 | #endif |
560 | } else { |
561 | use_of = 1; |
562 | } |
563 | |
564 | if (!pxa_last_gpio) |
565 | return -EINVAL; |
566 | |
567 | irq0 = platform_get_irq_byname(pdev, "gpio0"); |
568 | irq1 = platform_get_irq_byname(pdev, "gpio1"); |
569 | irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); |
570 | if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) |
571 | || (irq_mux <= 0)) |
572 | return -EINVAL; |
573 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
574 | if (!res) |
575 | return -EINVAL; |
576 | gpio_reg_base = ioremap(res->start, resource_size(res)); |
577 | if (!gpio_reg_base) |
578 | return -EINVAL; |
579 | |
580 | if (irq0 > 0) |
581 | gpio_offset = 2; |
582 | |
583 | clk = clk_get(&pdev->dev, NULL); |
584 | if (IS_ERR(clk)) { |
585 | dev_err(&pdev->dev, "Error %ld to get gpio clock\n", |
586 | PTR_ERR(clk)); |
587 | iounmap(gpio_reg_base); |
588 | return PTR_ERR(clk); |
589 | } |
590 | ret = clk_prepare_enable(clk); |
591 | if (ret) { |
592 | clk_put(clk); |
593 | iounmap(gpio_reg_base); |
594 | return ret; |
595 | } |
596 | |
597 | /* Initialize GPIO chips */ |
598 | info = dev_get_platdata(&pdev->dev); |
599 | pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL); |
600 | |
601 | /* clear all GPIO edge detects */ |
602 | for_each_gpio_chip(gpio, c) { |
603 | writel_relaxed(0, c->regbase + GFER_OFFSET); |
604 | writel_relaxed(0, c->regbase + GRER_OFFSET); |
605 | writel_relaxed(~0,c->regbase + GEDR_OFFSET); |
606 | /* unmask GPIO edge detect for AP side */ |
607 | if (gpio_is_mmp_type(gpio_type)) |
608 | writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); |
609 | } |
610 | |
611 | if (!use_of) { |
612 | #ifdef CONFIG_ARCH_PXA |
613 | irq = gpio_to_irq(0); |
614 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
615 | handle_edge_irq); |
616 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
617 | irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler); |
618 | |
619 | irq = gpio_to_irq(1); |
620 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
621 | handle_edge_irq); |
622 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
623 | irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler); |
624 | #endif |
625 | |
626 | for (irq = gpio_to_irq(gpio_offset); |
627 | irq <= gpio_to_irq(pxa_last_gpio); irq++) { |
628 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
629 | handle_edge_irq); |
630 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
631 | } |
632 | } |
633 | |
634 | irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler); |
635 | return 0; |
636 | } |
637 | |
638 | static struct platform_driver pxa_gpio_driver = { |
639 | .probe = pxa_gpio_probe, |
640 | .driver = { |
641 | .name = "pxa-gpio", |
642 | .of_match_table = of_match_ptr(pxa_gpio_dt_ids), |
643 | }, |
644 | }; |
645 | |
646 | static int __init pxa_gpio_init(void) |
647 | { |
648 | return platform_driver_register(&pxa_gpio_driver); |
649 | } |
650 | postcore_initcall(pxa_gpio_init); |
651 | |
652 | #ifdef CONFIG_PM |
653 | static int pxa_gpio_suspend(void) |
654 | { |
655 | struct pxa_gpio_chip *c; |
656 | int gpio; |
657 | |
658 | for_each_gpio_chip(gpio, c) { |
659 | c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); |
660 | c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
661 | c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); |
662 | c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); |
663 | |
664 | /* Clear GPIO transition detect bits */ |
665 | writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); |
666 | } |
667 | return 0; |
668 | } |
669 | |
670 | static void pxa_gpio_resume(void) |
671 | { |
672 | struct pxa_gpio_chip *c; |
673 | int gpio; |
674 | |
675 | for_each_gpio_chip(gpio, c) { |
676 | /* restore level with set/clear */ |
677 | writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET); |
678 | writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); |
679 | |
680 | writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); |
681 | writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); |
682 | writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); |
683 | } |
684 | } |
685 | #else |
686 | #define pxa_gpio_suspend NULL |
687 | #define pxa_gpio_resume NULL |
688 | #endif |
689 | |
690 | struct syscore_ops pxa_gpio_syscore_ops = { |
691 | .suspend = pxa_gpio_suspend, |
692 | .resume = pxa_gpio_resume, |
693 | }; |
694 | |
695 | static int __init pxa_gpio_sysinit(void) |
696 | { |
697 | register_syscore_ops(&pxa_gpio_syscore_ops); |
698 | return 0; |
699 | } |
700 | postcore_initcall(pxa_gpio_sysinit); |
701 |
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