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1 | /* |
2 | * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04 |
3 | * IDE driver for Linux. |
4 | * |
5 | * Copyright (c) 2000-2002 Vojtech Pavlik |
6 | * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz |
7 | * |
8 | * Based on the work of: |
9 | * Andre Hedrick |
10 | */ |
11 | |
12 | /* |
13 | * This program is free software; you can redistribute it and/or modify it |
14 | * under the terms of the GNU General Public License version 2 as published by |
15 | * the Free Software Foundation. |
16 | */ |
17 | |
18 | #include <linux/module.h> |
19 | #include <linux/kernel.h> |
20 | #include <linux/pci.h> |
21 | #include <linux/init.h> |
22 | #include <linux/ide.h> |
23 | |
24 | #define DRV_NAME "amd74xx" |
25 | |
26 | enum { |
27 | AMD_IDE_CONFIG = 0x41, |
28 | AMD_CABLE_DETECT = 0x42, |
29 | AMD_DRIVE_TIMING = 0x48, |
30 | AMD_8BIT_TIMING = 0x4e, |
31 | AMD_ADDRESS_SETUP = 0x4c, |
32 | AMD_UDMA_TIMING = 0x50, |
33 | }; |
34 | |
35 | static unsigned int amd_80w; |
36 | static unsigned int amd_clock; |
37 | |
38 | static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
39 | static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 }; |
40 | |
41 | static inline u8 amd_offset(struct pci_dev *dev) |
42 | { |
43 | return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0; |
44 | } |
45 | |
46 | /* |
47 | * amd_set_speed() writes timing values to the chipset registers |
48 | */ |
49 | |
50 | static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, |
51 | struct ide_timing *timing) |
52 | { |
53 | u8 t = 0, offset = amd_offset(dev); |
54 | |
55 | pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t); |
56 | t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); |
57 | pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t); |
58 | |
59 | pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)), |
60 | ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); |
61 | |
62 | pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn), |
63 | ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); |
64 | |
65 | switch (udma_mask) { |
66 | case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; |
67 | case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break; |
68 | case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break; |
69 | case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break; |
70 | default: return; |
71 | } |
72 | |
73 | if (timing->udma) |
74 | pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + 3 - dn, t); |
75 | } |
76 | |
77 | /* |
78 | * amd_set_drive() computes timing values and configures the chipset |
79 | * to a desired transfer mode. It also can be called by upper layers. |
80 | */ |
81 | |
82 | static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive) |
83 | { |
84 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
85 | ide_drive_t *peer = ide_get_pair_dev(drive); |
86 | struct ide_timing t, p; |
87 | int T, UT; |
88 | u8 udma_mask = hwif->ultra_mask; |
89 | const u8 speed = drive->dma_mode; |
90 | |
91 | T = 1000000000 / amd_clock; |
92 | UT = (udma_mask == ATA_UDMA2) ? T : (T / 2); |
93 | |
94 | ide_timing_compute(drive, speed, &t, T, UT); |
95 | |
96 | if (peer) { |
97 | ide_timing_compute(peer, peer->pio_mode, &p, T, UT); |
98 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); |
99 | } |
100 | |
101 | if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1; |
102 | if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15; |
103 | |
104 | amd_set_speed(dev, drive->dn, udma_mask, &t); |
105 | } |
106 | |
107 | /* |
108 | * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning. |
109 | */ |
110 | |
111 | static void amd_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
112 | { |
113 | drive->dma_mode = drive->pio_mode; |
114 | amd_set_drive(hwif, drive); |
115 | } |
116 | |
117 | static void amd7409_cable_detect(struct pci_dev *dev) |
118 | { |
119 | /* no host side cable detection */ |
120 | amd_80w = 0x03; |
121 | } |
122 | |
123 | static void amd7411_cable_detect(struct pci_dev *dev) |
124 | { |
125 | int i; |
126 | u32 u = 0; |
127 | u8 t = 0, offset = amd_offset(dev); |
128 | |
129 | pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t); |
130 | pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u); |
131 | amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0); |
132 | for (i = 24; i >= 0; i -= 8) |
133 | if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) { |
134 | printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set " |
135 | "cable bits correctly. Enabling workaround.\n", |
136 | pci_name(dev)); |
137 | amd_80w |= (1 << (1 - (i >> 4))); |
138 | } |
139 | } |
140 | |
141 | /* |
142 | * The initialization callback. Initialize drive independent registers. |
143 | */ |
144 | |
145 | static int init_chipset_amd74xx(struct pci_dev *dev) |
146 | { |
147 | u8 t = 0, offset = amd_offset(dev); |
148 | |
149 | /* |
150 | * Check 80-wire cable presence. |
151 | */ |
152 | |
153 | if (dev->vendor == PCI_VENDOR_ID_AMD && |
154 | dev->device == PCI_DEVICE_ID_AMD_COBRA_7401) |
155 | ; /* no UDMA > 2 */ |
156 | else if (dev->vendor == PCI_VENDOR_ID_AMD && |
157 | dev->device == PCI_DEVICE_ID_AMD_VIPER_7409) |
158 | amd7409_cable_detect(dev); |
159 | else |
160 | amd7411_cable_detect(dev); |
161 | |
162 | /* |
163 | * Take care of prefetch & postwrite. |
164 | */ |
165 | |
166 | pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t); |
167 | /* |
168 | * Check for broken FIFO support. |
169 | */ |
170 | if (dev->vendor == PCI_VENDOR_ID_AMD && |
171 | dev->device == PCI_DEVICE_ID_AMD_VIPER_7411) |
172 | t &= 0x0f; |
173 | else |
174 | t |= 0xf0; |
175 | pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t); |
176 | |
177 | return 0; |
178 | } |
179 | |
180 | static u8 amd_cable_detect(ide_hwif_t *hwif) |
181 | { |
182 | if ((amd_80w >> hwif->channel) & 1) |
183 | return ATA_CBL_PATA80; |
184 | else |
185 | return ATA_CBL_PATA40; |
186 | } |
187 | |
188 | static const struct ide_port_ops amd_port_ops = { |
189 | .set_pio_mode = amd_set_pio_mode, |
190 | .set_dma_mode = amd_set_drive, |
191 | .cable_detect = amd_cable_detect, |
192 | }; |
193 | |
194 | #define IDE_HFLAGS_AMD \ |
195 | (IDE_HFLAG_PIO_NO_BLACKLIST | \ |
196 | IDE_HFLAG_POST_SET_MODE | \ |
197 | IDE_HFLAG_IO_32BIT | \ |
198 | IDE_HFLAG_UNMASK_IRQS) |
199 | |
200 | #define DECLARE_AMD_DEV(swdma, udma) \ |
201 | { \ |
202 | .name = DRV_NAME, \ |
203 | .init_chipset = init_chipset_amd74xx, \ |
204 | .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \ |
205 | .port_ops = &amd_port_ops, \ |
206 | .host_flags = IDE_HFLAGS_AMD, \ |
207 | .pio_mask = ATA_PIO5, \ |
208 | .swdma_mask = swdma, \ |
209 | .mwdma_mask = ATA_MWDMA2, \ |
210 | .udma_mask = udma, \ |
211 | } |
212 | |
213 | #define DECLARE_NV_DEV(udma) \ |
214 | { \ |
215 | .name = DRV_NAME, \ |
216 | .init_chipset = init_chipset_amd74xx, \ |
217 | .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \ |
218 | .port_ops = &amd_port_ops, \ |
219 | .host_flags = IDE_HFLAGS_AMD, \ |
220 | .pio_mask = ATA_PIO5, \ |
221 | .swdma_mask = ATA_SWDMA2, \ |
222 | .mwdma_mask = ATA_MWDMA2, \ |
223 | .udma_mask = udma, \ |
224 | } |
225 | |
226 | static const struct ide_port_info amd74xx_chipsets[] = { |
227 | /* 0: AMD7401 */ DECLARE_AMD_DEV(0x00, ATA_UDMA2), |
228 | /* 1: AMD7409 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4), |
229 | /* 2: AMD7411/7441 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5), |
230 | /* 3: AMD8111 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6), |
231 | |
232 | /* 4: NFORCE */ DECLARE_NV_DEV(ATA_UDMA5), |
233 | /* 5: >= NFORCE2 */ DECLARE_NV_DEV(ATA_UDMA6), |
234 | |
235 | /* 6: AMD5536 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5), |
236 | }; |
237 | |
238 | static int amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id) |
239 | { |
240 | struct ide_port_info d; |
241 | u8 idx = id->driver_data; |
242 | |
243 | d = amd74xx_chipsets[idx]; |
244 | |
245 | /* |
246 | * Check for bad SWDMA and incorrectly wired Serenade mainboards. |
247 | */ |
248 | if (idx == 1) { |
249 | if (dev->revision <= 7) |
250 | d.swdma_mask = 0; |
251 | d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX; |
252 | } else if (idx == 3) { |
253 | if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD && |
254 | dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) |
255 | d.udma_mask = ATA_UDMA5; |
256 | } |
257 | |
258 | /* |
259 | * It seems that on some nVidia controllers using AltStatus |
260 | * register can be unreliable so default to Status register |
261 | * if the device is in Compatibility Mode. |
262 | */ |
263 | if (dev->vendor == PCI_VENDOR_ID_NVIDIA && |
264 | ide_pci_is_in_compatibility_mode(dev)) |
265 | d.host_flags |= IDE_HFLAG_BROKEN_ALTSTATUS; |
266 | |
267 | printk(KERN_INFO "%s %s: UDMA%s controller\n", |
268 | d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]); |
269 | |
270 | /* |
271 | * Determine the system bus clock. |
272 | */ |
273 | amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000; |
274 | |
275 | switch (amd_clock) { |
276 | case 33000: amd_clock = 33333; break; |
277 | case 37000: amd_clock = 37500; break; |
278 | case 41000: amd_clock = 41666; break; |
279 | } |
280 | |
281 | if (amd_clock < 20000 || amd_clock > 50000) { |
282 | printk(KERN_WARNING "%s: User given PCI clock speed impossible" |
283 | " (%d), using 33 MHz instead.\n", |
284 | d.name, amd_clock); |
285 | amd_clock = 33333; |
286 | } |
287 | |
288 | return ide_pci_init_one(dev, &d, NULL); |
289 | } |
290 | |
291 | static const struct pci_device_id amd74xx_pci_tbl[] = { |
292 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 }, |
293 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 }, |
294 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 }, |
295 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 2 }, |
296 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 3 }, |
297 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 4 }, |
298 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 5 }, |
299 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 5 }, |
300 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
301 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 5 }, |
302 | #endif |
303 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 5 }, |
304 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 5 }, |
305 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
306 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 5 }, |
307 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 5 }, |
308 | #endif |
309 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 5 }, |
310 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 5 }, |
311 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 5 }, |
312 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 5 }, |
313 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 5 }, |
314 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 5 }, |
315 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 5 }, |
316 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 5 }, |
317 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 5 }, |
318 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 6 }, |
319 | { 0, }, |
320 | }; |
321 | MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl); |
322 | |
323 | static struct pci_driver amd74xx_pci_driver = { |
324 | .name = "AMD_IDE", |
325 | .id_table = amd74xx_pci_tbl, |
326 | .probe = amd74xx_probe, |
327 | .remove = ide_pci_remove, |
328 | .suspend = ide_pci_suspend, |
329 | .resume = ide_pci_resume, |
330 | }; |
331 | |
332 | static int __init amd74xx_ide_init(void) |
333 | { |
334 | return ide_pci_register_driver(&amd74xx_pci_driver); |
335 | } |
336 | |
337 | static void __exit amd74xx_ide_exit(void) |
338 | { |
339 | pci_unregister_driver(&amd74xx_pci_driver); |
340 | } |
341 | |
342 | module_init(amd74xx_ide_init); |
343 | module_exit(amd74xx_ide_exit); |
344 | |
345 | MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz"); |
346 | MODULE_DESCRIPTION("AMD PCI IDE driver"); |
347 | MODULE_LICENSE("GPL"); |
348 |
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