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1 | /* |
2 | * Copyright (C) 2004-2005 Advanced Micro Devices, Inc. |
3 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
4 | * |
5 | * History: |
6 | * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com> |
7 | * - Reworked tuneproc, set_drive, misc mods to prep for mainline |
8 | * - Work was sponsored by CIS (M) Sdn Bhd. |
9 | * Ported to Kernel 2.6.11 on June 26, 2005 by |
10 | * Wolfgang Zuleger <wolfgang.zuleger@gmx.de> |
11 | * Alexander Kiausch <alex.kiausch@t-online.de> |
12 | * Originally developed by AMD for 2.4/2.6 |
13 | * |
14 | * Development of this chipset driver was funded |
15 | * by the nice folks at National Semiconductor/AMD. |
16 | * |
17 | * This program is free software; you can redistribute it and/or modify it |
18 | * under the terms of the GNU General Public License version 2 as published by |
19 | * the Free Software Foundation. |
20 | * |
21 | * Documentation: |
22 | * CS5535 documentation available from AMD |
23 | */ |
24 | |
25 | #include <linux/module.h> |
26 | #include <linux/pci.h> |
27 | #include <linux/ide.h> |
28 | |
29 | #define DRV_NAME "cs5535" |
30 | |
31 | #define MSR_ATAC_BASE 0x51300000 |
32 | #define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0) |
33 | #define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01) |
34 | #define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02) |
35 | #define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03) |
36 | #define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04) |
37 | #define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05) |
38 | #define ATAC_IO_BAR (MSR_ATAC_BASE+0x08) |
39 | #define ATAC_RESET (MSR_ATAC_BASE+0x10) |
40 | #define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20) |
41 | #define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21) |
42 | #define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22) |
43 | #define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23) |
44 | #define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24) |
45 | #define ATAC_BM0_CMD_PRIM 0x00 |
46 | #define ATAC_BM0_STS_PRIM 0x02 |
47 | #define ATAC_BM0_PRD 0x04 |
48 | #define CS5535_CABLE_DETECT 0x48 |
49 | |
50 | /* Format I PIO settings. We separate out cmd and data for safer timings */ |
51 | |
52 | static unsigned int cs5535_pio_cmd_timings[5] = |
53 | { 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 }; |
54 | static unsigned int cs5535_pio_dta_timings[5] = |
55 | { 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 }; |
56 | |
57 | static unsigned int cs5535_mwdma_timings[3] = |
58 | { 0x7F0FFFF3, 0x7F035352, 0x7f024241 }; |
59 | |
60 | static unsigned int cs5535_udma_timings[5] = |
61 | { 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 }; |
62 | |
63 | /* Macros to check if the register is the reset value - reset value is an |
64 | invalid timing and indicates the register has not been set previously */ |
65 | |
66 | #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 ) |
67 | #define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 ) |
68 | |
69 | /**** |
70 | * cs5535_set_speed - Configure the chipset to the new speed |
71 | * @drive: Drive to set up |
72 | * @speed: desired speed |
73 | * |
74 | * cs5535_set_speed() configures the chipset to a new speed. |
75 | */ |
76 | static void cs5535_set_speed(ide_drive_t *drive, const u8 speed) |
77 | { |
78 | u32 reg = 0, dummy; |
79 | u8 unit = drive->dn & 1; |
80 | |
81 | /* Set the PIO timings */ |
82 | if (speed < XFER_SW_DMA_0) { |
83 | ide_drive_t *pair = ide_get_pair_dev(drive); |
84 | u8 cmd, pioa; |
85 | |
86 | cmd = pioa = speed - XFER_PIO_0; |
87 | |
88 | if (pair) { |
89 | u8 piob = pair->pio_mode - XFER_PIO_0; |
90 | |
91 | if (piob < cmd) |
92 | cmd = piob; |
93 | } |
94 | |
95 | /* Write the speed of the current drive */ |
96 | reg = (cs5535_pio_cmd_timings[cmd] << 16) | |
97 | cs5535_pio_dta_timings[pioa]; |
98 | wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0); |
99 | |
100 | /* And if nessesary - change the speed of the other drive */ |
101 | rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy); |
102 | |
103 | if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) != |
104 | cs5535_pio_cmd_timings[cmd]) { |
105 | reg &= 0x0000FFFF; |
106 | reg |= cs5535_pio_cmd_timings[cmd] << 16; |
107 | wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0); |
108 | } |
109 | |
110 | /* Set bit 31 of the DMA register for PIO format 1 timings */ |
111 | rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); |
112 | wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, |
113 | reg | 0x80000000UL, 0); |
114 | } else { |
115 | rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); |
116 | |
117 | reg &= 0x80000000UL; /* Preserve the PIO format bit */ |
118 | |
119 | if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4) |
120 | reg |= cs5535_udma_timings[speed - XFER_UDMA_0]; |
121 | else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) |
122 | reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0]; |
123 | else |
124 | return; |
125 | |
126 | wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0); |
127 | } |
128 | } |
129 | |
130 | /** |
131 | * cs5535_set_dma_mode - set host controller for DMA mode |
132 | * @hwif: port |
133 | * @drive: drive |
134 | * |
135 | * Programs the chipset for DMA mode. |
136 | */ |
137 | |
138 | static void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
139 | { |
140 | cs5535_set_speed(drive, drive->dma_mode); |
141 | } |
142 | |
143 | /** |
144 | * cs5535_set_pio_mode - set host controller for PIO mode |
145 | * @hwif: port |
146 | * @drive: drive |
147 | * |
148 | * A callback from the upper layers for PIO-only tuning. |
149 | */ |
150 | |
151 | static void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
152 | { |
153 | cs5535_set_speed(drive, drive->pio_mode); |
154 | } |
155 | |
156 | static u8 cs5535_cable_detect(ide_hwif_t *hwif) |
157 | { |
158 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
159 | u8 bit; |
160 | |
161 | /* if a 80 wire cable was detected */ |
162 | pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit); |
163 | |
164 | return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
165 | } |
166 | |
167 | static const struct ide_port_ops cs5535_port_ops = { |
168 | .set_pio_mode = cs5535_set_pio_mode, |
169 | .set_dma_mode = cs5535_set_dma_mode, |
170 | .cable_detect = cs5535_cable_detect, |
171 | }; |
172 | |
173 | static const struct ide_port_info cs5535_chipset = { |
174 | .name = DRV_NAME, |
175 | .port_ops = &cs5535_port_ops, |
176 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE, |
177 | .pio_mask = ATA_PIO4, |
178 | .mwdma_mask = ATA_MWDMA2, |
179 | .udma_mask = ATA_UDMA4, |
180 | }; |
181 | |
182 | static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
183 | { |
184 | return ide_pci_init_one(dev, &cs5535_chipset, NULL); |
185 | } |
186 | |
187 | static const struct pci_device_id cs5535_pci_tbl[] = { |
188 | { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 }, |
189 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), }, |
190 | { 0, }, |
191 | }; |
192 | |
193 | MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl); |
194 | |
195 | static struct pci_driver cs5535_pci_driver = { |
196 | .name = "CS5535_IDE", |
197 | .id_table = cs5535_pci_tbl, |
198 | .probe = cs5535_init_one, |
199 | .remove = ide_pci_remove, |
200 | .suspend = ide_pci_suspend, |
201 | .resume = ide_pci_resume, |
202 | }; |
203 | |
204 | static int __init cs5535_ide_init(void) |
205 | { |
206 | return ide_pci_register_driver(&cs5535_pci_driver); |
207 | } |
208 | |
209 | static void __exit cs5535_ide_exit(void) |
210 | { |
211 | pci_unregister_driver(&cs5535_pci_driver); |
212 | } |
213 | |
214 | module_init(cs5535_ide_init); |
215 | module_exit(cs5535_ide_exit); |
216 | |
217 | MODULE_AUTHOR("AMD"); |
218 | MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE"); |
219 | MODULE_LICENSE("GPL"); |
220 |
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