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1 | /* |
2 | * linux/drivers/pinctrl/pinctrl-lantiq.h |
3 | * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License version 2 as |
7 | * publishhed by the Free Software Foundation. |
8 | * |
9 | * Copyright (C) 2012 John Crispin <blogic@openwrt.org> |
10 | */ |
11 | |
12 | #ifndef __PINCTRL_LANTIQ_H |
13 | |
14 | #include <linux/clkdev.h> |
15 | #include <linux/pinctrl/pinctrl.h> |
16 | #include <linux/pinctrl/pinconf.h> |
17 | #include <linux/pinctrl/pinmux.h> |
18 | #include <linux/pinctrl/consumer.h> |
19 | #include <linux/pinctrl/machine.h> |
20 | |
21 | #include "core.h" |
22 | |
23 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) |
24 | |
25 | #define LTQ_MAX_MUX 4 |
26 | #define MFPR_FUNC_MASK 0x3 |
27 | |
28 | #define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg)) |
29 | #define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16) |
30 | #define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff) |
31 | |
32 | enum ltq_pinconf_param { |
33 | LTQ_PINCONF_PARAM_PULL, |
34 | LTQ_PINCONF_PARAM_OPEN_DRAIN, |
35 | LTQ_PINCONF_PARAM_DRIVE_CURRENT, |
36 | LTQ_PINCONF_PARAM_SLEW_RATE, |
37 | LTQ_PINCONF_PARAM_OUTPUT, |
38 | }; |
39 | |
40 | struct ltq_cfg_param { |
41 | const char *property; |
42 | enum ltq_pinconf_param param; |
43 | }; |
44 | |
45 | struct ltq_mfp_pin { |
46 | const char *name; |
47 | const unsigned int pin; |
48 | const unsigned short func[LTQ_MAX_MUX]; |
49 | }; |
50 | |
51 | struct ltq_pin_group { |
52 | const char *name; |
53 | const unsigned mux; |
54 | const unsigned *pins; |
55 | const unsigned npins; |
56 | }; |
57 | |
58 | struct ltq_pmx_func { |
59 | const char *name; |
60 | const char * const *groups; |
61 | const unsigned num_groups; |
62 | }; |
63 | |
64 | struct ltq_pinmux_info { |
65 | struct device *dev; |
66 | struct pinctrl_dev *pctrl; |
67 | |
68 | /* we need to manage up to 5 pad controllers */ |
69 | void __iomem *membase[5]; |
70 | |
71 | /* the descriptor for the subsystem */ |
72 | struct pinctrl_desc *desc; |
73 | |
74 | /* we expose our pads to the subsystem */ |
75 | struct pinctrl_pin_desc *pads; |
76 | |
77 | /* the number of pads. this varies between socs */ |
78 | unsigned int num_pads; |
79 | |
80 | /* these are our multifunction pins */ |
81 | const struct ltq_mfp_pin *mfp; |
82 | unsigned int num_mfp; |
83 | |
84 | /* a number of multifunction pins can be grouped together */ |
85 | const struct ltq_pin_group *grps; |
86 | unsigned int num_grps; |
87 | |
88 | /* a mapping between function string and id */ |
89 | const struct ltq_pmx_func *funcs; |
90 | unsigned int num_funcs; |
91 | |
92 | /* the pinconf options that we are able to read from the DT */ |
93 | const struct ltq_cfg_param *params; |
94 | unsigned int num_params; |
95 | |
96 | /* the pad controller can have a irq mapping */ |
97 | const unsigned *exin; |
98 | unsigned int num_exin; |
99 | |
100 | /* we need 5 clocks max */ |
101 | struct clk *clk[5]; |
102 | |
103 | /* soc specific callback used to apply muxing */ |
104 | int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux); |
105 | }; |
106 | |
107 | enum ltq_pin { |
108 | GPIO0 = 0, |
109 | GPIO1, |
110 | GPIO2, |
111 | GPIO3, |
112 | GPIO4, |
113 | GPIO5, |
114 | GPIO6, |
115 | GPIO7, |
116 | GPIO8, |
117 | GPIO9, |
118 | GPIO10, /* 10 */ |
119 | GPIO11, |
120 | GPIO12, |
121 | GPIO13, |
122 | GPIO14, |
123 | GPIO15, |
124 | GPIO16, |
125 | GPIO17, |
126 | GPIO18, |
127 | GPIO19, |
128 | GPIO20, /* 20 */ |
129 | GPIO21, |
130 | GPIO22, |
131 | GPIO23, |
132 | GPIO24, |
133 | GPIO25, |
134 | GPIO26, |
135 | GPIO27, |
136 | GPIO28, |
137 | GPIO29, |
138 | GPIO30, /* 30 */ |
139 | GPIO31, |
140 | GPIO32, |
141 | GPIO33, |
142 | GPIO34, |
143 | GPIO35, |
144 | GPIO36, |
145 | GPIO37, |
146 | GPIO38, |
147 | GPIO39, |
148 | GPIO40, /* 40 */ |
149 | GPIO41, |
150 | GPIO42, |
151 | GPIO43, |
152 | GPIO44, |
153 | GPIO45, |
154 | GPIO46, |
155 | GPIO47, |
156 | GPIO48, |
157 | GPIO49, |
158 | GPIO50, /* 50 */ |
159 | GPIO51, |
160 | GPIO52, |
161 | GPIO53, |
162 | GPIO54, |
163 | GPIO55, |
164 | |
165 | GPIO64, |
166 | GPIO65, |
167 | GPIO66, |
168 | GPIO67, |
169 | GPIO68, |
170 | GPIO69, |
171 | GPIO70, |
172 | GPIO71, |
173 | GPIO72, |
174 | GPIO73, |
175 | GPIO74, |
176 | GPIO75, |
177 | GPIO76, |
178 | GPIO77, |
179 | GPIO78, |
180 | GPIO79, |
181 | GPIO80, |
182 | GPIO81, |
183 | GPIO82, |
184 | GPIO83, |
185 | GPIO84, |
186 | GPIO85, |
187 | GPIO86, |
188 | GPIO87, |
189 | GPIO88, |
190 | }; |
191 | |
192 | extern int ltq_pinctrl_register(struct platform_device *pdev, |
193 | struct ltq_pinmux_info *info); |
194 | extern int ltq_pinctrl_unregister(struct platform_device *pdev); |
195 | #endif /* __PINCTRL_PXA3XX_H */ |
196 |
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