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1 | /* |
2 | * TI OMAP1 Real Time Clock interface for Linux |
3 | * |
4 | * Copyright (C) 2003 MontaVista Software, Inc. |
5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> |
6 | * |
7 | * Copyright (C) 2006 David Brownell (new RTC framework) |
8 | * |
9 | * This program is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU General Public License |
11 | * as published by the Free Software Foundation; either version |
12 | * 2 of the License, or (at your option) any later version. |
13 | */ |
14 | |
15 | #include <linux/kernel.h> |
16 | #include <linux/init.h> |
17 | #include <linux/module.h> |
18 | #include <linux/ioport.h> |
19 | #include <linux/delay.h> |
20 | #include <linux/rtc.h> |
21 | #include <linux/bcd.h> |
22 | #include <linux/platform_device.h> |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> |
25 | #include <linux/pm_runtime.h> |
26 | |
27 | #include <asm/io.h> |
28 | |
29 | |
30 | /* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock |
31 | * with century-range alarm matching, driven by the 32kHz clock. |
32 | * |
33 | * The main user-visible ways it differs from PC RTCs are by omitting |
34 | * "don't care" alarm fields and sub-second periodic IRQs, and having |
35 | * an autoadjust mechanism to calibrate to the true oscillator rate. |
36 | * |
37 | * Board-specific wiring options include using split power mode with |
38 | * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), |
39 | * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from |
40 | * low power modes) for OMAP1 boards (OMAP-L138 has this built into |
41 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. |
42 | */ |
43 | |
44 | #define DRIVER_NAME "omap_rtc" |
45 | |
46 | #define OMAP_RTC_BASE 0xfffb4800 |
47 | |
48 | /* RTC registers */ |
49 | #define OMAP_RTC_SECONDS_REG 0x00 |
50 | #define OMAP_RTC_MINUTES_REG 0x04 |
51 | #define OMAP_RTC_HOURS_REG 0x08 |
52 | #define OMAP_RTC_DAYS_REG 0x0C |
53 | #define OMAP_RTC_MONTHS_REG 0x10 |
54 | #define OMAP_RTC_YEARS_REG 0x14 |
55 | #define OMAP_RTC_WEEKS_REG 0x18 |
56 | |
57 | #define OMAP_RTC_ALARM_SECONDS_REG 0x20 |
58 | #define OMAP_RTC_ALARM_MINUTES_REG 0x24 |
59 | #define OMAP_RTC_ALARM_HOURS_REG 0x28 |
60 | #define OMAP_RTC_ALARM_DAYS_REG 0x2c |
61 | #define OMAP_RTC_ALARM_MONTHS_REG 0x30 |
62 | #define OMAP_RTC_ALARM_YEARS_REG 0x34 |
63 | |
64 | #define OMAP_RTC_CTRL_REG 0x40 |
65 | #define OMAP_RTC_STATUS_REG 0x44 |
66 | #define OMAP_RTC_INTERRUPTS_REG 0x48 |
67 | |
68 | #define OMAP_RTC_COMP_LSB_REG 0x4c |
69 | #define OMAP_RTC_COMP_MSB_REG 0x50 |
70 | #define OMAP_RTC_OSC_REG 0x54 |
71 | |
72 | #define OMAP_RTC_KICK0_REG 0x6c |
73 | #define OMAP_RTC_KICK1_REG 0x70 |
74 | |
75 | /* OMAP_RTC_CTRL_REG bit fields: */ |
76 | #define OMAP_RTC_CTRL_SPLIT (1<<7) |
77 | #define OMAP_RTC_CTRL_DISABLE (1<<6) |
78 | #define OMAP_RTC_CTRL_SET_32_COUNTER (1<<5) |
79 | #define OMAP_RTC_CTRL_TEST (1<<4) |
80 | #define OMAP_RTC_CTRL_MODE_12_24 (1<<3) |
81 | #define OMAP_RTC_CTRL_AUTO_COMP (1<<2) |
82 | #define OMAP_RTC_CTRL_ROUND_30S (1<<1) |
83 | #define OMAP_RTC_CTRL_STOP (1<<0) |
84 | |
85 | /* OMAP_RTC_STATUS_REG bit fields: */ |
86 | #define OMAP_RTC_STATUS_POWER_UP (1<<7) |
87 | #define OMAP_RTC_STATUS_ALARM (1<<6) |
88 | #define OMAP_RTC_STATUS_1D_EVENT (1<<5) |
89 | #define OMAP_RTC_STATUS_1H_EVENT (1<<4) |
90 | #define OMAP_RTC_STATUS_1M_EVENT (1<<3) |
91 | #define OMAP_RTC_STATUS_1S_EVENT (1<<2) |
92 | #define OMAP_RTC_STATUS_RUN (1<<1) |
93 | #define OMAP_RTC_STATUS_BUSY (1<<0) |
94 | |
95 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ |
96 | #define OMAP_RTC_INTERRUPTS_IT_ALARM (1<<3) |
97 | #define OMAP_RTC_INTERRUPTS_IT_TIMER (1<<2) |
98 | |
99 | /* OMAP_RTC_KICKER values */ |
100 | #define KICK0_VALUE 0x83e70b13 |
101 | #define KICK1_VALUE 0x95a4f1e0 |
102 | |
103 | #define OMAP_RTC_HAS_KICKER 0x1 |
104 | |
105 | static void __iomem *rtc_base; |
106 | |
107 | #define rtc_read(addr) readb(rtc_base + (addr)) |
108 | #define rtc_write(val, addr) writeb(val, rtc_base + (addr)) |
109 | |
110 | #define rtc_writel(val, addr) writel(val, rtc_base + (addr)) |
111 | |
112 | |
113 | /* we rely on the rtc framework to handle locking (rtc->ops_lock), |
114 | * so the only other requirement is that register accesses which |
115 | * require BUSY to be clear are made with IRQs locally disabled |
116 | */ |
117 | static void rtc_wait_not_busy(void) |
118 | { |
119 | int count = 0; |
120 | u8 status; |
121 | |
122 | /* BUSY may stay active for 1/32768 second (~30 usec) */ |
123 | for (count = 0; count < 50; count++) { |
124 | status = rtc_read(OMAP_RTC_STATUS_REG); |
125 | if ((status & (u8)OMAP_RTC_STATUS_BUSY) == 0) |
126 | break; |
127 | udelay(1); |
128 | } |
129 | /* now we have ~15 usec to read/write various registers */ |
130 | } |
131 | |
132 | static irqreturn_t rtc_irq(int irq, void *rtc) |
133 | { |
134 | unsigned long events = 0; |
135 | u8 irq_data; |
136 | |
137 | irq_data = rtc_read(OMAP_RTC_STATUS_REG); |
138 | |
139 | /* alarm irq? */ |
140 | if (irq_data & OMAP_RTC_STATUS_ALARM) { |
141 | rtc_write(OMAP_RTC_STATUS_ALARM, OMAP_RTC_STATUS_REG); |
142 | events |= RTC_IRQF | RTC_AF; |
143 | } |
144 | |
145 | /* 1/sec periodic/update irq? */ |
146 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) |
147 | events |= RTC_IRQF | RTC_UF; |
148 | |
149 | rtc_update_irq(rtc, 1, events); |
150 | |
151 | return IRQ_HANDLED; |
152 | } |
153 | |
154 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
155 | { |
156 | u8 reg; |
157 | |
158 | local_irq_disable(); |
159 | rtc_wait_not_busy(); |
160 | reg = rtc_read(OMAP_RTC_INTERRUPTS_REG); |
161 | if (enabled) |
162 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
163 | else |
164 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
165 | rtc_wait_not_busy(); |
166 | rtc_write(reg, OMAP_RTC_INTERRUPTS_REG); |
167 | local_irq_enable(); |
168 | |
169 | return 0; |
170 | } |
171 | |
172 | /* this hardware doesn't support "don't care" alarm fields */ |
173 | static int tm2bcd(struct rtc_time *tm) |
174 | { |
175 | if (rtc_valid_tm(tm) != 0) |
176 | return -EINVAL; |
177 | |
178 | tm->tm_sec = bin2bcd(tm->tm_sec); |
179 | tm->tm_min = bin2bcd(tm->tm_min); |
180 | tm->tm_hour = bin2bcd(tm->tm_hour); |
181 | tm->tm_mday = bin2bcd(tm->tm_mday); |
182 | |
183 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); |
184 | |
185 | /* epoch == 1900 */ |
186 | if (tm->tm_year < 100 || tm->tm_year > 199) |
187 | return -EINVAL; |
188 | tm->tm_year = bin2bcd(tm->tm_year - 100); |
189 | |
190 | return 0; |
191 | } |
192 | |
193 | static void bcd2tm(struct rtc_time *tm) |
194 | { |
195 | tm->tm_sec = bcd2bin(tm->tm_sec); |
196 | tm->tm_min = bcd2bin(tm->tm_min); |
197 | tm->tm_hour = bcd2bin(tm->tm_hour); |
198 | tm->tm_mday = bcd2bin(tm->tm_mday); |
199 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; |
200 | /* epoch == 1900 */ |
201 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
202 | } |
203 | |
204 | |
205 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) |
206 | { |
207 | /* we don't report wday/yday/isdst ... */ |
208 | local_irq_disable(); |
209 | rtc_wait_not_busy(); |
210 | |
211 | tm->tm_sec = rtc_read(OMAP_RTC_SECONDS_REG); |
212 | tm->tm_min = rtc_read(OMAP_RTC_MINUTES_REG); |
213 | tm->tm_hour = rtc_read(OMAP_RTC_HOURS_REG); |
214 | tm->tm_mday = rtc_read(OMAP_RTC_DAYS_REG); |
215 | tm->tm_mon = rtc_read(OMAP_RTC_MONTHS_REG); |
216 | tm->tm_year = rtc_read(OMAP_RTC_YEARS_REG); |
217 | |
218 | local_irq_enable(); |
219 | |
220 | bcd2tm(tm); |
221 | return 0; |
222 | } |
223 | |
224 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) |
225 | { |
226 | if (tm2bcd(tm) < 0) |
227 | return -EINVAL; |
228 | local_irq_disable(); |
229 | rtc_wait_not_busy(); |
230 | |
231 | rtc_write(tm->tm_year, OMAP_RTC_YEARS_REG); |
232 | rtc_write(tm->tm_mon, OMAP_RTC_MONTHS_REG); |
233 | rtc_write(tm->tm_mday, OMAP_RTC_DAYS_REG); |
234 | rtc_write(tm->tm_hour, OMAP_RTC_HOURS_REG); |
235 | rtc_write(tm->tm_min, OMAP_RTC_MINUTES_REG); |
236 | rtc_write(tm->tm_sec, OMAP_RTC_SECONDS_REG); |
237 | |
238 | local_irq_enable(); |
239 | |
240 | return 0; |
241 | } |
242 | |
243 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) |
244 | { |
245 | local_irq_disable(); |
246 | rtc_wait_not_busy(); |
247 | |
248 | alm->time.tm_sec = rtc_read(OMAP_RTC_ALARM_SECONDS_REG); |
249 | alm->time.tm_min = rtc_read(OMAP_RTC_ALARM_MINUTES_REG); |
250 | alm->time.tm_hour = rtc_read(OMAP_RTC_ALARM_HOURS_REG); |
251 | alm->time.tm_mday = rtc_read(OMAP_RTC_ALARM_DAYS_REG); |
252 | alm->time.tm_mon = rtc_read(OMAP_RTC_ALARM_MONTHS_REG); |
253 | alm->time.tm_year = rtc_read(OMAP_RTC_ALARM_YEARS_REG); |
254 | |
255 | local_irq_enable(); |
256 | |
257 | bcd2tm(&alm->time); |
258 | alm->enabled = !!(rtc_read(OMAP_RTC_INTERRUPTS_REG) |
259 | & OMAP_RTC_INTERRUPTS_IT_ALARM); |
260 | |
261 | return 0; |
262 | } |
263 | |
264 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) |
265 | { |
266 | u8 reg; |
267 | |
268 | if (tm2bcd(&alm->time) < 0) |
269 | return -EINVAL; |
270 | |
271 | local_irq_disable(); |
272 | rtc_wait_not_busy(); |
273 | |
274 | rtc_write(alm->time.tm_year, OMAP_RTC_ALARM_YEARS_REG); |
275 | rtc_write(alm->time.tm_mon, OMAP_RTC_ALARM_MONTHS_REG); |
276 | rtc_write(alm->time.tm_mday, OMAP_RTC_ALARM_DAYS_REG); |
277 | rtc_write(alm->time.tm_hour, OMAP_RTC_ALARM_HOURS_REG); |
278 | rtc_write(alm->time.tm_min, OMAP_RTC_ALARM_MINUTES_REG); |
279 | rtc_write(alm->time.tm_sec, OMAP_RTC_ALARM_SECONDS_REG); |
280 | |
281 | reg = rtc_read(OMAP_RTC_INTERRUPTS_REG); |
282 | if (alm->enabled) |
283 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
284 | else |
285 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
286 | rtc_write(reg, OMAP_RTC_INTERRUPTS_REG); |
287 | |
288 | local_irq_enable(); |
289 | |
290 | return 0; |
291 | } |
292 | |
293 | static struct rtc_class_ops omap_rtc_ops = { |
294 | .read_time = omap_rtc_read_time, |
295 | .set_time = omap_rtc_set_time, |
296 | .read_alarm = omap_rtc_read_alarm, |
297 | .set_alarm = omap_rtc_set_alarm, |
298 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, |
299 | }; |
300 | |
301 | static int omap_rtc_alarm; |
302 | static int omap_rtc_timer; |
303 | |
304 | #define OMAP_RTC_DATA_DA830_IDX 1 |
305 | |
306 | static struct platform_device_id omap_rtc_devtype[] = { |
307 | { |
308 | .name = DRIVER_NAME, |
309 | }, { |
310 | .name = "da830-rtc", |
311 | .driver_data = OMAP_RTC_HAS_KICKER, |
312 | }, |
313 | {}, |
314 | }; |
315 | MODULE_DEVICE_TABLE(platform, omap_rtc_devtype); |
316 | |
317 | static const struct of_device_id omap_rtc_of_match[] = { |
318 | { .compatible = "ti,da830-rtc", |
319 | .data = &omap_rtc_devtype[OMAP_RTC_DATA_DA830_IDX], |
320 | }, |
321 | {}, |
322 | }; |
323 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); |
324 | |
325 | static int __init omap_rtc_probe(struct platform_device *pdev) |
326 | { |
327 | struct resource *res, *mem; |
328 | struct rtc_device *rtc; |
329 | u8 reg, new_ctrl; |
330 | const struct platform_device_id *id_entry; |
331 | const struct of_device_id *of_id; |
332 | |
333 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); |
334 | if (of_id) |
335 | pdev->id_entry = of_id->data; |
336 | |
337 | omap_rtc_timer = platform_get_irq(pdev, 0); |
338 | if (omap_rtc_timer <= 0) { |
339 | pr_debug("%s: no update irq?\n", pdev->name); |
340 | return -ENOENT; |
341 | } |
342 | |
343 | omap_rtc_alarm = platform_get_irq(pdev, 1); |
344 | if (omap_rtc_alarm <= 0) { |
345 | pr_debug("%s: no alarm irq?\n", pdev->name); |
346 | return -ENOENT; |
347 | } |
348 | |
349 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
350 | if (!res) { |
351 | pr_debug("%s: RTC resource data missing\n", pdev->name); |
352 | return -ENOENT; |
353 | } |
354 | |
355 | mem = request_mem_region(res->start, resource_size(res), pdev->name); |
356 | if (!mem) { |
357 | pr_debug("%s: RTC registers at %08x are not free\n", |
358 | pdev->name, res->start); |
359 | return -EBUSY; |
360 | } |
361 | |
362 | rtc_base = ioremap(res->start, resource_size(res)); |
363 | if (!rtc_base) { |
364 | pr_debug("%s: RTC registers can't be mapped\n", pdev->name); |
365 | goto fail; |
366 | } |
367 | |
368 | /* Enable the clock/module so that we can access the registers */ |
369 | pm_runtime_enable(&pdev->dev); |
370 | pm_runtime_get_sync(&pdev->dev); |
371 | |
372 | id_entry = platform_get_device_id(pdev); |
373 | if (id_entry && (id_entry->driver_data & OMAP_RTC_HAS_KICKER)) { |
374 | rtc_writel(KICK0_VALUE, OMAP_RTC_KICK0_REG); |
375 | rtc_writel(KICK1_VALUE, OMAP_RTC_KICK1_REG); |
376 | } |
377 | |
378 | rtc = rtc_device_register(pdev->name, &pdev->dev, |
379 | &omap_rtc_ops, THIS_MODULE); |
380 | if (IS_ERR(rtc)) { |
381 | pr_debug("%s: can't register RTC device, err %ld\n", |
382 | pdev->name, PTR_ERR(rtc)); |
383 | goto fail0; |
384 | } |
385 | platform_set_drvdata(pdev, rtc); |
386 | dev_set_drvdata(&rtc->dev, mem); |
387 | |
388 | /* clear pending irqs, and set 1/second periodic, |
389 | * which we'll use instead of update irqs |
390 | */ |
391 | rtc_write(0, OMAP_RTC_INTERRUPTS_REG); |
392 | |
393 | /* clear old status */ |
394 | reg = rtc_read(OMAP_RTC_STATUS_REG); |
395 | if (reg & (u8) OMAP_RTC_STATUS_POWER_UP) { |
396 | pr_info("%s: RTC power up reset detected\n", |
397 | pdev->name); |
398 | rtc_write(OMAP_RTC_STATUS_POWER_UP, OMAP_RTC_STATUS_REG); |
399 | } |
400 | if (reg & (u8) OMAP_RTC_STATUS_ALARM) |
401 | rtc_write(OMAP_RTC_STATUS_ALARM, OMAP_RTC_STATUS_REG); |
402 | |
403 | /* handle periodic and alarm irqs */ |
404 | if (request_irq(omap_rtc_timer, rtc_irq, 0, |
405 | dev_name(&rtc->dev), rtc)) { |
406 | pr_debug("%s: RTC timer interrupt IRQ%d already claimed\n", |
407 | pdev->name, omap_rtc_timer); |
408 | goto fail1; |
409 | } |
410 | if ((omap_rtc_timer != omap_rtc_alarm) && |
411 | (request_irq(omap_rtc_alarm, rtc_irq, 0, |
412 | dev_name(&rtc->dev), rtc))) { |
413 | pr_debug("%s: RTC alarm interrupt IRQ%d already claimed\n", |
414 | pdev->name, omap_rtc_alarm); |
415 | goto fail2; |
416 | } |
417 | |
418 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ |
419 | reg = rtc_read(OMAP_RTC_CTRL_REG); |
420 | if (reg & (u8) OMAP_RTC_CTRL_STOP) |
421 | pr_info("%s: already running\n", pdev->name); |
422 | |
423 | /* force to 24 hour mode */ |
424 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT|OMAP_RTC_CTRL_AUTO_COMP); |
425 | new_ctrl |= OMAP_RTC_CTRL_STOP; |
426 | |
427 | /* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: |
428 | * |
429 | * - Device wake-up capability setting should come through chip |
430 | * init logic. OMAP1 boards should initialize the "wakeup capable" |
431 | * flag in the platform device if the board is wired right for |
432 | * being woken up by RTC alarm. For OMAP-L138, this capability |
433 | * is built into the SoC by the "Deep Sleep" capability. |
434 | * |
435 | * - Boards wired so RTC_ON_nOFF is used as the reset signal, |
436 | * rather than nPWRON_RESET, should forcibly enable split |
437 | * power mode. (Some chip errata report that RTC_CTRL_SPLIT |
438 | * is write-only, and always reads as zero...) |
439 | */ |
440 | |
441 | if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT) |
442 | pr_info("%s: split power mode\n", pdev->name); |
443 | |
444 | if (reg != new_ctrl) |
445 | rtc_write(new_ctrl, OMAP_RTC_CTRL_REG); |
446 | |
447 | return 0; |
448 | |
449 | fail2: |
450 | free_irq(omap_rtc_timer, rtc); |
451 | fail1: |
452 | rtc_device_unregister(rtc); |
453 | fail0: |
454 | if (id_entry && (id_entry->driver_data & OMAP_RTC_HAS_KICKER)) |
455 | rtc_writel(0, OMAP_RTC_KICK0_REG); |
456 | pm_runtime_put_sync(&pdev->dev); |
457 | pm_runtime_disable(&pdev->dev); |
458 | iounmap(rtc_base); |
459 | fail: |
460 | release_mem_region(mem->start, resource_size(mem)); |
461 | return -EIO; |
462 | } |
463 | |
464 | static int __exit omap_rtc_remove(struct platform_device *pdev) |
465 | { |
466 | struct rtc_device *rtc = platform_get_drvdata(pdev); |
467 | struct resource *mem = dev_get_drvdata(&rtc->dev); |
468 | const struct platform_device_id *id_entry = |
469 | platform_get_device_id(pdev); |
470 | |
471 | device_init_wakeup(&pdev->dev, 0); |
472 | |
473 | /* leave rtc running, but disable irqs */ |
474 | rtc_write(0, OMAP_RTC_INTERRUPTS_REG); |
475 | |
476 | free_irq(omap_rtc_timer, rtc); |
477 | |
478 | if (omap_rtc_timer != omap_rtc_alarm) |
479 | free_irq(omap_rtc_alarm, rtc); |
480 | |
481 | rtc_device_unregister(rtc); |
482 | if (id_entry && (id_entry->driver_data & OMAP_RTC_HAS_KICKER)) |
483 | rtc_writel(0, OMAP_RTC_KICK0_REG); |
484 | |
485 | /* Disable the clock/module */ |
486 | pm_runtime_put_sync(&pdev->dev); |
487 | pm_runtime_disable(&pdev->dev); |
488 | |
489 | iounmap(rtc_base); |
490 | release_mem_region(mem->start, resource_size(mem)); |
491 | return 0; |
492 | } |
493 | |
494 | #ifdef CONFIG_PM |
495 | |
496 | static u8 irqstat; |
497 | |
498 | static int omap_rtc_suspend(struct platform_device *pdev, pm_message_t state) |
499 | { |
500 | irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG); |
501 | |
502 | /* FIXME the RTC alarm is not currently acting as a wakeup event |
503 | * source, and in fact this enable() call is just saving a flag |
504 | * that's never used... |
505 | */ |
506 | if (device_may_wakeup(&pdev->dev)) |
507 | enable_irq_wake(omap_rtc_alarm); |
508 | else |
509 | rtc_write(0, OMAP_RTC_INTERRUPTS_REG); |
510 | |
511 | /* Disable the clock/module */ |
512 | pm_runtime_put_sync(&pdev->dev); |
513 | |
514 | return 0; |
515 | } |
516 | |
517 | static int omap_rtc_resume(struct platform_device *pdev) |
518 | { |
519 | /* Enable the clock/module so that we can access the registers */ |
520 | pm_runtime_get_sync(&pdev->dev); |
521 | |
522 | if (device_may_wakeup(&pdev->dev)) |
523 | disable_irq_wake(omap_rtc_alarm); |
524 | else |
525 | rtc_write(irqstat, OMAP_RTC_INTERRUPTS_REG); |
526 | return 0; |
527 | } |
528 | |
529 | #else |
530 | #define omap_rtc_suspend NULL |
531 | #define omap_rtc_resume NULL |
532 | #endif |
533 | |
534 | static void omap_rtc_shutdown(struct platform_device *pdev) |
535 | { |
536 | rtc_write(0, OMAP_RTC_INTERRUPTS_REG); |
537 | } |
538 | |
539 | MODULE_ALIAS("platform:omap_rtc"); |
540 | static struct platform_driver omap_rtc_driver = { |
541 | .remove = __exit_p(omap_rtc_remove), |
542 | .suspend = omap_rtc_suspend, |
543 | .resume = omap_rtc_resume, |
544 | .shutdown = omap_rtc_shutdown, |
545 | .driver = { |
546 | .name = DRIVER_NAME, |
547 | .owner = THIS_MODULE, |
548 | .of_match_table = of_match_ptr(omap_rtc_of_match), |
549 | }, |
550 | .id_table = omap_rtc_devtype, |
551 | }; |
552 | |
553 | static int __init rtc_init(void) |
554 | { |
555 | return platform_driver_probe(&omap_rtc_driver, omap_rtc_probe); |
556 | } |
557 | module_init(rtc_init); |
558 | |
559 | static void __exit rtc_exit(void) |
560 | { |
561 | platform_driver_unregister(&omap_rtc_driver); |
562 | } |
563 | module_exit(rtc_exit); |
564 | |
565 | MODULE_AUTHOR("George G. Davis (and others)"); |
566 | MODULE_LICENSE("GPL"); |
567 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
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jz-3.3
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jz-3.6-rc2-pwm
jz-3.9
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jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9