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1 | /* |
2 | * An RTC driver for the NVIDIA Tegra 200 series internal RTC. |
3 | * |
4 | * Copyright (c) 2010, NVIDIA Corporation. |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or |
9 | * (at your option) any later version. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
14 | * more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License along |
17 | * with this program; if not, write to the Free Software Foundation, Inc., |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
19 | */ |
20 | #include <linux/kernel.h> |
21 | #include <linux/init.h> |
22 | #include <linux/module.h> |
23 | #include <linux/slab.h> |
24 | #include <linux/irq.h> |
25 | #include <linux/io.h> |
26 | #include <linux/delay.h> |
27 | #include <linux/rtc.h> |
28 | #include <linux/platform_device.h> |
29 | |
30 | /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */ |
31 | #define TEGRA_RTC_REG_BUSY 0x004 |
32 | #define TEGRA_RTC_REG_SECONDS 0x008 |
33 | /* when msec is read, the seconds are buffered into shadow seconds. */ |
34 | #define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c |
35 | #define TEGRA_RTC_REG_MILLI_SECONDS 0x010 |
36 | #define TEGRA_RTC_REG_SECONDS_ALARM0 0x014 |
37 | #define TEGRA_RTC_REG_SECONDS_ALARM1 0x018 |
38 | #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c |
39 | #define TEGRA_RTC_REG_INTR_MASK 0x028 |
40 | /* write 1 bits to clear status bits */ |
41 | #define TEGRA_RTC_REG_INTR_STATUS 0x02c |
42 | |
43 | /* bits in INTR_MASK */ |
44 | #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4) |
45 | #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3) |
46 | #define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2) |
47 | #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1) |
48 | #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0) |
49 | |
50 | /* bits in INTR_STATUS */ |
51 | #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4) |
52 | #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3) |
53 | #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2) |
54 | #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1) |
55 | #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0) |
56 | |
57 | struct tegra_rtc_info { |
58 | struct platform_device *pdev; |
59 | struct rtc_device *rtc_dev; |
60 | void __iomem *rtc_base; /* NULL if not initialized. */ |
61 | int tegra_rtc_irq; /* alarm and periodic irq */ |
62 | spinlock_t tegra_rtc_lock; |
63 | }; |
64 | |
65 | /* RTC hardware is busy when it is updating its values over AHB once |
66 | * every eight 32kHz clocks (~250uS). |
67 | * outside of these updates the CPU is free to write. |
68 | * CPU is always free to read. |
69 | */ |
70 | static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info) |
71 | { |
72 | return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1; |
73 | } |
74 | |
75 | /* Wait for hardware to be ready for writing. |
76 | * This function tries to maximize the amount of time before the next update. |
77 | * It does this by waiting for the RTC to become busy with its periodic update, |
78 | * then returning once the RTC first becomes not busy. |
79 | * This periodic update (where the seconds and milliseconds are copied to the |
80 | * AHB side) occurs every eight 32kHz clocks (~250uS). |
81 | * The behavior of this function allows us to make some assumptions without |
82 | * introducing a race, because 250uS is plenty of time to read/write a value. |
83 | */ |
84 | static int tegra_rtc_wait_while_busy(struct device *dev) |
85 | { |
86 | struct tegra_rtc_info *info = dev_get_drvdata(dev); |
87 | |
88 | int retries = 500; /* ~490 us is the worst case, ~250 us is best. */ |
89 | |
90 | /* first wait for the RTC to become busy. this is when it |
91 | * posts its updated seconds+msec registers to AHB side. */ |
92 | while (tegra_rtc_check_busy(info)) { |
93 | if (!retries--) |
94 | goto retry_failed; |
95 | udelay(1); |
96 | } |
97 | |
98 | /* now we have about 250 us to manipulate registers */ |
99 | return 0; |
100 | |
101 | retry_failed: |
102 | dev_err(dev, "write failed:retry count exceeded.\n"); |
103 | return -ETIMEDOUT; |
104 | } |
105 | |
106 | static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm) |
107 | { |
108 | struct tegra_rtc_info *info = dev_get_drvdata(dev); |
109 | unsigned long sec, msec; |
110 | unsigned long sl_irq_flags; |
111 | |
112 | /* RTC hardware copies seconds to shadow seconds when a read |
113 | * of milliseconds occurs. use a lock to keep other threads out. */ |
114 | spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); |
115 | |
116 | msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS); |
117 | sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS); |
118 | |
119 | spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); |
120 | |
121 | rtc_time_to_tm(sec, tm); |
122 | |
123 | dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n", |
124 | sec, |
125 | tm->tm_mon + 1, |
126 | tm->tm_mday, |
127 | tm->tm_year + 1900, |
128 | tm->tm_hour, |
129 | tm->tm_min, |
130 | tm->tm_sec |
131 | ); |
132 | |
133 | return 0; |
134 | } |
135 | |
136 | static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm) |
137 | { |
138 | struct tegra_rtc_info *info = dev_get_drvdata(dev); |
139 | unsigned long sec; |
140 | int ret; |
141 | |
142 | /* convert tm to seconds. */ |
143 | ret = rtc_valid_tm(tm); |
144 | if (ret) |
145 | return ret; |
146 | |
147 | rtc_tm_to_time(tm, &sec); |
148 | |
149 | dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n", |
150 | sec, |
151 | tm->tm_mon+1, |
152 | tm->tm_mday, |
153 | tm->tm_year+1900, |
154 | tm->tm_hour, |
155 | tm->tm_min, |
156 | tm->tm_sec |
157 | ); |
158 | |
159 | /* seconds only written if wait succeeded. */ |
160 | ret = tegra_rtc_wait_while_busy(dev); |
161 | if (!ret) |
162 | writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS); |
163 | |
164 | dev_vdbg(dev, "time read back as %d\n", |
165 | readl(info->rtc_base + TEGRA_RTC_REG_SECONDS)); |
166 | |
167 | return ret; |
168 | } |
169 | |
170 | static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
171 | { |
172 | struct tegra_rtc_info *info = dev_get_drvdata(dev); |
173 | unsigned long sec; |
174 | unsigned tmp; |
175 | |
176 | sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); |
177 | |
178 | if (sec == 0) { |
179 | /* alarm is disabled. */ |
180 | alarm->enabled = 0; |
181 | alarm->time.tm_mon = -1; |
182 | alarm->time.tm_mday = -1; |
183 | alarm->time.tm_year = -1; |
184 | alarm->time.tm_hour = -1; |
185 | alarm->time.tm_min = -1; |
186 | alarm->time.tm_sec = -1; |
187 | } else { |
188 | /* alarm is enabled. */ |
189 | alarm->enabled = 1; |
190 | rtc_time_to_tm(sec, &alarm->time); |
191 | } |
192 | |
193 | tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); |
194 | alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0; |
195 | |
196 | return 0; |
197 | } |
198 | |
199 | static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
200 | { |
201 | struct tegra_rtc_info *info = dev_get_drvdata(dev); |
202 | unsigned status; |
203 | unsigned long sl_irq_flags; |
204 | |
205 | tegra_rtc_wait_while_busy(dev); |
206 | spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); |
207 | |
208 | /* read the original value, and OR in the flag. */ |
209 | status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK); |
210 | if (enabled) |
211 | status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */ |
212 | else |
213 | status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */ |
214 | |
215 | writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); |
216 | |
217 | spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); |
218 | |
219 | return 0; |
220 | } |
221 | |
222 | static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
223 | { |
224 | struct tegra_rtc_info *info = dev_get_drvdata(dev); |
225 | unsigned long sec; |
226 | |
227 | if (alarm->enabled) |
228 | rtc_tm_to_time(&alarm->time, &sec); |
229 | else |
230 | sec = 0; |
231 | |
232 | tegra_rtc_wait_while_busy(dev); |
233 | writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); |
234 | dev_vdbg(dev, "alarm read back as %d\n", |
235 | readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); |
236 | |
237 | /* if successfully written and alarm is enabled ... */ |
238 | if (sec) { |
239 | tegra_rtc_alarm_irq_enable(dev, 1); |
240 | |
241 | dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n", |
242 | sec, |
243 | alarm->time.tm_mon+1, |
244 | alarm->time.tm_mday, |
245 | alarm->time.tm_year+1900, |
246 | alarm->time.tm_hour, |
247 | alarm->time.tm_min, |
248 | alarm->time.tm_sec); |
249 | } else { |
250 | /* disable alarm if 0 or write error. */ |
251 | dev_vdbg(dev, "alarm disabled\n"); |
252 | tegra_rtc_alarm_irq_enable(dev, 0); |
253 | } |
254 | |
255 | return 0; |
256 | } |
257 | |
258 | static int tegra_rtc_proc(struct device *dev, struct seq_file *seq) |
259 | { |
260 | if (!dev || !dev->driver) |
261 | return 0; |
262 | |
263 | return seq_printf(seq, "name\t\t: %s\n", dev_name(dev)); |
264 | } |
265 | |
266 | static irqreturn_t tegra_rtc_irq_handler(int irq, void *data) |
267 | { |
268 | struct device *dev = data; |
269 | struct tegra_rtc_info *info = dev_get_drvdata(dev); |
270 | unsigned long events = 0; |
271 | unsigned status; |
272 | unsigned long sl_irq_flags; |
273 | |
274 | status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); |
275 | if (status) { |
276 | /* clear the interrupt masks and status on any irq. */ |
277 | tegra_rtc_wait_while_busy(dev); |
278 | spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); |
279 | writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); |
280 | writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); |
281 | spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); |
282 | } |
283 | |
284 | /* check if Alarm */ |
285 | if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)) |
286 | events |= RTC_IRQF | RTC_AF; |
287 | |
288 | /* check if Periodic */ |
289 | if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)) |
290 | events |= RTC_IRQF | RTC_PF; |
291 | |
292 | rtc_update_irq(info->rtc_dev, 1, events); |
293 | |
294 | return IRQ_HANDLED; |
295 | } |
296 | |
297 | static struct rtc_class_ops tegra_rtc_ops = { |
298 | .read_time = tegra_rtc_read_time, |
299 | .set_time = tegra_rtc_set_time, |
300 | .read_alarm = tegra_rtc_read_alarm, |
301 | .set_alarm = tegra_rtc_set_alarm, |
302 | .proc = tegra_rtc_proc, |
303 | .alarm_irq_enable = tegra_rtc_alarm_irq_enable, |
304 | }; |
305 | |
306 | static const struct of_device_id tegra_rtc_dt_match[] = { |
307 | { .compatible = "nvidia,tegra20-rtc", }, |
308 | {} |
309 | }; |
310 | MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match); |
311 | |
312 | static int tegra_rtc_probe(struct platform_device *pdev) |
313 | { |
314 | struct tegra_rtc_info *info; |
315 | struct resource *res; |
316 | int ret; |
317 | |
318 | info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info), |
319 | GFP_KERNEL); |
320 | if (!info) |
321 | return -ENOMEM; |
322 | |
323 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
324 | if (!res) { |
325 | dev_err(&pdev->dev, |
326 | "Unable to allocate resources for device.\n"); |
327 | return -EBUSY; |
328 | } |
329 | |
330 | info->rtc_base = devm_ioremap_resource(&pdev->dev, res); |
331 | if (IS_ERR(info->rtc_base)) |
332 | return PTR_ERR(info->rtc_base); |
333 | |
334 | info->tegra_rtc_irq = platform_get_irq(pdev, 0); |
335 | if (info->tegra_rtc_irq <= 0) |
336 | return -EBUSY; |
337 | |
338 | /* set context info. */ |
339 | info->pdev = pdev; |
340 | spin_lock_init(&info->tegra_rtc_lock); |
341 | |
342 | platform_set_drvdata(pdev, info); |
343 | |
344 | /* clear out the hardware. */ |
345 | writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); |
346 | writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); |
347 | writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); |
348 | |
349 | device_init_wakeup(&pdev->dev, 1); |
350 | |
351 | info->rtc_dev = rtc_device_register( |
352 | pdev->name, &pdev->dev, &tegra_rtc_ops, THIS_MODULE); |
353 | if (IS_ERR(info->rtc_dev)) { |
354 | ret = PTR_ERR(info->rtc_dev); |
355 | info->rtc_dev = NULL; |
356 | dev_err(&pdev->dev, |
357 | "Unable to register device (err=%d).\n", |
358 | ret); |
359 | return ret; |
360 | } |
361 | |
362 | ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq, |
363 | tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH, |
364 | "rtc alarm", &pdev->dev); |
365 | if (ret) { |
366 | dev_err(&pdev->dev, |
367 | "Unable to request interrupt for device (err=%d).\n", |
368 | ret); |
369 | goto err_dev_unreg; |
370 | } |
371 | |
372 | dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n"); |
373 | |
374 | return 0; |
375 | |
376 | err_dev_unreg: |
377 | rtc_device_unregister(info->rtc_dev); |
378 | |
379 | return ret; |
380 | } |
381 | |
382 | static int tegra_rtc_remove(struct platform_device *pdev) |
383 | { |
384 | struct tegra_rtc_info *info = platform_get_drvdata(pdev); |
385 | |
386 | rtc_device_unregister(info->rtc_dev); |
387 | |
388 | platform_set_drvdata(pdev, NULL); |
389 | |
390 | return 0; |
391 | } |
392 | |
393 | #ifdef CONFIG_PM |
394 | static int tegra_rtc_suspend(struct platform_device *pdev, pm_message_t state) |
395 | { |
396 | struct device *dev = &pdev->dev; |
397 | struct tegra_rtc_info *info = platform_get_drvdata(pdev); |
398 | |
399 | tegra_rtc_wait_while_busy(dev); |
400 | |
401 | /* only use ALARM0 as a wake source. */ |
402 | writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); |
403 | writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0, |
404 | info->rtc_base + TEGRA_RTC_REG_INTR_MASK); |
405 | |
406 | dev_vdbg(dev, "alarm sec = %d\n", |
407 | readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); |
408 | |
409 | dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n", |
410 | device_may_wakeup(dev), info->tegra_rtc_irq); |
411 | |
412 | /* leave the alarms on as a wake source. */ |
413 | if (device_may_wakeup(dev)) |
414 | enable_irq_wake(info->tegra_rtc_irq); |
415 | |
416 | return 0; |
417 | } |
418 | |
419 | static int tegra_rtc_resume(struct platform_device *pdev) |
420 | { |
421 | struct device *dev = &pdev->dev; |
422 | struct tegra_rtc_info *info = platform_get_drvdata(pdev); |
423 | |
424 | dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n", |
425 | device_may_wakeup(dev)); |
426 | /* alarms were left on as a wake source, turn them off. */ |
427 | if (device_may_wakeup(dev)) |
428 | disable_irq_wake(info->tegra_rtc_irq); |
429 | |
430 | return 0; |
431 | } |
432 | #endif |
433 | |
434 | static void tegra_rtc_shutdown(struct platform_device *pdev) |
435 | { |
436 | dev_vdbg(&pdev->dev, "disabling interrupts.\n"); |
437 | tegra_rtc_alarm_irq_enable(&pdev->dev, 0); |
438 | } |
439 | |
440 | MODULE_ALIAS("platform:tegra_rtc"); |
441 | static struct platform_driver tegra_rtc_driver = { |
442 | .remove = tegra_rtc_remove, |
443 | .shutdown = tegra_rtc_shutdown, |
444 | .driver = { |
445 | .name = "tegra_rtc", |
446 | .owner = THIS_MODULE, |
447 | .of_match_table = tegra_rtc_dt_match, |
448 | }, |
449 | #ifdef CONFIG_PM |
450 | .suspend = tegra_rtc_suspend, |
451 | .resume = tegra_rtc_resume, |
452 | #endif |
453 | }; |
454 | |
455 | static int __init tegra_rtc_init(void) |
456 | { |
457 | return platform_driver_probe(&tegra_rtc_driver, tegra_rtc_probe); |
458 | } |
459 | module_init(tegra_rtc_init); |
460 | |
461 | static void __exit tegra_rtc_exit(void) |
462 | { |
463 | platform_driver_unregister(&tegra_rtc_driver); |
464 | } |
465 | module_exit(tegra_rtc_exit); |
466 | |
467 | MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>"); |
468 | MODULE_DESCRIPTION("driver for Tegra internal RTC"); |
469 | MODULE_LICENSE("GPL"); |
470 |
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