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1 | /* |
2 | * rtc-tps6586x.c: RTC driver for TI PMIC TPS6586X |
3 | * |
4 | * Copyright (c) 2012, NVIDIA Corporation. |
5 | * |
6 | * Author: Laxman Dewangan <ldewangan@nvidia.com> |
7 | * |
8 | * This program is free software; you can redistribute it and/or |
9 | * modify it under the terms of the GNU General Public License as |
10 | * published by the Free Software Foundation version 2. |
11 | * |
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, |
13 | * whether express or implied; without even the implied warranty of |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
15 | * General Public License for more details. |
16 | * |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
20 | * 02111-1307, USA |
21 | */ |
22 | |
23 | #include <linux/device.h> |
24 | #include <linux/err.h> |
25 | #include <linux/init.h> |
26 | #include <linux/kernel.h> |
27 | #include <linux/mfd/tps6586x.h> |
28 | #include <linux/module.h> |
29 | #include <linux/platform_device.h> |
30 | #include <linux/pm_runtime.h> |
31 | #include <linux/rtc.h> |
32 | #include <linux/slab.h> |
33 | |
34 | #define RTC_CTRL 0xc0 |
35 | #define POR_RESET_N BIT(7) |
36 | #define OSC_SRC_SEL BIT(6) |
37 | #define RTC_ENABLE BIT(5) /* enables alarm */ |
38 | #define RTC_BUF_ENABLE BIT(4) /* 32 KHz buffer enable */ |
39 | #define PRE_BYPASS BIT(3) /* 0=1KHz or 1=32KHz updates */ |
40 | #define CL_SEL_MASK (BIT(2)|BIT(1)) |
41 | #define CL_SEL_POS 1 |
42 | #define RTC_ALARM1_HI 0xc1 |
43 | #define RTC_COUNT4 0xc6 |
44 | |
45 | /* start a PMU RTC access by reading the register prior to the RTC_COUNT4 */ |
46 | #define RTC_COUNT4_DUMMYREAD 0xc5 |
47 | |
48 | /*only 14-bits width in second*/ |
49 | #define ALM1_VALID_RANGE_IN_SEC 0x3FFF |
50 | |
51 | #define TPS6586X_RTC_CL_SEL_1_5PF 0x0 |
52 | #define TPS6586X_RTC_CL_SEL_6_5PF 0x1 |
53 | #define TPS6586X_RTC_CL_SEL_7_5PF 0x2 |
54 | #define TPS6586X_RTC_CL_SEL_12_5PF 0x3 |
55 | |
56 | struct tps6586x_rtc { |
57 | struct device *dev; |
58 | struct rtc_device *rtc; |
59 | int irq; |
60 | bool irq_en; |
61 | unsigned long long epoch_start; |
62 | }; |
63 | |
64 | static inline struct device *to_tps6586x_dev(struct device *dev) |
65 | { |
66 | return dev->parent; |
67 | } |
68 | |
69 | static int tps6586x_rtc_read_time(struct device *dev, struct rtc_time *tm) |
70 | { |
71 | struct tps6586x_rtc *rtc = dev_get_drvdata(dev); |
72 | struct device *tps_dev = to_tps6586x_dev(dev); |
73 | unsigned long long ticks = 0; |
74 | unsigned long seconds; |
75 | u8 buff[6]; |
76 | int ret; |
77 | int i; |
78 | |
79 | ret = tps6586x_reads(tps_dev, RTC_COUNT4_DUMMYREAD, sizeof(buff), buff); |
80 | if (ret < 0) { |
81 | dev_err(dev, "read counter failed with err %d\n", ret); |
82 | return ret; |
83 | } |
84 | |
85 | for (i = 1; i < sizeof(buff); i++) { |
86 | ticks <<= 8; |
87 | ticks |= buff[i]; |
88 | } |
89 | |
90 | seconds = ticks >> 10; |
91 | seconds += rtc->epoch_start; |
92 | rtc_time_to_tm(seconds, tm); |
93 | return rtc_valid_tm(tm); |
94 | } |
95 | |
96 | static int tps6586x_rtc_set_time(struct device *dev, struct rtc_time *tm) |
97 | { |
98 | struct tps6586x_rtc *rtc = dev_get_drvdata(dev); |
99 | struct device *tps_dev = to_tps6586x_dev(dev); |
100 | unsigned long long ticks; |
101 | unsigned long seconds; |
102 | u8 buff[5]; |
103 | int ret; |
104 | |
105 | rtc_tm_to_time(tm, &seconds); |
106 | if (seconds < rtc->epoch_start) { |
107 | dev_err(dev, "requested time unsupported\n"); |
108 | return -EINVAL; |
109 | } |
110 | seconds -= rtc->epoch_start; |
111 | |
112 | ticks = (unsigned long long)seconds << 10; |
113 | buff[0] = (ticks >> 32) & 0xff; |
114 | buff[1] = (ticks >> 24) & 0xff; |
115 | buff[2] = (ticks >> 16) & 0xff; |
116 | buff[3] = (ticks >> 8) & 0xff; |
117 | buff[4] = ticks & 0xff; |
118 | |
119 | /* Disable RTC before changing time */ |
120 | ret = tps6586x_clr_bits(tps_dev, RTC_CTRL, RTC_ENABLE); |
121 | if (ret < 0) { |
122 | dev_err(dev, "failed to clear RTC_ENABLE\n"); |
123 | return ret; |
124 | } |
125 | |
126 | ret = tps6586x_writes(tps_dev, RTC_COUNT4, sizeof(buff), buff); |
127 | if (ret < 0) { |
128 | dev_err(dev, "failed to program new time\n"); |
129 | return ret; |
130 | } |
131 | |
132 | /* Enable RTC */ |
133 | ret = tps6586x_set_bits(tps_dev, RTC_CTRL, RTC_ENABLE); |
134 | if (ret < 0) { |
135 | dev_err(dev, "failed to set RTC_ENABLE\n"); |
136 | return ret; |
137 | } |
138 | return 0; |
139 | } |
140 | |
141 | static int tps6586x_rtc_alarm_irq_enable(struct device *dev, |
142 | unsigned int enabled) |
143 | { |
144 | struct tps6586x_rtc *rtc = dev_get_drvdata(dev); |
145 | |
146 | if (enabled && !rtc->irq_en) { |
147 | enable_irq(rtc->irq); |
148 | rtc->irq_en = true; |
149 | } else if (!enabled && rtc->irq_en) { |
150 | disable_irq(rtc->irq); |
151 | rtc->irq_en = false; |
152 | } |
153 | return 0; |
154 | } |
155 | |
156 | static int tps6586x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
157 | { |
158 | struct tps6586x_rtc *rtc = dev_get_drvdata(dev); |
159 | struct device *tps_dev = to_tps6586x_dev(dev); |
160 | unsigned long seconds; |
161 | unsigned long ticks; |
162 | unsigned long rtc_current_time; |
163 | unsigned long long rticks = 0; |
164 | u8 buff[3]; |
165 | u8 rbuff[6]; |
166 | int ret; |
167 | int i; |
168 | |
169 | rtc_tm_to_time(&alrm->time, &seconds); |
170 | |
171 | if (alrm->enabled && (seconds < rtc->epoch_start)) { |
172 | dev_err(dev, "can't set alarm to requested time\n"); |
173 | return -EINVAL; |
174 | } |
175 | |
176 | ret = tps6586x_rtc_alarm_irq_enable(dev, alrm->enabled); |
177 | if (ret < 0) { |
178 | dev_err(dev, "can't set alarm irq, err %d\n", ret); |
179 | return ret; |
180 | } |
181 | |
182 | seconds -= rtc->epoch_start; |
183 | ret = tps6586x_reads(tps_dev, RTC_COUNT4_DUMMYREAD, |
184 | sizeof(rbuff), rbuff); |
185 | if (ret < 0) { |
186 | dev_err(dev, "read counter failed with err %d\n", ret); |
187 | return ret; |
188 | } |
189 | |
190 | for (i = 1; i < sizeof(rbuff); i++) { |
191 | rticks <<= 8; |
192 | rticks |= rbuff[i]; |
193 | } |
194 | |
195 | rtc_current_time = rticks >> 10; |
196 | if ((seconds - rtc_current_time) > ALM1_VALID_RANGE_IN_SEC) |
197 | seconds = rtc_current_time - 1; |
198 | |
199 | ticks = (unsigned long long)seconds << 10; |
200 | buff[0] = (ticks >> 16) & 0xff; |
201 | buff[1] = (ticks >> 8) & 0xff; |
202 | buff[2] = ticks & 0xff; |
203 | |
204 | ret = tps6586x_writes(tps_dev, RTC_ALARM1_HI, sizeof(buff), buff); |
205 | if (ret) |
206 | dev_err(dev, "programming alarm failed with err %d\n", ret); |
207 | |
208 | return ret; |
209 | } |
210 | |
211 | static int tps6586x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
212 | { |
213 | struct tps6586x_rtc *rtc = dev_get_drvdata(dev); |
214 | struct device *tps_dev = to_tps6586x_dev(dev); |
215 | unsigned long ticks; |
216 | unsigned long seconds; |
217 | u8 buff[3]; |
218 | int ret; |
219 | |
220 | ret = tps6586x_reads(tps_dev, RTC_ALARM1_HI, sizeof(buff), buff); |
221 | if (ret) { |
222 | dev_err(dev, "read RTC_ALARM1_HI failed with err %d\n", ret); |
223 | return ret; |
224 | } |
225 | |
226 | ticks = (buff[0] << 16) | (buff[1] << 8) | buff[2]; |
227 | seconds = ticks >> 10; |
228 | seconds += rtc->epoch_start; |
229 | |
230 | rtc_time_to_tm(seconds, &alrm->time); |
231 | return 0; |
232 | } |
233 | |
234 | static const struct rtc_class_ops tps6586x_rtc_ops = { |
235 | .read_time = tps6586x_rtc_read_time, |
236 | .set_time = tps6586x_rtc_set_time, |
237 | .set_alarm = tps6586x_rtc_set_alarm, |
238 | .read_alarm = tps6586x_rtc_read_alarm, |
239 | .alarm_irq_enable = tps6586x_rtc_alarm_irq_enable, |
240 | }; |
241 | |
242 | static irqreturn_t tps6586x_rtc_irq(int irq, void *data) |
243 | { |
244 | struct tps6586x_rtc *rtc = data; |
245 | |
246 | rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF); |
247 | return IRQ_HANDLED; |
248 | } |
249 | |
250 | static int tps6586x_rtc_probe(struct platform_device *pdev) |
251 | { |
252 | struct device *tps_dev = to_tps6586x_dev(&pdev->dev); |
253 | struct tps6586x_rtc *rtc; |
254 | int ret; |
255 | |
256 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
257 | if (!rtc) |
258 | return -ENOMEM; |
259 | |
260 | rtc->dev = &pdev->dev; |
261 | rtc->irq = platform_get_irq(pdev, 0); |
262 | |
263 | /* Set epoch start as 00:00:00:01:01:2009 */ |
264 | rtc->epoch_start = mktime(2009, 1, 1, 0, 0, 0); |
265 | |
266 | /* 1 kHz tick mode, enable tick counting */ |
267 | ret = tps6586x_update(tps_dev, RTC_CTRL, |
268 | RTC_ENABLE | OSC_SRC_SEL | |
269 | ((TPS6586X_RTC_CL_SEL_1_5PF << CL_SEL_POS) & CL_SEL_MASK), |
270 | RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK); |
271 | if (ret < 0) { |
272 | dev_err(&pdev->dev, "unable to start counter\n"); |
273 | return ret; |
274 | } |
275 | |
276 | platform_set_drvdata(pdev, rtc); |
277 | rtc->rtc = rtc_device_register(dev_name(&pdev->dev), &pdev->dev, |
278 | &tps6586x_rtc_ops, THIS_MODULE); |
279 | if (IS_ERR(rtc->rtc)) { |
280 | ret = PTR_ERR(rtc->rtc); |
281 | dev_err(&pdev->dev, "RTC device register: ret %d\n", ret); |
282 | goto fail_rtc_register; |
283 | } |
284 | |
285 | ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL, |
286 | tps6586x_rtc_irq, |
287 | IRQF_ONESHOT | IRQF_EARLY_RESUME, |
288 | dev_name(&pdev->dev), rtc); |
289 | if (ret < 0) { |
290 | dev_err(&pdev->dev, "request IRQ(%d) failed with ret %d\n", |
291 | rtc->irq, ret); |
292 | goto fail_req_irq; |
293 | } |
294 | disable_irq(rtc->irq); |
295 | device_set_wakeup_capable(&pdev->dev, 1); |
296 | return 0; |
297 | |
298 | fail_req_irq: |
299 | rtc_device_unregister(rtc->rtc); |
300 | |
301 | fail_rtc_register: |
302 | tps6586x_update(tps_dev, RTC_CTRL, 0, |
303 | RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK); |
304 | return ret; |
305 | }; |
306 | |
307 | static int tps6586x_rtc_remove(struct platform_device *pdev) |
308 | { |
309 | struct tps6586x_rtc *rtc = platform_get_drvdata(pdev); |
310 | struct device *tps_dev = to_tps6586x_dev(&pdev->dev); |
311 | |
312 | tps6586x_update(tps_dev, RTC_CTRL, 0, |
313 | RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK); |
314 | rtc_device_unregister(rtc->rtc); |
315 | return 0; |
316 | } |
317 | |
318 | #ifdef CONFIG_PM_SLEEP |
319 | static int tps6586x_rtc_suspend(struct device *dev) |
320 | { |
321 | struct tps6586x_rtc *rtc = dev_get_drvdata(dev); |
322 | |
323 | if (device_may_wakeup(dev)) |
324 | enable_irq_wake(rtc->irq); |
325 | return 0; |
326 | } |
327 | |
328 | static int tps6586x_rtc_resume(struct device *dev) |
329 | { |
330 | struct tps6586x_rtc *rtc = dev_get_drvdata(dev); |
331 | |
332 | if (device_may_wakeup(dev)) |
333 | disable_irq_wake(rtc->irq); |
334 | return 0; |
335 | } |
336 | #endif |
337 | |
338 | static const struct dev_pm_ops tps6586x_pm_ops = { |
339 | SET_SYSTEM_SLEEP_PM_OPS(tps6586x_rtc_suspend, tps6586x_rtc_resume) |
340 | }; |
341 | |
342 | static struct platform_driver tps6586x_rtc_driver = { |
343 | .driver = { |
344 | .name = "tps6586x-rtc", |
345 | .owner = THIS_MODULE, |
346 | .pm = &tps6586x_pm_ops, |
347 | }, |
348 | .probe = tps6586x_rtc_probe, |
349 | .remove = tps6586x_rtc_remove, |
350 | }; |
351 | module_platform_driver(tps6586x_rtc_driver); |
352 | |
353 | MODULE_ALIAS("platform:rtc-tps6586x"); |
354 | MODULE_DESCRIPTION("TI TPS6586x RTC driver"); |
355 | MODULE_AUTHOR("Laxman dewangan <ldewangan@nvidia.com>"); |
356 | MODULE_LICENSE("GPL v2"); |
357 |
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