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1 | /* |
2 | * rtc-twl.c -- TWL Real Time Clock interface |
3 | * |
4 | * Copyright (C) 2007 MontaVista Software, Inc |
5 | * Author: Alexandre Rusev <source@mvista.com> |
6 | * |
7 | * Based on original TI driver twl4030-rtc.c |
8 | * Copyright (C) 2006 Texas Instruments, Inc. |
9 | * |
10 | * Based on rtc-omap.c |
11 | * Copyright (C) 2003 MontaVista Software, Inc. |
12 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> |
13 | * Copyright (C) 2006 David Brownell |
14 | * |
15 | * This program is free software; you can redistribute it and/or |
16 | * modify it under the terms of the GNU General Public License |
17 | * as published by the Free Software Foundation; either version |
18 | * 2 of the License, or (at your option) any later version. |
19 | */ |
20 | |
21 | #include <linux/kernel.h> |
22 | #include <linux/errno.h> |
23 | #include <linux/init.h> |
24 | #include <linux/module.h> |
25 | #include <linux/types.h> |
26 | #include <linux/rtc.h> |
27 | #include <linux/bcd.h> |
28 | #include <linux/platform_device.h> |
29 | #include <linux/interrupt.h> |
30 | #include <linux/of.h> |
31 | |
32 | #include <linux/i2c/twl.h> |
33 | |
34 | |
35 | /* |
36 | * RTC block register offsets (use TWL_MODULE_RTC) |
37 | */ |
38 | enum { |
39 | REG_SECONDS_REG = 0, |
40 | REG_MINUTES_REG, |
41 | REG_HOURS_REG, |
42 | REG_DAYS_REG, |
43 | REG_MONTHS_REG, |
44 | REG_YEARS_REG, |
45 | REG_WEEKS_REG, |
46 | |
47 | REG_ALARM_SECONDS_REG, |
48 | REG_ALARM_MINUTES_REG, |
49 | REG_ALARM_HOURS_REG, |
50 | REG_ALARM_DAYS_REG, |
51 | REG_ALARM_MONTHS_REG, |
52 | REG_ALARM_YEARS_REG, |
53 | |
54 | REG_RTC_CTRL_REG, |
55 | REG_RTC_STATUS_REG, |
56 | REG_RTC_INTERRUPTS_REG, |
57 | |
58 | REG_RTC_COMP_LSB_REG, |
59 | REG_RTC_COMP_MSB_REG, |
60 | }; |
61 | static const u8 twl4030_rtc_reg_map[] = { |
62 | [REG_SECONDS_REG] = 0x00, |
63 | [REG_MINUTES_REG] = 0x01, |
64 | [REG_HOURS_REG] = 0x02, |
65 | [REG_DAYS_REG] = 0x03, |
66 | [REG_MONTHS_REG] = 0x04, |
67 | [REG_YEARS_REG] = 0x05, |
68 | [REG_WEEKS_REG] = 0x06, |
69 | |
70 | [REG_ALARM_SECONDS_REG] = 0x07, |
71 | [REG_ALARM_MINUTES_REG] = 0x08, |
72 | [REG_ALARM_HOURS_REG] = 0x09, |
73 | [REG_ALARM_DAYS_REG] = 0x0A, |
74 | [REG_ALARM_MONTHS_REG] = 0x0B, |
75 | [REG_ALARM_YEARS_REG] = 0x0C, |
76 | |
77 | [REG_RTC_CTRL_REG] = 0x0D, |
78 | [REG_RTC_STATUS_REG] = 0x0E, |
79 | [REG_RTC_INTERRUPTS_REG] = 0x0F, |
80 | |
81 | [REG_RTC_COMP_LSB_REG] = 0x10, |
82 | [REG_RTC_COMP_MSB_REG] = 0x11, |
83 | }; |
84 | static const u8 twl6030_rtc_reg_map[] = { |
85 | [REG_SECONDS_REG] = 0x00, |
86 | [REG_MINUTES_REG] = 0x01, |
87 | [REG_HOURS_REG] = 0x02, |
88 | [REG_DAYS_REG] = 0x03, |
89 | [REG_MONTHS_REG] = 0x04, |
90 | [REG_YEARS_REG] = 0x05, |
91 | [REG_WEEKS_REG] = 0x06, |
92 | |
93 | [REG_ALARM_SECONDS_REG] = 0x08, |
94 | [REG_ALARM_MINUTES_REG] = 0x09, |
95 | [REG_ALARM_HOURS_REG] = 0x0A, |
96 | [REG_ALARM_DAYS_REG] = 0x0B, |
97 | [REG_ALARM_MONTHS_REG] = 0x0C, |
98 | [REG_ALARM_YEARS_REG] = 0x0D, |
99 | |
100 | [REG_RTC_CTRL_REG] = 0x10, |
101 | [REG_RTC_STATUS_REG] = 0x11, |
102 | [REG_RTC_INTERRUPTS_REG] = 0x12, |
103 | |
104 | [REG_RTC_COMP_LSB_REG] = 0x13, |
105 | [REG_RTC_COMP_MSB_REG] = 0x14, |
106 | }; |
107 | |
108 | /* RTC_CTRL_REG bitfields */ |
109 | #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01 |
110 | #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02 |
111 | #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04 |
112 | #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08 |
113 | #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10 |
114 | #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20 |
115 | #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40 |
116 | #define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80 |
117 | |
118 | /* RTC_STATUS_REG bitfields */ |
119 | #define BIT_RTC_STATUS_REG_RUN_M 0x02 |
120 | #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04 |
121 | #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08 |
122 | #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10 |
123 | #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20 |
124 | #define BIT_RTC_STATUS_REG_ALARM_M 0x40 |
125 | #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80 |
126 | |
127 | /* RTC_INTERRUPTS_REG bitfields */ |
128 | #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03 |
129 | #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04 |
130 | #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08 |
131 | |
132 | |
133 | /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */ |
134 | #define ALL_TIME_REGS 6 |
135 | |
136 | /*----------------------------------------------------------------------*/ |
137 | static u8 *rtc_reg_map; |
138 | |
139 | /* |
140 | * Supports 1 byte read from TWL RTC register. |
141 | */ |
142 | static int twl_rtc_read_u8(u8 *data, u8 reg) |
143 | { |
144 | int ret; |
145 | |
146 | ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg])); |
147 | if (ret < 0) |
148 | pr_err("twl_rtc: Could not read TWL" |
149 | "register %X - error %d\n", reg, ret); |
150 | return ret; |
151 | } |
152 | |
153 | /* |
154 | * Supports 1 byte write to TWL RTC registers. |
155 | */ |
156 | static int twl_rtc_write_u8(u8 data, u8 reg) |
157 | { |
158 | int ret; |
159 | |
160 | ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg])); |
161 | if (ret < 0) |
162 | pr_err("twl_rtc: Could not write TWL" |
163 | "register %X - error %d\n", reg, ret); |
164 | return ret; |
165 | } |
166 | |
167 | /* |
168 | * Cache the value for timer/alarm interrupts register; this is |
169 | * only changed by callers holding rtc ops lock (or resume). |
170 | */ |
171 | static unsigned char rtc_irq_bits; |
172 | |
173 | /* |
174 | * Enable 1/second update and/or alarm interrupts. |
175 | */ |
176 | static int set_rtc_irq_bit(unsigned char bit) |
177 | { |
178 | unsigned char val; |
179 | int ret; |
180 | |
181 | /* if the bit is set, return from here */ |
182 | if (rtc_irq_bits & bit) |
183 | return 0; |
184 | |
185 | val = rtc_irq_bits | bit; |
186 | val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M; |
187 | ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG); |
188 | if (ret == 0) |
189 | rtc_irq_bits = val; |
190 | |
191 | return ret; |
192 | } |
193 | |
194 | /* |
195 | * Disable update and/or alarm interrupts. |
196 | */ |
197 | static int mask_rtc_irq_bit(unsigned char bit) |
198 | { |
199 | unsigned char val; |
200 | int ret; |
201 | |
202 | /* if the bit is clear, return from here */ |
203 | if (!(rtc_irq_bits & bit)) |
204 | return 0; |
205 | |
206 | val = rtc_irq_bits & ~bit; |
207 | ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG); |
208 | if (ret == 0) |
209 | rtc_irq_bits = val; |
210 | |
211 | return ret; |
212 | } |
213 | |
214 | static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled) |
215 | { |
216 | int ret; |
217 | |
218 | if (enabled) |
219 | ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); |
220 | else |
221 | ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); |
222 | |
223 | return ret; |
224 | } |
225 | |
226 | /* |
227 | * Gets current TWL RTC time and date parameters. |
228 | * |
229 | * The RTC's time/alarm representation is not what gmtime(3) requires |
230 | * Linux to use: |
231 | * |
232 | * - Months are 1..12 vs Linux 0-11 |
233 | * - Years are 0..99 vs Linux 1900..N (we assume 21st century) |
234 | */ |
235 | static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm) |
236 | { |
237 | unsigned char rtc_data[ALL_TIME_REGS]; |
238 | int ret; |
239 | u8 save_control; |
240 | u8 rtc_control; |
241 | |
242 | ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG); |
243 | if (ret < 0) { |
244 | dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret); |
245 | return ret; |
246 | } |
247 | /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */ |
248 | if (twl_class_is_6030()) { |
249 | if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) { |
250 | save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M; |
251 | ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG); |
252 | if (ret < 0) { |
253 | dev_err(dev, "%s clr GET_TIME, error %d\n", |
254 | __func__, ret); |
255 | return ret; |
256 | } |
257 | } |
258 | } |
259 | |
260 | /* Copy RTC counting registers to static registers or latches */ |
261 | rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M; |
262 | |
263 | /* for twl6030/32 enable read access to static shadowed registers */ |
264 | if (twl_class_is_6030()) |
265 | rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT; |
266 | |
267 | ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG); |
268 | if (ret < 0) { |
269 | dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret); |
270 | return ret; |
271 | } |
272 | |
273 | ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data, |
274 | (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS); |
275 | |
276 | if (ret < 0) { |
277 | dev_err(dev, "%s: reading data, error %d\n", __func__, ret); |
278 | return ret; |
279 | } |
280 | |
281 | /* for twl6030 restore original state of rtc control register */ |
282 | if (twl_class_is_6030()) { |
283 | ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG); |
284 | if (ret < 0) { |
285 | dev_err(dev, "%s: restore CTRL_REG, error %d\n", |
286 | __func__, ret); |
287 | return ret; |
288 | } |
289 | } |
290 | |
291 | tm->tm_sec = bcd2bin(rtc_data[0]); |
292 | tm->tm_min = bcd2bin(rtc_data[1]); |
293 | tm->tm_hour = bcd2bin(rtc_data[2]); |
294 | tm->tm_mday = bcd2bin(rtc_data[3]); |
295 | tm->tm_mon = bcd2bin(rtc_data[4]) - 1; |
296 | tm->tm_year = bcd2bin(rtc_data[5]) + 100; |
297 | |
298 | return ret; |
299 | } |
300 | |
301 | static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm) |
302 | { |
303 | unsigned char save_control; |
304 | unsigned char rtc_data[ALL_TIME_REGS]; |
305 | int ret; |
306 | |
307 | rtc_data[0] = bin2bcd(tm->tm_sec); |
308 | rtc_data[1] = bin2bcd(tm->tm_min); |
309 | rtc_data[2] = bin2bcd(tm->tm_hour); |
310 | rtc_data[3] = bin2bcd(tm->tm_mday); |
311 | rtc_data[4] = bin2bcd(tm->tm_mon + 1); |
312 | rtc_data[5] = bin2bcd(tm->tm_year - 100); |
313 | |
314 | /* Stop RTC while updating the TC registers */ |
315 | ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG); |
316 | if (ret < 0) |
317 | goto out; |
318 | |
319 | save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M; |
320 | ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG); |
321 | if (ret < 0) |
322 | goto out; |
323 | |
324 | /* update all the time registers in one shot */ |
325 | ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data, |
326 | (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS); |
327 | if (ret < 0) { |
328 | dev_err(dev, "rtc_set_time error %d\n", ret); |
329 | goto out; |
330 | } |
331 | |
332 | /* Start back RTC */ |
333 | save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M; |
334 | ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG); |
335 | |
336 | out: |
337 | return ret; |
338 | } |
339 | |
340 | /* |
341 | * Gets current TWL RTC alarm time. |
342 | */ |
343 | static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) |
344 | { |
345 | unsigned char rtc_data[ALL_TIME_REGS]; |
346 | int ret; |
347 | |
348 | ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data, |
349 | (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS); |
350 | if (ret < 0) { |
351 | dev_err(dev, "rtc_read_alarm error %d\n", ret); |
352 | return ret; |
353 | } |
354 | |
355 | /* some of these fields may be wildcard/"match all" */ |
356 | alm->time.tm_sec = bcd2bin(rtc_data[0]); |
357 | alm->time.tm_min = bcd2bin(rtc_data[1]); |
358 | alm->time.tm_hour = bcd2bin(rtc_data[2]); |
359 | alm->time.tm_mday = bcd2bin(rtc_data[3]); |
360 | alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1; |
361 | alm->time.tm_year = bcd2bin(rtc_data[5]) + 100; |
362 | |
363 | /* report cached alarm enable state */ |
364 | if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M) |
365 | alm->enabled = 1; |
366 | |
367 | return ret; |
368 | } |
369 | |
370 | static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) |
371 | { |
372 | unsigned char alarm_data[ALL_TIME_REGS]; |
373 | int ret; |
374 | |
375 | ret = twl_rtc_alarm_irq_enable(dev, 0); |
376 | if (ret) |
377 | goto out; |
378 | |
379 | alarm_data[0] = bin2bcd(alm->time.tm_sec); |
380 | alarm_data[1] = bin2bcd(alm->time.tm_min); |
381 | alarm_data[2] = bin2bcd(alm->time.tm_hour); |
382 | alarm_data[3] = bin2bcd(alm->time.tm_mday); |
383 | alarm_data[4] = bin2bcd(alm->time.tm_mon + 1); |
384 | alarm_data[5] = bin2bcd(alm->time.tm_year - 100); |
385 | |
386 | /* update all the alarm registers in one shot */ |
387 | ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data, |
388 | (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS); |
389 | if (ret) { |
390 | dev_err(dev, "rtc_set_alarm error %d\n", ret); |
391 | goto out; |
392 | } |
393 | |
394 | if (alm->enabled) |
395 | ret = twl_rtc_alarm_irq_enable(dev, 1); |
396 | out: |
397 | return ret; |
398 | } |
399 | |
400 | static irqreturn_t twl_rtc_interrupt(int irq, void *rtc) |
401 | { |
402 | unsigned long events; |
403 | int ret = IRQ_NONE; |
404 | int res; |
405 | u8 rd_reg; |
406 | |
407 | res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG); |
408 | if (res) |
409 | goto out; |
410 | /* |
411 | * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG. |
412 | * only one (ALARM or RTC) interrupt source may be enabled |
413 | * at time, we also could check our results |
414 | * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM] |
415 | */ |
416 | if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M) |
417 | events = RTC_IRQF | RTC_AF; |
418 | else |
419 | events = RTC_IRQF | RTC_PF; |
420 | |
421 | res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M, |
422 | REG_RTC_STATUS_REG); |
423 | if (res) |
424 | goto out; |
425 | |
426 | if (twl_class_is_4030()) { |
427 | /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1 |
428 | * needs 2 reads to clear the interrupt. One read is done in |
429 | * do_twl_pwrirq(). Doing the second read, to clear |
430 | * the bit. |
431 | * |
432 | * FIXME the reason PWR_ISR1 needs an extra read is that |
433 | * RTC_IF retriggered until we cleared REG_ALARM_M above. |
434 | * But re-reading like this is a bad hack; by doing so we |
435 | * risk wrongly clearing status for some other IRQ (losing |
436 | * the interrupt). Be smarter about handling RTC_UF ... |
437 | */ |
438 | res = twl_i2c_read_u8(TWL4030_MODULE_INT, |
439 | &rd_reg, TWL4030_INT_PWR_ISR1); |
440 | if (res) |
441 | goto out; |
442 | } |
443 | |
444 | /* Notify RTC core on event */ |
445 | rtc_update_irq(rtc, 1, events); |
446 | |
447 | ret = IRQ_HANDLED; |
448 | out: |
449 | return ret; |
450 | } |
451 | |
452 | static struct rtc_class_ops twl_rtc_ops = { |
453 | .read_time = twl_rtc_read_time, |
454 | .set_time = twl_rtc_set_time, |
455 | .read_alarm = twl_rtc_read_alarm, |
456 | .set_alarm = twl_rtc_set_alarm, |
457 | .alarm_irq_enable = twl_rtc_alarm_irq_enable, |
458 | }; |
459 | |
460 | /*----------------------------------------------------------------------*/ |
461 | |
462 | static int twl_rtc_probe(struct platform_device *pdev) |
463 | { |
464 | struct rtc_device *rtc; |
465 | int ret = -EINVAL; |
466 | int irq = platform_get_irq(pdev, 0); |
467 | u8 rd_reg; |
468 | |
469 | if (irq <= 0) |
470 | goto out1; |
471 | |
472 | ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG); |
473 | if (ret < 0) |
474 | goto out1; |
475 | |
476 | if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M) |
477 | dev_warn(&pdev->dev, "Power up reset detected.\n"); |
478 | |
479 | if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M) |
480 | dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n"); |
481 | |
482 | /* Clear RTC Power up reset and pending alarm interrupts */ |
483 | ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG); |
484 | if (ret < 0) |
485 | goto out1; |
486 | |
487 | if (twl_class_is_6030()) { |
488 | twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK, |
489 | REG_INT_MSK_LINE_A); |
490 | twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK, |
491 | REG_INT_MSK_STS_A); |
492 | } |
493 | |
494 | dev_info(&pdev->dev, "Enabling TWL-RTC\n"); |
495 | ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG); |
496 | if (ret < 0) |
497 | goto out1; |
498 | |
499 | /* ensure interrupts are disabled, bootloaders can be strange */ |
500 | ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG); |
501 | if (ret < 0) |
502 | dev_warn(&pdev->dev, "unable to disable interrupt\n"); |
503 | |
504 | /* init cached IRQ enable bits */ |
505 | ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG); |
506 | if (ret < 0) |
507 | goto out1; |
508 | |
509 | rtc = rtc_device_register(pdev->name, |
510 | &pdev->dev, &twl_rtc_ops, THIS_MODULE); |
511 | if (IS_ERR(rtc)) { |
512 | ret = PTR_ERR(rtc); |
513 | dev_err(&pdev->dev, "can't register RTC device, err %ld\n", |
514 | PTR_ERR(rtc)); |
515 | goto out1; |
516 | } |
517 | |
518 | ret = request_threaded_irq(irq, NULL, twl_rtc_interrupt, |
519 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, |
520 | dev_name(&rtc->dev), rtc); |
521 | if (ret < 0) { |
522 | dev_err(&pdev->dev, "IRQ is not free.\n"); |
523 | goto out2; |
524 | } |
525 | |
526 | platform_set_drvdata(pdev, rtc); |
527 | return 0; |
528 | |
529 | out2: |
530 | rtc_device_unregister(rtc); |
531 | out1: |
532 | return ret; |
533 | } |
534 | |
535 | /* |
536 | * Disable all TWL RTC module interrupts. |
537 | * Sets status flag to free. |
538 | */ |
539 | static int twl_rtc_remove(struct platform_device *pdev) |
540 | { |
541 | /* leave rtc running, but disable irqs */ |
542 | struct rtc_device *rtc = platform_get_drvdata(pdev); |
543 | int irq = platform_get_irq(pdev, 0); |
544 | |
545 | mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); |
546 | mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); |
547 | if (twl_class_is_6030()) { |
548 | twl6030_interrupt_mask(TWL6030_RTC_INT_MASK, |
549 | REG_INT_MSK_LINE_A); |
550 | twl6030_interrupt_mask(TWL6030_RTC_INT_MASK, |
551 | REG_INT_MSK_STS_A); |
552 | } |
553 | |
554 | |
555 | free_irq(irq, rtc); |
556 | |
557 | rtc_device_unregister(rtc); |
558 | platform_set_drvdata(pdev, NULL); |
559 | return 0; |
560 | } |
561 | |
562 | static void twl_rtc_shutdown(struct platform_device *pdev) |
563 | { |
564 | /* mask timer interrupts, but leave alarm interrupts on to enable |
565 | power-on when alarm is triggered */ |
566 | mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); |
567 | } |
568 | |
569 | #ifdef CONFIG_PM |
570 | |
571 | static unsigned char irqstat; |
572 | |
573 | static int twl_rtc_suspend(struct platform_device *pdev, pm_message_t state) |
574 | { |
575 | irqstat = rtc_irq_bits; |
576 | |
577 | mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); |
578 | return 0; |
579 | } |
580 | |
581 | static int twl_rtc_resume(struct platform_device *pdev) |
582 | { |
583 | set_rtc_irq_bit(irqstat); |
584 | return 0; |
585 | } |
586 | |
587 | #else |
588 | #define twl_rtc_suspend NULL |
589 | #define twl_rtc_resume NULL |
590 | #endif |
591 | |
592 | #ifdef CONFIG_OF |
593 | static const struct of_device_id twl_rtc_of_match[] = { |
594 | {.compatible = "ti,twl4030-rtc", }, |
595 | { }, |
596 | }; |
597 | MODULE_DEVICE_TABLE(of, twl_rtc_of_match); |
598 | #endif |
599 | |
600 | MODULE_ALIAS("platform:twl_rtc"); |
601 | |
602 | static struct platform_driver twl4030rtc_driver = { |
603 | .probe = twl_rtc_probe, |
604 | .remove = twl_rtc_remove, |
605 | .shutdown = twl_rtc_shutdown, |
606 | .suspend = twl_rtc_suspend, |
607 | .resume = twl_rtc_resume, |
608 | .driver = { |
609 | .owner = THIS_MODULE, |
610 | .name = "twl_rtc", |
611 | .of_match_table = of_match_ptr(twl_rtc_of_match), |
612 | }, |
613 | }; |
614 | |
615 | static int __init twl_rtc_init(void) |
616 | { |
617 | if (twl_class_is_4030()) |
618 | rtc_reg_map = (u8 *) twl4030_rtc_reg_map; |
619 | else |
620 | rtc_reg_map = (u8 *) twl6030_rtc_reg_map; |
621 | |
622 | return platform_driver_register(&twl4030rtc_driver); |
623 | } |
624 | module_init(twl_rtc_init); |
625 | |
626 | static void __exit twl_rtc_exit(void) |
627 | { |
628 | platform_driver_unregister(&twl4030rtc_driver); |
629 | } |
630 | module_exit(twl_rtc_exit); |
631 | |
632 | MODULE_AUTHOR("Texas Instruments, MontaVista Software"); |
633 | MODULE_LICENSE("GPL"); |
634 |
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