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1 | #ifndef _GDTH_H |
2 | #define _GDTH_H |
3 | |
4 | /* |
5 | * Header file for the GDT Disk Array/Storage RAID controllers driver for Linux |
6 | * |
7 | * gdth.h Copyright (C) 1995-06 ICP vortex, Achim Leubner |
8 | * See gdth.c for further informations and |
9 | * below for supported controller types |
10 | * |
11 | * <achim_leubner@adaptec.com> |
12 | * |
13 | * $Id: gdth.h,v 1.58 2006/01/11 16:14:09 achim Exp $ |
14 | */ |
15 | |
16 | #include <linux/types.h> |
17 | |
18 | #ifndef TRUE |
19 | #define TRUE 1 |
20 | #endif |
21 | #ifndef FALSE |
22 | #define FALSE 0 |
23 | #endif |
24 | |
25 | /* defines, macros */ |
26 | |
27 | /* driver version */ |
28 | #define GDTH_VERSION_STR "3.05" |
29 | #define GDTH_VERSION 3 |
30 | #define GDTH_SUBVERSION 5 |
31 | |
32 | /* protocol version */ |
33 | #define PROTOCOL_VERSION 1 |
34 | |
35 | /* OEM IDs */ |
36 | #define OEM_ID_ICP 0x941c |
37 | #define OEM_ID_INTEL 0x8000 |
38 | |
39 | /* controller classes */ |
40 | #define GDT_ISA 0x01 /* ISA controller */ |
41 | #define GDT_EISA 0x02 /* EISA controller */ |
42 | #define GDT_PCI 0x03 /* PCI controller */ |
43 | #define GDT_PCINEW 0x04 /* new PCI controller */ |
44 | #define GDT_PCIMPR 0x05 /* PCI MPR controller */ |
45 | /* GDT_EISA, controller subtypes EISA */ |
46 | #define GDT3_ID 0x0130941c /* GDT3000/3020 */ |
47 | #define GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */ |
48 | #define GDT3B_ID 0x0330941c /* GDT3000B/3010A */ |
49 | /* GDT_ISA */ |
50 | #define GDT2_ID 0x0120941c /* GDT2000/2020 */ |
51 | |
52 | #ifndef PCI_DEVICE_ID_VORTEX_GDT60x0 |
53 | /* GDT_PCI */ |
54 | #define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */ |
55 | #define PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */ |
56 | /* GDT_PCINEW */ |
57 | #define PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */ |
58 | #define PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */ |
59 | #define PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */ |
60 | #define PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */ |
61 | /* GDT_PCINEW, wide/ultra SCSI controllers */ |
62 | #define PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */ |
63 | #define PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */ |
64 | #define PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */ |
65 | #define PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */ |
66 | /* GDT_PCINEW, wide SCSI controllers */ |
67 | #define PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */ |
68 | #define PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */ |
69 | #define PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */ |
70 | #define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */ |
71 | #endif |
72 | |
73 | #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP |
74 | /* GDT_MPR, RP series, wide/ultra SCSI */ |
75 | #define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */ |
76 | #define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */ |
77 | #define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */ |
78 | #define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */ |
79 | /* GDT_MPR, RP series, narrow/ultra SCSI */ |
80 | #define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */ |
81 | #define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */ |
82 | #endif |
83 | #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD |
84 | /* GDT_MPR, RD series, wide/ultra SCSI */ |
85 | #define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */ |
86 | #define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */ |
87 | #define PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */ |
88 | #define PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */ |
89 | /* GDT_MPR, RD series, narrow/ultra SCSI */ |
90 | #define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */ |
91 | #define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */ |
92 | /* GDT_MPR, RD series, wide/ultra2 SCSI */ |
93 | #define PCI_DEVICE_ID_VORTEX_GDT6x18RD 0x118 /* GDT6118RD/GDT6518RD/ |
94 | GDT6618RD */ |
95 | #define PCI_DEVICE_ID_VORTEX_GDT6x28RD 0x119 /* GDT6128RD/GDT6528RD/ |
96 | GDT6628RD */ |
97 | #define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */ |
98 | #define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */ |
99 | /* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */ |
100 | #define PCI_DEVICE_ID_VORTEX_GDT7x18RN 0x168 /* GDT7118RN/GDT7518RN/ |
101 | GDT7618RN */ |
102 | #define PCI_DEVICE_ID_VORTEX_GDT7x28RN 0x169 /* GDT7128RN/GDT7528RN/ |
103 | GDT7628RN */ |
104 | #define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */ |
105 | #define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */ |
106 | #endif |
107 | |
108 | #ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD |
109 | /* GDT_MPR, RD series, Fibre Channel */ |
110 | #define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */ |
111 | #define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */ |
112 | /* GDT_MPR, RN series (64-bit PCI), Fibre Channel */ |
113 | #define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */ |
114 | #define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */ |
115 | #endif |
116 | |
117 | #ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP |
118 | /* GDT_MPR, last device ID */ |
119 | #define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff |
120 | #endif |
121 | |
122 | #ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX |
123 | /* new GDT Rx Controller */ |
124 | #define PCI_DEVICE_ID_VORTEX_GDTNEWRX 0x300 |
125 | #endif |
126 | |
127 | #ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX2 |
128 | /* new(2) GDT Rx Controller */ |
129 | #define PCI_DEVICE_ID_VORTEX_GDTNEWRX2 0x301 |
130 | #endif |
131 | |
132 | #ifndef PCI_DEVICE_ID_INTEL_SRC |
133 | /* Intel Storage RAID Controller */ |
134 | #define PCI_DEVICE_ID_INTEL_SRC 0x600 |
135 | #endif |
136 | |
137 | #ifndef PCI_DEVICE_ID_INTEL_SRC_XSCALE |
138 | /* Intel Storage RAID Controller */ |
139 | #define PCI_DEVICE_ID_INTEL_SRC_XSCALE 0x601 |
140 | #endif |
141 | |
142 | /* limits */ |
143 | #define GDTH_SCRATCH PAGE_SIZE /* 4KB scratch buffer */ |
144 | #define GDTH_MAXCMDS 120 |
145 | #define GDTH_MAXC_P_L 16 /* max. cmds per lun */ |
146 | #define GDTH_MAX_RAW 2 /* max. cmds per raw device */ |
147 | #define MAXOFFSETS 128 |
148 | #define MAXHA 16 |
149 | #define MAXID 127 |
150 | #define MAXLUN 8 |
151 | #define MAXBUS 6 |
152 | #define MAX_EVENTS 100 /* event buffer count */ |
153 | #define MAX_RES_ARGS 40 /* device reservation, |
154 | must be a multiple of 4 */ |
155 | #define MAXCYLS 1024 |
156 | #define HEADS 64 |
157 | #define SECS 32 /* mapping 64*32 */ |
158 | #define MEDHEADS 127 |
159 | #define MEDSECS 63 /* mapping 127*63 */ |
160 | #define BIGHEADS 255 |
161 | #define BIGSECS 63 /* mapping 255*63 */ |
162 | |
163 | /* special command ptr. */ |
164 | #define UNUSED_CMND ((Scsi_Cmnd *)-1) |
165 | #define INTERNAL_CMND ((Scsi_Cmnd *)-2) |
166 | #define SCREEN_CMND ((Scsi_Cmnd *)-3) |
167 | #define SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND) |
168 | |
169 | /* controller services */ |
170 | #define SCSIRAWSERVICE 3 |
171 | #define CACHESERVICE 9 |
172 | #define SCREENSERVICE 11 |
173 | |
174 | /* screenservice defines */ |
175 | #define MSG_INV_HANDLE -1 /* special message handle */ |
176 | #define MSGLEN 16 /* size of message text */ |
177 | #define MSG_SIZE 34 /* size of message structure */ |
178 | #define MSG_REQUEST 0 /* async. event: message */ |
179 | |
180 | /* cacheservice defines */ |
181 | #define SECTOR_SIZE 0x200 /* always 512 bytes per sec. */ |
182 | |
183 | /* DPMEM constants */ |
184 | #define DPMEM_MAGIC 0xC0FFEE11 |
185 | #define IC_HEADER_BYTES 48 |
186 | #define IC_QUEUE_BYTES 4 |
187 | #define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS |
188 | |
189 | /* cluster_type constants */ |
190 | #define CLUSTER_DRIVE 1 |
191 | #define CLUSTER_MOUNTED 2 |
192 | #define CLUSTER_RESERVED 4 |
193 | #define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED) |
194 | |
195 | /* commands for all services, cache service */ |
196 | #define GDT_INIT 0 /* service initialization */ |
197 | #define GDT_READ 1 /* read command */ |
198 | #define GDT_WRITE 2 /* write command */ |
199 | #define GDT_INFO 3 /* information about devices */ |
200 | #define GDT_FLUSH 4 /* flush dirty cache buffers */ |
201 | #define GDT_IOCTL 5 /* ioctl command */ |
202 | #define GDT_DEVTYPE 9 /* additional information */ |
203 | #define GDT_MOUNT 10 /* mount cache device */ |
204 | #define GDT_UNMOUNT 11 /* unmount cache device */ |
205 | #define GDT_SET_FEAT 12 /* set feat. (scatter/gather) */ |
206 | #define GDT_GET_FEAT 13 /* get features */ |
207 | #define GDT_WRITE_THR 16 /* write through */ |
208 | #define GDT_READ_THR 17 /* read through */ |
209 | #define GDT_EXT_INFO 18 /* extended info */ |
210 | #define GDT_RESET 19 /* controller reset */ |
211 | #define GDT_RESERVE_DRV 20 /* reserve host drive */ |
212 | #define GDT_RELEASE_DRV 21 /* release host drive */ |
213 | #define GDT_CLUST_INFO 22 /* cluster info */ |
214 | #define GDT_RW_ATTRIBS 23 /* R/W attribs (write thru,..)*/ |
215 | #define GDT_CLUST_RESET 24 /* releases the cluster drives*/ |
216 | #define GDT_FREEZE_IO 25 /* freezes all IOs */ |
217 | #define GDT_UNFREEZE_IO 26 /* unfreezes all IOs */ |
218 | #define GDT_X_INIT_HOST 29 /* ext. init: 64 bit support */ |
219 | #define GDT_X_INFO 30 /* ext. info for drives>2TB */ |
220 | |
221 | /* raw service commands */ |
222 | #define GDT_RESERVE 14 /* reserve dev. to raw serv. */ |
223 | #define GDT_RELEASE 15 /* release device */ |
224 | #define GDT_RESERVE_ALL 16 /* reserve all devices */ |
225 | #define GDT_RELEASE_ALL 17 /* release all devices */ |
226 | #define GDT_RESET_BUS 18 /* reset bus */ |
227 | #define GDT_SCAN_START 19 /* start device scan */ |
228 | #define GDT_SCAN_END 20 /* stop device scan */ |
229 | #define GDT_X_INIT_RAW 21 /* ext. init: 64 bit support */ |
230 | |
231 | /* screen service commands */ |
232 | #define GDT_REALTIME 3 /* realtime clock to screens. */ |
233 | #define GDT_X_INIT_SCR 4 /* ext. init: 64 bit support */ |
234 | |
235 | /* IOCTL command defines */ |
236 | #define SCSI_DR_INFO 0x00 /* SCSI drive info */ |
237 | #define SCSI_CHAN_CNT 0x05 /* SCSI channel count */ |
238 | #define SCSI_DR_LIST 0x06 /* SCSI drive list */ |
239 | #define SCSI_DEF_CNT 0x15 /* grown/primary defects */ |
240 | #define DSK_STATISTICS 0x4b /* SCSI disk statistics */ |
241 | #define IOCHAN_DESC 0x5d /* description of IO channel */ |
242 | #define IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */ |
243 | #define L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */ |
244 | #define ARRAY_INFO 0x12 /* array drive info */ |
245 | #define ARRAY_DRV_LIST 0x0f /* array drive list */ |
246 | #define ARRAY_DRV_LIST2 0x34 /* array drive list (new) */ |
247 | #define LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */ |
248 | #define CACHE_DRV_CNT 0x01 /* cache drive count */ |
249 | #define CACHE_DRV_LIST 0x02 /* cache drive list */ |
250 | #define CACHE_INFO 0x04 /* cache info */ |
251 | #define CACHE_CONFIG 0x05 /* cache configuration */ |
252 | #define CACHE_DRV_INFO 0x07 /* cache drive info */ |
253 | #define BOARD_FEATURES 0x15 /* controller features */ |
254 | #define BOARD_INFO 0x28 /* controller info */ |
255 | #define SET_PERF_MODES 0x82 /* set mode (coalescing,..) */ |
256 | #define GET_PERF_MODES 0x83 /* get mode */ |
257 | #define CACHE_READ_OEM_STRING_RECORD 0x84 /* read OEM string record */ |
258 | #define HOST_GET 0x10001L /* get host drive list */ |
259 | #define IO_CHANNEL 0x00020000L /* default IO channel */ |
260 | #define INVALID_CHANNEL 0x0000ffffL /* invalid channel */ |
261 | |
262 | /* service errors */ |
263 | #define S_OK 1 /* no error */ |
264 | #define S_GENERR 6 /* general error */ |
265 | #define S_BSY 7 /* controller busy */ |
266 | #define S_CACHE_UNKNOWN 12 /* cache serv.: drive unknown */ |
267 | #define S_RAW_SCSI 12 /* raw serv.: target error */ |
268 | #define S_RAW_ILL 0xff /* raw serv.: illegal */ |
269 | #define S_NOFUNC -2 /* unknown function */ |
270 | #define S_CACHE_RESERV -24 /* cache: reserv. conflict */ |
271 | |
272 | /* timeout values */ |
273 | #define INIT_RETRIES 100000 /* 100000 * 1ms = 100s */ |
274 | #define INIT_TIMEOUT 100000 /* 100000 * 1ms = 100s */ |
275 | #define POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */ |
276 | |
277 | /* priorities */ |
278 | #define DEFAULT_PRI 0x20 |
279 | #define IOCTL_PRI 0x10 |
280 | #define HIGH_PRI 0x08 |
281 | |
282 | /* data directions */ |
283 | #define GDTH_DATA_IN 0x01000000L /* data from target */ |
284 | #define GDTH_DATA_OUT 0x00000000L /* data to target */ |
285 | |
286 | /* BMIC registers (EISA controllers) */ |
287 | #define ID0REG 0x0c80 /* board ID */ |
288 | #define EINTENABREG 0x0c89 /* interrupt enable */ |
289 | #define SEMA0REG 0x0c8a /* command semaphore */ |
290 | #define SEMA1REG 0x0c8b /* status semaphore */ |
291 | #define LDOORREG 0x0c8d /* local doorbell */ |
292 | #define EDENABREG 0x0c8e /* EISA system doorbell enab. */ |
293 | #define EDOORREG 0x0c8f /* EISA system doorbell */ |
294 | #define MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */ |
295 | #define EISAREG 0x0cc0 /* EISA configuration */ |
296 | |
297 | /* other defines */ |
298 | #define LINUX_OS 8 /* used for cache optim. */ |
299 | #define SECS32 0x1f /* round capacity */ |
300 | #define BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */ |
301 | #define LOCALBOARD 0 /* board node always 0 */ |
302 | #define ASYNCINDEX 0 /* cmd index async. event */ |
303 | #define SPEZINDEX 1 /* cmd index unknown service */ |
304 | #define COALINDEX (GDTH_MAXCMDS + 2) |
305 | |
306 | /* features */ |
307 | #define SCATTER_GATHER 1 /* s/g feature */ |
308 | #define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */ |
309 | #define GDT_64BIT 0x200 /* 64bit / drv>2TB support */ |
310 | |
311 | #include "gdth_ioctl.h" |
312 | |
313 | /* screenservice message */ |
314 | typedef struct { |
315 | u32 msg_handle; /* message handle */ |
316 | u32 msg_len; /* size of message */ |
317 | u32 msg_alen; /* answer length */ |
318 | u8 msg_answer; /* answer flag */ |
319 | u8 msg_ext; /* more messages */ |
320 | u8 msg_reserved[2]; |
321 | char msg_text[MSGLEN+2]; /* the message text */ |
322 | } __attribute__((packed)) gdth_msg_str; |
323 | |
324 | |
325 | /* IOCTL data structures */ |
326 | |
327 | /* Status coalescing buffer for returning multiple requests per interrupt */ |
328 | typedef struct { |
329 | u32 status; |
330 | u32 ext_status; |
331 | u32 info0; |
332 | u32 info1; |
333 | } __attribute__((packed)) gdth_coal_status; |
334 | |
335 | /* performance mode data structure */ |
336 | typedef struct { |
337 | u32 version; /* The version of this IOCTL structure. */ |
338 | u32 st_mode; /* 0=dis., 1=st_buf_addr1 valid, 2=both */ |
339 | u32 st_buff_addr1; /* physical address of status buffer 1 */ |
340 | u32 st_buff_u_addr1; /* reserved for 64 bit addressing */ |
341 | u32 st_buff_indx1; /* reserved command idx. for this buffer */ |
342 | u32 st_buff_addr2; /* physical address of status buffer 1 */ |
343 | u32 st_buff_u_addr2; /* reserved for 64 bit addressing */ |
344 | u32 st_buff_indx2; /* reserved command idx. for this buffer */ |
345 | u32 st_buff_size; /* size of each buffer in bytes */ |
346 | u32 cmd_mode; /* 0 = mode disabled, 1 = cmd_buff_addr1 */ |
347 | u32 cmd_buff_addr1; /* physical address of cmd buffer 1 */ |
348 | u32 cmd_buff_u_addr1; /* reserved for 64 bit addressing */ |
349 | u32 cmd_buff_indx1; /* cmd buf addr1 unique identifier */ |
350 | u32 cmd_buff_addr2; /* physical address of cmd buffer 1 */ |
351 | u32 cmd_buff_u_addr2; /* reserved for 64 bit addressing */ |
352 | u32 cmd_buff_indx2; /* cmd buf addr1 unique identifier */ |
353 | u32 cmd_buff_size; /* size of each cmd buffer in bytes */ |
354 | u32 reserved1; |
355 | u32 reserved2; |
356 | } __attribute__((packed)) gdth_perf_modes; |
357 | |
358 | /* SCSI drive info */ |
359 | typedef struct { |
360 | u8 vendor[8]; /* vendor string */ |
361 | u8 product[16]; /* product string */ |
362 | u8 revision[4]; /* revision */ |
363 | u32 sy_rate; /* current rate for sync. tr. */ |
364 | u32 sy_max_rate; /* max. rate for sync. tr. */ |
365 | u32 no_ldrive; /* belongs to this log. drv.*/ |
366 | u32 blkcnt; /* number of blocks */ |
367 | u16 blksize; /* size of block in bytes */ |
368 | u8 available; /* flag: access is available */ |
369 | u8 init; /* medium is initialized */ |
370 | u8 devtype; /* SCSI devicetype */ |
371 | u8 rm_medium; /* medium is removable */ |
372 | u8 wp_medium; /* medium is write protected */ |
373 | u8 ansi; /* SCSI I/II or III? */ |
374 | u8 protocol; /* same as ansi */ |
375 | u8 sync; /* flag: sync. transfer enab. */ |
376 | u8 disc; /* flag: disconnect enabled */ |
377 | u8 queueing; /* flag: command queing enab. */ |
378 | u8 cached; /* flag: caching enabled */ |
379 | u8 target_id; /* target ID of device */ |
380 | u8 lun; /* LUN id of device */ |
381 | u8 orphan; /* flag: drive fragment */ |
382 | u32 last_error; /* sense key or drive state */ |
383 | u32 last_result; /* result of last command */ |
384 | u32 check_errors; /* err. in last surface check */ |
385 | u8 percent; /* progress for surface check */ |
386 | u8 last_check; /* IOCTRL operation */ |
387 | u8 res[2]; |
388 | u32 flags; /* from 1.19/2.19: raw reserv.*/ |
389 | u8 multi_bus; /* multi bus dev? (fibre ch.) */ |
390 | u8 mb_status; /* status: available? */ |
391 | u8 res2[2]; |
392 | u8 mb_alt_status; /* status on second bus */ |
393 | u8 mb_alt_bid; /* number of second bus */ |
394 | u8 mb_alt_tid; /* target id on second bus */ |
395 | u8 res3; |
396 | u8 fc_flag; /* from 1.22/2.22: info valid?*/ |
397 | u8 res4; |
398 | u16 fc_frame_size; /* frame size (bytes) */ |
399 | char wwn[8]; /* world wide name */ |
400 | } __attribute__((packed)) gdth_diskinfo_str; |
401 | |
402 | /* get SCSI channel count */ |
403 | typedef struct { |
404 | u32 channel_no; /* number of channel */ |
405 | u32 drive_cnt; /* drive count */ |
406 | u8 siop_id; /* SCSI processor ID */ |
407 | u8 siop_state; /* SCSI processor state */ |
408 | } __attribute__((packed)) gdth_getch_str; |
409 | |
410 | /* get SCSI drive numbers */ |
411 | typedef struct { |
412 | u32 sc_no; /* SCSI channel */ |
413 | u32 sc_cnt; /* sc_list[] elements */ |
414 | u32 sc_list[MAXID]; /* minor device numbers */ |
415 | } __attribute__((packed)) gdth_drlist_str; |
416 | |
417 | /* get grown/primary defect count */ |
418 | typedef struct { |
419 | u8 sddc_type; /* 0x08: grown, 0x10: prim. */ |
420 | u8 sddc_format; /* list entry format */ |
421 | u8 sddc_len; /* list entry length */ |
422 | u8 sddc_res; |
423 | u32 sddc_cnt; /* entry count */ |
424 | } __attribute__((packed)) gdth_defcnt_str; |
425 | |
426 | /* disk statistics */ |
427 | typedef struct { |
428 | u32 bid; /* SCSI channel */ |
429 | u32 first; /* first SCSI disk */ |
430 | u32 entries; /* number of elements */ |
431 | u32 count; /* (R) number of init. el. */ |
432 | u32 mon_time; /* time stamp */ |
433 | struct { |
434 | u8 tid; /* target ID */ |
435 | u8 lun; /* LUN */ |
436 | u8 res[2]; |
437 | u32 blk_size; /* block size in bytes */ |
438 | u32 rd_count; /* bytes read */ |
439 | u32 wr_count; /* bytes written */ |
440 | u32 rd_blk_count; /* blocks read */ |
441 | u32 wr_blk_count; /* blocks written */ |
442 | u32 retries; /* retries */ |
443 | u32 reassigns; /* reassigns */ |
444 | } __attribute__((packed)) list[1]; |
445 | } __attribute__((packed)) gdth_dskstat_str; |
446 | |
447 | /* IO channel header */ |
448 | typedef struct { |
449 | u32 version; /* version (-1UL: newest) */ |
450 | u8 list_entries; /* list entry count */ |
451 | u8 first_chan; /* first channel number */ |
452 | u8 last_chan; /* last channel number */ |
453 | u8 chan_count; /* (R) channel count */ |
454 | u32 list_offset; /* offset of list[0] */ |
455 | } __attribute__((packed)) gdth_iochan_header; |
456 | |
457 | /* get IO channel description */ |
458 | typedef struct { |
459 | gdth_iochan_header hdr; |
460 | struct { |
461 | u32 address; /* channel address */ |
462 | u8 type; /* type (SCSI, FCAL) */ |
463 | u8 local_no; /* local number */ |
464 | u16 features; /* channel features */ |
465 | } __attribute__((packed)) list[MAXBUS]; |
466 | } __attribute__((packed)) gdth_iochan_str; |
467 | |
468 | /* get raw IO channel description */ |
469 | typedef struct { |
470 | gdth_iochan_header hdr; |
471 | struct { |
472 | u8 proc_id; /* processor id */ |
473 | u8 proc_defect; /* defect ? */ |
474 | u8 reserved[2]; |
475 | } __attribute__((packed)) list[MAXBUS]; |
476 | } __attribute__((packed)) gdth_raw_iochan_str; |
477 | |
478 | /* array drive component */ |
479 | typedef struct { |
480 | u32 al_controller; /* controller ID */ |
481 | u8 al_cache_drive; /* cache drive number */ |
482 | u8 al_status; /* cache drive state */ |
483 | u8 al_res[2]; |
484 | } __attribute__((packed)) gdth_arraycomp_str; |
485 | |
486 | /* array drive information */ |
487 | typedef struct { |
488 | u8 ai_type; /* array type (RAID0,4,5) */ |
489 | u8 ai_cache_drive_cnt; /* active cachedrives */ |
490 | u8 ai_state; /* array drive state */ |
491 | u8 ai_master_cd; /* master cachedrive */ |
492 | u32 ai_master_controller; /* ID of master controller */ |
493 | u32 ai_size; /* user capacity [sectors] */ |
494 | u32 ai_striping_size; /* striping size [sectors] */ |
495 | u32 ai_secsize; /* sector size [bytes] */ |
496 | u32 ai_err_info; /* failed cache drive */ |
497 | u8 ai_name[8]; /* name of the array drive */ |
498 | u8 ai_controller_cnt; /* number of controllers */ |
499 | u8 ai_removable; /* flag: removable */ |
500 | u8 ai_write_protected; /* flag: write protected */ |
501 | u8 ai_devtype; /* type: always direct access */ |
502 | gdth_arraycomp_str ai_drives[35]; /* drive components: */ |
503 | u8 ai_drive_entries; /* number of drive components */ |
504 | u8 ai_protected; /* protection flag */ |
505 | u8 ai_verify_state; /* state of a parity verify */ |
506 | u8 ai_ext_state; /* extended array drive state */ |
507 | u8 ai_expand_state; /* array expand state (>=2.18)*/ |
508 | u8 ai_reserved[3]; |
509 | } __attribute__((packed)) gdth_arrayinf_str; |
510 | |
511 | /* get array drive list */ |
512 | typedef struct { |
513 | u32 controller_no; /* controller no. */ |
514 | u8 cd_handle; /* master cachedrive */ |
515 | u8 is_arrayd; /* Flag: is array drive? */ |
516 | u8 is_master; /* Flag: is array master? */ |
517 | u8 is_parity; /* Flag: is parity drive? */ |
518 | u8 is_hotfix; /* Flag: is hotfix drive? */ |
519 | u8 res[3]; |
520 | } __attribute__((packed)) gdth_alist_str; |
521 | |
522 | typedef struct { |
523 | u32 entries_avail; /* allocated entries */ |
524 | u32 entries_init; /* returned entries */ |
525 | u32 first_entry; /* first entry number */ |
526 | u32 list_offset; /* offset of following list */ |
527 | gdth_alist_str list[1]; /* list */ |
528 | } __attribute__((packed)) gdth_arcdl_str; |
529 | |
530 | /* cache info/config IOCTL */ |
531 | typedef struct { |
532 | u32 version; /* firmware version */ |
533 | u16 state; /* cache state (on/off) */ |
534 | u16 strategy; /* cache strategy */ |
535 | u16 write_back; /* write back state (on/off) */ |
536 | u16 block_size; /* cache block size */ |
537 | } __attribute__((packed)) gdth_cpar_str; |
538 | |
539 | typedef struct { |
540 | u32 csize; /* cache size */ |
541 | u32 read_cnt; /* read/write counter */ |
542 | u32 write_cnt; |
543 | u32 tr_hits; /* hits */ |
544 | u32 sec_hits; |
545 | u32 sec_miss; /* misses */ |
546 | } __attribute__((packed)) gdth_cstat_str; |
547 | |
548 | typedef struct { |
549 | gdth_cpar_str cpar; |
550 | gdth_cstat_str cstat; |
551 | } __attribute__((packed)) gdth_cinfo_str; |
552 | |
553 | /* cache drive info */ |
554 | typedef struct { |
555 | u8 cd_name[8]; /* cache drive name */ |
556 | u32 cd_devtype; /* SCSI devicetype */ |
557 | u32 cd_ldcnt; /* number of log. drives */ |
558 | u32 cd_last_error; /* last error */ |
559 | u8 cd_initialized; /* drive is initialized */ |
560 | u8 cd_removable; /* media is removable */ |
561 | u8 cd_write_protected; /* write protected */ |
562 | u8 cd_flags; /* Pool Hot Fix? */ |
563 | u32 ld_blkcnt; /* number of blocks */ |
564 | u32 ld_blksize; /* blocksize */ |
565 | u32 ld_dcnt; /* number of disks */ |
566 | u32 ld_slave; /* log. drive index */ |
567 | u32 ld_dtype; /* type of logical drive */ |
568 | u32 ld_last_error; /* last error */ |
569 | u8 ld_name[8]; /* log. drive name */ |
570 | u8 ld_error; /* error */ |
571 | } __attribute__((packed)) gdth_cdrinfo_str; |
572 | |
573 | /* OEM string */ |
574 | typedef struct { |
575 | u32 ctl_version; |
576 | u32 file_major_version; |
577 | u32 file_minor_version; |
578 | u32 buffer_size; |
579 | u32 cpy_count; |
580 | u32 ext_error; |
581 | u32 oem_id; |
582 | u32 board_id; |
583 | } __attribute__((packed)) gdth_oem_str_params; |
584 | |
585 | typedef struct { |
586 | u8 product_0_1_name[16]; |
587 | u8 product_4_5_name[16]; |
588 | u8 product_cluster_name[16]; |
589 | u8 product_reserved[16]; |
590 | u8 scsi_cluster_target_vendor_id[16]; |
591 | u8 cluster_raid_fw_name[16]; |
592 | u8 oem_brand_name[16]; |
593 | u8 oem_raid_type[16]; |
594 | u8 bios_type[13]; |
595 | u8 bios_title[50]; |
596 | u8 oem_company_name[37]; |
597 | u32 pci_id_1; |
598 | u32 pci_id_2; |
599 | u8 validation_status[80]; |
600 | u8 reserved_1[4]; |
601 | u8 scsi_host_drive_inquiry_vendor_id[16]; |
602 | u8 library_file_template[16]; |
603 | u8 reserved_2[16]; |
604 | u8 tool_name_1[32]; |
605 | u8 tool_name_2[32]; |
606 | u8 tool_name_3[32]; |
607 | u8 oem_contact_1[84]; |
608 | u8 oem_contact_2[84]; |
609 | u8 oem_contact_3[84]; |
610 | } __attribute__((packed)) gdth_oem_str; |
611 | |
612 | typedef struct { |
613 | gdth_oem_str_params params; |
614 | gdth_oem_str text; |
615 | } __attribute__((packed)) gdth_oem_str_ioctl; |
616 | |
617 | /* board features */ |
618 | typedef struct { |
619 | u8 chaining; /* Chaining supported */ |
620 | u8 striping; /* Striping (RAID-0) supp. */ |
621 | u8 mirroring; /* Mirroring (RAID-1) supp. */ |
622 | u8 raid; /* RAID-4/5/10 supported */ |
623 | } __attribute__((packed)) gdth_bfeat_str; |
624 | |
625 | /* board info IOCTL */ |
626 | typedef struct { |
627 | u32 ser_no; /* serial no. */ |
628 | u8 oem_id[2]; /* OEM ID */ |
629 | u16 ep_flags; /* eprom flags */ |
630 | u32 proc_id; /* processor ID */ |
631 | u32 memsize; /* memory size (bytes) */ |
632 | u8 mem_banks; /* memory banks */ |
633 | u8 chan_type; /* channel type */ |
634 | u8 chan_count; /* channel count */ |
635 | u8 rdongle_pres; /* dongle present? */ |
636 | u32 epr_fw_ver; /* (eprom) firmware version */ |
637 | u32 upd_fw_ver; /* (update) firmware version */ |
638 | u32 upd_revision; /* update revision */ |
639 | char type_string[16]; /* controller name */ |
640 | char raid_string[16]; /* RAID firmware name */ |
641 | u8 update_pres; /* update present? */ |
642 | u8 xor_pres; /* XOR engine present? */ |
643 | u8 prom_type; /* ROM type (eprom/flash) */ |
644 | u8 prom_count; /* number of ROM devices */ |
645 | u32 dup_pres; /* duplexing module present? */ |
646 | u32 chan_pres; /* number of expansion chn. */ |
647 | u32 mem_pres; /* memory expansion inst. ? */ |
648 | u8 ft_bus_system; /* fault bus supported? */ |
649 | u8 subtype_valid; /* board_subtype valid? */ |
650 | u8 board_subtype; /* subtype/hardware level */ |
651 | u8 ramparity_pres; /* RAM parity check hardware? */ |
652 | } __attribute__((packed)) gdth_binfo_str; |
653 | |
654 | /* get host drive info */ |
655 | typedef struct { |
656 | char name[8]; /* host drive name */ |
657 | u32 size; /* size (sectors) */ |
658 | u8 host_drive; /* host drive number */ |
659 | u8 log_drive; /* log. drive (master) */ |
660 | u8 reserved; |
661 | u8 rw_attribs; /* r/w attribs */ |
662 | u32 start_sec; /* start sector */ |
663 | } __attribute__((packed)) gdth_hentry_str; |
664 | |
665 | typedef struct { |
666 | u32 entries; /* entry count */ |
667 | u32 offset; /* offset of entries */ |
668 | u8 secs_p_head; /* sectors/head */ |
669 | u8 heads_p_cyl; /* heads/cylinder */ |
670 | u8 reserved; |
671 | u8 clust_drvtype; /* cluster drive type */ |
672 | u32 location; /* controller number */ |
673 | gdth_hentry_str entry[MAX_HDRIVES]; /* entries */ |
674 | } __attribute__((packed)) gdth_hget_str; |
675 | |
676 | |
677 | /* DPRAM structures */ |
678 | |
679 | /* interface area ISA/PCI */ |
680 | typedef struct { |
681 | u8 S_Cmd_Indx; /* special command */ |
682 | u8 volatile S_Status; /* status special command */ |
683 | u16 reserved1; |
684 | u32 S_Info[4]; /* add. info special command */ |
685 | u8 volatile Sema0; /* command semaphore */ |
686 | u8 reserved2[3]; |
687 | u8 Cmd_Index; /* command number */ |
688 | u8 reserved3[3]; |
689 | u16 volatile Status; /* command status */ |
690 | u16 Service; /* service(for async.events) */ |
691 | u32 Info[2]; /* additional info */ |
692 | struct { |
693 | u16 offset; /* command offs. in the DPRAM*/ |
694 | u16 serv_id; /* service */ |
695 | } __attribute__((packed)) comm_queue[MAXOFFSETS]; /* command queue */ |
696 | u32 bios_reserved[2]; |
697 | u8 gdt_dpr_cmd[1]; /* commands */ |
698 | } __attribute__((packed)) gdt_dpr_if; |
699 | |
700 | /* SRAM structure PCI controllers */ |
701 | typedef struct { |
702 | u32 magic; /* controller ID from BIOS */ |
703 | u16 need_deinit; /* switch betw. BIOS/driver */ |
704 | u8 switch_support; /* see need_deinit */ |
705 | u8 padding[9]; |
706 | u8 os_used[16]; /* OS code per service */ |
707 | u8 unused[28]; |
708 | u8 fw_magic; /* contr. ID from firmware */ |
709 | } __attribute__((packed)) gdt_pci_sram; |
710 | |
711 | /* SRAM structure EISA controllers (but NOT GDT3000/3020) */ |
712 | typedef struct { |
713 | u8 os_used[16]; /* OS code per service */ |
714 | u16 need_deinit; /* switch betw. BIOS/driver */ |
715 | u8 switch_support; /* see need_deinit */ |
716 | u8 padding; |
717 | } __attribute__((packed)) gdt_eisa_sram; |
718 | |
719 | |
720 | /* DPRAM ISA controllers */ |
721 | typedef struct { |
722 | union { |
723 | struct { |
724 | u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */ |
725 | u32 magic; /* controller (EISA) ID */ |
726 | u16 need_deinit; /* switch betw. BIOS/driver */ |
727 | u8 switch_support; /* see need_deinit */ |
728 | u8 padding[9]; |
729 | u8 os_used[16]; /* OS code per service */ |
730 | } __attribute__((packed)) dp_sram; |
731 | u8 bios_area[0x4000]; /* 16KB reserved for BIOS */ |
732 | } bu; |
733 | union { |
734 | gdt_dpr_if ic; /* interface area */ |
735 | u8 if_area[0x3000]; /* 12KB for interface */ |
736 | } u; |
737 | struct { |
738 | u8 memlock; /* write protection DPRAM */ |
739 | u8 event; /* release event */ |
740 | u8 irqen; /* board interrupts enable */ |
741 | u8 irqdel; /* acknowledge board int. */ |
742 | u8 volatile Sema1; /* status semaphore */ |
743 | u8 rq; /* IRQ/DRQ configuration */ |
744 | } __attribute__((packed)) io; |
745 | } __attribute__((packed)) gdt2_dpram_str; |
746 | |
747 | /* DPRAM PCI controllers */ |
748 | typedef struct { |
749 | union { |
750 | gdt_dpr_if ic; /* interface area */ |
751 | u8 if_area[0xff0-sizeof(gdt_pci_sram)]; |
752 | } u; |
753 | gdt_pci_sram gdt6sr; /* SRAM structure */ |
754 | struct { |
755 | u8 unused0[1]; |
756 | u8 volatile Sema1; /* command semaphore */ |
757 | u8 unused1[3]; |
758 | u8 irqen; /* board interrupts enable */ |
759 | u8 unused2[2]; |
760 | u8 event; /* release event */ |
761 | u8 unused3[3]; |
762 | u8 irqdel; /* acknowledge board int. */ |
763 | u8 unused4[3]; |
764 | } __attribute__((packed)) io; |
765 | } __attribute__((packed)) gdt6_dpram_str; |
766 | |
767 | /* PLX register structure (new PCI controllers) */ |
768 | typedef struct { |
769 | u8 cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/ |
770 | u8 unused1[0x3f]; |
771 | u8 volatile sema0_reg; /* command semaphore */ |
772 | u8 volatile sema1_reg; /* status semaphore */ |
773 | u8 unused2[2]; |
774 | u16 volatile status; /* command status */ |
775 | u16 service; /* service */ |
776 | u32 info[2]; /* additional info */ |
777 | u8 unused3[0x10]; |
778 | u8 ldoor_reg; /* PCI to local doorbell */ |
779 | u8 unused4[3]; |
780 | u8 volatile edoor_reg; /* local to PCI doorbell */ |
781 | u8 unused5[3]; |
782 | u8 control0; /* control0 register(unused) */ |
783 | u8 control1; /* board interrupts enable */ |
784 | u8 unused6[0x16]; |
785 | } __attribute__((packed)) gdt6c_plx_regs; |
786 | |
787 | /* DPRAM new PCI controllers */ |
788 | typedef struct { |
789 | union { |
790 | gdt_dpr_if ic; /* interface area */ |
791 | u8 if_area[0x4000-sizeof(gdt_pci_sram)]; |
792 | } u; |
793 | gdt_pci_sram gdt6sr; /* SRAM structure */ |
794 | } __attribute__((packed)) gdt6c_dpram_str; |
795 | |
796 | /* i960 register structure (PCI MPR controllers) */ |
797 | typedef struct { |
798 | u8 unused1[16]; |
799 | u8 volatile sema0_reg; /* command semaphore */ |
800 | u8 unused2; |
801 | u8 volatile sema1_reg; /* status semaphore */ |
802 | u8 unused3; |
803 | u16 volatile status; /* command status */ |
804 | u16 service; /* service */ |
805 | u32 info[2]; /* additional info */ |
806 | u8 ldoor_reg; /* PCI to local doorbell */ |
807 | u8 unused4[11]; |
808 | u8 volatile edoor_reg; /* local to PCI doorbell */ |
809 | u8 unused5[7]; |
810 | u8 edoor_en_reg; /* board interrupts enable */ |
811 | u8 unused6[27]; |
812 | u32 unused7[939]; |
813 | u32 severity; |
814 | char evt_str[256]; /* event string */ |
815 | } __attribute__((packed)) gdt6m_i960_regs; |
816 | |
817 | /* DPRAM PCI MPR controllers */ |
818 | typedef struct { |
819 | gdt6m_i960_regs i960r; /* 4KB i960 registers */ |
820 | union { |
821 | gdt_dpr_if ic; /* interface area */ |
822 | u8 if_area[0x3000-sizeof(gdt_pci_sram)]; |
823 | } u; |
824 | gdt_pci_sram gdt6sr; /* SRAM structure */ |
825 | } __attribute__((packed)) gdt6m_dpram_str; |
826 | |
827 | |
828 | /* PCI resources */ |
829 | typedef struct { |
830 | struct pci_dev *pdev; |
831 | unsigned long dpmem; /* DPRAM address */ |
832 | unsigned long io; /* IO address */ |
833 | } gdth_pci_str; |
834 | |
835 | |
836 | /* controller information structure */ |
837 | typedef struct { |
838 | struct Scsi_Host *shost; |
839 | struct list_head list; |
840 | u16 hanum; |
841 | u16 oem_id; /* OEM */ |
842 | u16 type; /* controller class */ |
843 | u32 stype; /* subtype (PCI: device ID) */ |
844 | u16 fw_vers; /* firmware version */ |
845 | u16 cache_feat; /* feat. cache serv. (s/g,..)*/ |
846 | u16 raw_feat; /* feat. raw service (s/g,..)*/ |
847 | u16 screen_feat; /* feat. raw service (s/g,..)*/ |
848 | u16 bmic; /* BMIC address (EISA) */ |
849 | void __iomem *brd; /* DPRAM address */ |
850 | u32 brd_phys; /* slot number/BIOS address */ |
851 | gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */ |
852 | gdth_cmd_str cmdext; |
853 | gdth_cmd_str *pccb; /* address command structure */ |
854 | u32 ccb_phys; /* phys. address */ |
855 | #ifdef INT_COAL |
856 | gdth_coal_status *coal_stat; /* buffer for coalescing int.*/ |
857 | u64 coal_stat_phys; /* phys. address */ |
858 | #endif |
859 | char *pscratch; /* scratch (DMA) buffer */ |
860 | u64 scratch_phys; /* phys. address */ |
861 | u8 scratch_busy; /* in use? */ |
862 | u8 dma64_support; /* 64-bit DMA supported? */ |
863 | gdth_msg_str *pmsg; /* message buffer */ |
864 | u64 msg_phys; /* phys. address */ |
865 | u8 scan_mode; /* current scan mode */ |
866 | u8 irq; /* IRQ */ |
867 | u8 drq; /* DRQ (ISA controllers) */ |
868 | u16 status; /* command status */ |
869 | u16 service; /* service/firmware ver./.. */ |
870 | u32 info; |
871 | u32 info2; /* additional info */ |
872 | Scsi_Cmnd *req_first; /* top of request queue */ |
873 | struct { |
874 | u8 present; /* Flag: host drive present? */ |
875 | u8 is_logdrv; /* Flag: log. drive (master)? */ |
876 | u8 is_arraydrv; /* Flag: array drive? */ |
877 | u8 is_master; /* Flag: array drive master? */ |
878 | u8 is_parity; /* Flag: parity drive? */ |
879 | u8 is_hotfix; /* Flag: hotfix drive? */ |
880 | u8 master_no; /* number of master drive */ |
881 | u8 lock; /* drive locked? (hot plug) */ |
882 | u8 heads; /* mapping */ |
883 | u8 secs; |
884 | u16 devtype; /* further information */ |
885 | u64 size; /* capacity */ |
886 | u8 ldr_no; /* log. drive no. */ |
887 | u8 rw_attribs; /* r/w attributes */ |
888 | u8 cluster_type; /* cluster properties */ |
889 | u8 media_changed; /* Flag:MOUNT/UNMOUNT occurred */ |
890 | u32 start_sec; /* start sector */ |
891 | } hdr[MAX_LDRIVES]; /* host drives */ |
892 | struct { |
893 | u8 lock; /* channel locked? (hot plug) */ |
894 | u8 pdev_cnt; /* physical device count */ |
895 | u8 local_no; /* local channel number */ |
896 | u8 io_cnt[MAXID]; /* current IO count */ |
897 | u32 address; /* channel address */ |
898 | u32 id_list[MAXID]; /* IDs of the phys. devices */ |
899 | } raw[MAXBUS]; /* SCSI channels */ |
900 | struct { |
901 | Scsi_Cmnd *cmnd; /* pending request */ |
902 | u16 service; /* service */ |
903 | } cmd_tab[GDTH_MAXCMDS]; /* table of pend. requests */ |
904 | struct gdth_cmndinfo { /* per-command private info */ |
905 | int index; |
906 | int internal_command; /* don't call scsi_done */ |
907 | gdth_cmd_str *internal_cmd_str; /* crier for internal messages*/ |
908 | dma_addr_t sense_paddr; /* sense dma-addr */ |
909 | u8 priority; |
910 | int timeout_count; /* # of timeout calls */ |
911 | volatile int wait_for_completion; |
912 | u16 status; |
913 | u32 info; |
914 | enum dma_data_direction dma_dir; |
915 | int phase; /* ???? */ |
916 | int OpCode; |
917 | } cmndinfo[GDTH_MAXCMDS]; /* index==0 is free */ |
918 | u8 bus_cnt; /* SCSI bus count */ |
919 | u8 tid_cnt; /* Target ID count */ |
920 | u8 bus_id[MAXBUS]; /* IOP IDs */ |
921 | u8 virt_bus; /* number of virtual bus */ |
922 | u8 more_proc; /* more /proc info supported */ |
923 | u16 cmd_cnt; /* command count in DPRAM */ |
924 | u16 cmd_len; /* length of actual command */ |
925 | u16 cmd_offs_dpmem; /* actual offset in DPRAM */ |
926 | u16 ic_all_size; /* sizeof DPRAM interf. area */ |
927 | gdth_cpar_str cpar; /* controller cache par. */ |
928 | gdth_bfeat_str bfeat; /* controller features */ |
929 | gdth_binfo_str binfo; /* controller info */ |
930 | gdth_evt_data dvr; /* event structure */ |
931 | spinlock_t smp_lock; |
932 | struct pci_dev *pdev; |
933 | char oem_name[8]; |
934 | #ifdef GDTH_DMA_STATISTICS |
935 | unsigned long dma32_cnt, dma64_cnt; /* statistics: DMA buffer */ |
936 | #endif |
937 | struct scsi_device *sdev; |
938 | } gdth_ha_str; |
939 | |
940 | static inline struct gdth_cmndinfo *gdth_cmnd_priv(struct scsi_cmnd* cmd) |
941 | { |
942 | return (struct gdth_cmndinfo *)cmd->host_scribble; |
943 | } |
944 | |
945 | /* INQUIRY data format */ |
946 | typedef struct { |
947 | u8 type_qual; |
948 | u8 modif_rmb; |
949 | u8 version; |
950 | u8 resp_aenc; |
951 | u8 add_length; |
952 | u8 reserved1; |
953 | u8 reserved2; |
954 | u8 misc; |
955 | u8 vendor[8]; |
956 | u8 product[16]; |
957 | u8 revision[4]; |
958 | } __attribute__((packed)) gdth_inq_data; |
959 | |
960 | /* READ_CAPACITY data format */ |
961 | typedef struct { |
962 | u32 last_block_no; |
963 | u32 block_length; |
964 | } __attribute__((packed)) gdth_rdcap_data; |
965 | |
966 | /* READ_CAPACITY (16) data format */ |
967 | typedef struct { |
968 | u64 last_block_no; |
969 | u32 block_length; |
970 | } __attribute__((packed)) gdth_rdcap16_data; |
971 | |
972 | /* REQUEST_SENSE data format */ |
973 | typedef struct { |
974 | u8 errorcode; |
975 | u8 segno; |
976 | u8 key; |
977 | u32 info; |
978 | u8 add_length; |
979 | u32 cmd_info; |
980 | u8 adsc; |
981 | u8 adsq; |
982 | u8 fruc; |
983 | u8 key_spec[3]; |
984 | } __attribute__((packed)) gdth_sense_data; |
985 | |
986 | /* MODE_SENSE data format */ |
987 | typedef struct { |
988 | struct { |
989 | u8 data_length; |
990 | u8 med_type; |
991 | u8 dev_par; |
992 | u8 bd_length; |
993 | } __attribute__((packed)) hd; |
994 | struct { |
995 | u8 dens_code; |
996 | u8 block_count[3]; |
997 | u8 reserved; |
998 | u8 block_length[3]; |
999 | } __attribute__((packed)) bd; |
1000 | } __attribute__((packed)) gdth_modep_data; |
1001 | |
1002 | /* stack frame */ |
1003 | typedef struct { |
1004 | unsigned long b[10]; /* 32/64 bit compiler ! */ |
1005 | } __attribute__((packed)) gdth_stackframe; |
1006 | |
1007 | |
1008 | /* function prototyping */ |
1009 | |
1010 | int gdth_proc_info(struct Scsi_Host *, char *,char **,off_t,int,int); |
1011 | |
1012 | #endif |
1013 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9