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Root/drivers/tty/serial/samsung.c

1	/*
2	* Driver core for Samsung SoC onboard UARTs.
3	*
4	* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5	* http://armlinux.simtec.co.uk/
6	*
7	* This program is free software; you can redistribute it and/or modify
8	* it under the terms of the GNU General Public License version 2 as
9	* published by the Free Software Foundation.
10	*/
11
12	/* Hote on 2410 error handling
13	*
14	* The s3c2410 manual has a love/hate affair with the contents of the
15	* UERSTAT register in the UART blocks, and keeps marking some of the
16	* error bits as reserved. Having checked with the s3c2410x01,
17	* it copes with BREAKs properly, so I am happy to ignore the RESERVED
18	* feature from the latter versions of the manual.
19	*
20	* If it becomes aparrent that latter versions of the 2410 remove these
21	* bits, then action will have to be taken to differentiate the versions
22	* and change the policy on BREAK
23	*
24	* BJD, 04-Nov-2004
25	*/
26
27	#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28	#define SUPPORT_SYSRQ
29	#endif
30
31	#include <linux/module.h>
32	#include <linux/ioport.h>
33	#include <linux/io.h>
34	#include <linux/platform_device.h>
35	#include <linux/init.h>
36	#include <linux/sysrq.h>
37	#include <linux/console.h>
38	#include <linux/tty.h>
39	#include <linux/tty_flip.h>
40	#include <linux/serial_core.h>
41	#include <linux/serial.h>
42	#include <linux/delay.h>
43	#include <linux/clk.h>
44	#include <linux/cpufreq.h>
45	#include <linux/of.h>
46
47	#include <asm/irq.h>
48
49	#include <mach/hardware.h>
50
51	#include <plat/regs-serial.h>
52	#include <plat/clock.h>
53
54	#include "samsung.h"
55
56	/* UART name and device definitions */
57
58	#define S3C24XX_SERIAL_NAME "ttySAC"
59	#define S3C24XX_SERIAL_MAJOR 204
60	#define S3C24XX_SERIAL_MINOR 64
61
62	/* macros to change one thing to another */
63
64	#define tx_enabled(port) ((port)->unused[0])
65	#define rx_enabled(port) ((port)->unused[1])
66
67	/* flag to ignore all characters coming in */
68	#define RXSTAT_DUMMY_READ (0x10000000)
69
70	static inline struct s3c24xx_uart_port to_ourport(struct uart_port port)
71	{
72	return container_of(port, struct s3c24xx_uart_port, port);
73	}
74
75	/* translate a port to the device name */
76
77	static inline const char s3c24xx_serial_portname(struct uart_port port)
78	{
79	return to_platform_device(port->dev)->name;
80	}
81
82	static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83	{
84	return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
85	}
86
87	/*
88	* s3c64xx and later SoC's include the interrupt mask and status registers in
89	* the controller itself, unlike the s3c24xx SoC's which have these registers
90	* in the interrupt controller. Check if the port type is s3c64xx or higher.
91	*/
92	static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93	{
94	return to_ourport(port)->info->type == PORT_S3C6400;
95	}
96
97	static void s3c24xx_serial_rx_enable(struct uart_port *port)
98	{
99	unsigned long flags;
100	unsigned int ucon, ufcon;
101	int count = 10000;
102
103	spin_lock_irqsave(&port->lock, flags);
104
105	while (--count && !s3c24xx_serial_txempty_nofifo(port))
106	udelay(100);
107
108	ufcon = rd_regl(port, S3C2410_UFCON);
109	ufcon \|= S3C2410_UFCON_RESETRX;
110	wr_regl(port, S3C2410_UFCON, ufcon);
111
112	ucon = rd_regl(port, S3C2410_UCON);
113	ucon \|= S3C2410_UCON_RXIRQMODE;
114	wr_regl(port, S3C2410_UCON, ucon);
115
116	rx_enabled(port) = 1;
117	spin_unlock_irqrestore(&port->lock, flags);
118	}
119
120	static void s3c24xx_serial_rx_disable(struct uart_port *port)
121	{
122	unsigned long flags;
123	unsigned int ucon;
124
125	spin_lock_irqsave(&port->lock, flags);
126
127	ucon = rd_regl(port, S3C2410_UCON);
128	ucon &= ~S3C2410_UCON_RXIRQMODE;
129	wr_regl(port, S3C2410_UCON, ucon);
130
131	rx_enabled(port) = 0;
132	spin_unlock_irqrestore(&port->lock, flags);
133	}
134
135	static void s3c24xx_serial_stop_tx(struct uart_port *port)
136	{
137	struct s3c24xx_uart_port *ourport = to_ourport(port);
138
139	if (tx_enabled(port)) {
140	if (s3c24xx_serial_has_interrupt_mask(port))
141	__set_bit(S3C64XX_UINTM_TXD,
142	portaddrl(port, S3C64XX_UINTM));
143	else
144	disable_irq_nosync(ourport->tx_irq);
145	tx_enabled(port) = 0;
146	if (port->flags & UPF_CONS_FLOW)
147	s3c24xx_serial_rx_enable(port);
148	}
149	}
150
151	static void s3c24xx_serial_start_tx(struct uart_port *port)
152	{
153	struct s3c24xx_uart_port *ourport = to_ourport(port);
154
155	if (!tx_enabled(port)) {
156	if (port->flags & UPF_CONS_FLOW)
157	s3c24xx_serial_rx_disable(port);
158
159	if (s3c24xx_serial_has_interrupt_mask(port))
160	__clear_bit(S3C64XX_UINTM_TXD,
161	portaddrl(port, S3C64XX_UINTM));
162	else
163	enable_irq(ourport->tx_irq);
164	tx_enabled(port) = 1;
165	}
166	}
167
168	static void s3c24xx_serial_stop_rx(struct uart_port *port)
169	{
170	struct s3c24xx_uart_port *ourport = to_ourport(port);
171
172	if (rx_enabled(port)) {
173	dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
174	if (s3c24xx_serial_has_interrupt_mask(port))
175	__set_bit(S3C64XX_UINTM_RXD,
176	portaddrl(port, S3C64XX_UINTM));
177	else
178	disable_irq_nosync(ourport->rx_irq);
179	rx_enabled(port) = 0;
180	}
181	}
182
183	static void s3c24xx_serial_enable_ms(struct uart_port *port)
184	{
185	}
186
187	static inline struct s3c24xx_uart_info s3c24xx_port_to_info(struct uart_port port)
188	{
189	return to_ourport(port)->info;
190	}
191
192	static inline struct s3c2410_uartcfg s3c24xx_port_to_cfg(struct uart_port port)
193	{
194	struct s3c24xx_uart_port *ourport;
195
196	if (port->dev == NULL)
197	return NULL;
198
199	ourport = container_of(port, struct s3c24xx_uart_port, port);
200	return ourport->cfg;
201	}
202
203	static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204	unsigned long ufstat)
205	{
206	struct s3c24xx_uart_info *info = ourport->info;
207
208	if (ufstat & info->rx_fifofull)
209	return ourport->port.fifosize;
210
211	return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
212	}
213
214
215	/* ? - where has parity gone?? */
216	#define S3C2410_UERSTAT_PARITY (0x1000)
217
218	static irqreturn_t
219	s3c24xx_serial_rx_chars(int irq, void *dev_id)
220	{
221	struct s3c24xx_uart_port *ourport = dev_id;
222	struct uart_port *port = &ourport->port;
223	unsigned int ufcon, ch, flag, ufstat, uerstat;
224	unsigned long flags;
225	int max_count = 64;
226
227	spin_lock_irqsave(&port->lock, flags);
228
229	while (max_count-- > 0) {
230	ufcon = rd_regl(port, S3C2410_UFCON);
231	ufstat = rd_regl(port, S3C2410_UFSTAT);
232
233	if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
234	break;
235
236	uerstat = rd_regl(port, S3C2410_UERSTAT);
237	ch = rd_regb(port, S3C2410_URXH);
238
239	if (port->flags & UPF_CONS_FLOW) {
240	int txe = s3c24xx_serial_txempty_nofifo(port);
241
242	if (rx_enabled(port)) {
243	if (!txe) {
244	rx_enabled(port) = 0;
245	continue;
246	}
247	} else {
248	if (txe) {
249	ufcon \|= S3C2410_UFCON_RESETRX;
250	wr_regl(port, S3C2410_UFCON, ufcon);
251	rx_enabled(port) = 1;
252	goto out;
253	}
254	continue;
255	}
256	}
257
258	/* insert the character into the buffer */
259
260	flag = TTY_NORMAL;
261	port->icount.rx++;
262
263	if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
264	dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
265	ch, uerstat);
266
267	/* check for break */
268	if (uerstat & S3C2410_UERSTAT_BREAK) {
269	dbg("break!\n");
270	port->icount.brk++;
271	if (uart_handle_break(port))
272	goto ignore_char;
273	}
274
275	if (uerstat & S3C2410_UERSTAT_FRAME)
276	port->icount.frame++;
277	if (uerstat & S3C2410_UERSTAT_OVERRUN)
278	port->icount.overrun++;
279
280	uerstat &= port->read_status_mask;
281
282	if (uerstat & S3C2410_UERSTAT_BREAK)
283	flag = TTY_BREAK;
284	else if (uerstat & S3C2410_UERSTAT_PARITY)
285	flag = TTY_PARITY;
286	else if (uerstat & (S3C2410_UERSTAT_FRAME \|
287	S3C2410_UERSTAT_OVERRUN))
288	flag = TTY_FRAME;
289	}
290
291	if (uart_handle_sysrq_char(port, ch))
292	goto ignore_char;
293
294	uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
295	ch, flag);
296
297	ignore_char:
298	continue;
299	}
300	tty_flip_buffer_push(&port->state->port);
301
302	out:
303	spin_unlock_irqrestore(&port->lock, flags);
304	return IRQ_HANDLED;
305	}
306
307	static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
308	{
309	struct s3c24xx_uart_port *ourport = id;
310	struct uart_port *port = &ourport->port;
311	struct circ_buf *xmit = &port->state->xmit;
312	unsigned long flags;
313	int count = 256;
314
315	spin_lock_irqsave(&port->lock, flags);
316
317	if (port->x_char) {
318	wr_regb(port, S3C2410_UTXH, port->x_char);
319	port->icount.tx++;
320	port->x_char = 0;
321	goto out;
322	}
323
324	/* if there isn't anything more to transmit, or the uart is now
325	* stopped, disable the uart and exit
326	*/
327
328	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
329	s3c24xx_serial_stop_tx(port);
330	goto out;
331	}
332
333	/* try and drain the buffer... */
334
335	while (!uart_circ_empty(xmit) && count-- > 0) {
336	if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
337	break;
338
339	wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
340	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
341	port->icount.tx++;
342	}
343
344	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
345	spin_unlock(&port->lock);
346	uart_write_wakeup(port);
347	spin_lock(&port->lock);
348	}
349
350	if (uart_circ_empty(xmit))
351	s3c24xx_serial_stop_tx(port);
352
353	out:
354	spin_unlock_irqrestore(&port->lock, flags);
355	return IRQ_HANDLED;
356	}
357
358	/* interrupt handler for s3c64xx and later SoC's.*/
359	static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
360	{
361	struct s3c24xx_uart_port *ourport = id;
362	struct uart_port *port = &ourport->port;
363	unsigned int pend = rd_regl(port, S3C64XX_UINTP);
364	irqreturn_t ret = IRQ_HANDLED;
365
366	if (pend & S3C64XX_UINTM_RXD_MSK) {
367	ret = s3c24xx_serial_rx_chars(irq, id);
368	wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
369	}
370	if (pend & S3C64XX_UINTM_TXD_MSK) {
371	ret = s3c24xx_serial_tx_chars(irq, id);
372	wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
373	}
374	return ret;
375	}
376
377	static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
378	{
379	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
380	unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
381	unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
382
383	if (ufcon & S3C2410_UFCON_FIFOMODE) {
384	if ((ufstat & info->tx_fifomask) != 0 \|\|
385	(ufstat & info->tx_fifofull))
386	return 0;
387
388	return 1;
389	}
390
391	return s3c24xx_serial_txempty_nofifo(port);
392	}
393
394	/* no modem control lines */
395	static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
396	{
397	unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
398
399	if (umstat & S3C2410_UMSTAT_CTS)
400	return TIOCM_CAR \| TIOCM_DSR \| TIOCM_CTS;
401	else
402	return TIOCM_CAR \| TIOCM_DSR;
403	}
404
405	static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
406	{
407	/* todo - possibly remove AFC and do manual CTS */
408	}
409
410	static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
411	{
412	unsigned long flags;
413	unsigned int ucon;
414
415	spin_lock_irqsave(&port->lock, flags);
416
417	ucon = rd_regl(port, S3C2410_UCON);
418
419	if (break_state)
420	ucon \|= S3C2410_UCON_SBREAK;
421	else
422	ucon &= ~S3C2410_UCON_SBREAK;
423
424	wr_regl(port, S3C2410_UCON, ucon);
425
426	spin_unlock_irqrestore(&port->lock, flags);
427	}
428
429	static void s3c24xx_serial_shutdown(struct uart_port *port)
430	{
431	struct s3c24xx_uart_port *ourport = to_ourport(port);
432
433	if (ourport->tx_claimed) {
434	if (!s3c24xx_serial_has_interrupt_mask(port))
435	free_irq(ourport->tx_irq, ourport);
436	tx_enabled(port) = 0;
437	ourport->tx_claimed = 0;
438	}
439
440	if (ourport->rx_claimed) {
441	if (!s3c24xx_serial_has_interrupt_mask(port))
442	free_irq(ourport->rx_irq, ourport);
443	ourport->rx_claimed = 0;
444	rx_enabled(port) = 0;
445	}
446
447	/* Clear pending interrupts and mask all interrupts */
448	if (s3c24xx_serial_has_interrupt_mask(port)) {
449	wr_regl(port, S3C64XX_UINTP, 0xf);
450	wr_regl(port, S3C64XX_UINTM, 0xf);
451	}
452	}
453
454	static int s3c24xx_serial_startup(struct uart_port *port)
455	{
456	struct s3c24xx_uart_port *ourport = to_ourport(port);
457	int ret;
458
459	dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
460	port->mapbase, port->membase);
461
462	rx_enabled(port) = 1;
463
464	ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
465	s3c24xx_serial_portname(port), ourport);
466
467	if (ret != 0) {
468	dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
469	return ret;
470	}
471
472	ourport->rx_claimed = 1;
473
474	dbg("requesting tx irq...\n");
475
476	tx_enabled(port) = 1;
477
478	ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
479	s3c24xx_serial_portname(port), ourport);
480
481	if (ret) {
482	dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
483	goto err;
484	}
485
486	ourport->tx_claimed = 1;
487
488	dbg("s3c24xx_serial_startup ok\n");
489
490	/* the port reset code should have done the correct
491	* register setup for the port controls */
492
493	return ret;
494
495	err:
496	s3c24xx_serial_shutdown(port);
497	return ret;
498	}
499
500	static int s3c64xx_serial_startup(struct uart_port *port)
501	{
502	struct s3c24xx_uart_port *ourport = to_ourport(port);
503	int ret;
504
505	dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
506	port->mapbase, port->membase);
507
508	ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
509	s3c24xx_serial_portname(port), ourport);
510	if (ret) {
511	dev_err(port->dev, "cannot get irq %d\n", port->irq);
512	return ret;
513	}
514
515	/* For compatibility with s3c24xx Soc's */
516	rx_enabled(port) = 1;
517	ourport->rx_claimed = 1;
518	tx_enabled(port) = 0;
519	ourport->tx_claimed = 1;
520
521	/* Enable Rx Interrupt */
522	__clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
523	dbg("s3c64xx_serial_startup ok\n");
524	return ret;
525	}
526
527	/* power power management control */
528
529	static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
530	unsigned int old)
531	{
532	struct s3c24xx_uart_port *ourport = to_ourport(port);
533
534	ourport->pm_level = level;
535
536	switch (level) {
537	case 3:
538	if (!IS_ERR(ourport->baudclk))
539	clk_disable_unprepare(ourport->baudclk);
540
541	clk_disable_unprepare(ourport->clk);
542	break;
543
544	case 0:
545	clk_prepare_enable(ourport->clk);
546
547	if (!IS_ERR(ourport->baudclk))
548	clk_prepare_enable(ourport->baudclk);
549
550	break;
551	default:
552	dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
553	}
554	}
555
556	/* baud rate calculation
557	*
558	* The UARTs on the S3C2410/S3C2440 can take their clocks from a number
559	* of different sources, including the peripheral clock ("pclk") and an
560	* external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
561	* with a programmable extra divisor.
562	*
563	* The following code goes through the clock sources, and calculates the
564	* baud clocks (and the resultant actual baud rates) and then tries to
565	* pick the closest one and select that.
566	*
567	*/
568
569	#define MAX_CLK_NAME_LENGTH 15
570
571	static inline int s3c24xx_serial_getsource(struct uart_port *port)
572	{
573	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
574	unsigned int ucon;
575
576	if (info->num_clks == 1)
577	return 0;
578
579	ucon = rd_regl(port, S3C2410_UCON);
580	ucon &= info->clksel_mask;
581	return ucon >> info->clksel_shift;
582	}
583
584	static void s3c24xx_serial_setsource(struct uart_port *port,
585	unsigned int clk_sel)
586	{
587	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
588	unsigned int ucon;
589
590	if (info->num_clks == 1)
591	return;
592
593	ucon = rd_regl(port, S3C2410_UCON);
594	if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
595	return;
596
597	ucon &= ~info->clksel_mask;
598	ucon \|= clk_sel << info->clksel_shift;
599	wr_regl(port, S3C2410_UCON, ucon);
600	}
601
602	static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
603	unsigned int req_baud, struct clk **best_clk,
604	unsigned int *clk_num)
605	{
606	struct s3c24xx_uart_info *info = ourport->info;
607	struct clk *clk;
608	unsigned long rate;
609	unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
610	char clkname[MAX_CLK_NAME_LENGTH];
611	int calc_deviation, deviation = (1 << 30) - 1;
612
613	clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
614	ourport->info->def_clk_sel;
615	for (cnt = 0; cnt < info->num_clks; cnt++) {
616	if (!(clk_sel & (1 << cnt)))
617	continue;
618
619	sprintf(clkname, "clk_uart_baud%d", cnt);
620	clk = clk_get(ourport->port.dev, clkname);
621	if (IS_ERR(clk))
622	continue;
623
624	rate = clk_get_rate(clk);
625	if (!rate)
626	continue;
627
628	if (ourport->info->has_divslot) {
629	unsigned long div = rate / req_baud;
630
631	/* The UDIVSLOT register on the newer UARTs allows us to
632	* get a divisor adjustment of 1/16th on the baud clock.
633	*
634	* We don't keep the UDIVSLOT value (the 16ths we
635	* calculated by not multiplying the baud by 16) as it
636	* is easy enough to recalculate.
637	*/
638
639	quot = div / 16;
640	baud = rate / div;
641	} else {
642	quot = (rate + (8 * req_baud)) / (16 * req_baud);
643	baud = rate / (quot * 16);
644	}
645	quot--;
646
647	calc_deviation = req_baud - baud;
648	if (calc_deviation < 0)
649	calc_deviation = -calc_deviation;
650
651	if (calc_deviation < deviation) {
652	*best_clk = clk;
653	best_quot = quot;
654	*clk_num = cnt;
655	deviation = calc_deviation;
656	}
657	}
658
659	return best_quot;
660	}
661
662	/* udivslot_table[]
663	*
664	* This table takes the fractional value of the baud divisor and gives
665	* the recommended setting for the UDIVSLOT register.
666	*/
667	static u16 udivslot_table[16] = {
668	[0] = 0x0000,
669	[1] = 0x0080,
670	[2] = 0x0808,
671	[3] = 0x0888,
672	[4] = 0x2222,
673	[5] = 0x4924,
674	[6] = 0x4A52,
675	[7] = 0x54AA,
676	[8] = 0x5555,
677	[9] = 0xD555,
678	[10] = 0xD5D5,
679	[11] = 0xDDD5,
680	[12] = 0xDDDD,
681	[13] = 0xDFDD,
682	[14] = 0xDFDF,
683	[15] = 0xFFDF,
684	};
685
686	static void s3c24xx_serial_set_termios(struct uart_port *port,
687	struct ktermios *termios,
688	struct ktermios *old)
689	{
690	struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
691	struct s3c24xx_uart_port *ourport = to_ourport(port);
692	struct clk *clk = ERR_PTR(-EINVAL);
693	unsigned long flags;
694	unsigned int baud, quot, clk_sel = 0;
695	unsigned int ulcon;
696	unsigned int umcon;
697	unsigned int udivslot = 0;
698
699	/*
700	* We don't support modem control lines.
701	*/
702	termios->c_cflag &= ~(HUPCL \| CMSPAR);
703	termios->c_cflag \|= CLOCAL;
704
705	/*
706	* Ask the core to calculate the divisor for us.
707	*/
708
709	baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
710	quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
711	if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
712	quot = port->custom_divisor;
713	if (IS_ERR(clk))
714	return;
715
716	/* check to see if we need to change clock source */
717
718	if (ourport->baudclk != clk) {
719	s3c24xx_serial_setsource(port, clk_sel);
720
721	if (!IS_ERR(ourport->baudclk)) {
722	clk_disable_unprepare(ourport->baudclk);
723	ourport->baudclk = ERR_PTR(-EINVAL);
724	}
725
726	clk_prepare_enable(clk);
727
728	ourport->baudclk = clk;
729	ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
730	}
731
732	if (ourport->info->has_divslot) {
733	unsigned int div = ourport->baudclk_rate / baud;
734
735	if (cfg->has_fracval) {
736	udivslot = (div & 15);
737	dbg("fracval = %04x\n", udivslot);
738	} else {
739	udivslot = udivslot_table[div & 15];
740	dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
741	}
742	}
743
744	switch (termios->c_cflag & CSIZE) {
745	case CS5:
746	dbg("config: 5bits/char\n");
747	ulcon = S3C2410_LCON_CS5;
748	break;
749	case CS6:
750	dbg("config: 6bits/char\n");
751	ulcon = S3C2410_LCON_CS6;
752	break;
753	case CS7:
754	dbg("config: 7bits/char\n");
755	ulcon = S3C2410_LCON_CS7;
756	break;
757	case CS8:
758	default:
759	dbg("config: 8bits/char\n");
760	ulcon = S3C2410_LCON_CS8;
761	break;
762	}
763
764	/* preserve original lcon IR settings */
765	ulcon \|= (cfg->ulcon & S3C2410_LCON_IRM);
766
767	if (termios->c_cflag & CSTOPB)
768	ulcon \|= S3C2410_LCON_STOPB;
769
770	umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
771
772	if (termios->c_cflag & PARENB) {
773	if (termios->c_cflag & PARODD)
774	ulcon \|= S3C2410_LCON_PODD;
775	else
776	ulcon \|= S3C2410_LCON_PEVEN;
777	} else {
778	ulcon \|= S3C2410_LCON_PNONE;
779	}
780
781	spin_lock_irqsave(&port->lock, flags);
782
783	dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
784	ulcon, quot, udivslot);
785
786	wr_regl(port, S3C2410_ULCON, ulcon);
787	wr_regl(port, S3C2410_UBRDIV, quot);
788	wr_regl(port, S3C2410_UMCON, umcon);
789
790	if (ourport->info->has_divslot)
791	wr_regl(port, S3C2443_DIVSLOT, udivslot);
792
793	dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
794	rd_regl(port, S3C2410_ULCON),
795	rd_regl(port, S3C2410_UCON),
796	rd_regl(port, S3C2410_UFCON));
797
798	/*
799	* Update the per-port timeout.
800	*/
801	uart_update_timeout(port, termios->c_cflag, baud);
802
803	/*
804	* Which character status flags are we interested in?
805	*/
806	port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
807	if (termios->c_iflag & INPCK)
808	port->read_status_mask \|= S3C2410_UERSTAT_FRAME \| S3C2410_UERSTAT_PARITY;
809
810	/*
811	* Which character status flags should we ignore?
812	*/
813	port->ignore_status_mask = 0;
814	if (termios->c_iflag & IGNPAR)
815	port->ignore_status_mask \|= S3C2410_UERSTAT_OVERRUN;
816	if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
817	port->ignore_status_mask \|= S3C2410_UERSTAT_FRAME;
818
819	/*
820	* Ignore all characters if CREAD is not set.
821	*/
822	if ((termios->c_cflag & CREAD) == 0)
823	port->ignore_status_mask \|= RXSTAT_DUMMY_READ;
824
825	spin_unlock_irqrestore(&port->lock, flags);
826	}
827
828	static const char s3c24xx_serial_type(struct uart_port port)
829	{
830	switch (port->type) {
831	case PORT_S3C2410:
832	return "S3C2410";
833	case PORT_S3C2440:
834	return "S3C2440";
835	case PORT_S3C2412:
836	return "S3C2412";
837	case PORT_S3C6400:
838	return "S3C6400/10";
839	default:
840	return NULL;
841	}
842	}
843
844	#define MAP_SIZE (0x100)
845
846	static void s3c24xx_serial_release_port(struct uart_port *port)
847	{
848	release_mem_region(port->mapbase, MAP_SIZE);
849	}
850
851	static int s3c24xx_serial_request_port(struct uart_port *port)
852	{
853	const char *name = s3c24xx_serial_portname(port);
854	return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
855	}
856
857	static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
858	{
859	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
860
861	if (flags & UART_CONFIG_TYPE &&
862	s3c24xx_serial_request_port(port) == 0)
863	port->type = info->type;
864	}
865
866	/*
867	* verify the new serial_struct (for TIOCSSERIAL).
868	*/
869	static int
870	s3c24xx_serial_verify_port(struct uart_port port, struct serial_struct ser)
871	{
872	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
873
874	if (ser->type != PORT_UNKNOWN && ser->type != info->type)
875	return -EINVAL;
876
877	return 0;
878	}
879
880
881	#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
882
883	static struct console s3c24xx_serial_console;
884
885	static int __init s3c24xx_serial_console_init(void)
886	{
887	register_console(&s3c24xx_serial_console);
888	return 0;
889	}
890	console_initcall(s3c24xx_serial_console_init);
891
892	#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
893	#else
894	#define S3C24XX_SERIAL_CONSOLE NULL
895	#endif
896
897	#ifdef CONFIG_CONSOLE_POLL
898	static int s3c24xx_serial_get_poll_char(struct uart_port *port);
899	static void s3c24xx_serial_put_poll_char(struct uart_port *port,
900	unsigned char c);
901	#endif
902
903	static struct uart_ops s3c24xx_serial_ops = {
904	.pm = s3c24xx_serial_pm,
905	.tx_empty = s3c24xx_serial_tx_empty,
906	.get_mctrl = s3c24xx_serial_get_mctrl,
907	.set_mctrl = s3c24xx_serial_set_mctrl,
908	.stop_tx = s3c24xx_serial_stop_tx,
909	.start_tx = s3c24xx_serial_start_tx,
910	.stop_rx = s3c24xx_serial_stop_rx,
911	.enable_ms = s3c24xx_serial_enable_ms,
912	.break_ctl = s3c24xx_serial_break_ctl,
913	.startup = s3c24xx_serial_startup,
914	.shutdown = s3c24xx_serial_shutdown,
915	.set_termios = s3c24xx_serial_set_termios,
916	.type = s3c24xx_serial_type,
917	.release_port = s3c24xx_serial_release_port,
918	.request_port = s3c24xx_serial_request_port,
919	.config_port = s3c24xx_serial_config_port,
920	.verify_port = s3c24xx_serial_verify_port,
921	#ifdef CONFIG_CONSOLE_POLL
922	.poll_get_char = s3c24xx_serial_get_poll_char,
923	.poll_put_char = s3c24xx_serial_put_poll_char,
924	#endif
925	};
926
927	static struct uart_driver s3c24xx_uart_drv = {
928	.owner = THIS_MODULE,
929	.driver_name = "s3c2410_serial",
930	.nr = CONFIG_SERIAL_SAMSUNG_UARTS,
931	.cons = S3C24XX_SERIAL_CONSOLE,
932	.dev_name = S3C24XX_SERIAL_NAME,
933	.major = S3C24XX_SERIAL_MAJOR,
934	.minor = S3C24XX_SERIAL_MINOR,
935	};
936
937	static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
938	[0] = {
939	.port = {
940	.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
941	.iotype = UPIO_MEM,
942	.uartclk = 0,
943	.fifosize = 16,
944	.ops = &s3c24xx_serial_ops,
945	.flags = UPF_BOOT_AUTOCONF,
946	.line = 0,
947	}
948	},
949	[1] = {
950	.port = {
951	.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
952	.iotype = UPIO_MEM,
953	.uartclk = 0,
954	.fifosize = 16,
955	.ops = &s3c24xx_serial_ops,
956	.flags = UPF_BOOT_AUTOCONF,
957	.line = 1,
958	}
959	},
960	#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
961
962	[2] = {
963	.port = {
964	.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
965	.iotype = UPIO_MEM,
966	.uartclk = 0,
967	.fifosize = 16,
968	.ops = &s3c24xx_serial_ops,
969	.flags = UPF_BOOT_AUTOCONF,
970	.line = 2,
971	}
972	},
973	#endif
974	#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
975	[3] = {
976	.port = {
977	.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
978	.iotype = UPIO_MEM,
979	.uartclk = 0,
980	.fifosize = 16,
981	.ops = &s3c24xx_serial_ops,
982	.flags = UPF_BOOT_AUTOCONF,
983	.line = 3,
984	}
985	}
986	#endif
987	};
988
989	/* s3c24xx_serial_resetport
990	*
991	* reset the fifos and other the settings.
992	*/
993
994	static void s3c24xx_serial_resetport(struct uart_port *port,
995	struct s3c2410_uartcfg *cfg)
996	{
997	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
998	unsigned long ucon = rd_regl(port, S3C2410_UCON);
999	unsigned int ucon_mask;
1000
1001	ucon_mask = info->clksel_mask;
1002	if (info->type == PORT_S3C2440)
1003	ucon_mask \|= S3C2440_UCON0_DIVMASK;
1004
1005	ucon &= ucon_mask;
1006	wr_regl(port, S3C2410_UCON, ucon \| cfg->ucon);
1007
1008	/* reset both fifos */
1009	wr_regl(port, S3C2410_UFCON, cfg->ufcon \| S3C2410_UFCON_RESETBOTH);
1010	wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1011
1012	/* some delay is required after fifo reset */
1013	udelay(1);
1014	}
1015
1016
1017	#ifdef CONFIG_CPU_FREQ
1018
1019	static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1020	unsigned long val, void *data)
1021	{
1022	struct s3c24xx_uart_port *port;
1023	struct uart_port *uport;
1024
1025	port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1026	uport = &port->port;
1027
1028	/* check to see if port is enabled */
1029
1030	if (port->pm_level != 0)
1031	return 0;
1032
1033	/* try and work out if the baudrate is changing, we can detect
1034	* a change in rate, but we do not have support for detecting
1035	* a disturbance in the clock-rate over the change.
1036	*/
1037
1038	if (IS_ERR(port->baudclk))
1039	goto exit;
1040
1041	if (port->baudclk_rate == clk_get_rate(port->baudclk))
1042	goto exit;
1043
1044	if (val == CPUFREQ_PRECHANGE) {
1045	/* we should really shut the port down whilst the
1046	* frequency change is in progress. */
1047
1048	} else if (val == CPUFREQ_POSTCHANGE) {
1049	struct ktermios *termios;
1050	struct tty_struct *tty;
1051
1052	if (uport->state == NULL)
1053	goto exit;
1054
1055	tty = uport->state->port.tty;
1056
1057	if (tty == NULL)
1058	goto exit;
1059
1060	termios = &tty->termios;
1061
1062	if (termios == NULL) {
1063	dev_warn(uport->dev, "%s: no termios?\n", __func__);
1064	goto exit;
1065	}
1066
1067	s3c24xx_serial_set_termios(uport, termios, NULL);
1068	}
1069
1070	exit:
1071	return 0;
1072	}
1073
1074	static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1075	{
1076	port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1077
1078	return cpufreq_register_notifier(&port->freq_transition,
1079	CPUFREQ_TRANSITION_NOTIFIER);
1080	}
1081
1082	static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1083	{
1084	cpufreq_unregister_notifier(&port->freq_transition,
1085	CPUFREQ_TRANSITION_NOTIFIER);
1086	}
1087
1088	#else
1089	static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1090	{
1091	return 0;
1092	}
1093
1094	static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1095	{
1096	}
1097	#endif
1098
1099	/* s3c24xx_serial_init_port
1100	*
1101	* initialise a single serial port from the platform device given
1102	*/
1103
1104	static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1105	struct platform_device *platdev)
1106	{
1107	struct uart_port *port = &ourport->port;
1108	struct s3c2410_uartcfg *cfg = ourport->cfg;
1109	struct resource *res;
1110	int ret;
1111
1112	dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1113
1114	if (platdev == NULL)
1115	return -ENODEV;
1116
1117	if (port->mapbase != 0)
1118	return 0;
1119
1120	/* setup info for port */
1121	port->dev = &platdev->dev;
1122
1123	/* Startup sequence is different for s3c64xx and higher SoC's */
1124	if (s3c24xx_serial_has_interrupt_mask(port))
1125	s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1126
1127	port->uartclk = 1;
1128
1129	if (cfg->uart_flags & UPF_CONS_FLOW) {
1130	dbg("s3c24xx_serial_init_port: enabling flow control\n");
1131	port->flags \|= UPF_CONS_FLOW;
1132	}
1133
1134	/* sort our the physical and virtual addresses for each UART */
1135
1136	res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1137	if (res == NULL) {
1138	dev_err(port->dev, "failed to find memory resource for uart\n");
1139	return -EINVAL;
1140	}
1141
1142	dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1143
1144	port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1145	if (!port->membase) {
1146	dev_err(port->dev, "failed to remap controller address\n");
1147	return -EBUSY;
1148	}
1149
1150	port->mapbase = res->start;
1151	ret = platform_get_irq(platdev, 0);
1152	if (ret < 0)
1153	port->irq = 0;
1154	else {
1155	port->irq = ret;
1156	ourport->rx_irq = ret;
1157	ourport->tx_irq = ret + 1;
1158	}
1159
1160	ret = platform_get_irq(platdev, 1);
1161	if (ret > 0)
1162	ourport->tx_irq = ret;
1163
1164	ourport->clk = clk_get(&platdev->dev, "uart");
1165
1166	/* Keep all interrupts masked and cleared */
1167	if (s3c24xx_serial_has_interrupt_mask(port)) {
1168	wr_regl(port, S3C64XX_UINTM, 0xf);
1169	wr_regl(port, S3C64XX_UINTP, 0xf);
1170	wr_regl(port, S3C64XX_UINTSP, 0xf);
1171	}
1172
1173	dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1174	port->mapbase, port->membase, port->irq,
1175	ourport->rx_irq, ourport->tx_irq, port->uartclk);
1176
1177	/* reset the fifos (and setup the uart) */
1178	s3c24xx_serial_resetport(port, cfg);
1179	return 0;
1180	}
1181
1182	static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1183	struct device_attribute *attr,
1184	char *buf)
1185	{
1186	struct uart_port *port = s3c24xx_dev_to_port(dev);
1187	struct s3c24xx_uart_port *ourport = to_ourport(port);
1188
1189	if (IS_ERR(ourport->baudclk))
1190	return -EINVAL;
1191
1192	return snprintf(buf, PAGE_SIZE, "* %s\n",
1193	ourport->baudclk->name ?: "(null)");
1194	}
1195
1196	static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1197
1198
1199	/* Device driver serial port probe */
1200
1201	static const struct of_device_id s3c24xx_uart_dt_match[];
1202	static int probe_index;
1203
1204	static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1205	struct platform_device *pdev)
1206	{
1207	#ifdef CONFIG_OF
1208	if (pdev->dev.of_node) {
1209	const struct of_device_id *match;
1210	match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1211	return (struct s3c24xx_serial_drv_data *)match->data;
1212	}
1213	#endif
1214	return (struct s3c24xx_serial_drv_data *)
1215	platform_get_device_id(pdev)->driver_data;
1216	}
1217
1218	static int s3c24xx_serial_probe(struct platform_device *pdev)
1219	{
1220	struct s3c24xx_uart_port *ourport;
1221	int ret;
1222
1223	dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1224
1225	ourport = &s3c24xx_serial_ports[probe_index];
1226
1227	ourport->drv_data = s3c24xx_get_driver_data(pdev);
1228	if (!ourport->drv_data) {
1229	dev_err(&pdev->dev, "could not find driver data\n");
1230	return -ENODEV;
1231	}
1232
1233	ourport->baudclk = ERR_PTR(-EINVAL);
1234	ourport->info = ourport->drv_data->info;
1235	ourport->cfg = (pdev->dev.platform_data) ?
1236	(struct s3c2410_uartcfg *)pdev->dev.platform_data :
1237	ourport->drv_data->def_cfg;
1238
1239	ourport->port.fifosize = (ourport->info->fifosize) ?
1240	ourport->info->fifosize :
1241	ourport->drv_data->fifosize[probe_index];
1242
1243	probe_index++;
1244
1245	dbg("%s: initialising port %p...\n", __func__, ourport);
1246
1247	ret = s3c24xx_serial_init_port(ourport, pdev);
1248	if (ret < 0)
1249	goto probe_err;
1250
1251	dbg("%s: adding port\n", __func__);
1252	uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1253	platform_set_drvdata(pdev, &ourport->port);
1254
1255	ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1256	if (ret < 0)
1257	dev_err(&pdev->dev, "failed to add clock source attr.\n");
1258
1259	ret = s3c24xx_serial_cpufreq_register(ourport);
1260	if (ret < 0)
1261	dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1262
1263	return 0;
1264
1265	probe_err:
1266	return ret;
1267	}
1268
1269	static int s3c24xx_serial_remove(struct platform_device *dev)
1270	{
1271	struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1272
1273	if (port) {
1274	s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1275	device_remove_file(&dev->dev, &dev_attr_clock_source);
1276	uart_remove_one_port(&s3c24xx_uart_drv, port);
1277	}
1278
1279	return 0;
1280	}
1281
1282	/* UART power management code */
1283	#ifdef CONFIG_PM_SLEEP
1284	static int s3c24xx_serial_suspend(struct device *dev)
1285	{
1286	struct uart_port *port = s3c24xx_dev_to_port(dev);
1287
1288	if (port)
1289	uart_suspend_port(&s3c24xx_uart_drv, port);
1290
1291	return 0;
1292	}
1293
1294	static int s3c24xx_serial_resume(struct device *dev)
1295	{
1296	struct uart_port *port = s3c24xx_dev_to_port(dev);
1297	struct s3c24xx_uart_port *ourport = to_ourport(port);
1298
1299	if (port) {
1300	clk_prepare_enable(ourport->clk);
1301	s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1302	clk_disable_unprepare(ourport->clk);
1303
1304	uart_resume_port(&s3c24xx_uart_drv, port);
1305	}
1306
1307	return 0;
1308	}
1309
1310	static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1311	.suspend = s3c24xx_serial_suspend,
1312	.resume = s3c24xx_serial_resume,
1313	};
1314	#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1315
1316	#else /* !CONFIG_PM_SLEEP */
1317
1318	#define SERIAL_SAMSUNG_PM_OPS NULL
1319	#endif /* CONFIG_PM_SLEEP */
1320
1321	/* Console code */
1322
1323	#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1324
1325	static struct uart_port *cons_uart;
1326
1327	static int
1328	s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1329	{
1330	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1331	unsigned long ufstat, utrstat;
1332
1333	if (ufcon & S3C2410_UFCON_FIFOMODE) {
1334	/* fifo mode - check amount of data in fifo registers... */
1335
1336	ufstat = rd_regl(port, S3C2410_UFSTAT);
1337	return (ufstat & info->tx_fifofull) ? 0 : 1;
1338	}
1339
1340	/* in non-fifo mode, we go and use the tx buffer empty */
1341
1342	utrstat = rd_regl(port, S3C2410_UTRSTAT);
1343	return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1344	}
1345
1346	#ifdef CONFIG_CONSOLE_POLL
1347	/*
1348	* Console polling routines for writing and reading from the uart while
1349	* in an interrupt or debug context.
1350	*/
1351
1352	static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1353	{
1354	struct s3c24xx_uart_port *ourport = to_ourport(port);
1355	unsigned int ufstat;
1356
1357	ufstat = rd_regl(port, S3C2410_UFSTAT);
1358	if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1359	return NO_POLL_CHAR;
1360
1361	return rd_regb(port, S3C2410_URXH);
1362	}
1363
1364	static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1365	unsigned char c)
1366	{
1367	unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1368
1369	while (!s3c24xx_serial_console_txrdy(port, ufcon))
1370	cpu_relax();
1371	wr_regb(cons_uart, S3C2410_UTXH, c);
1372	}
1373
1374	#endif /* CONFIG_CONSOLE_POLL */
1375
1376	static void
1377	s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1378	{
1379	unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1380	while (!s3c24xx_serial_console_txrdy(port, ufcon))
1381	barrier();
1382	wr_regb(cons_uart, S3C2410_UTXH, ch);
1383	}
1384
1385	static void
1386	s3c24xx_serial_console_write(struct console co, const char s,
1387	unsigned int count)
1388	{
1389	uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1390	}
1391
1392	static void __init
1393	s3c24xx_serial_get_options(struct uart_port port, int baud,
1394	int parity, int bits)
1395	{
1396	struct clk *clk;
1397	unsigned int ulcon;
1398	unsigned int ucon;
1399	unsigned int ubrdiv;
1400	unsigned long rate;
1401	unsigned int clk_sel;
1402	char clk_name[MAX_CLK_NAME_LENGTH];
1403
1404	ulcon = rd_regl(port, S3C2410_ULCON);
1405	ucon = rd_regl(port, S3C2410_UCON);
1406	ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1407
1408	dbg("s3c24xx_serial_get_options: port=%p\n"
1409	"registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1410	port, ulcon, ucon, ubrdiv);
1411
1412	if ((ucon & 0xf) != 0) {
1413	/* consider the serial port configured if the tx/rx mode set */
1414
1415	switch (ulcon & S3C2410_LCON_CSMASK) {
1416	case S3C2410_LCON_CS5:
1417	*bits = 5;
1418	break;
1419	case S3C2410_LCON_CS6:
1420	*bits = 6;
1421	break;
1422	case S3C2410_LCON_CS7:
1423	*bits = 7;
1424	break;
1425	default:
1426	case S3C2410_LCON_CS8:
1427	*bits = 8;
1428	break;
1429	}
1430
1431	switch (ulcon & S3C2410_LCON_PMASK) {
1432	case S3C2410_LCON_PEVEN:
1433	*parity = 'e';
1434	break;
1435
1436	case S3C2410_LCON_PODD:
1437	*parity = 'o';
1438	break;
1439
1440	case S3C2410_LCON_PNONE:
1441	default:
1442	*parity = 'n';
1443	}
1444
1445	/* now calculate the baud rate */
1446
1447	clk_sel = s3c24xx_serial_getsource(port);
1448	sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1449
1450	clk = clk_get(port->dev, clk_name);
1451	if (!IS_ERR(clk))
1452	rate = clk_get_rate(clk);
1453	else
1454	rate = 1;
1455
1456	baud = rate / (16 (ubrdiv + 1));
1457	dbg("calculated baud %d\n", *baud);
1458	}
1459
1460	}
1461
1462	static int __init
1463	s3c24xx_serial_console_setup(struct console co, char options)
1464	{
1465	struct uart_port *port;
1466	int baud = 9600;
1467	int bits = 8;
1468	int parity = 'n';
1469	int flow = 'n';
1470
1471	dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1472	co, co->index, options);
1473
1474	/* is this a valid port */
1475
1476	if (co->index == -1 \|\| co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1477	co->index = 0;
1478
1479	port = &s3c24xx_serial_ports[co->index].port;
1480
1481	/* is the port configured? */
1482
1483	if (port->mapbase == 0x0)
1484	return -ENODEV;
1485
1486	cons_uart = port;
1487
1488	dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1489
1490	/*
1491	* Check whether an invalid uart number has been specified, and
1492	* if so, search for the first available port that does have
1493	* console support.
1494	*/
1495	if (options)
1496	uart_parse_options(options, &baud, &parity, &bits, &flow);
1497	else
1498	s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1499
1500	dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1501
1502	return uart_set_options(port, co, baud, parity, bits, flow);
1503	}
1504
1505	static struct console s3c24xx_serial_console = {
1506	.name = S3C24XX_SERIAL_NAME,
1507	.device = uart_console_device,
1508	.flags = CON_PRINTBUFFER,
1509	.index = -1,
1510	.write = s3c24xx_serial_console_write,
1511	.setup = s3c24xx_serial_console_setup,
1512	.data = &s3c24xx_uart_drv,
1513	};
1514	#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1515
1516	#ifdef CONFIG_CPU_S3C2410
1517	static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1518	.info = &(struct s3c24xx_uart_info) {
1519	.name = "Samsung S3C2410 UART",
1520	.type = PORT_S3C2410,
1521	.fifosize = 16,
1522	.rx_fifomask = S3C2410_UFSTAT_RXMASK,
1523	.rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1524	.rx_fifofull = S3C2410_UFSTAT_RXFULL,
1525	.tx_fifofull = S3C2410_UFSTAT_TXFULL,
1526	.tx_fifomask = S3C2410_UFSTAT_TXMASK,
1527	.tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1528	.def_clk_sel = S3C2410_UCON_CLKSEL0,
1529	.num_clks = 2,
1530	.clksel_mask = S3C2410_UCON_CLKMASK,
1531	.clksel_shift = S3C2410_UCON_CLKSHIFT,
1532	},
1533	.def_cfg = &(struct s3c2410_uartcfg) {
1534	.ucon = S3C2410_UCON_DEFAULT,
1535	.ufcon = S3C2410_UFCON_DEFAULT,
1536	},
1537	};
1538	#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1539	#else
1540	#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1541	#endif
1542
1543	#ifdef CONFIG_CPU_S3C2412
1544	static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1545	.info = &(struct s3c24xx_uart_info) {
1546	.name = "Samsung S3C2412 UART",
1547	.type = PORT_S3C2412,
1548	.fifosize = 64,
1549	.has_divslot = 1,
1550	.rx_fifomask = S3C2440_UFSTAT_RXMASK,
1551	.rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1552	.rx_fifofull = S3C2440_UFSTAT_RXFULL,
1553	.tx_fifofull = S3C2440_UFSTAT_TXFULL,
1554	.tx_fifomask = S3C2440_UFSTAT_TXMASK,
1555	.tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1556	.def_clk_sel = S3C2410_UCON_CLKSEL2,
1557	.num_clks = 4,
1558	.clksel_mask = S3C2412_UCON_CLKMASK,
1559	.clksel_shift = S3C2412_UCON_CLKSHIFT,
1560	},
1561	.def_cfg = &(struct s3c2410_uartcfg) {
1562	.ucon = S3C2410_UCON_DEFAULT,
1563	.ufcon = S3C2410_UFCON_DEFAULT,
1564	},
1565	};
1566	#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1567	#else
1568	#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1569	#endif
1570
1571	#if defined(CONFIG_CPU_S3C2440) \|\| defined(CONFIG_CPU_S3C2416) \|\| \
1572	defined(CONFIG_CPU_S3C2443) \|\| defined(CONFIG_CPU_S3C2442)
1573	static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1574	.info = &(struct s3c24xx_uart_info) {
1575	.name = "Samsung S3C2440 UART",
1576	.type = PORT_S3C2440,
1577	.fifosize = 64,
1578	.has_divslot = 1,
1579	.rx_fifomask = S3C2440_UFSTAT_RXMASK,
1580	.rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1581	.rx_fifofull = S3C2440_UFSTAT_RXFULL,
1582	.tx_fifofull = S3C2440_UFSTAT_TXFULL,
1583	.tx_fifomask = S3C2440_UFSTAT_TXMASK,
1584	.tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1585	.def_clk_sel = S3C2410_UCON_CLKSEL2,
1586	.num_clks = 4,
1587	.clksel_mask = S3C2412_UCON_CLKMASK,
1588	.clksel_shift = S3C2412_UCON_CLKSHIFT,
1589	},
1590	.def_cfg = &(struct s3c2410_uartcfg) {
1591	.ucon = S3C2410_UCON_DEFAULT,
1592	.ufcon = S3C2410_UFCON_DEFAULT,
1593	},
1594	};
1595	#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1596	#else
1597	#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1598	#endif
1599
1600	#if defined(CONFIG_CPU_S3C6400) \|\| defined(CONFIG_CPU_S3C6410) \|\| \
1601	defined(CONFIG_CPU_S5P6440) \|\| defined(CONFIG_CPU_S5P6450) \|\| \
1602	defined(CONFIG_CPU_S5PC100)
1603	static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1604	.info = &(struct s3c24xx_uart_info) {
1605	.name = "Samsung S3C6400 UART",
1606	.type = PORT_S3C6400,
1607	.fifosize = 64,
1608	.has_divslot = 1,
1609	.rx_fifomask = S3C2440_UFSTAT_RXMASK,
1610	.rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1611	.rx_fifofull = S3C2440_UFSTAT_RXFULL,
1612	.tx_fifofull = S3C2440_UFSTAT_TXFULL,
1613	.tx_fifomask = S3C2440_UFSTAT_TXMASK,
1614	.tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1615	.def_clk_sel = S3C2410_UCON_CLKSEL2,
1616	.num_clks = 4,
1617	.clksel_mask = S3C6400_UCON_CLKMASK,
1618	.clksel_shift = S3C6400_UCON_CLKSHIFT,
1619	},
1620	.def_cfg = &(struct s3c2410_uartcfg) {
1621	.ucon = S3C2410_UCON_DEFAULT,
1622	.ufcon = S3C2410_UFCON_DEFAULT,
1623	},
1624	};
1625	#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1626	#else
1627	#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1628	#endif
1629
1630	#ifdef CONFIG_CPU_S5PV210
1631	static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1632	.info = &(struct s3c24xx_uart_info) {
1633	.name = "Samsung S5PV210 UART",
1634	.type = PORT_S3C6400,
1635	.has_divslot = 1,
1636	.rx_fifomask = S5PV210_UFSTAT_RXMASK,
1637	.rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1638	.rx_fifofull = S5PV210_UFSTAT_RXFULL,
1639	.tx_fifofull = S5PV210_UFSTAT_TXFULL,
1640	.tx_fifomask = S5PV210_UFSTAT_TXMASK,
1641	.tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1642	.def_clk_sel = S3C2410_UCON_CLKSEL0,
1643	.num_clks = 2,
1644	.clksel_mask = S5PV210_UCON_CLKMASK,
1645	.clksel_shift = S5PV210_UCON_CLKSHIFT,
1646	},
1647	.def_cfg = &(struct s3c2410_uartcfg) {
1648	.ucon = S5PV210_UCON_DEFAULT,
1649	.ufcon = S5PV210_UFCON_DEFAULT,
1650	},
1651	.fifosize = { 256, 64, 16, 16 },
1652	};
1653	#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1654	#else
1655	#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1656	#endif
1657
1658	#if defined(CONFIG_CPU_EXYNOS4210) \|\| defined(CONFIG_SOC_EXYNOS4212) \|\| \
1659	defined(CONFIG_SOC_EXYNOS4412) \|\| defined(CONFIG_SOC_EXYNOS5250) \|\| \
1660	defined(CONFIG_SOC_EXYNOS5440)
1661	static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1662	.info = &(struct s3c24xx_uart_info) {
1663	.name = "Samsung Exynos4 UART",
1664	.type = PORT_S3C6400,
1665	.has_divslot = 1,
1666	.rx_fifomask = S5PV210_UFSTAT_RXMASK,
1667	.rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1668	.rx_fifofull = S5PV210_UFSTAT_RXFULL,
1669	.tx_fifofull = S5PV210_UFSTAT_TXFULL,
1670	.tx_fifomask = S5PV210_UFSTAT_TXMASK,
1671	.tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1672	.def_clk_sel = S3C2410_UCON_CLKSEL0,
1673	.num_clks = 1,
1674	.clksel_mask = 0,
1675	.clksel_shift = 0,
1676	},
1677	.def_cfg = &(struct s3c2410_uartcfg) {
1678	.ucon = S5PV210_UCON_DEFAULT,
1679	.ufcon = S5PV210_UFCON_DEFAULT,
1680	.has_fracval = 1,
1681	},
1682	.fifosize = { 256, 64, 16, 16 },
1683	};
1684	#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1685	#else
1686	#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1687	#endif
1688
1689	static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1690	{
1691	.name = "s3c2410-uart",
1692	.driver_data = S3C2410_SERIAL_DRV_DATA,
1693	}, {
1694	.name = "s3c2412-uart",
1695	.driver_data = S3C2412_SERIAL_DRV_DATA,
1696	}, {
1697	.name = "s3c2440-uart",
1698	.driver_data = S3C2440_SERIAL_DRV_DATA,
1699	}, {
1700	.name = "s3c6400-uart",
1701	.driver_data = S3C6400_SERIAL_DRV_DATA,
1702	}, {
1703	.name = "s5pv210-uart",
1704	.driver_data = S5PV210_SERIAL_DRV_DATA,
1705	}, {
1706	.name = "exynos4210-uart",
1707	.driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1708	},
1709	{ },
1710	};
1711	MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1712
1713	#ifdef CONFIG_OF
1714	static const struct of_device_id s3c24xx_uart_dt_match[] = {
1715	{ .compatible = "samsung,s3c2410-uart",
1716	.data = (void *)S3C2410_SERIAL_DRV_DATA },
1717	{ .compatible = "samsung,s3c2412-uart",
1718	.data = (void *)S3C2412_SERIAL_DRV_DATA },
1719	{ .compatible = "samsung,s3c2440-uart",
1720	.data = (void *)S3C2440_SERIAL_DRV_DATA },
1721	{ .compatible = "samsung,s3c6400-uart",
1722	.data = (void *)S3C6400_SERIAL_DRV_DATA },
1723	{ .compatible = "samsung,s5pv210-uart",
1724	.data = (void *)S5PV210_SERIAL_DRV_DATA },
1725	{ .compatible = "samsung,exynos4210-uart",
1726	.data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1727	{},
1728	};
1729	MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1730	#endif
1731
1732	static struct platform_driver samsung_serial_driver = {
1733	.probe = s3c24xx_serial_probe,
1734	.remove = s3c24xx_serial_remove,
1735	.id_table = s3c24xx_serial_driver_ids,
1736	.driver = {
1737	.name = "samsung-uart",
1738	.owner = THIS_MODULE,
1739	.pm = SERIAL_SAMSUNG_PM_OPS,
1740	.of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
1741	},
1742	};
1743
1744	/* module initialisation code */
1745
1746	static int __init s3c24xx_serial_modinit(void)
1747	{
1748	int ret;
1749
1750	ret = uart_register_driver(&s3c24xx_uart_drv);
1751	if (ret < 0) {
1752	pr_err("Failed to register Samsung UART driver\n");
1753	return ret;
1754	}
1755
1756	return platform_driver_register(&samsung_serial_driver);
1757	}
1758
1759	static void __exit s3c24xx_serial_modexit(void)
1760	{
1761	uart_unregister_driver(&s3c24xx_uart_drv);
1762	}
1763
1764	module_init(s3c24xx_serial_modinit);
1765	module_exit(s3c24xx_serial_modexit);
1766
1767	MODULE_ALIAS("platform:samsung-uart");
1768	MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1769	MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1770	MODULE_LICENSE("GPL v2");
1771

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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9

Kernel

Kernel Git Source Tree

Root/drivers/tty/serial/samsung.c

interactive