Root/drivers/tty/synclink.c

1/*
2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink ISA and PCI
5 * high speed multiprotocol serial adapters.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 *
14 * Original release 01/11/99
15 *
16 * This code is released under the GNU General Public License (GPL)
17 *
18 * This driver is primarily intended for use in synchronous
19 * HDLC mode. Asynchronous mode is also provided.
20 *
21 * When operating in synchronous mode, each call to mgsl_write()
22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
23 * will start assembling an HDLC frame that will not be sent until
24 * mgsl_flush_chars or mgsl_write is called.
25 *
26 * Synchronous receive data is reported as complete frames. To accomplish
27 * this, the TTY flip buffer is bypassed (too small to hold largest
28 * frame and may fragment frames) and the line discipline
29 * receive entry point is called directly.
30 *
31 * This driver has been tested with a slightly modified ppp.c driver
32 * for synchronous PPP.
33 *
34 * 2000/02/16
35 * Added interface for syncppp.c driver (an alternate synchronous PPP
36 * implementation that also supports Cisco HDLC). Each device instance
37 * registers as a tty device AND a network device (if dosyncppp option
38 * is set for the device). The functionality is determined by which
39 * device interface is opened.
40 *
41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
51 * OF THE POSSIBILITY OF SUCH DAMAGE.
52 */
53
54#if defined(__i386__)
55# define BREAKPOINT() asm(" int $3");
56#else
57# define BREAKPOINT() { }
58#endif
59
60#define MAX_ISA_DEVICES 10
61#define MAX_PCI_DEVICES 10
62#define MAX_TOTAL_DEVICES 20
63
64#include <linux/module.h>
65#include <linux/errno.h>
66#include <linux/signal.h>
67#include <linux/sched.h>
68#include <linux/timer.h>
69#include <linux/interrupt.h>
70#include <linux/pci.h>
71#include <linux/tty.h>
72#include <linux/tty_flip.h>
73#include <linux/serial.h>
74#include <linux/major.h>
75#include <linux/string.h>
76#include <linux/fcntl.h>
77#include <linux/ptrace.h>
78#include <linux/ioport.h>
79#include <linux/mm.h>
80#include <linux/seq_file.h>
81#include <linux/slab.h>
82#include <linux/delay.h>
83#include <linux/netdevice.h>
84#include <linux/vmalloc.h>
85#include <linux/init.h>
86#include <linux/ioctl.h>
87#include <linux/synclink.h>
88
89#include <asm/io.h>
90#include <asm/irq.h>
91#include <asm/dma.h>
92#include <linux/bitops.h>
93#include <asm/types.h>
94#include <linux/termios.h>
95#include <linux/workqueue.h>
96#include <linux/hdlc.h>
97#include <linux/dma-mapping.h>
98
99#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100#define SYNCLINK_GENERIC_HDLC 1
101#else
102#define SYNCLINK_GENERIC_HDLC 0
103#endif
104
105#define GET_USER(error,value,addr) error = get_user(value,addr)
106#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107#define PUT_USER(error,value,addr) error = put_user(value,addr)
108#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
109
110#include <asm/uaccess.h>
111
112#define RCLRVALUE 0xffff
113
114static MGSL_PARAMS default_params = {
115    MGSL_MODE_HDLC, /* unsigned long mode */
116    0, /* unsigned char loopback; */
117    HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
118    HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
119    0, /* unsigned long clock_speed; */
120    0xff, /* unsigned char addr_filter; */
121    HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
122    HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
123    HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
124    9600, /* unsigned long data_rate; */
125    8, /* unsigned char data_bits; */
126    1, /* unsigned char stop_bits; */
127    ASYNC_PARITY_NONE /* unsigned char parity; */
128};
129
130#define SHARED_MEM_ADDRESS_SIZE 0x40000
131#define BUFFERLISTSIZE 4096
132#define DMABUFFERSIZE 4096
133#define MAXRXFRAMES 7
134
135typedef struct _DMABUFFERENTRY
136{
137    u32 phys_addr; /* 32-bit flat physical address of data buffer */
138    volatile u16 count; /* buffer size/data count */
139    volatile u16 status; /* Control/status field */
140    volatile u16 rcc; /* character count field */
141    u16 reserved; /* padding required by 16C32 */
142    u32 link; /* 32-bit flat link to next buffer entry */
143    char *virt_addr; /* virtual address of data buffer */
144    u32 phys_entry; /* physical address of this buffer entry */
145    dma_addr_t dma_addr;
146} DMABUFFERENTRY, *DMAPBUFFERENTRY;
147
148/* The queue of BH actions to be performed */
149
150#define BH_RECEIVE 1
151#define BH_TRANSMIT 2
152#define BH_STATUS 4
153
154#define IO_PIN_SHUTDOWN_LIMIT 100
155
156struct _input_signal_events {
157    int ri_up;
158    int ri_down;
159    int dsr_up;
160    int dsr_down;
161    int dcd_up;
162    int dcd_down;
163    int cts_up;
164    int cts_down;
165};
166
167/* transmit holding buffer definitions*/
168#define MAX_TX_HOLDING_BUFFERS 5
169struct tx_holding_buffer {
170    int buffer_size;
171    unsigned char * buffer;
172};
173
174
175/*
176 * Device instance data structure
177 */
178 
179struct mgsl_struct {
180    int magic;
181    struct tty_port port;
182    int line;
183    int hw_version;
184    
185    struct mgsl_icount icount;
186    
187    int timeout;
188    int x_char; /* xon/xoff character */
189    u16 read_status_mask;
190    u16 ignore_status_mask;
191    unsigned char *xmit_buf;
192    int xmit_head;
193    int xmit_tail;
194    int xmit_cnt;
195    
196    wait_queue_head_t status_event_wait_q;
197    wait_queue_head_t event_wait_q;
198    struct timer_list tx_timer; /* HDLC transmit timeout timer */
199    struct mgsl_struct *next_device; /* device list link */
200    
201    spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
202    struct work_struct task; /* task structure for scheduling bh */
203
204    u32 EventMask; /* event trigger mask */
205    u32 RecordedEvents; /* pending events */
206
207    u32 max_frame_size; /* as set by device config */
208
209    u32 pending_bh;
210
211    bool bh_running; /* Protection from multiple */
212    int isr_overflow;
213    bool bh_requested;
214    
215    int dcd_chkcount; /* check counts to prevent */
216    int cts_chkcount; /* too many IRQs if a signal */
217    int dsr_chkcount; /* is floating */
218    int ri_chkcount;
219
220    char *buffer_list; /* virtual address of Rx & Tx buffer lists */
221    u32 buffer_list_phys;
222    dma_addr_t buffer_list_dma_addr;
223
224    unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
225    DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
226    unsigned int current_rx_buffer;
227
228    int num_tx_dma_buffers; /* number of tx dma frames required */
229     int tx_dma_buffers_used;
230    unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
231    DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
232    int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
233    int current_tx_buffer; /* next tx dma buffer to be loaded */
234    
235    unsigned char *intermediate_rxbuffer;
236
237    int num_tx_holding_buffers; /* number of tx holding buffer allocated */
238    int get_tx_holding_index; /* next tx holding buffer for adapter to load */
239    int put_tx_holding_index; /* next tx holding buffer to store user request */
240    int tx_holding_count; /* number of tx holding buffers waiting */
241    struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
242
243    bool rx_enabled;
244    bool rx_overflow;
245    bool rx_rcc_underrun;
246
247    bool tx_enabled;
248    bool tx_active;
249    u32 idle_mode;
250
251    u16 cmr_value;
252    u16 tcsr_value;
253
254    char device_name[25]; /* device instance name */
255
256    unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
257    unsigned char bus; /* expansion bus number (zero based) */
258    unsigned char function; /* PCI device number */
259
260    unsigned int io_base; /* base I/O address of adapter */
261    unsigned int io_addr_size; /* size of the I/O address range */
262    bool io_addr_requested; /* true if I/O address requested */
263    
264    unsigned int irq_level; /* interrupt level */
265    unsigned long irq_flags;
266    bool irq_requested; /* true if IRQ requested */
267    
268    unsigned int dma_level; /* DMA channel */
269    bool dma_requested; /* true if dma channel requested */
270
271    u16 mbre_bit;
272    u16 loopback_bits;
273    u16 usc_idle_mode;
274
275    MGSL_PARAMS params; /* communications parameters */
276
277    unsigned char serial_signals; /* current serial signal states */
278
279    bool irq_occurred; /* for diagnostics use */
280    unsigned int init_error; /* Initialization startup error (DIAGS) */
281    int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
282
283    u32 last_mem_alloc;
284    unsigned char* memory_base; /* shared memory address (PCI only) */
285    u32 phys_memory_base;
286    bool shared_mem_requested;
287
288    unsigned char* lcr_base; /* local config registers (PCI only) */
289    u32 phys_lcr_base;
290    u32 lcr_offset;
291    bool lcr_mem_requested;
292
293    u32 misc_ctrl_value;
294    char *flag_buf;
295    bool drop_rts_on_tx_done;
296
297    bool loopmode_insert_requested;
298    bool loopmode_send_done_requested;
299    
300    struct _input_signal_events input_signal_events;
301
302    /* generic HDLC device parts */
303    int netcount;
304    spinlock_t netlock;
305
306#if SYNCLINK_GENERIC_HDLC
307    struct net_device *netdev;
308#endif
309};
310
311#define MGSL_MAGIC 0x5401
312
313/*
314 * The size of the serial xmit buffer is 1 page, or 4096 bytes
315 */
316#ifndef SERIAL_XMIT_SIZE
317#define SERIAL_XMIT_SIZE 4096
318#endif
319
320/*
321 * These macros define the offsets used in calculating the
322 * I/O address of the specified USC registers.
323 */
324
325
326#define DCPIN 2 /* Bit 1 of I/O address */
327#define SDPIN 4 /* Bit 2 of I/O address */
328
329#define DCAR 0 /* DMA command/address register */
330#define CCAR SDPIN /* channel command/address register */
331#define DATAREG DCPIN + SDPIN /* serial data register */
332#define MSBONLY 0x41
333#define LSBONLY 0x40
334
335/*
336 * These macros define the register address (ordinal number)
337 * used for writing address/value pairs to the USC.
338 */
339
340#define CMR 0x02 /* Channel mode Register */
341#define CCSR 0x04 /* Channel Command/status Register */
342#define CCR 0x06 /* Channel Control Register */
343#define PSR 0x08 /* Port status Register */
344#define PCR 0x0a /* Port Control Register */
345#define TMDR 0x0c /* Test mode Data Register */
346#define TMCR 0x0e /* Test mode Control Register */
347#define CMCR 0x10 /* Clock mode Control Register */
348#define HCR 0x12 /* Hardware Configuration Register */
349#define IVR 0x14 /* Interrupt Vector Register */
350#define IOCR 0x16 /* Input/Output Control Register */
351#define ICR 0x18 /* Interrupt Control Register */
352#define DCCR 0x1a /* Daisy Chain Control Register */
353#define MISR 0x1c /* Misc Interrupt status Register */
354#define SICR 0x1e /* status Interrupt Control Register */
355#define RDR 0x20 /* Receive Data Register */
356#define RMR 0x22 /* Receive mode Register */
357#define RCSR 0x24 /* Receive Command/status Register */
358#define RICR 0x26 /* Receive Interrupt Control Register */
359#define RSR 0x28 /* Receive Sync Register */
360#define RCLR 0x2a /* Receive count Limit Register */
361#define RCCR 0x2c /* Receive Character count Register */
362#define TC0R 0x2e /* Time Constant 0 Register */
363#define TDR 0x30 /* Transmit Data Register */
364#define TMR 0x32 /* Transmit mode Register */
365#define TCSR 0x34 /* Transmit Command/status Register */
366#define TICR 0x36 /* Transmit Interrupt Control Register */
367#define TSR 0x38 /* Transmit Sync Register */
368#define TCLR 0x3a /* Transmit count Limit Register */
369#define TCCR 0x3c /* Transmit Character count Register */
370#define TC1R 0x3e /* Time Constant 1 Register */
371
372
373/*
374 * MACRO DEFINITIONS FOR DMA REGISTERS
375 */
376
377#define DCR 0x06 /* DMA Control Register (shared) */
378#define DACR 0x08 /* DMA Array count Register (shared) */
379#define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
380#define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
381#define DICR 0x18 /* DMA Interrupt Control Register (shared) */
382#define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
383#define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
384
385#define TDMR 0x02 /* Transmit DMA mode Register */
386#define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
387#define TBCR 0x2a /* Transmit Byte count Register */
388#define TARL 0x2c /* Transmit Address Register (low) */
389#define TARU 0x2e /* Transmit Address Register (high) */
390#define NTBCR 0x3a /* Next Transmit Byte count Register */
391#define NTARL 0x3c /* Next Transmit Address Register (low) */
392#define NTARU 0x3e /* Next Transmit Address Register (high) */
393
394#define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
395#define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
396#define RBCR 0xaa /* Receive Byte count Register */
397#define RARL 0xac /* Receive Address Register (low) */
398#define RARU 0xae /* Receive Address Register (high) */
399#define NRBCR 0xba /* Next Receive Byte count Register */
400#define NRARL 0xbc /* Next Receive Address Register (low) */
401#define NRARU 0xbe /* Next Receive Address Register (high) */
402
403
404/*
405 * MACRO DEFINITIONS FOR MODEM STATUS BITS
406 */
407
408#define MODEMSTATUS_DTR 0x80
409#define MODEMSTATUS_DSR 0x40
410#define MODEMSTATUS_RTS 0x20
411#define MODEMSTATUS_CTS 0x10
412#define MODEMSTATUS_RI 0x04
413#define MODEMSTATUS_DCD 0x01
414
415
416/*
417 * Channel Command/Address Register (CCAR) Command Codes
418 */
419
420#define RTCmd_Null 0x0000
421#define RTCmd_ResetHighestIus 0x1000
422#define RTCmd_TriggerChannelLoadDma 0x2000
423#define RTCmd_TriggerRxDma 0x2800
424#define RTCmd_TriggerTxDma 0x3000
425#define RTCmd_TriggerRxAndTxDma 0x3800
426#define RTCmd_PurgeRxFifo 0x4800
427#define RTCmd_PurgeTxFifo 0x5000
428#define RTCmd_PurgeRxAndTxFifo 0x5800
429#define RTCmd_LoadRcc 0x6800
430#define RTCmd_LoadTcc 0x7000
431#define RTCmd_LoadRccAndTcc 0x7800
432#define RTCmd_LoadTC0 0x8800
433#define RTCmd_LoadTC1 0x9000
434#define RTCmd_LoadTC0AndTC1 0x9800
435#define RTCmd_SerialDataLSBFirst 0xa000
436#define RTCmd_SerialDataMSBFirst 0xa800
437#define RTCmd_SelectBigEndian 0xb000
438#define RTCmd_SelectLittleEndian 0xb800
439
440
441/*
442 * DMA Command/Address Register (DCAR) Command Codes
443 */
444
445#define DmaCmd_Null 0x0000
446#define DmaCmd_ResetTxChannel 0x1000
447#define DmaCmd_ResetRxChannel 0x1200
448#define DmaCmd_StartTxChannel 0x2000
449#define DmaCmd_StartRxChannel 0x2200
450#define DmaCmd_ContinueTxChannel 0x3000
451#define DmaCmd_ContinueRxChannel 0x3200
452#define DmaCmd_PauseTxChannel 0x4000
453#define DmaCmd_PauseRxChannel 0x4200
454#define DmaCmd_AbortTxChannel 0x5000
455#define DmaCmd_AbortRxChannel 0x5200
456#define DmaCmd_InitTxChannel 0x7000
457#define DmaCmd_InitRxChannel 0x7200
458#define DmaCmd_ResetHighestDmaIus 0x8000
459#define DmaCmd_ResetAllChannels 0x9000
460#define DmaCmd_StartAllChannels 0xa000
461#define DmaCmd_ContinueAllChannels 0xb000
462#define DmaCmd_PauseAllChannels 0xc000
463#define DmaCmd_AbortAllChannels 0xd000
464#define DmaCmd_InitAllChannels 0xf000
465
466#define TCmd_Null 0x0000
467#define TCmd_ClearTxCRC 0x2000
468#define TCmd_SelectTicrTtsaData 0x4000
469#define TCmd_SelectTicrTxFifostatus 0x5000
470#define TCmd_SelectTicrIntLevel 0x6000
471#define TCmd_SelectTicrdma_level 0x7000
472#define TCmd_SendFrame 0x8000
473#define TCmd_SendAbort 0x9000
474#define TCmd_EnableDleInsertion 0xc000
475#define TCmd_DisableDleInsertion 0xd000
476#define TCmd_ClearEofEom 0xe000
477#define TCmd_SetEofEom 0xf000
478
479#define RCmd_Null 0x0000
480#define RCmd_ClearRxCRC 0x2000
481#define RCmd_EnterHuntmode 0x3000
482#define RCmd_SelectRicrRtsaData 0x4000
483#define RCmd_SelectRicrRxFifostatus 0x5000
484#define RCmd_SelectRicrIntLevel 0x6000
485#define RCmd_SelectRicrdma_level 0x7000
486
487/*
488 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
489 */
490 
491#define RECEIVE_STATUS BIT5
492#define RECEIVE_DATA BIT4
493#define TRANSMIT_STATUS BIT3
494#define TRANSMIT_DATA BIT2
495#define IO_PIN BIT1
496#define MISC BIT0
497
498
499/*
500 * Receive status Bits in Receive Command/status Register RCSR
501 */
502
503#define RXSTATUS_SHORT_FRAME BIT8
504#define RXSTATUS_CODE_VIOLATION BIT8
505#define RXSTATUS_EXITED_HUNT BIT7
506#define RXSTATUS_IDLE_RECEIVED BIT6
507#define RXSTATUS_BREAK_RECEIVED BIT5
508#define RXSTATUS_ABORT_RECEIVED BIT5
509#define RXSTATUS_RXBOUND BIT4
510#define RXSTATUS_CRC_ERROR BIT3
511#define RXSTATUS_FRAMING_ERROR BIT3
512#define RXSTATUS_ABORT BIT2
513#define RXSTATUS_PARITY_ERROR BIT2
514#define RXSTATUS_OVERRUN BIT1
515#define RXSTATUS_DATA_AVAILABLE BIT0
516#define RXSTATUS_ALL 0x01f6
517#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
518
519/*
520 * Values for setting transmit idle mode in
521 * Transmit Control/status Register (TCSR)
522 */
523#define IDLEMODE_FLAGS 0x0000
524#define IDLEMODE_ALT_ONE_ZERO 0x0100
525#define IDLEMODE_ZERO 0x0200
526#define IDLEMODE_ONE 0x0300
527#define IDLEMODE_ALT_MARK_SPACE 0x0500
528#define IDLEMODE_SPACE 0x0600
529#define IDLEMODE_MARK 0x0700
530#define IDLEMODE_MASK 0x0700
531
532/*
533 * IUSC revision identifiers
534 */
535#define IUSC_SL1660 0x4d44
536#define IUSC_PRE_SL1660 0x4553
537
538/*
539 * Transmit status Bits in Transmit Command/status Register (TCSR)
540 */
541
542#define TCSR_PRESERVE 0x0F00
543
544#define TCSR_UNDERWAIT BIT11
545#define TXSTATUS_PREAMBLE_SENT BIT7
546#define TXSTATUS_IDLE_SENT BIT6
547#define TXSTATUS_ABORT_SENT BIT5
548#define TXSTATUS_EOF_SENT BIT4
549#define TXSTATUS_EOM_SENT BIT4
550#define TXSTATUS_CRC_SENT BIT3
551#define TXSTATUS_ALL_SENT BIT2
552#define TXSTATUS_UNDERRUN BIT1
553#define TXSTATUS_FIFO_EMPTY BIT0
554#define TXSTATUS_ALL 0x00fa
555#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
556                
557
558#define MISCSTATUS_RXC_LATCHED BIT15
559#define MISCSTATUS_RXC BIT14
560#define MISCSTATUS_TXC_LATCHED BIT13
561#define MISCSTATUS_TXC BIT12
562#define MISCSTATUS_RI_LATCHED BIT11
563#define MISCSTATUS_RI BIT10
564#define MISCSTATUS_DSR_LATCHED BIT9
565#define MISCSTATUS_DSR BIT8
566#define MISCSTATUS_DCD_LATCHED BIT7
567#define MISCSTATUS_DCD BIT6
568#define MISCSTATUS_CTS_LATCHED BIT5
569#define MISCSTATUS_CTS BIT4
570#define MISCSTATUS_RCC_UNDERRUN BIT3
571#define MISCSTATUS_DPLL_NO_SYNC BIT2
572#define MISCSTATUS_BRG1_ZERO BIT1
573#define MISCSTATUS_BRG0_ZERO BIT0
574
575#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
576#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
577
578#define SICR_RXC_ACTIVE BIT15
579#define SICR_RXC_INACTIVE BIT14
580#define SICR_RXC (BIT15+BIT14)
581#define SICR_TXC_ACTIVE BIT13
582#define SICR_TXC_INACTIVE BIT12
583#define SICR_TXC (BIT13+BIT12)
584#define SICR_RI_ACTIVE BIT11
585#define SICR_RI_INACTIVE BIT10
586#define SICR_RI (BIT11+BIT10)
587#define SICR_DSR_ACTIVE BIT9
588#define SICR_DSR_INACTIVE BIT8
589#define SICR_DSR (BIT9+BIT8)
590#define SICR_DCD_ACTIVE BIT7
591#define SICR_DCD_INACTIVE BIT6
592#define SICR_DCD (BIT7+BIT6)
593#define SICR_CTS_ACTIVE BIT5
594#define SICR_CTS_INACTIVE BIT4
595#define SICR_CTS (BIT5+BIT4)
596#define SICR_RCC_UNDERFLOW BIT3
597#define SICR_DPLL_NO_SYNC BIT2
598#define SICR_BRG1_ZERO BIT1
599#define SICR_BRG0_ZERO BIT0
600
601void usc_DisableMasterIrqBit( struct mgsl_struct *info );
602void usc_EnableMasterIrqBit( struct mgsl_struct *info );
603void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
604void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
605void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
606
607#define usc_EnableInterrupts( a, b ) \
608    usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
609
610#define usc_DisableInterrupts( a, b ) \
611    usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
612
613#define usc_EnableMasterIrqBit(a) \
614    usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
615
616#define usc_DisableMasterIrqBit(a) \
617    usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
618
619#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
620
621/*
622 * Transmit status Bits in Transmit Control status Register (TCSR)
623 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
624 */
625
626#define TXSTATUS_PREAMBLE_SENT BIT7
627#define TXSTATUS_IDLE_SENT BIT6
628#define TXSTATUS_ABORT_SENT BIT5
629#define TXSTATUS_EOF BIT4
630#define TXSTATUS_CRC_SENT BIT3
631#define TXSTATUS_ALL_SENT BIT2
632#define TXSTATUS_UNDERRUN BIT1
633#define TXSTATUS_FIFO_EMPTY BIT0
634
635#define DICR_MASTER BIT15
636#define DICR_TRANSMIT BIT0
637#define DICR_RECEIVE BIT1
638
639#define usc_EnableDmaInterrupts(a,b) \
640    usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
641
642#define usc_DisableDmaInterrupts(a,b) \
643    usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
644
645#define usc_EnableStatusIrqs(a,b) \
646    usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
647
648#define usc_DisablestatusIrqs(a,b) \
649    usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
650
651/* Transmit status Bits in Transmit Control status Register (TCSR) */
652/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
653
654
655#define DISABLE_UNCONDITIONAL 0
656#define DISABLE_END_OF_FRAME 1
657#define ENABLE_UNCONDITIONAL 2
658#define ENABLE_AUTO_CTS 3
659#define ENABLE_AUTO_DCD 3
660#define usc_EnableTransmitter(a,b) \
661    usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
662#define usc_EnableReceiver(a,b) \
663    usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
664
665static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
666static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
667static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
668
669static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
670static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
671static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
672void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
673void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
674
675#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
676#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
677
678#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
679
680static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
681static void usc_start_receiver( struct mgsl_struct *info );
682static void usc_stop_receiver( struct mgsl_struct *info );
683
684static void usc_start_transmitter( struct mgsl_struct *info );
685static void usc_stop_transmitter( struct mgsl_struct *info );
686static void usc_set_txidle( struct mgsl_struct *info );
687static void usc_load_txfifo( struct mgsl_struct *info );
688
689static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
690static void usc_enable_loopback( struct mgsl_struct *info, int enable );
691
692static void usc_get_serial_signals( struct mgsl_struct *info );
693static void usc_set_serial_signals( struct mgsl_struct *info );
694
695static void usc_reset( struct mgsl_struct *info );
696
697static void usc_set_sync_mode( struct mgsl_struct *info );
698static void usc_set_sdlc_mode( struct mgsl_struct *info );
699static void usc_set_async_mode( struct mgsl_struct *info );
700static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
701
702static void usc_loopback_frame( struct mgsl_struct *info );
703
704static void mgsl_tx_timeout(unsigned long context);
705
706
707static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
708static void usc_loopmode_insert_request( struct mgsl_struct * info );
709static int usc_loopmode_active( struct mgsl_struct * info);
710static void usc_loopmode_send_done( struct mgsl_struct * info );
711
712static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
713
714#if SYNCLINK_GENERIC_HDLC
715#define dev_to_port(D) (dev_to_hdlc(D)->priv)
716static void hdlcdev_tx_done(struct mgsl_struct *info);
717static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
718static int hdlcdev_init(struct mgsl_struct *info);
719static void hdlcdev_exit(struct mgsl_struct *info);
720#endif
721
722/*
723 * Defines a BUS descriptor value for the PCI adapter
724 * local bus address ranges.
725 */
726
727#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
728(0x00400020 + \
729((WrHold) << 30) + \
730((WrDly) << 28) + \
731((RdDly) << 26) + \
732((Nwdd) << 20) + \
733((Nwad) << 15) + \
734((Nxda) << 13) + \
735((Nrdd) << 11) + \
736((Nrad) << 6) )
737
738static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
739
740/*
741 * Adapter diagnostic routines
742 */
743static bool mgsl_register_test( struct mgsl_struct *info );
744static bool mgsl_irq_test( struct mgsl_struct *info );
745static bool mgsl_dma_test( struct mgsl_struct *info );
746static bool mgsl_memory_test( struct mgsl_struct *info );
747static int mgsl_adapter_test( struct mgsl_struct *info );
748
749/*
750 * device and resource management routines
751 */
752static int mgsl_claim_resources(struct mgsl_struct *info);
753static void mgsl_release_resources(struct mgsl_struct *info);
754static void mgsl_add_device(struct mgsl_struct *info);
755static struct mgsl_struct* mgsl_allocate_device(void);
756
757/*
758 * DMA buffer manupulation functions.
759 */
760static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
761static bool mgsl_get_rx_frame( struct mgsl_struct *info );
762static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
763static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
764static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
765static int num_free_tx_dma_buffers(struct mgsl_struct *info);
766static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
767static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
768
769/*
770 * DMA and Shared Memory buffer allocation and formatting
771 */
772static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
773static void mgsl_free_dma_buffers(struct mgsl_struct *info);
774static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
775static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
776static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
777static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
778static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
779static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
780static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
781static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
782static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
783static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
784
785/*
786 * Bottom half interrupt handlers
787 */
788static void mgsl_bh_handler(struct work_struct *work);
789static void mgsl_bh_receive(struct mgsl_struct *info);
790static void mgsl_bh_transmit(struct mgsl_struct *info);
791static void mgsl_bh_status(struct mgsl_struct *info);
792
793/*
794 * Interrupt handler routines and dispatch table.
795 */
796static void mgsl_isr_null( struct mgsl_struct *info );
797static void mgsl_isr_transmit_data( struct mgsl_struct *info );
798static void mgsl_isr_receive_data( struct mgsl_struct *info );
799static void mgsl_isr_receive_status( struct mgsl_struct *info );
800static void mgsl_isr_transmit_status( struct mgsl_struct *info );
801static void mgsl_isr_io_pin( struct mgsl_struct *info );
802static void mgsl_isr_misc( struct mgsl_struct *info );
803static void mgsl_isr_receive_dma( struct mgsl_struct *info );
804static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
805
806typedef void (*isr_dispatch_func)(struct mgsl_struct *);
807
808static isr_dispatch_func UscIsrTable[7] =
809{
810    mgsl_isr_null,
811    mgsl_isr_misc,
812    mgsl_isr_io_pin,
813    mgsl_isr_transmit_data,
814    mgsl_isr_transmit_status,
815    mgsl_isr_receive_data,
816    mgsl_isr_receive_status
817};
818
819/*
820 * ioctl call handlers
821 */
822static int tiocmget(struct tty_struct *tty);
823static int tiocmset(struct tty_struct *tty,
824            unsigned int set, unsigned int clear);
825static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
826    __user *user_icount);
827static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
828static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
829static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
830static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
831static int mgsl_txenable(struct mgsl_struct * info, int enable);
832static int mgsl_txabort(struct mgsl_struct * info);
833static int mgsl_rxenable(struct mgsl_struct * info, int enable);
834static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
835static int mgsl_loopmode_send_done( struct mgsl_struct * info );
836
837/* set non-zero on successful registration with PCI subsystem */
838static bool pci_registered;
839
840/*
841 * Global linked list of SyncLink devices
842 */
843static struct mgsl_struct *mgsl_device_list;
844static int mgsl_device_count;
845
846/*
847 * Set this param to non-zero to load eax with the
848 * .text section address and breakpoint on module load.
849 * This is useful for use with gdb and add-symbol-file command.
850 */
851static bool break_on_load;
852
853/*
854 * Driver major number, defaults to zero to get auto
855 * assigned major number. May be forced as module parameter.
856 */
857static int ttymajor;
858
859/*
860 * Array of user specified options for ISA adapters.
861 */
862static int io[MAX_ISA_DEVICES];
863static int irq[MAX_ISA_DEVICES];
864static int dma[MAX_ISA_DEVICES];
865static int debug_level;
866static int maxframe[MAX_TOTAL_DEVICES];
867static int txdmabufs[MAX_TOTAL_DEVICES];
868static int txholdbufs[MAX_TOTAL_DEVICES];
869    
870module_param(break_on_load, bool, 0);
871module_param(ttymajor, int, 0);
872module_param_array(io, int, NULL, 0);
873module_param_array(irq, int, NULL, 0);
874module_param_array(dma, int, NULL, 0);
875module_param(debug_level, int, 0);
876module_param_array(maxframe, int, NULL, 0);
877module_param_array(txdmabufs, int, NULL, 0);
878module_param_array(txholdbufs, int, NULL, 0);
879
880static char *driver_name = "SyncLink serial driver";
881static char *driver_version = "$Revision: 4.38 $";
882
883static int synclink_init_one (struct pci_dev *dev,
884                     const struct pci_device_id *ent);
885static void synclink_remove_one (struct pci_dev *dev);
886
887static struct pci_device_id synclink_pci_tbl[] = {
888    { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
889    { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
890    { 0, }, /* terminate list */
891};
892MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
893
894MODULE_LICENSE("GPL");
895
896static struct pci_driver synclink_pci_driver = {
897    .name = "synclink",
898    .id_table = synclink_pci_tbl,
899    .probe = synclink_init_one,
900    .remove = synclink_remove_one,
901};
902
903static struct tty_driver *serial_driver;
904
905/* number of characters left in xmit buffer before we ask for more */
906#define WAKEUP_CHARS 256
907
908
909static void mgsl_change_params(struct mgsl_struct *info);
910static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
911
912/*
913 * 1st function defined in .text section. Calling this function in
914 * init_module() followed by a breakpoint allows a remote debugger
915 * (gdb) to get the .text address for the add-symbol-file command.
916 * This allows remote debugging of dynamically loadable modules.
917 */
918static void* mgsl_get_text_ptr(void)
919{
920    return mgsl_get_text_ptr;
921}
922
923static inline int mgsl_paranoia_check(struct mgsl_struct *info,
924                    char *name, const char *routine)
925{
926#ifdef MGSL_PARANOIA_CHECK
927    static const char *badmagic =
928        "Warning: bad magic number for mgsl struct (%s) in %s\n";
929    static const char *badinfo =
930        "Warning: null mgsl_struct for (%s) in %s\n";
931
932    if (!info) {
933        printk(badinfo, name, routine);
934        return 1;
935    }
936    if (info->magic != MGSL_MAGIC) {
937        printk(badmagic, name, routine);
938        return 1;
939    }
940#else
941    if (!info)
942        return 1;
943#endif
944    return 0;
945}
946
947/**
948 * line discipline callback wrappers
949 *
950 * The wrappers maintain line discipline references
951 * while calling into the line discipline.
952 *
953 * ldisc_receive_buf - pass receive data to line discipline
954 */
955
956static void ldisc_receive_buf(struct tty_struct *tty,
957                  const __u8 *data, char *flags, int count)
958{
959    struct tty_ldisc *ld;
960    if (!tty)
961        return;
962    ld = tty_ldisc_ref(tty);
963    if (ld) {
964        if (ld->ops->receive_buf)
965            ld->ops->receive_buf(tty, data, flags, count);
966        tty_ldisc_deref(ld);
967    }
968}
969
970/* mgsl_stop() throttle (stop) transmitter
971 *
972 * Arguments: tty pointer to tty info structure
973 * Return Value: None
974 */
975static void mgsl_stop(struct tty_struct *tty)
976{
977    struct mgsl_struct *info = tty->driver_data;
978    unsigned long flags;
979    
980    if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
981        return;
982    
983    if ( debug_level >= DEBUG_LEVEL_INFO )
984        printk("mgsl_stop(%s)\n",info->device_name);
985        
986    spin_lock_irqsave(&info->irq_spinlock,flags);
987    if (info->tx_enabled)
988         usc_stop_transmitter(info);
989    spin_unlock_irqrestore(&info->irq_spinlock,flags);
990    
991} /* end of mgsl_stop() */
992
993/* mgsl_start() release (start) transmitter
994 *
995 * Arguments: tty pointer to tty info structure
996 * Return Value: None
997 */
998static void mgsl_start(struct tty_struct *tty)
999{
1000    struct mgsl_struct *info = tty->driver_data;
1001    unsigned long flags;
1002    
1003    if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1004        return;
1005    
1006    if ( debug_level >= DEBUG_LEVEL_INFO )
1007        printk("mgsl_start(%s)\n",info->device_name);
1008        
1009    spin_lock_irqsave(&info->irq_spinlock,flags);
1010    if (!info->tx_enabled)
1011         usc_start_transmitter(info);
1012    spin_unlock_irqrestore(&info->irq_spinlock,flags);
1013    
1014} /* end of mgsl_start() */
1015
1016/*
1017 * Bottom half work queue access functions
1018 */
1019
1020/* mgsl_bh_action() Return next bottom half action to perform.
1021 * Return Value: BH action code or 0 if nothing to do.
1022 */
1023static int mgsl_bh_action(struct mgsl_struct *info)
1024{
1025    unsigned long flags;
1026    int rc = 0;
1027    
1028    spin_lock_irqsave(&info->irq_spinlock,flags);
1029
1030    if (info->pending_bh & BH_RECEIVE) {
1031        info->pending_bh &= ~BH_RECEIVE;
1032        rc = BH_RECEIVE;
1033    } else if (info->pending_bh & BH_TRANSMIT) {
1034        info->pending_bh &= ~BH_TRANSMIT;
1035        rc = BH_TRANSMIT;
1036    } else if (info->pending_bh & BH_STATUS) {
1037        info->pending_bh &= ~BH_STATUS;
1038        rc = BH_STATUS;
1039    }
1040
1041    if (!rc) {
1042        /* Mark BH routine as complete */
1043        info->bh_running = false;
1044        info->bh_requested = false;
1045    }
1046    
1047    spin_unlock_irqrestore(&info->irq_spinlock,flags);
1048    
1049    return rc;
1050}
1051
1052/*
1053 * Perform bottom half processing of work items queued by ISR.
1054 */
1055static void mgsl_bh_handler(struct work_struct *work)
1056{
1057    struct mgsl_struct *info =
1058        container_of(work, struct mgsl_struct, task);
1059    int action;
1060
1061    if (!info)
1062        return;
1063        
1064    if ( debug_level >= DEBUG_LEVEL_BH )
1065        printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1066            __FILE__,__LINE__,info->device_name);
1067    
1068    info->bh_running = true;
1069
1070    while((action = mgsl_bh_action(info)) != 0) {
1071    
1072        /* Process work item */
1073        if ( debug_level >= DEBUG_LEVEL_BH )
1074            printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1075                __FILE__,__LINE__,action);
1076
1077        switch (action) {
1078        
1079        case BH_RECEIVE:
1080            mgsl_bh_receive(info);
1081            break;
1082        case BH_TRANSMIT:
1083            mgsl_bh_transmit(info);
1084            break;
1085        case BH_STATUS:
1086            mgsl_bh_status(info);
1087            break;
1088        default:
1089            /* unknown work item ID */
1090            printk("Unknown work item ID=%08X!\n", action);
1091            break;
1092        }
1093    }
1094
1095    if ( debug_level >= DEBUG_LEVEL_BH )
1096        printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1097            __FILE__,__LINE__,info->device_name);
1098}
1099
1100static void mgsl_bh_receive(struct mgsl_struct *info)
1101{
1102    bool (*get_rx_frame)(struct mgsl_struct *info) =
1103        (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1104
1105    if ( debug_level >= DEBUG_LEVEL_BH )
1106        printk( "%s(%d):mgsl_bh_receive(%s)\n",
1107            __FILE__,__LINE__,info->device_name);
1108    
1109    do
1110    {
1111        if (info->rx_rcc_underrun) {
1112            unsigned long flags;
1113            spin_lock_irqsave(&info->irq_spinlock,flags);
1114            usc_start_receiver(info);
1115            spin_unlock_irqrestore(&info->irq_spinlock,flags);
1116            return;
1117        }
1118    } while(get_rx_frame(info));
1119}
1120
1121static void mgsl_bh_transmit(struct mgsl_struct *info)
1122{
1123    struct tty_struct *tty = info->port.tty;
1124    unsigned long flags;
1125    
1126    if ( debug_level >= DEBUG_LEVEL_BH )
1127        printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1128            __FILE__,__LINE__,info->device_name);
1129
1130    if (tty)
1131        tty_wakeup(tty);
1132
1133    /* if transmitter idle and loopmode_send_done_requested
1134     * then start echoing RxD to TxD
1135     */
1136    spin_lock_irqsave(&info->irq_spinlock,flags);
1137     if ( !info->tx_active && info->loopmode_send_done_requested )
1138         usc_loopmode_send_done( info );
1139    spin_unlock_irqrestore(&info->irq_spinlock,flags);
1140}
1141
1142static void mgsl_bh_status(struct mgsl_struct *info)
1143{
1144    if ( debug_level >= DEBUG_LEVEL_BH )
1145        printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1146            __FILE__,__LINE__,info->device_name);
1147
1148    info->ri_chkcount = 0;
1149    info->dsr_chkcount = 0;
1150    info->dcd_chkcount = 0;
1151    info->cts_chkcount = 0;
1152}
1153
1154/* mgsl_isr_receive_status()
1155 *
1156 * Service a receive status interrupt. The type of status
1157 * interrupt is indicated by the state of the RCSR.
1158 * This is only used for HDLC mode.
1159 *
1160 * Arguments: info pointer to device instance data
1161 * Return Value: None
1162 */
1163static void mgsl_isr_receive_status( struct mgsl_struct *info )
1164{
1165    u16 status = usc_InReg( info, RCSR );
1166
1167    if ( debug_level >= DEBUG_LEVEL_ISR )
1168        printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1169            __FILE__,__LINE__,status);
1170            
1171     if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1172        info->loopmode_insert_requested &&
1173         usc_loopmode_active(info) )
1174     {
1175        ++info->icount.rxabort;
1176         info->loopmode_insert_requested = false;
1177 
1178         /* clear CMR:13 to start echoing RxD to TxD */
1179        info->cmr_value &= ~BIT13;
1180         usc_OutReg(info, CMR, info->cmr_value);
1181 
1182        /* disable received abort irq (no longer required) */
1183         usc_OutReg(info, RICR,
1184             (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1185     }
1186
1187    if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1188        if (status & RXSTATUS_EXITED_HUNT)
1189            info->icount.exithunt++;
1190        if (status & RXSTATUS_IDLE_RECEIVED)
1191            info->icount.rxidle++;
1192        wake_up_interruptible(&info->event_wait_q);
1193    }
1194
1195    if (status & RXSTATUS_OVERRUN){
1196        info->icount.rxover++;
1197        usc_process_rxoverrun_sync( info );
1198    }
1199
1200    usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1201    usc_UnlatchRxstatusBits( info, status );
1202
1203} /* end of mgsl_isr_receive_status() */
1204
1205/* mgsl_isr_transmit_status()
1206 *
1207 * Service a transmit status interrupt
1208 * HDLC mode :end of transmit frame
1209 * Async mode:all data is sent
1210 * transmit status is indicated by bits in the TCSR.
1211 *
1212 * Arguments: info pointer to device instance data
1213 * Return Value: None
1214 */
1215static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1216{
1217    u16 status = usc_InReg( info, TCSR );
1218
1219    if ( debug_level >= DEBUG_LEVEL_ISR )
1220        printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1221            __FILE__,__LINE__,status);
1222    
1223    usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1224    usc_UnlatchTxstatusBits( info, status );
1225    
1226    if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1227    {
1228        /* finished sending HDLC abort. This may leave */
1229        /* the TxFifo with data from the aborted frame */
1230        /* so purge the TxFifo. Also shutdown the DMA */
1231        /* channel in case there is data remaining in */
1232        /* the DMA buffer */
1233         usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1234         usc_RTCmd( info, RTCmd_PurgeTxFifo );
1235    }
1236 
1237    if ( status & TXSTATUS_EOF_SENT )
1238        info->icount.txok++;
1239    else if ( status & TXSTATUS_UNDERRUN )
1240        info->icount.txunder++;
1241    else if ( status & TXSTATUS_ABORT_SENT )
1242        info->icount.txabort++;
1243    else
1244        info->icount.txunder++;
1245            
1246    info->tx_active = false;
1247    info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1248    del_timer(&info->tx_timer);
1249    
1250    if ( info->drop_rts_on_tx_done ) {
1251        usc_get_serial_signals( info );
1252        if ( info->serial_signals & SerialSignal_RTS ) {
1253            info->serial_signals &= ~SerialSignal_RTS;
1254            usc_set_serial_signals( info );
1255        }
1256        info->drop_rts_on_tx_done = false;
1257    }
1258
1259#if SYNCLINK_GENERIC_HDLC
1260    if (info->netcount)
1261        hdlcdev_tx_done(info);
1262    else
1263#endif
1264    {
1265        if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1266            usc_stop_transmitter(info);
1267            return;
1268        }
1269        info->pending_bh |= BH_TRANSMIT;
1270    }
1271
1272} /* end of mgsl_isr_transmit_status() */
1273
1274/* mgsl_isr_io_pin()
1275 *
1276 * Service an Input/Output pin interrupt. The type of
1277 * interrupt is indicated by bits in the MISR
1278 *
1279 * Arguments: info pointer to device instance data
1280 * Return Value: None
1281 */
1282static void mgsl_isr_io_pin( struct mgsl_struct *info )
1283{
1284     struct mgsl_icount *icount;
1285    u16 status = usc_InReg( info, MISR );
1286
1287    if ( debug_level >= DEBUG_LEVEL_ISR )
1288        printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1289            __FILE__,__LINE__,status);
1290            
1291    usc_ClearIrqPendingBits( info, IO_PIN );
1292    usc_UnlatchIostatusBits( info, status );
1293
1294    if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1295                  MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1296        icount = &info->icount;
1297        /* update input line counters */
1298        if (status & MISCSTATUS_RI_LATCHED) {
1299            if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1300                usc_DisablestatusIrqs(info,SICR_RI);
1301            icount->rng++;
1302            if ( status & MISCSTATUS_RI )
1303                info->input_signal_events.ri_up++;
1304            else
1305                info->input_signal_events.ri_down++;
1306        }
1307        if (status & MISCSTATUS_DSR_LATCHED) {
1308            if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1309                usc_DisablestatusIrqs(info,SICR_DSR);
1310            icount->dsr++;
1311            if ( status & MISCSTATUS_DSR )
1312                info->input_signal_events.dsr_up++;
1313            else
1314                info->input_signal_events.dsr_down++;
1315        }
1316        if (status & MISCSTATUS_DCD_LATCHED) {
1317            if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1318                usc_DisablestatusIrqs(info,SICR_DCD);
1319            icount->dcd++;
1320            if (status & MISCSTATUS_DCD) {
1321                info->input_signal_events.dcd_up++;
1322            } else
1323                info->input_signal_events.dcd_down++;
1324#if SYNCLINK_GENERIC_HDLC
1325            if (info->netcount) {
1326                if (status & MISCSTATUS_DCD)
1327                    netif_carrier_on(info->netdev);
1328                else
1329                    netif_carrier_off(info->netdev);
1330            }
1331#endif
1332        }
1333        if (status & MISCSTATUS_CTS_LATCHED)
1334        {
1335            if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1336                usc_DisablestatusIrqs(info,SICR_CTS);
1337            icount->cts++;
1338            if ( status & MISCSTATUS_CTS )
1339                info->input_signal_events.cts_up++;
1340            else
1341                info->input_signal_events.cts_down++;
1342        }
1343        wake_up_interruptible(&info->status_event_wait_q);
1344        wake_up_interruptible(&info->event_wait_q);
1345
1346        if ( (info->port.flags & ASYNC_CHECK_CD) &&
1347             (status & MISCSTATUS_DCD_LATCHED) ) {
1348            if ( debug_level >= DEBUG_LEVEL_ISR )
1349                printk("%s CD now %s...", info->device_name,
1350                       (status & MISCSTATUS_DCD) ? "on" : "off");
1351            if (status & MISCSTATUS_DCD)
1352                wake_up_interruptible(&info->port.open_wait);
1353            else {
1354                if ( debug_level >= DEBUG_LEVEL_ISR )
1355                    printk("doing serial hangup...");
1356                if (info->port.tty)
1357                    tty_hangup(info->port.tty);
1358            }
1359        }
1360    
1361        if (tty_port_cts_enabled(&info->port) &&
1362             (status & MISCSTATUS_CTS_LATCHED) ) {
1363            if (info->port.tty->hw_stopped) {
1364                if (status & MISCSTATUS_CTS) {
1365                    if ( debug_level >= DEBUG_LEVEL_ISR )
1366                        printk("CTS tx start...");
1367                    if (info->port.tty)
1368                        info->port.tty->hw_stopped = 0;
1369                    usc_start_transmitter(info);
1370                    info->pending_bh |= BH_TRANSMIT;
1371                    return;
1372                }
1373            } else {
1374                if (!(status & MISCSTATUS_CTS)) {
1375                    if ( debug_level >= DEBUG_LEVEL_ISR )
1376                        printk("CTS tx stop...");
1377                    if (info->port.tty)
1378                        info->port.tty->hw_stopped = 1;
1379                    usc_stop_transmitter(info);
1380                }
1381            }
1382        }
1383    }
1384
1385    info->pending_bh |= BH_STATUS;
1386    
1387    /* for diagnostics set IRQ flag */
1388    if ( status & MISCSTATUS_TXC_LATCHED ){
1389        usc_OutReg( info, SICR,
1390            (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1391        usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1392        info->irq_occurred = true;
1393    }
1394
1395} /* end of mgsl_isr_io_pin() */
1396
1397/* mgsl_isr_transmit_data()
1398 *
1399 * Service a transmit data interrupt (async mode only).
1400 *
1401 * Arguments: info pointer to device instance data
1402 * Return Value: None
1403 */
1404static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1405{
1406    if ( debug_level >= DEBUG_LEVEL_ISR )
1407        printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1408            __FILE__,__LINE__,info->xmit_cnt);
1409            
1410    usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1411    
1412    if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1413        usc_stop_transmitter(info);
1414        return;
1415    }
1416    
1417    if ( info->xmit_cnt )
1418        usc_load_txfifo( info );
1419    else
1420        info->tx_active = false;
1421        
1422    if (info->xmit_cnt < WAKEUP_CHARS)
1423        info->pending_bh |= BH_TRANSMIT;
1424
1425} /* end of mgsl_isr_transmit_data() */
1426
1427/* mgsl_isr_receive_data()
1428 *
1429 * Service a receive data interrupt. This occurs
1430 * when operating in asynchronous interrupt transfer mode.
1431 * The receive data FIFO is flushed to the receive data buffers.
1432 *
1433 * Arguments: info pointer to device instance data
1434 * Return Value: None
1435 */
1436static void mgsl_isr_receive_data( struct mgsl_struct *info )
1437{
1438    int Fifocount;
1439    u16 status;
1440    int work = 0;
1441    unsigned char DataByte;
1442     struct mgsl_icount *icount = &info->icount;
1443    
1444    if ( debug_level >= DEBUG_LEVEL_ISR )
1445        printk("%s(%d):mgsl_isr_receive_data\n",
1446            __FILE__,__LINE__);
1447
1448    usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1449    
1450    /* select FIFO status for RICR readback */
1451    usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1452
1453    /* clear the Wordstatus bit so that status readback */
1454    /* only reflects the status of this byte */
1455    usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1456
1457    /* flush the receive FIFO */
1458
1459    while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1460        int flag;
1461
1462        /* read one byte from RxFIFO */
1463        outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1464              info->io_base + CCAR );
1465        DataByte = inb( info->io_base + CCAR );
1466
1467        /* get the status of the received byte */
1468        status = usc_InReg(info, RCSR);
1469        if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1470                RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1471            usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1472        
1473        icount->rx++;
1474        
1475        flag = 0;
1476        if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1477                RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1478            printk("rxerr=%04X\n",status);
1479            /* update error statistics */
1480            if ( status & RXSTATUS_BREAK_RECEIVED ) {
1481                status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1482                icount->brk++;
1483            } else if (status & RXSTATUS_PARITY_ERROR)
1484                icount->parity++;
1485            else if (status & RXSTATUS_FRAMING_ERROR)
1486                icount->frame++;
1487            else if (status & RXSTATUS_OVERRUN) {
1488                /* must issue purge fifo cmd before */
1489                /* 16C32 accepts more receive chars */
1490                usc_RTCmd(info,RTCmd_PurgeRxFifo);
1491                icount->overrun++;
1492            }
1493
1494            /* discard char if tty control flags say so */
1495            if (status & info->ignore_status_mask)
1496                continue;
1497                
1498            status &= info->read_status_mask;
1499        
1500            if (status & RXSTATUS_BREAK_RECEIVED) {
1501                flag = TTY_BREAK;
1502                if (info->port.flags & ASYNC_SAK)
1503                    do_SAK(info->port.tty);
1504            } else if (status & RXSTATUS_PARITY_ERROR)
1505                flag = TTY_PARITY;
1506            else if (status & RXSTATUS_FRAMING_ERROR)
1507                flag = TTY_FRAME;
1508        } /* end of if (error) */
1509        tty_insert_flip_char(&info->port, DataByte, flag);
1510        if (status & RXSTATUS_OVERRUN) {
1511            /* Overrun is special, since it's
1512             * reported immediately, and doesn't
1513             * affect the current character
1514             */
1515            work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
1516        }
1517    }
1518
1519    if ( debug_level >= DEBUG_LEVEL_ISR ) {
1520        printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1521            __FILE__,__LINE__,icount->rx,icount->brk,
1522            icount->parity,icount->frame,icount->overrun);
1523    }
1524            
1525    if(work)
1526        tty_flip_buffer_push(&info->port);
1527}
1528
1529/* mgsl_isr_misc()
1530 *
1531 * Service a miscellaneous interrupt source.
1532 *
1533 * Arguments: info pointer to device extension (instance data)
1534 * Return Value: None
1535 */
1536static void mgsl_isr_misc( struct mgsl_struct *info )
1537{
1538    u16 status = usc_InReg( info, MISR );
1539
1540    if ( debug_level >= DEBUG_LEVEL_ISR )
1541        printk("%s(%d):mgsl_isr_misc status=%04X\n",
1542            __FILE__,__LINE__,status);
1543            
1544    if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1545        (info->params.mode == MGSL_MODE_HDLC)) {
1546
1547        /* turn off receiver and rx DMA */
1548        usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1549        usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1550        usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1551        usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1552        usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1553
1554        /* schedule BH handler to restart receiver */
1555        info->pending_bh |= BH_RECEIVE;
1556        info->rx_rcc_underrun = true;
1557    }
1558
1559    usc_ClearIrqPendingBits( info, MISC );
1560    usc_UnlatchMiscstatusBits( info, status );
1561
1562} /* end of mgsl_isr_misc() */
1563
1564/* mgsl_isr_null()
1565 *
1566 * Services undefined interrupt vectors from the
1567 * USC. (hence this function SHOULD never be called)
1568 *
1569 * Arguments: info pointer to device extension (instance data)
1570 * Return Value: None
1571 */
1572static void mgsl_isr_null( struct mgsl_struct *info )
1573{
1574
1575} /* end of mgsl_isr_null() */
1576
1577/* mgsl_isr_receive_dma()
1578 *
1579 * Service a receive DMA channel interrupt.
1580 * For this driver there are two sources of receive DMA interrupts
1581 * as identified in the Receive DMA mode Register (RDMR):
1582 *
1583 * BIT3 EOA/EOL End of List, all receive buffers in receive
1584 * buffer list have been filled (no more free buffers
1585 * available). The DMA controller has shut down.
1586 *
1587 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1588 * DMA buffer is terminated in response to completion
1589 * of a good frame or a frame with errors. The status
1590 * of the frame is stored in the buffer entry in the
1591 * list of receive buffer entries.
1592 *
1593 * Arguments: info pointer to device instance data
1594 * Return Value: None
1595 */
1596static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1597{
1598    u16 status;
1599    
1600    /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1601    usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1602
1603    /* Read the receive DMA status to identify interrupt type. */
1604    /* This also clears the status bits. */
1605    status = usc_InDmaReg( info, RDMR );
1606
1607    if ( debug_level >= DEBUG_LEVEL_ISR )
1608        printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1609            __FILE__,__LINE__,info->device_name,status);
1610            
1611    info->pending_bh |= BH_RECEIVE;
1612    
1613    if ( status & BIT3 ) {
1614        info->rx_overflow = true;
1615        info->icount.buf_overrun++;
1616    }
1617
1618} /* end of mgsl_isr_receive_dma() */
1619
1620/* mgsl_isr_transmit_dma()
1621 *
1622 * This function services a transmit DMA channel interrupt.
1623 *
1624 * For this driver there is one source of transmit DMA interrupts
1625 * as identified in the Transmit DMA Mode Register (TDMR):
1626 *
1627 * BIT2 EOB End of Buffer. This interrupt occurs when a
1628 * transmit DMA buffer has been emptied.
1629 *
1630 * The driver maintains enough transmit DMA buffers to hold at least
1631 * one max frame size transmit frame. When operating in a buffered
1632 * transmit mode, there may be enough transmit DMA buffers to hold at
1633 * least two or more max frame size frames. On an EOB condition,
1634 * determine if there are any queued transmit buffers and copy into
1635 * transmit DMA buffers if we have room.
1636 *
1637 * Arguments: info pointer to device instance data
1638 * Return Value: None
1639 */
1640static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1641{
1642    u16 status;
1643
1644    /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1645    usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1646
1647    /* Read the transmit DMA status to identify interrupt type. */
1648    /* This also clears the status bits. */
1649
1650    status = usc_InDmaReg( info, TDMR );
1651
1652    if ( debug_level >= DEBUG_LEVEL_ISR )
1653        printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1654            __FILE__,__LINE__,info->device_name,status);
1655
1656    if ( status & BIT2 ) {
1657        --info->tx_dma_buffers_used;
1658
1659        /* if there are transmit frames queued,
1660         * try to load the next one
1661         */
1662        if ( load_next_tx_holding_buffer(info) ) {
1663            /* if call returns non-zero value, we have
1664             * at least one free tx holding buffer
1665             */
1666            info->pending_bh |= BH_TRANSMIT;
1667        }
1668    }
1669
1670} /* end of mgsl_isr_transmit_dma() */
1671
1672/* mgsl_interrupt()
1673 *
1674 * Interrupt service routine entry point.
1675 *
1676 * Arguments:
1677 *
1678 * irq interrupt number that caused interrupt
1679 * dev_id device ID supplied during interrupt registration
1680 *
1681 * Return Value: None
1682 */
1683static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1684{
1685    struct mgsl_struct *info = dev_id;
1686    u16 UscVector;
1687    u16 DmaVector;
1688
1689    if ( debug_level >= DEBUG_LEVEL_ISR )
1690        printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1691            __FILE__, __LINE__, info->irq_level);
1692
1693    spin_lock(&info->irq_spinlock);
1694
1695    for(;;) {
1696        /* Read the interrupt vectors from hardware. */
1697        UscVector = usc_InReg(info, IVR) >> 9;
1698        DmaVector = usc_InDmaReg(info, DIVR);
1699        
1700        if ( debug_level >= DEBUG_LEVEL_ISR )
1701            printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1702                __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1703            
1704        if ( !UscVector && !DmaVector )
1705            break;
1706            
1707        /* Dispatch interrupt vector */
1708        if ( UscVector )
1709            (*UscIsrTable[UscVector])(info);
1710        else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1711            mgsl_isr_transmit_dma(info);
1712        else
1713            mgsl_isr_receive_dma(info);
1714
1715        if ( info->isr_overflow ) {
1716            printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1717                __FILE__, __LINE__, info->device_name, info->irq_level);
1718            usc_DisableMasterIrqBit(info);
1719            usc_DisableDmaInterrupts(info,DICR_MASTER);
1720            break;
1721        }
1722    }
1723    
1724    /* Request bottom half processing if there's something
1725     * for it to do and the bh is not already running
1726     */
1727
1728    if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1729        if ( debug_level >= DEBUG_LEVEL_ISR )
1730            printk("%s(%d):%s queueing bh task.\n",
1731                __FILE__,__LINE__,info->device_name);
1732        schedule_work(&info->task);
1733        info->bh_requested = true;
1734    }
1735
1736    spin_unlock(&info->irq_spinlock);
1737    
1738    if ( debug_level >= DEBUG_LEVEL_ISR )
1739        printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1740            __FILE__, __LINE__, info->irq_level);
1741
1742    return IRQ_HANDLED;
1743} /* end of mgsl_interrupt() */
1744
1745/* startup()
1746 *
1747 * Initialize and start device.
1748 *
1749 * Arguments: info pointer to device instance data
1750 * Return Value: 0 if success, otherwise error code
1751 */
1752static int startup(struct mgsl_struct * info)
1753{
1754    int retval = 0;
1755    
1756    if ( debug_level >= DEBUG_LEVEL_INFO )
1757        printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1758        
1759    if (info->port.flags & ASYNC_INITIALIZED)
1760        return 0;
1761    
1762    if (!info->xmit_buf) {
1763        /* allocate a page of memory for a transmit buffer */
1764        info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1765        if (!info->xmit_buf) {
1766            printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1767                __FILE__,__LINE__,info->device_name);
1768            return -ENOMEM;
1769        }
1770    }
1771
1772    info->pending_bh = 0;
1773    
1774    memset(&info->icount, 0, sizeof(info->icount));
1775
1776    setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1777    
1778    /* Allocate and claim adapter resources */
1779    retval = mgsl_claim_resources(info);
1780    
1781    /* perform existence check and diagnostics */
1782    if ( !retval )
1783        retval = mgsl_adapter_test(info);
1784        
1785    if ( retval ) {
1786          if (capable(CAP_SYS_ADMIN) && info->port.tty)
1787            set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1788        mgsl_release_resources(info);
1789          return retval;
1790      }
1791
1792    /* program hardware for current parameters */
1793    mgsl_change_params(info);
1794    
1795    if (info->port.tty)
1796        clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1797
1798    info->port.flags |= ASYNC_INITIALIZED;
1799    
1800    return 0;
1801    
1802} /* end of startup() */
1803
1804/* shutdown()
1805 *
1806 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1807 *
1808 * Arguments: info pointer to device instance data
1809 * Return Value: None
1810 */
1811static void shutdown(struct mgsl_struct * info)
1812{
1813    unsigned long flags;
1814    
1815    if (!(info->port.flags & ASYNC_INITIALIZED))
1816        return;
1817
1818    if (debug_level >= DEBUG_LEVEL_INFO)
1819        printk("%s(%d):mgsl_shutdown(%s)\n",
1820             __FILE__,__LINE__, info->device_name );
1821
1822    /* clear status wait queue because status changes */
1823    /* can't happen after shutting down the hardware */
1824    wake_up_interruptible(&info->status_event_wait_q);
1825    wake_up_interruptible(&info->event_wait_q);
1826
1827    del_timer_sync(&info->tx_timer);
1828
1829    if (info->xmit_buf) {
1830        free_page((unsigned long) info->xmit_buf);
1831        info->xmit_buf = NULL;
1832    }
1833
1834    spin_lock_irqsave(&info->irq_spinlock,flags);
1835    usc_DisableMasterIrqBit(info);
1836    usc_stop_receiver(info);
1837    usc_stop_transmitter(info);
1838    usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1839        TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1840    usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1841
1842    /* Disable DMAEN (Port 7, Bit 14) */
1843    /* This disconnects the DMA request signal from the ISA bus */
1844    /* on the ISA adapter. This has no effect for the PCI adapter */
1845    usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1846
1847    /* Disable INTEN (Port 6, Bit12) */
1848    /* This disconnects the IRQ request signal to the ISA bus */
1849    /* on the ISA adapter. This has no effect for the PCI adapter */
1850    usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1851
1852    if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
1853        info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1854        usc_set_serial_signals(info);
1855    }
1856
1857    spin_unlock_irqrestore(&info->irq_spinlock,flags);
1858
1859    mgsl_release_resources(info);
1860    
1861    if (info->port.tty)
1862        set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1863
1864    info->port.flags &= ~ASYNC_INITIALIZED;
1865    
1866} /* end of shutdown() */
1867
1868static void mgsl_program_hw(struct mgsl_struct *info)
1869{
1870    unsigned long flags;
1871
1872    spin_lock_irqsave(&info->irq_spinlock,flags);
1873    
1874    usc_stop_receiver(info);
1875    usc_stop_transmitter(info);
1876    info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1877    
1878    if (info->params.mode == MGSL_MODE_HDLC ||
1879        info->params.mode == MGSL_MODE_RAW ||
1880        info->netcount)
1881        usc_set_sync_mode(info);
1882    else
1883        usc_set_async_mode(info);
1884        
1885    usc_set_serial_signals(info);
1886    
1887    info->dcd_chkcount = 0;
1888    info->cts_chkcount = 0;
1889    info->ri_chkcount = 0;
1890    info->dsr_chkcount = 0;
1891
1892    usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1893    usc_EnableInterrupts(info, IO_PIN);
1894    usc_get_serial_signals(info);
1895        
1896    if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
1897        usc_start_receiver(info);
1898        
1899    spin_unlock_irqrestore(&info->irq_spinlock,flags);
1900}
1901
1902/* Reconfigure adapter based on new parameters
1903 */
1904static void mgsl_change_params(struct mgsl_struct *info)
1905{
1906    unsigned cflag;
1907    int bits_per_char;
1908
1909    if (!info->port.tty)
1910        return;
1911        
1912    if (debug_level >= DEBUG_LEVEL_INFO)
1913        printk("%s(%d):mgsl_change_params(%s)\n",
1914             __FILE__,__LINE__, info->device_name );
1915             
1916    cflag = info->port.tty->termios.c_cflag;
1917
1918    /* if B0 rate (hangup) specified then negate RTS and DTR */
1919    /* otherwise assert RTS and DTR */
1920     if (cflag & CBAUD)
1921        info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1922    else
1923        info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1924    
1925    /* byte size and parity */
1926    
1927    switch (cflag & CSIZE) {
1928          case CS5: info->params.data_bits = 5; break;
1929          case CS6: info->params.data_bits = 6; break;
1930          case CS7: info->params.data_bits = 7; break;
1931          case CS8: info->params.data_bits = 8; break;
1932          /* Never happens, but GCC is too dumb to figure it out */
1933          default: info->params.data_bits = 7; break;
1934          }
1935          
1936    if (cflag & CSTOPB)
1937        info->params.stop_bits = 2;
1938    else
1939        info->params.stop_bits = 1;
1940
1941    info->params.parity = ASYNC_PARITY_NONE;
1942    if (cflag & PARENB) {
1943        if (cflag & PARODD)
1944            info->params.parity = ASYNC_PARITY_ODD;
1945        else
1946            info->params.parity = ASYNC_PARITY_EVEN;
1947#ifdef CMSPAR
1948        if (cflag & CMSPAR)
1949            info->params.parity = ASYNC_PARITY_SPACE;
1950#endif
1951    }
1952
1953    /* calculate number of jiffies to transmit a full
1954     * FIFO (32 bytes) at specified data rate
1955     */
1956    bits_per_char = info->params.data_bits +
1957            info->params.stop_bits + 1;
1958
1959    /* if port data rate is set to 460800 or less then
1960     * allow tty settings to override, otherwise keep the
1961     * current data rate.
1962     */
1963    if (info->params.data_rate <= 460800)
1964        info->params.data_rate = tty_get_baud_rate(info->port.tty);
1965    
1966    if ( info->params.data_rate ) {
1967        info->timeout = (32*HZ*bits_per_char) /
1968                info->params.data_rate;
1969    }
1970    info->timeout += HZ/50; /* Add .02 seconds of slop */
1971
1972    if (cflag & CRTSCTS)
1973        info->port.flags |= ASYNC_CTS_FLOW;
1974    else
1975        info->port.flags &= ~ASYNC_CTS_FLOW;
1976        
1977    if (cflag & CLOCAL)
1978        info->port.flags &= ~ASYNC_CHECK_CD;
1979    else
1980        info->port.flags |= ASYNC_CHECK_CD;
1981
1982    /* process tty input control flags */
1983    
1984    info->read_status_mask = RXSTATUS_OVERRUN;
1985    if (I_INPCK(info->port.tty))
1986        info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1987     if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1988         info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1989    
1990    if (I_IGNPAR(info->port.tty))
1991        info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1992    if (I_IGNBRK(info->port.tty)) {
1993        info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1994        /* If ignoring parity and break indicators, ignore
1995         * overruns too. (For real raw support).
1996         */
1997        if (I_IGNPAR(info->port.tty))
1998            info->ignore_status_mask |= RXSTATUS_OVERRUN;
1999    }
2000
2001    mgsl_program_hw(info);
2002
2003} /* end of mgsl_change_params() */
2004
2005/* mgsl_put_char()
2006 *
2007 * Add a character to the transmit buffer.
2008 *
2009 * Arguments: tty pointer to tty information structure
2010 * ch character to add to transmit buffer
2011 *
2012 * Return Value: None
2013 */
2014static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2015{
2016    struct mgsl_struct *info = tty->driver_data;
2017    unsigned long flags;
2018    int ret = 0;
2019
2020    if (debug_level >= DEBUG_LEVEL_INFO) {
2021        printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2022            __FILE__, __LINE__, ch, info->device_name);
2023    }
2024    
2025    if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2026        return 0;
2027
2028    if (!info->xmit_buf)
2029        return 0;
2030
2031    spin_lock_irqsave(&info->irq_spinlock, flags);
2032    
2033    if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2034        if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2035            info->xmit_buf[info->xmit_head++] = ch;
2036            info->xmit_head &= SERIAL_XMIT_SIZE-1;
2037            info->xmit_cnt++;
2038            ret = 1;
2039        }
2040    }
2041    spin_unlock_irqrestore(&info->irq_spinlock, flags);
2042    return ret;
2043    
2044} /* end of mgsl_put_char() */
2045
2046/* mgsl_flush_chars()
2047 *
2048 * Enable transmitter so remaining characters in the
2049 * transmit buffer are sent.
2050 *
2051 * Arguments: tty pointer to tty information structure
2052 * Return Value: None
2053 */
2054static void mgsl_flush_chars(struct tty_struct *tty)
2055{
2056    struct mgsl_struct *info = tty->driver_data;
2057    unsigned long flags;
2058                
2059    if ( debug_level >= DEBUG_LEVEL_INFO )
2060        printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2061            __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2062    
2063    if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2064        return;
2065
2066    if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2067        !info->xmit_buf)
2068        return;
2069
2070    if ( debug_level >= DEBUG_LEVEL_INFO )
2071        printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2072            __FILE__,__LINE__,info->device_name );
2073
2074    spin_lock_irqsave(&info->irq_spinlock,flags);
2075    
2076    if (!info->tx_active) {
2077        if ( (info->params.mode == MGSL_MODE_HDLC ||
2078            info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2079            /* operating in synchronous (frame oriented) mode */
2080            /* copy data from circular xmit_buf to */
2081            /* transmit DMA buffer. */
2082            mgsl_load_tx_dma_buffer(info,
2083                 info->xmit_buf,info->xmit_cnt);
2084        }
2085         usc_start_transmitter(info);
2086    }
2087    
2088    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2089    
2090} /* end of mgsl_flush_chars() */
2091
2092/* mgsl_write()
2093 *
2094 * Send a block of data
2095 *
2096 * Arguments:
2097 *
2098 * tty pointer to tty information structure
2099 * buf pointer to buffer containing send data
2100 * count size of send data in bytes
2101 *
2102 * Return Value: number of characters written
2103 */
2104static int mgsl_write(struct tty_struct * tty,
2105            const unsigned char *buf, int count)
2106{
2107    int c, ret = 0;
2108    struct mgsl_struct *info = tty->driver_data;
2109    unsigned long flags;
2110    
2111    if ( debug_level >= DEBUG_LEVEL_INFO )
2112        printk( "%s(%d):mgsl_write(%s) count=%d\n",
2113            __FILE__,__LINE__,info->device_name,count);
2114    
2115    if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2116        goto cleanup;
2117
2118    if (!info->xmit_buf)
2119        goto cleanup;
2120
2121    if ( info->params.mode == MGSL_MODE_HDLC ||
2122            info->params.mode == MGSL_MODE_RAW ) {
2123        /* operating in synchronous (frame oriented) mode */
2124        if (info->tx_active) {
2125
2126            if ( info->params.mode == MGSL_MODE_HDLC ) {
2127                ret = 0;
2128                goto cleanup;
2129            }
2130            /* transmitter is actively sending data -
2131             * if we have multiple transmit dma and
2132             * holding buffers, attempt to queue this
2133             * frame for transmission at a later time.
2134             */
2135            if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2136                /* no tx holding buffers available */
2137                ret = 0;
2138                goto cleanup;
2139            }
2140
2141            /* queue transmit frame request */
2142            ret = count;
2143            save_tx_buffer_request(info,buf,count);
2144
2145            /* if we have sufficient tx dma buffers,
2146             * load the next buffered tx request
2147             */
2148            spin_lock_irqsave(&info->irq_spinlock,flags);
2149            load_next_tx_holding_buffer(info);
2150            spin_unlock_irqrestore(&info->irq_spinlock,flags);
2151            goto cleanup;
2152        }
2153    
2154        /* if operating in HDLC LoopMode and the adapter */
2155        /* has yet to be inserted into the loop, we can't */
2156        /* transmit */
2157
2158        if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2159            !usc_loopmode_active(info) )
2160        {
2161            ret = 0;
2162            goto cleanup;
2163        }
2164
2165        if ( info->xmit_cnt ) {
2166            /* Send accumulated from send_char() calls */
2167            /* as frame and wait before accepting more data. */
2168            ret = 0;
2169            
2170            /* copy data from circular xmit_buf to */
2171            /* transmit DMA buffer. */
2172            mgsl_load_tx_dma_buffer(info,
2173                info->xmit_buf,info->xmit_cnt);
2174            if ( debug_level >= DEBUG_LEVEL_INFO )
2175                printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2176                    __FILE__,__LINE__,info->device_name);
2177        } else {
2178            if ( debug_level >= DEBUG_LEVEL_INFO )
2179                printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2180                    __FILE__,__LINE__,info->device_name);
2181            ret = count;
2182            info->xmit_cnt = count;
2183            mgsl_load_tx_dma_buffer(info,buf,count);
2184        }
2185    } else {
2186        while (1) {
2187            spin_lock_irqsave(&info->irq_spinlock,flags);
2188            c = min_t(int, count,
2189                min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2190                    SERIAL_XMIT_SIZE - info->xmit_head));
2191            if (c <= 0) {
2192                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2193                break;
2194            }
2195            memcpy(info->xmit_buf + info->xmit_head, buf, c);
2196            info->xmit_head = ((info->xmit_head + c) &
2197                       (SERIAL_XMIT_SIZE-1));
2198            info->xmit_cnt += c;
2199            spin_unlock_irqrestore(&info->irq_spinlock,flags);
2200            buf += c;
2201            count -= c;
2202            ret += c;
2203        }
2204    }
2205    
2206     if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2207        spin_lock_irqsave(&info->irq_spinlock,flags);
2208        if (!info->tx_active)
2209             usc_start_transmitter(info);
2210        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2211     }
2212cleanup:
2213    if ( debug_level >= DEBUG_LEVEL_INFO )
2214        printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2215            __FILE__,__LINE__,info->device_name,ret);
2216            
2217    return ret;
2218    
2219} /* end of mgsl_write() */
2220
2221/* mgsl_write_room()
2222 *
2223 * Return the count of free bytes in transmit buffer
2224 *
2225 * Arguments: tty pointer to tty info structure
2226 * Return Value: None
2227 */
2228static int mgsl_write_room(struct tty_struct *tty)
2229{
2230    struct mgsl_struct *info = tty->driver_data;
2231    int ret;
2232                
2233    if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2234        return 0;
2235    ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2236    if (ret < 0)
2237        ret = 0;
2238        
2239    if (debug_level >= DEBUG_LEVEL_INFO)
2240        printk("%s(%d):mgsl_write_room(%s)=%d\n",
2241             __FILE__,__LINE__, info->device_name,ret );
2242             
2243    if ( info->params.mode == MGSL_MODE_HDLC ||
2244        info->params.mode == MGSL_MODE_RAW ) {
2245        /* operating in synchronous (frame oriented) mode */
2246        if ( info->tx_active )
2247            return 0;
2248        else
2249            return HDLC_MAX_FRAME_SIZE;
2250    }
2251    
2252    return ret;
2253    
2254} /* end of mgsl_write_room() */
2255
2256/* mgsl_chars_in_buffer()
2257 *
2258 * Return the count of bytes in transmit buffer
2259 *
2260 * Arguments: tty pointer to tty info structure
2261 * Return Value: None
2262 */
2263static int mgsl_chars_in_buffer(struct tty_struct *tty)
2264{
2265    struct mgsl_struct *info = tty->driver_data;
2266             
2267    if (debug_level >= DEBUG_LEVEL_INFO)
2268        printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2269             __FILE__,__LINE__, info->device_name );
2270             
2271    if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2272        return 0;
2273        
2274    if (debug_level >= DEBUG_LEVEL_INFO)
2275        printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2276             __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2277             
2278    if ( info->params.mode == MGSL_MODE_HDLC ||
2279        info->params.mode == MGSL_MODE_RAW ) {
2280        /* operating in synchronous (frame oriented) mode */
2281        if ( info->tx_active )
2282            return info->max_frame_size;
2283        else
2284            return 0;
2285    }
2286             
2287    return info->xmit_cnt;
2288} /* end of mgsl_chars_in_buffer() */
2289
2290/* mgsl_flush_buffer()
2291 *
2292 * Discard all data in the send buffer
2293 *
2294 * Arguments: tty pointer to tty info structure
2295 * Return Value: None
2296 */
2297static void mgsl_flush_buffer(struct tty_struct *tty)
2298{
2299    struct mgsl_struct *info = tty->driver_data;
2300    unsigned long flags;
2301    
2302    if (debug_level >= DEBUG_LEVEL_INFO)
2303        printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2304             __FILE__,__LINE__, info->device_name );
2305    
2306    if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2307        return;
2308        
2309    spin_lock_irqsave(&info->irq_spinlock,flags);
2310    info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2311    del_timer(&info->tx_timer);
2312    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2313    
2314    tty_wakeup(tty);
2315}
2316
2317/* mgsl_send_xchar()
2318 *
2319 * Send a high-priority XON/XOFF character
2320 *
2321 * Arguments: tty pointer to tty info structure
2322 * ch character to send
2323 * Return Value: None
2324 */
2325static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2326{
2327    struct mgsl_struct *info = tty->driver_data;
2328    unsigned long flags;
2329
2330    if (debug_level >= DEBUG_LEVEL_INFO)
2331        printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2332             __FILE__,__LINE__, info->device_name, ch );
2333             
2334    if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2335        return;
2336
2337    info->x_char = ch;
2338    if (ch) {
2339        /* Make sure transmit interrupts are on */
2340        spin_lock_irqsave(&info->irq_spinlock,flags);
2341        if (!info->tx_enabled)
2342             usc_start_transmitter(info);
2343        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2344    }
2345} /* end of mgsl_send_xchar() */
2346
2347/* mgsl_throttle()
2348 *
2349 * Signal remote device to throttle send data (our receive data)
2350 *
2351 * Arguments: tty pointer to tty info structure
2352 * Return Value: None
2353 */
2354static void mgsl_throttle(struct tty_struct * tty)
2355{
2356    struct mgsl_struct *info = tty->driver_data;
2357    unsigned long flags;
2358    
2359    if (debug_level >= DEBUG_LEVEL_INFO)
2360        printk("%s(%d):mgsl_throttle(%s) entry\n",
2361             __FILE__,__LINE__, info->device_name );
2362
2363    if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2364        return;
2365    
2366    if (I_IXOFF(tty))
2367        mgsl_send_xchar(tty, STOP_CHAR(tty));
2368
2369    if (tty->termios.c_cflag & CRTSCTS) {
2370        spin_lock_irqsave(&info->irq_spinlock,flags);
2371        info->serial_signals &= ~SerialSignal_RTS;
2372         usc_set_serial_signals(info);
2373        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2374    }
2375} /* end of mgsl_throttle() */
2376
2377/* mgsl_unthrottle()
2378 *
2379 * Signal remote device to stop throttling send data (our receive data)
2380 *
2381 * Arguments: tty pointer to tty info structure
2382 * Return Value: None
2383 */
2384static void mgsl_unthrottle(struct tty_struct * tty)
2385{
2386    struct mgsl_struct *info = tty->driver_data;
2387    unsigned long flags;
2388    
2389    if (debug_level >= DEBUG_LEVEL_INFO)
2390        printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2391             __FILE__,__LINE__, info->device_name );
2392
2393    if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2394        return;
2395    
2396    if (I_IXOFF(tty)) {
2397        if (info->x_char)
2398            info->x_char = 0;
2399        else
2400            mgsl_send_xchar(tty, START_CHAR(tty));
2401    }
2402
2403    if (tty->termios.c_cflag & CRTSCTS) {
2404        spin_lock_irqsave(&info->irq_spinlock,flags);
2405        info->serial_signals |= SerialSignal_RTS;
2406         usc_set_serial_signals(info);
2407        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2408    }
2409    
2410} /* end of mgsl_unthrottle() */
2411
2412/* mgsl_get_stats()
2413 *
2414 * get the current serial parameters information
2415 *
2416 * Arguments: info pointer to device instance data
2417 * user_icount pointer to buffer to hold returned stats
2418 *
2419 * Return Value: 0 if success, otherwise error code
2420 */
2421static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2422{
2423    int err;
2424    
2425    if (debug_level >= DEBUG_LEVEL_INFO)
2426        printk("%s(%d):mgsl_get_params(%s)\n",
2427             __FILE__,__LINE__, info->device_name);
2428            
2429    if (!user_icount) {
2430        memset(&info->icount, 0, sizeof(info->icount));
2431    } else {
2432        mutex_lock(&info->port.mutex);
2433        COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2434        mutex_unlock(&info->port.mutex);
2435        if (err)
2436            return -EFAULT;
2437    }
2438    
2439    return 0;
2440    
2441} /* end of mgsl_get_stats() */
2442
2443/* mgsl_get_params()
2444 *
2445 * get the current serial parameters information
2446 *
2447 * Arguments: info pointer to device instance data
2448 * user_params pointer to buffer to hold returned params
2449 *
2450 * Return Value: 0 if success, otherwise error code
2451 */
2452static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2453{
2454    int err;
2455    if (debug_level >= DEBUG_LEVEL_INFO)
2456        printk("%s(%d):mgsl_get_params(%s)\n",
2457             __FILE__,__LINE__, info->device_name);
2458            
2459    mutex_lock(&info->port.mutex);
2460    COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2461    mutex_unlock(&info->port.mutex);
2462    if (err) {
2463        if ( debug_level >= DEBUG_LEVEL_INFO )
2464            printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2465                __FILE__,__LINE__,info->device_name);
2466        return -EFAULT;
2467    }
2468    
2469    return 0;
2470    
2471} /* end of mgsl_get_params() */
2472
2473/* mgsl_set_params()
2474 *
2475 * set the serial parameters
2476 *
2477 * Arguments:
2478 *
2479 * info pointer to device instance data
2480 * new_params user buffer containing new serial params
2481 *
2482 * Return Value: 0 if success, otherwise error code
2483 */
2484static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2485{
2486     unsigned long flags;
2487    MGSL_PARAMS tmp_params;
2488    int err;
2489 
2490    if (debug_level >= DEBUG_LEVEL_INFO)
2491        printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2492            info->device_name );
2493    COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2494    if (err) {
2495        if ( debug_level >= DEBUG_LEVEL_INFO )
2496            printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2497                __FILE__,__LINE__,info->device_name);
2498        return -EFAULT;
2499    }
2500    
2501    mutex_lock(&info->port.mutex);
2502    spin_lock_irqsave(&info->irq_spinlock,flags);
2503    memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2504    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2505    
2506     mgsl_change_params(info);
2507    mutex_unlock(&info->port.mutex);
2508    
2509    return 0;
2510    
2511} /* end of mgsl_set_params() */
2512
2513/* mgsl_get_txidle()
2514 *
2515 * get the current transmit idle mode
2516 *
2517 * Arguments: info pointer to device instance data
2518 * idle_mode pointer to buffer to hold returned idle mode
2519 *
2520 * Return Value: 0 if success, otherwise error code
2521 */
2522static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2523{
2524    int err;
2525    
2526    if (debug_level >= DEBUG_LEVEL_INFO)
2527        printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2528             __FILE__,__LINE__, info->device_name, info->idle_mode);
2529            
2530    COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2531    if (err) {
2532        if ( debug_level >= DEBUG_LEVEL_INFO )
2533            printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2534                __FILE__,__LINE__,info->device_name);
2535        return -EFAULT;
2536    }
2537    
2538    return 0;
2539    
2540} /* end of mgsl_get_txidle() */
2541
2542/* mgsl_set_txidle() service ioctl to set transmit idle mode
2543 *
2544 * Arguments: info pointer to device instance data
2545 * idle_mode new idle mode
2546 *
2547 * Return Value: 0 if success, otherwise error code
2548 */
2549static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2550{
2551     unsigned long flags;
2552 
2553    if (debug_level >= DEBUG_LEVEL_INFO)
2554        printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2555            info->device_name, idle_mode );
2556            
2557    spin_lock_irqsave(&info->irq_spinlock,flags);
2558    info->idle_mode = idle_mode;
2559    usc_set_txidle( info );
2560    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2561    return 0;
2562    
2563} /* end of mgsl_set_txidle() */
2564
2565/* mgsl_txenable()
2566 *
2567 * enable or disable the transmitter
2568 *
2569 * Arguments:
2570 *
2571 * info pointer to device instance data
2572 * enable 1 = enable, 0 = disable
2573 *
2574 * Return Value: 0 if success, otherwise error code
2575 */
2576static int mgsl_txenable(struct mgsl_struct * info, int enable)
2577{
2578     unsigned long flags;
2579 
2580    if (debug_level >= DEBUG_LEVEL_INFO)
2581        printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2582            info->device_name, enable);
2583            
2584    spin_lock_irqsave(&info->irq_spinlock,flags);
2585    if ( enable ) {
2586        if ( !info->tx_enabled ) {
2587
2588            usc_start_transmitter(info);
2589            /*--------------------------------------------------
2590             * if HDLC/SDLC Loop mode, attempt to insert the
2591             * station in the 'loop' by setting CMR:13. Upon
2592             * receipt of the next GoAhead (RxAbort) sequence,
2593             * the OnLoop indicator (CCSR:7) should go active
2594             * to indicate that we are on the loop
2595             *--------------------------------------------------*/
2596            if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2597                usc_loopmode_insert_request( info );
2598        }
2599    } else {
2600        if ( info->tx_enabled )
2601            usc_stop_transmitter(info);
2602    }
2603    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2604    return 0;
2605    
2606} /* end of mgsl_txenable() */
2607
2608/* mgsl_txabort() abort send HDLC frame
2609 *
2610 * Arguments: info pointer to device instance data
2611 * Return Value: 0 if success, otherwise error code
2612 */
2613static int mgsl_txabort(struct mgsl_struct * info)
2614{
2615     unsigned long flags;
2616 
2617    if (debug_level >= DEBUG_LEVEL_INFO)
2618        printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2619            info->device_name);
2620            
2621    spin_lock_irqsave(&info->irq_spinlock,flags);
2622    if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2623    {
2624        if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2625            usc_loopmode_cancel_transmit( info );
2626        else
2627            usc_TCmd(info,TCmd_SendAbort);
2628    }
2629    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2630    return 0;
2631    
2632} /* end of mgsl_txabort() */
2633
2634/* mgsl_rxenable() enable or disable the receiver
2635 *
2636 * Arguments: info pointer to device instance data
2637 * enable 1 = enable, 0 = disable
2638 * Return Value: 0 if success, otherwise error code
2639 */
2640static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2641{
2642     unsigned long flags;
2643 
2644    if (debug_level >= DEBUG_LEVEL_INFO)
2645        printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2646            info->device_name, enable);
2647            
2648    spin_lock_irqsave(&info->irq_spinlock,flags);
2649    if ( enable ) {
2650        if ( !info->rx_enabled )
2651            usc_start_receiver(info);
2652    } else {
2653        if ( info->rx_enabled )
2654            usc_stop_receiver(info);
2655    }
2656    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2657    return 0;
2658    
2659} /* end of mgsl_rxenable() */
2660
2661/* mgsl_wait_event() wait for specified event to occur
2662 *
2663 * Arguments: info pointer to device instance data
2664 * mask pointer to bitmask of events to wait for
2665 * Return Value: 0 if successful and bit mask updated with
2666 * of events triggerred,
2667 * otherwise error code
2668 */
2669static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2670{
2671     unsigned long flags;
2672    int s;
2673    int rc=0;
2674    struct mgsl_icount cprev, cnow;
2675    int events;
2676    int mask;
2677    struct _input_signal_events oldsigs, newsigs;
2678    DECLARE_WAITQUEUE(wait, current);
2679
2680    COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2681    if (rc) {
2682        return -EFAULT;
2683    }
2684         
2685    if (debug_level >= DEBUG_LEVEL_INFO)
2686        printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2687            info->device_name, mask);
2688
2689    spin_lock_irqsave(&info->irq_spinlock,flags);
2690
2691    /* return immediately if state matches requested events */
2692    usc_get_serial_signals(info);
2693    s = info->serial_signals;
2694    events = mask &
2695        ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2696           ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2697          ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2698          ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2699    if (events) {
2700        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2701        goto exit;
2702    }
2703
2704    /* save current irq counts */
2705    cprev = info->icount;
2706    oldsigs = info->input_signal_events;
2707    
2708    /* enable hunt and idle irqs if needed */
2709    if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2710        u16 oldreg = usc_InReg(info,RICR);
2711        u16 newreg = oldreg +
2712             (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2713             (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2714        if (oldreg != newreg)
2715            usc_OutReg(info, RICR, newreg);
2716    }
2717    
2718    set_current_state(TASK_INTERRUPTIBLE);
2719    add_wait_queue(&info->event_wait_q, &wait);
2720    
2721    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2722    
2723
2724    for(;;) {
2725        schedule();
2726        if (signal_pending(current)) {
2727            rc = -ERESTARTSYS;
2728            break;
2729        }
2730            
2731        /* get current irq counts */
2732        spin_lock_irqsave(&info->irq_spinlock,flags);
2733        cnow = info->icount;
2734        newsigs = info->input_signal_events;
2735        set_current_state(TASK_INTERRUPTIBLE);
2736        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2737
2738        /* if no change, wait aborted for some reason */
2739        if (newsigs.dsr_up == oldsigs.dsr_up &&
2740            newsigs.dsr_down == oldsigs.dsr_down &&
2741            newsigs.dcd_up == oldsigs.dcd_up &&
2742            newsigs.dcd_down == oldsigs.dcd_down &&
2743            newsigs.cts_up == oldsigs.cts_up &&
2744            newsigs.cts_down == oldsigs.cts_down &&
2745            newsigs.ri_up == oldsigs.ri_up &&
2746            newsigs.ri_down == oldsigs.ri_down &&
2747            cnow.exithunt == cprev.exithunt &&
2748            cnow.rxidle == cprev.rxidle) {
2749            rc = -EIO;
2750            break;
2751        }
2752
2753        events = mask &
2754            ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2755            (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2756            (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2757            (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2758            (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2759            (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2760            (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2761            (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2762            (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2763              (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2764        if (events)
2765            break;
2766        
2767        cprev = cnow;
2768        oldsigs = newsigs;
2769    }
2770    
2771    remove_wait_queue(&info->event_wait_q, &wait);
2772    set_current_state(TASK_RUNNING);
2773
2774    if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2775        spin_lock_irqsave(&info->irq_spinlock,flags);
2776        if (!waitqueue_active(&info->event_wait_q)) {
2777            /* disable enable exit hunt mode/idle rcvd IRQs */
2778            usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2779                ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2780        }
2781        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2782    }
2783exit:
2784    if ( rc == 0 )
2785        PUT_USER(rc, events, mask_ptr);
2786        
2787    return rc;
2788    
2789} /* end of mgsl_wait_event() */
2790
2791static int modem_input_wait(struct mgsl_struct *info,int arg)
2792{
2793     unsigned long flags;
2794    int rc;
2795    struct mgsl_icount cprev, cnow;
2796    DECLARE_WAITQUEUE(wait, current);
2797
2798    /* save current irq counts */
2799    spin_lock_irqsave(&info->irq_spinlock,flags);
2800    cprev = info->icount;
2801    add_wait_queue(&info->status_event_wait_q, &wait);
2802    set_current_state(TASK_INTERRUPTIBLE);
2803    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2804
2805    for(;;) {
2806        schedule();
2807        if (signal_pending(current)) {
2808            rc = -ERESTARTSYS;
2809            break;
2810        }
2811
2812        /* get new irq counts */
2813        spin_lock_irqsave(&info->irq_spinlock,flags);
2814        cnow = info->icount;
2815        set_current_state(TASK_INTERRUPTIBLE);
2816        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2817
2818        /* if no change, wait aborted for some reason */
2819        if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2820            cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2821            rc = -EIO;
2822            break;
2823        }
2824
2825        /* check for change in caller specified modem input */
2826        if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2827            (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2828            (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2829            (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2830            rc = 0;
2831            break;
2832        }
2833
2834        cprev = cnow;
2835    }
2836    remove_wait_queue(&info->status_event_wait_q, &wait);
2837    set_current_state(TASK_RUNNING);
2838    return rc;
2839}
2840
2841/* return the state of the serial control and status signals
2842 */
2843static int tiocmget(struct tty_struct *tty)
2844{
2845    struct mgsl_struct *info = tty->driver_data;
2846    unsigned int result;
2847     unsigned long flags;
2848
2849    spin_lock_irqsave(&info->irq_spinlock,flags);
2850     usc_get_serial_signals(info);
2851    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2852
2853    result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2854        ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2855        ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2856        ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2857        ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2858        ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2859
2860    if (debug_level >= DEBUG_LEVEL_INFO)
2861        printk("%s(%d):%s tiocmget() value=%08X\n",
2862             __FILE__,__LINE__, info->device_name, result );
2863    return result;
2864}
2865
2866/* set modem control signals (DTR/RTS)
2867 */
2868static int tiocmset(struct tty_struct *tty,
2869                    unsigned int set, unsigned int clear)
2870{
2871    struct mgsl_struct *info = tty->driver_data;
2872     unsigned long flags;
2873
2874    if (debug_level >= DEBUG_LEVEL_INFO)
2875        printk("%s(%d):%s tiocmset(%x,%x)\n",
2876            __FILE__,__LINE__,info->device_name, set, clear);
2877
2878    if (set & TIOCM_RTS)
2879        info->serial_signals |= SerialSignal_RTS;
2880    if (set & TIOCM_DTR)
2881        info->serial_signals |= SerialSignal_DTR;
2882    if (clear & TIOCM_RTS)
2883        info->serial_signals &= ~SerialSignal_RTS;
2884    if (clear & TIOCM_DTR)
2885        info->serial_signals &= ~SerialSignal_DTR;
2886
2887    spin_lock_irqsave(&info->irq_spinlock,flags);
2888     usc_set_serial_signals(info);
2889    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2890
2891    return 0;
2892}
2893
2894/* mgsl_break() Set or clear transmit break condition
2895 *
2896 * Arguments: tty pointer to tty instance data
2897 * break_state -1=set break condition, 0=clear
2898 * Return Value: error code
2899 */
2900static int mgsl_break(struct tty_struct *tty, int break_state)
2901{
2902    struct mgsl_struct * info = tty->driver_data;
2903    unsigned long flags;
2904    
2905    if (debug_level >= DEBUG_LEVEL_INFO)
2906        printk("%s(%d):mgsl_break(%s,%d)\n",
2907             __FILE__,__LINE__, info->device_name, break_state);
2908             
2909    if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2910        return -EINVAL;
2911
2912    spin_lock_irqsave(&info->irq_spinlock,flags);
2913     if (break_state == -1)
2914        usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2915    else
2916        usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2917    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2918    return 0;
2919    
2920} /* end of mgsl_break() */
2921
2922/*
2923 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2924 * Return: write counters to the user passed counter struct
2925 * NB: both 1->0 and 0->1 transitions are counted except for
2926 * RI where only 0->1 is counted.
2927 */
2928static int msgl_get_icount(struct tty_struct *tty,
2929                struct serial_icounter_struct *icount)
2930
2931{
2932    struct mgsl_struct * info = tty->driver_data;
2933    struct mgsl_icount cnow; /* kernel counter temps */
2934    unsigned long flags;
2935
2936    spin_lock_irqsave(&info->irq_spinlock,flags);
2937    cnow = info->icount;
2938    spin_unlock_irqrestore(&info->irq_spinlock,flags);
2939
2940    icount->cts = cnow.cts;
2941    icount->dsr = cnow.dsr;
2942    icount->rng = cnow.rng;
2943    icount->dcd = cnow.dcd;
2944    icount->rx = cnow.rx;
2945    icount->tx = cnow.tx;
2946    icount->frame = cnow.frame;
2947    icount->overrun = cnow.overrun;
2948    icount->parity = cnow.parity;
2949    icount->brk = cnow.brk;
2950    icount->buf_overrun = cnow.buf_overrun;
2951    return 0;
2952}
2953
2954/* mgsl_ioctl() Service an IOCTL request
2955 *
2956 * Arguments:
2957 *
2958 * tty pointer to tty instance data
2959 * cmd IOCTL command code
2960 * arg command argument/context
2961 *
2962 * Return Value: 0 if success, otherwise error code
2963 */
2964static int mgsl_ioctl(struct tty_struct *tty,
2965            unsigned int cmd, unsigned long arg)
2966{
2967    struct mgsl_struct * info = tty->driver_data;
2968    
2969    if (debug_level >= DEBUG_LEVEL_INFO)
2970        printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2971            info->device_name, cmd );
2972    
2973    if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2974        return -ENODEV;
2975
2976    if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2977        (cmd != TIOCMIWAIT)) {
2978        if (tty->flags & (1 << TTY_IO_ERROR))
2979            return -EIO;
2980    }
2981
2982    return mgsl_ioctl_common(info, cmd, arg);
2983}
2984
2985static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2986{
2987    void __user *argp = (void __user *)arg;
2988    
2989    switch (cmd) {
2990        case MGSL_IOCGPARAMS:
2991            return mgsl_get_params(info, argp);
2992        case MGSL_IOCSPARAMS:
2993            return mgsl_set_params(info, argp);
2994        case MGSL_IOCGTXIDLE:
2995            return mgsl_get_txidle(info, argp);
2996        case MGSL_IOCSTXIDLE:
2997            return mgsl_set_txidle(info,(int)arg);
2998        case MGSL_IOCTXENABLE:
2999            return mgsl_txenable(info,(int)arg);
3000        case MGSL_IOCRXENABLE:
3001            return mgsl_rxenable(info,(int)arg);
3002        case MGSL_IOCTXABORT:
3003            return mgsl_txabort(info);
3004        case MGSL_IOCGSTATS:
3005            return mgsl_get_stats(info, argp);
3006        case MGSL_IOCWAITEVENT:
3007            return mgsl_wait_event(info, argp);
3008        case MGSL_IOCLOOPTXDONE:
3009            return mgsl_loopmode_send_done(info);
3010        /* Wait for modem input (DCD,RI,DSR,CTS) change
3011         * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3012         */
3013        case TIOCMIWAIT:
3014            return modem_input_wait(info,(int)arg);
3015
3016        default:
3017            return -ENOIOCTLCMD;
3018    }
3019    return 0;
3020}
3021
3022/* mgsl_set_termios()
3023 *
3024 * Set new termios settings
3025 *
3026 * Arguments:
3027 *
3028 * tty pointer to tty structure
3029 * termios pointer to buffer to hold returned old termios
3030 *
3031 * Return Value: None
3032 */
3033static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3034{
3035    struct mgsl_struct *info = tty->driver_data;
3036    unsigned long flags;
3037    
3038    if (debug_level >= DEBUG_LEVEL_INFO)
3039        printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3040            tty->driver->name );
3041    
3042    mgsl_change_params(info);
3043
3044    /* Handle transition to B0 status */
3045    if (old_termios->c_cflag & CBAUD &&
3046        !(tty->termios.c_cflag & CBAUD)) {
3047        info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3048        spin_lock_irqsave(&info->irq_spinlock,flags);
3049         usc_set_serial_signals(info);
3050        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3051    }
3052    
3053    /* Handle transition away from B0 status */
3054    if (!(old_termios->c_cflag & CBAUD) &&
3055        tty->termios.c_cflag & CBAUD) {
3056        info->serial_signals |= SerialSignal_DTR;
3057         if (!(tty->termios.c_cflag & CRTSCTS) ||
3058             !test_bit(TTY_THROTTLED, &tty->flags)) {
3059            info->serial_signals |= SerialSignal_RTS;
3060         }
3061        spin_lock_irqsave(&info->irq_spinlock,flags);
3062         usc_set_serial_signals(info);
3063        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3064    }
3065    
3066    /* Handle turning off CRTSCTS */
3067    if (old_termios->c_cflag & CRTSCTS &&
3068        !(tty->termios.c_cflag & CRTSCTS)) {
3069        tty->hw_stopped = 0;
3070        mgsl_start(tty);
3071    }
3072
3073} /* end of mgsl_set_termios() */
3074
3075/* mgsl_close()
3076 *
3077 * Called when port is closed. Wait for remaining data to be
3078 * sent. Disable port and free resources.
3079 *
3080 * Arguments:
3081 *
3082 * tty pointer to open tty structure
3083 * filp pointer to open file object
3084 *
3085 * Return Value: None
3086 */
3087static void mgsl_close(struct tty_struct *tty, struct file * filp)
3088{
3089    struct mgsl_struct * info = tty->driver_data;
3090
3091    if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3092        return;
3093    
3094    if (debug_level >= DEBUG_LEVEL_INFO)
3095        printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3096             __FILE__,__LINE__, info->device_name, info->port.count);
3097
3098    if (tty_port_close_start(&info->port, tty, filp) == 0)
3099        goto cleanup;
3100
3101    mutex_lock(&info->port.mutex);
3102     if (info->port.flags & ASYNC_INITIALIZED)
3103         mgsl_wait_until_sent(tty, info->timeout);
3104    mgsl_flush_buffer(tty);
3105    tty_ldisc_flush(tty);
3106    shutdown(info);
3107    mutex_unlock(&info->port.mutex);
3108
3109    tty_port_close_end(&info->port, tty);
3110    info->port.tty = NULL;
3111cleanup:
3112    if (debug_level >= DEBUG_LEVEL_INFO)
3113        printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3114            tty->driver->name, info->port.count);
3115            
3116} /* end of mgsl_close() */
3117
3118/* mgsl_wait_until_sent()
3119 *
3120 * Wait until the transmitter is empty.
3121 *
3122 * Arguments:
3123 *
3124 * tty pointer to tty info structure
3125 * timeout time to wait for send completion
3126 *
3127 * Return Value: None
3128 */
3129static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3130{
3131    struct mgsl_struct * info = tty->driver_data;
3132    unsigned long orig_jiffies, char_time;
3133
3134    if (!info )
3135        return;
3136
3137    if (debug_level >= DEBUG_LEVEL_INFO)
3138        printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3139             __FILE__,__LINE__, info->device_name );
3140      
3141    if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3142        return;
3143
3144    if (!(info->port.flags & ASYNC_INITIALIZED))
3145        goto exit;
3146     
3147    orig_jiffies = jiffies;
3148      
3149    /* Set check interval to 1/5 of estimated time to
3150     * send a character, and make it at least 1. The check
3151     * interval should also be less than the timeout.
3152     * Note: use tight timings here to satisfy the NIST-PCTS.
3153     */
3154
3155    if ( info->params.data_rate ) {
3156               char_time = info->timeout/(32 * 5);
3157        if (!char_time)
3158            char_time++;
3159    } else
3160        char_time = 1;
3161        
3162    if (timeout)
3163        char_time = min_t(unsigned long, char_time, timeout);
3164        
3165    if ( info->params.mode == MGSL_MODE_HDLC ||
3166        info->params.mode == MGSL_MODE_RAW ) {
3167        while (info->tx_active) {
3168            msleep_interruptible(jiffies_to_msecs(char_time));
3169            if (signal_pending(current))
3170                break;
3171            if (timeout && time_after(jiffies, orig_jiffies + timeout))
3172                break;
3173        }
3174    } else {
3175        while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3176            info->tx_enabled) {
3177            msleep_interruptible(jiffies_to_msecs(char_time));
3178            if (signal_pending(current))
3179                break;
3180            if (timeout && time_after(jiffies, orig_jiffies + timeout))
3181                break;
3182        }
3183    }
3184      
3185exit:
3186    if (debug_level >= DEBUG_LEVEL_INFO)
3187        printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3188             __FILE__,__LINE__, info->device_name );
3189             
3190} /* end of mgsl_wait_until_sent() */
3191
3192/* mgsl_hangup()
3193 *
3194 * Called by tty_hangup() when a hangup is signaled.
3195 * This is the same as to closing all open files for the port.
3196 *
3197 * Arguments: tty pointer to associated tty object
3198 * Return Value: None
3199 */
3200static void mgsl_hangup(struct tty_struct *tty)
3201{
3202    struct mgsl_struct * info = tty->driver_data;
3203    
3204    if (debug_level >= DEBUG_LEVEL_INFO)
3205        printk("%s(%d):mgsl_hangup(%s)\n",
3206             __FILE__,__LINE__, info->device_name );
3207             
3208    if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3209        return;
3210
3211    mgsl_flush_buffer(tty);
3212    shutdown(info);
3213    
3214    info->port.count = 0;
3215    info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3216    info->port.tty = NULL;
3217
3218    wake_up_interruptible(&info->port.open_wait);
3219    
3220} /* end of mgsl_hangup() */
3221
3222/*
3223 * carrier_raised()
3224 *
3225 * Return true if carrier is raised
3226 */
3227
3228static int carrier_raised(struct tty_port *port)
3229{
3230    unsigned long flags;
3231    struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3232    
3233    spin_lock_irqsave(&info->irq_spinlock, flags);
3234     usc_get_serial_signals(info);
3235    spin_unlock_irqrestore(&info->irq_spinlock, flags);
3236    return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3237}
3238
3239static void dtr_rts(struct tty_port *port, int on)
3240{
3241    struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3242    unsigned long flags;
3243
3244    spin_lock_irqsave(&info->irq_spinlock,flags);
3245    if (on)
3246        info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3247    else
3248        info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3249     usc_set_serial_signals(info);
3250    spin_unlock_irqrestore(&info->irq_spinlock,flags);
3251}
3252
3253
3254/* block_til_ready()
3255 *
3256 * Block the current process until the specified port
3257 * is ready to be opened.
3258 *
3259 * Arguments:
3260 *
3261 * tty pointer to tty info structure
3262 * filp pointer to open file object
3263 * info pointer to device instance data
3264 *
3265 * Return Value: 0 if success, otherwise error code
3266 */
3267static int block_til_ready(struct tty_struct *tty, struct file * filp,
3268               struct mgsl_struct *info)
3269{
3270    DECLARE_WAITQUEUE(wait, current);
3271    int retval;
3272    bool do_clocal = false;
3273    bool extra_count = false;
3274    unsigned long flags;
3275    int dcd;
3276    struct tty_port *port = &info->port;
3277    
3278    if (debug_level >= DEBUG_LEVEL_INFO)
3279        printk("%s(%d):block_til_ready on %s\n",
3280             __FILE__,__LINE__, tty->driver->name );
3281
3282    if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3283        /* nonblock mode is set or port is not enabled */
3284        port->flags |= ASYNC_NORMAL_ACTIVE;
3285        return 0;
3286    }
3287
3288    if (tty->termios.c_cflag & CLOCAL)
3289        do_clocal = true;
3290
3291    /* Wait for carrier detect and the line to become
3292     * free (i.e., not in use by the callout). While we are in
3293     * this loop, port->count is dropped by one, so that
3294     * mgsl_close() knows when to free things. We restore it upon
3295     * exit, either normal or abnormal.
3296     */
3297     
3298    retval = 0;
3299    add_wait_queue(&port->open_wait, &wait);
3300    
3301    if (debug_level >= DEBUG_LEVEL_INFO)
3302        printk("%s(%d):block_til_ready before block on %s count=%d\n",
3303             __FILE__,__LINE__, tty->driver->name, port->count );
3304
3305    spin_lock_irqsave(&info->irq_spinlock, flags);
3306    if (!tty_hung_up_p(filp)) {
3307        extra_count = true;
3308        port->count--;
3309    }
3310    spin_unlock_irqrestore(&info->irq_spinlock, flags);
3311    port->blocked_open++;
3312    
3313    while (1) {
3314        if (tty->termios.c_cflag & CBAUD)
3315            tty_port_raise_dtr_rts(port);
3316        
3317        set_current_state(TASK_INTERRUPTIBLE);
3318        
3319        if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3320            retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3321                    -EAGAIN : -ERESTARTSYS;
3322            break;
3323        }
3324        
3325        dcd = tty_port_carrier_raised(&info->port);
3326        
3327         if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3328             break;
3329            
3330        if (signal_pending(current)) {
3331            retval = -ERESTARTSYS;
3332            break;
3333        }
3334        
3335        if (debug_level >= DEBUG_LEVEL_INFO)
3336            printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3337                 __FILE__,__LINE__, tty->driver->name, port->count );
3338                 
3339        tty_unlock(tty);
3340        schedule();
3341        tty_lock(tty);
3342    }
3343    
3344    set_current_state(TASK_RUNNING);
3345    remove_wait_queue(&port->open_wait, &wait);
3346    
3347    /* FIXME: Racy on hangup during close wait */
3348    if (extra_count)
3349        port->count++;
3350    port->blocked_open--;
3351    
3352    if (debug_level >= DEBUG_LEVEL_INFO)
3353        printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3354             __FILE__,__LINE__, tty->driver->name, port->count );
3355             
3356    if (!retval)
3357        port->flags |= ASYNC_NORMAL_ACTIVE;
3358        
3359    return retval;
3360    
3361} /* end of block_til_ready() */
3362
3363static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
3364{
3365    struct mgsl_struct *info;
3366    int line = tty->index;
3367
3368    /* verify range of specified line number */
3369    if (line >= mgsl_device_count) {
3370        printk("%s(%d):mgsl_open with invalid line #%d.\n",
3371            __FILE__, __LINE__, line);
3372        return -ENODEV;
3373    }
3374
3375    /* find the info structure for the specified line */
3376    info = mgsl_device_list;
3377    while (info && info->line != line)
3378        info = info->next_device;
3379    if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3380        return -ENODEV;
3381    tty->driver_data = info;
3382
3383    return tty_port_install(&info->port, driver, tty);
3384}
3385
3386/* mgsl_open()
3387 *
3388 * Called when a port is opened. Init and enable port.
3389 * Perform serial-specific initialization for the tty structure.
3390 *
3391 * Arguments: tty pointer to tty info structure
3392 * filp associated file pointer
3393 *
3394 * Return Value: 0 if success, otherwise error code
3395 */
3396static int mgsl_open(struct tty_struct *tty, struct file * filp)
3397{
3398    struct mgsl_struct *info = tty->driver_data;
3399    unsigned long flags;
3400    int retval;
3401
3402    info->port.tty = tty;
3403        
3404    if (debug_level >= DEBUG_LEVEL_INFO)
3405        printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3406             __FILE__,__LINE__,tty->driver->name, info->port.count);
3407
3408    /* If port is closing, signal caller to try again */
3409    if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3410        if (info->port.flags & ASYNC_CLOSING)
3411            interruptible_sleep_on(&info->port.close_wait);
3412        retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3413            -EAGAIN : -ERESTARTSYS);
3414        goto cleanup;
3415    }
3416    
3417    info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3418
3419    spin_lock_irqsave(&info->netlock, flags);
3420    if (info->netcount) {
3421        retval = -EBUSY;
3422        spin_unlock_irqrestore(&info->netlock, flags);
3423        goto cleanup;
3424    }
3425    info->port.count++;
3426    spin_unlock_irqrestore(&info->netlock, flags);
3427
3428    if (info->port.count == 1) {
3429        /* 1st open on this device, init hardware */
3430        retval = startup(info);
3431        if (retval < 0)
3432            goto cleanup;
3433    }
3434
3435    retval = block_til_ready(tty, filp, info);
3436    if (retval) {
3437        if (debug_level >= DEBUG_LEVEL_INFO)
3438            printk("%s(%d):block_til_ready(%s) returned %d\n",
3439                 __FILE__,__LINE__, info->device_name, retval);
3440        goto cleanup;
3441    }
3442
3443    if (debug_level >= DEBUG_LEVEL_INFO)
3444        printk("%s(%d):mgsl_open(%s) success\n",
3445             __FILE__,__LINE__, info->device_name);
3446    retval = 0;
3447    
3448cleanup:
3449    if (retval) {
3450        if (tty->count == 1)
3451            info->port.tty = NULL; /* tty layer will release tty struct */
3452        if(info->port.count)
3453            info->port.count--;
3454    }
3455    
3456    return retval;
3457    
3458} /* end of mgsl_open() */
3459
3460/*
3461 * /proc fs routines....
3462 */
3463
3464static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3465{
3466    char stat_buf[30];
3467    unsigned long flags;
3468
3469    if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3470        seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3471            info->device_name, info->io_base, info->irq_level,
3472            info->phys_memory_base, info->phys_lcr_base);
3473    } else {
3474        seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3475            info->device_name, info->io_base,
3476            info->irq_level, info->dma_level);
3477    }
3478
3479    /* output current serial signal states */
3480    spin_lock_irqsave(&info->irq_spinlock,flags);
3481     usc_get_serial_signals(info);
3482    spin_unlock_irqrestore(&info->irq_spinlock,flags);
3483    
3484    stat_buf[0] = 0;
3485    stat_buf[1] = 0;
3486    if (info->serial_signals & SerialSignal_RTS)
3487        strcat(stat_buf, "|RTS");
3488    if (info->serial_signals & SerialSignal_CTS)
3489        strcat(stat_buf, "|CTS");
3490    if (info->serial_signals & SerialSignal_DTR)
3491        strcat(stat_buf, "|DTR");
3492    if (info->serial_signals & SerialSignal_DSR)
3493        strcat(stat_buf, "|DSR");
3494    if (info->serial_signals & SerialSignal_DCD)
3495        strcat(stat_buf, "|CD");
3496    if (info->serial_signals & SerialSignal_RI)
3497        strcat(stat_buf, "|RI");
3498
3499    if (info->params.mode == MGSL_MODE_HDLC ||
3500        info->params.mode == MGSL_MODE_RAW ) {
3501        seq_printf(m, " HDLC txok:%d rxok:%d",
3502                  info->icount.txok, info->icount.rxok);
3503        if (info->icount.txunder)
3504            seq_printf(m, " txunder:%d", info->icount.txunder);
3505        if (info->icount.txabort)
3506            seq_printf(m, " txabort:%d", info->icount.txabort);
3507        if (info->icount.rxshort)
3508            seq_printf(m, " rxshort:%d", info->icount.rxshort);
3509        if (info->icount.rxlong)
3510            seq_printf(m, " rxlong:%d", info->icount.rxlong);
3511        if (info->icount.rxover)
3512            seq_printf(m, " rxover:%d", info->icount.rxover);
3513        if (info->icount.rxcrc)
3514            seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3515    } else {
3516        seq_printf(m, " ASYNC tx:%d rx:%d",
3517                  info->icount.tx, info->icount.rx);
3518        if (info->icount.frame)
3519            seq_printf(m, " fe:%d", info->icount.frame);
3520        if (info->icount.parity)
3521            seq_printf(m, " pe:%d", info->icount.parity);
3522        if (info->icount.brk)
3523            seq_printf(m, " brk:%d", info->icount.brk);
3524        if (info->icount.overrun)
3525            seq_printf(m, " oe:%d", info->icount.overrun);
3526    }
3527    
3528    /* Append serial signal status to end */
3529    seq_printf(m, " %s\n", stat_buf+1);
3530    
3531    seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3532     info->tx_active,info->bh_requested,info->bh_running,
3533     info->pending_bh);
3534     
3535    spin_lock_irqsave(&info->irq_spinlock,flags);
3536    {
3537    u16 Tcsr = usc_InReg( info, TCSR );
3538    u16 Tdmr = usc_InDmaReg( info, TDMR );
3539    u16 Ticr = usc_InReg( info, TICR );
3540    u16 Rscr = usc_InReg( info, RCSR );
3541    u16 Rdmr = usc_InDmaReg( info, RDMR );
3542    u16 Ricr = usc_InReg( info, RICR );
3543    u16 Icr = usc_InReg( info, ICR );
3544    u16 Dccr = usc_InReg( info, DCCR );
3545    u16 Tmr = usc_InReg( info, TMR );
3546    u16 Tccr = usc_InReg( info, TCCR );
3547    u16 Ccar = inw( info->io_base + CCAR );
3548    seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3549                        "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3550             Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3551    }
3552    spin_unlock_irqrestore(&info->irq_spinlock,flags);
3553}
3554
3555/* Called to print information about devices */
3556static int mgsl_proc_show(struct seq_file *m, void *v)
3557{
3558    struct mgsl_struct *info;
3559    
3560    seq_printf(m, "synclink driver:%s\n", driver_version);
3561    
3562    info = mgsl_device_list;
3563    while( info ) {
3564        line_info(m, info);
3565        info = info->next_device;
3566    }
3567    return 0;
3568}
3569
3570static int mgsl_proc_open(struct inode *inode, struct file *file)
3571{
3572    return single_open(file, mgsl_proc_show, NULL);
3573}
3574
3575static const struct file_operations mgsl_proc_fops = {
3576    .owner = THIS_MODULE,
3577    .open = mgsl_proc_open,
3578    .read = seq_read,
3579    .llseek = seq_lseek,
3580    .release = single_release,
3581};
3582
3583/* mgsl_allocate_dma_buffers()
3584 *
3585 * Allocate and format DMA buffers (ISA adapter)
3586 * or format shared memory buffers (PCI adapter).
3587 *
3588 * Arguments: info pointer to device instance data
3589 * Return Value: 0 if success, otherwise error
3590 */
3591static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3592{
3593    unsigned short BuffersPerFrame;
3594
3595    info->last_mem_alloc = 0;
3596
3597    /* Calculate the number of DMA buffers necessary to hold the */
3598    /* largest allowable frame size. Note: If the max frame size is */
3599    /* not an even multiple of the DMA buffer size then we need to */
3600    /* round the buffer count per frame up one. */
3601
3602    BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3603    if ( info->max_frame_size % DMABUFFERSIZE )
3604        BuffersPerFrame++;
3605
3606    if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3607        /*
3608         * The PCI adapter has 256KBytes of shared memory to use.
3609         * This is 64 PAGE_SIZE buffers.
3610         *
3611         * The first page is used for padding at this time so the
3612         * buffer list does not begin at offset 0 of the PCI
3613         * adapter's shared memory.
3614         *
3615         * The 2nd page is used for the buffer list. A 4K buffer
3616         * list can hold 128 DMA_BUFFER structures at 32 bytes
3617         * each.
3618         *
3619         * This leaves 62 4K pages.
3620         *
3621         * The next N pages are used for transmit frame(s). We
3622         * reserve enough 4K page blocks to hold the required
3623         * number of transmit dma buffers (num_tx_dma_buffers),
3624         * each of MaxFrameSize size.
3625         *
3626         * Of the remaining pages (62-N), determine how many can
3627         * be used to receive full MaxFrameSize inbound frames
3628         */
3629        info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3630        info->rx_buffer_count = 62 - info->tx_buffer_count;
3631    } else {
3632        /* Calculate the number of PAGE_SIZE buffers needed for */
3633        /* receive and transmit DMA buffers. */
3634
3635
3636        /* Calculate the number of DMA buffers necessary to */
3637        /* hold 7 max size receive frames and one max size transmit frame. */
3638        /* The receive buffer count is bumped by one so we avoid an */
3639        /* End of List condition if all receive buffers are used when */
3640        /* using linked list DMA buffers. */
3641
3642        info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3643        info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3644        
3645        /*
3646         * limit total TxBuffers & RxBuffers to 62 4K total
3647         * (ala PCI Allocation)
3648         */
3649        
3650        if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3651            info->rx_buffer_count = 62 - info->tx_buffer_count;
3652
3653    }
3654
3655    if ( debug_level >= DEBUG_LEVEL_INFO )
3656        printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3657            __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3658    
3659    if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3660          mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3661          mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3662          mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3663          mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3664        printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3665        return -ENOMEM;
3666    }
3667    
3668    mgsl_reset_rx_dma_buffers( info );
3669      mgsl_reset_tx_dma_buffers( info );
3670
3671    return 0;
3672
3673} /* end of mgsl_allocate_dma_buffers() */
3674
3675/*
3676 * mgsl_alloc_buffer_list_memory()
3677 *
3678 * Allocate a common DMA buffer for use as the
3679 * receive and transmit buffer lists.
3680 *
3681 * A buffer list is a set of buffer entries where each entry contains
3682 * a pointer to an actual buffer and a pointer to the next buffer entry
3683 * (plus some other info about the buffer).
3684 *
3685 * The buffer entries for a list are built to form a circular list so
3686 * that when the entire list has been traversed you start back at the
3687 * beginning.
3688 *
3689 * This function allocates memory for just the buffer entries.
3690 * The links (pointer to next entry) are filled in with the physical
3691 * address of the next entry so the adapter can navigate the list
3692 * using bus master DMA. The pointers to the actual buffers are filled
3693 * out later when the actual buffers are allocated.
3694 *
3695 * Arguments: info pointer to device instance data
3696 * Return Value: 0 if success, otherwise error
3697 */
3698static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3699{
3700    unsigned int i;
3701
3702    if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3703        /* PCI adapter uses shared memory. */
3704        info->buffer_list = info->memory_base + info->last_mem_alloc;
3705        info->buffer_list_phys = info->last_mem_alloc;
3706        info->last_mem_alloc += BUFFERLISTSIZE;
3707    } else {
3708        /* ISA adapter uses system memory. */
3709        /* The buffer lists are allocated as a common buffer that both */
3710        /* the processor and adapter can access. This allows the driver to */
3711        /* inspect portions of the buffer while other portions are being */
3712        /* updated by the adapter using Bus Master DMA. */
3713
3714        info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3715        if (info->buffer_list == NULL)
3716            return -ENOMEM;
3717        info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3718    }
3719
3720    /* We got the memory for the buffer entry lists. */
3721    /* Initialize the memory block to all zeros. */
3722    memset( info->buffer_list, 0, BUFFERLISTSIZE );
3723
3724    /* Save virtual address pointers to the receive and */
3725    /* transmit buffer lists. (Receive 1st). These pointers will */
3726    /* be used by the processor to access the lists. */
3727    info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3728    info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3729    info->tx_buffer_list += info->rx_buffer_count;
3730
3731    /*
3732     * Build the links for the buffer entry lists such that
3733     * two circular lists are built. (Transmit and Receive).
3734     *
3735     * Note: the links are physical addresses
3736     * which are read by the adapter to determine the next
3737     * buffer entry to use.
3738     */
3739
3740    for ( i = 0; i < info->rx_buffer_count; i++ ) {
3741        /* calculate and store physical address of this buffer entry */
3742        info->rx_buffer_list[i].phys_entry =
3743            info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3744
3745        /* calculate and store physical address of */
3746        /* next entry in cirular list of entries */
3747
3748        info->rx_buffer_list[i].link = info->buffer_list_phys;
3749
3750        if ( i < info->rx_buffer_count - 1 )
3751            info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3752    }
3753
3754    for ( i = 0; i < info->tx_buffer_count; i++ ) {
3755        /* calculate and store physical address of this buffer entry */
3756        info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3757            ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3758
3759        /* calculate and store physical address of */
3760        /* next entry in cirular list of entries */
3761
3762        info->tx_buffer_list[i].link = info->buffer_list_phys +
3763            info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3764
3765        if ( i < info->tx_buffer_count - 1 )
3766            info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3767    }
3768
3769    return 0;
3770
3771} /* end of mgsl_alloc_buffer_list_memory() */
3772
3773/* Free DMA buffers allocated for use as the
3774 * receive and transmit buffer lists.
3775 * Warning:
3776 *
3777 * The data transfer buffers associated with the buffer list
3778 * MUST be freed before freeing the buffer list itself because
3779 * the buffer list contains the information necessary to free
3780 * the individual buffers!
3781 */
3782static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3783{
3784    if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3785        dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3786        
3787    info->buffer_list = NULL;
3788    info->rx_buffer_list = NULL;
3789    info->tx_buffer_list = NULL;
3790
3791} /* end of mgsl_free_buffer_list_memory() */
3792
3793/*
3794 * mgsl_alloc_frame_memory()
3795 *
3796 * Allocate the frame DMA buffers used by the specified buffer list.
3797 * Each DMA buffer will be one memory page in size. This is necessary
3798 * because memory can fragment enough that it may be impossible
3799 * contiguous pages.
3800 *
3801 * Arguments:
3802 *
3803 * info pointer to device instance data
3804 * BufferList pointer to list of buffer entries
3805 * Buffercount count of buffer entries in buffer list
3806 *
3807 * Return Value: 0 if success, otherwise -ENOMEM
3808 */
3809static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3810{
3811    int i;
3812    u32 phys_addr;
3813
3814    /* Allocate page sized buffers for the receive buffer list */
3815
3816    for ( i = 0; i < Buffercount; i++ ) {
3817        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3818            /* PCI adapter uses shared memory buffers. */
3819            BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3820            phys_addr = info->last_mem_alloc;
3821            info->last_mem_alloc += DMABUFFERSIZE;
3822        } else {
3823            /* ISA adapter uses system memory. */
3824            BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3825            if (BufferList[i].virt_addr == NULL)
3826                return -ENOMEM;
3827            phys_addr = (u32)(BufferList[i].dma_addr);
3828        }
3829        BufferList[i].phys_addr = phys_addr;
3830    }
3831
3832    return 0;
3833
3834} /* end of mgsl_alloc_frame_memory() */
3835
3836/*
3837 * mgsl_free_frame_memory()
3838 *
3839 * Free the buffers associated with
3840 * each buffer entry of a buffer list.
3841 *
3842 * Arguments:
3843 *
3844 * info pointer to device instance data
3845 * BufferList pointer to list of buffer entries
3846 * Buffercount count of buffer entries in buffer list
3847 *
3848 * Return Value: None
3849 */
3850static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3851{
3852    int i;
3853
3854    if ( BufferList ) {
3855        for ( i = 0 ; i < Buffercount ; i++ ) {
3856            if ( BufferList[i].virt_addr ) {
3857                if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3858                    dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3859                BufferList[i].virt_addr = NULL;
3860            }
3861        }
3862    }
3863
3864} /* end of mgsl_free_frame_memory() */
3865
3866/* mgsl_free_dma_buffers()
3867 *
3868 * Free DMA buffers
3869 *
3870 * Arguments: info pointer to device instance data
3871 * Return Value: None
3872 */
3873static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3874{
3875    mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3876    mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3877    mgsl_free_buffer_list_memory( info );
3878
3879} /* end of mgsl_free_dma_buffers() */
3880
3881
3882/*
3883 * mgsl_alloc_intermediate_rxbuffer_memory()
3884 *
3885 * Allocate a buffer large enough to hold max_frame_size. This buffer
3886 * is used to pass an assembled frame to the line discipline.
3887 *
3888 * Arguments:
3889 *
3890 * info pointer to device instance data
3891 *
3892 * Return Value: 0 if success, otherwise -ENOMEM
3893 */
3894static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3895{
3896    info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3897    if ( info->intermediate_rxbuffer == NULL )
3898        return -ENOMEM;
3899    /* unused flag buffer to satisfy receive_buf calling interface */
3900    info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3901    if (!info->flag_buf) {
3902        kfree(info->intermediate_rxbuffer);
3903        info->intermediate_rxbuffer = NULL;
3904        return -ENOMEM;
3905    }
3906    return 0;
3907
3908} /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3909
3910/*
3911 * mgsl_free_intermediate_rxbuffer_memory()
3912 *
3913 *
3914 * Arguments:
3915 *
3916 * info pointer to device instance data
3917 *
3918 * Return Value: None
3919 */
3920static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3921{
3922    kfree(info->intermediate_rxbuffer);
3923    info->intermediate_rxbuffer = NULL;
3924    kfree(info->flag_buf);
3925    info->flag_buf = NULL;
3926
3927} /* end of mgsl_free_intermediate_rxbuffer_memory() */
3928
3929/*
3930 * mgsl_alloc_intermediate_txbuffer_memory()
3931 *
3932 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3933 * This buffer is used to load transmit frames into the adapter's dma transfer
3934 * buffers when there is sufficient space.
3935 *
3936 * Arguments:
3937 *
3938 * info pointer to device instance data
3939 *
3940 * Return Value: 0 if success, otherwise -ENOMEM
3941 */
3942static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3943{
3944    int i;
3945
3946    if ( debug_level >= DEBUG_LEVEL_INFO )
3947        printk("%s %s(%d) allocating %d tx holding buffers\n",
3948                info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3949
3950    memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3951
3952    for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3953        info->tx_holding_buffers[i].buffer =
3954            kmalloc(info->max_frame_size, GFP_KERNEL);
3955        if (info->tx_holding_buffers[i].buffer == NULL) {
3956            for (--i; i >= 0; i--) {
3957                kfree(info->tx_holding_buffers[i].buffer);
3958                info->tx_holding_buffers[i].buffer = NULL;
3959            }
3960            return -ENOMEM;
3961        }
3962    }
3963
3964    return 0;
3965
3966} /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3967
3968/*
3969 * mgsl_free_intermediate_txbuffer_memory()
3970 *
3971 *
3972 * Arguments:
3973 *
3974 * info pointer to device instance data
3975 *
3976 * Return Value: None
3977 */
3978static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3979{
3980    int i;
3981
3982    for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3983        kfree(info->tx_holding_buffers[i].buffer);
3984        info->tx_holding_buffers[i].buffer = NULL;
3985    }
3986
3987    info->get_tx_holding_index = 0;
3988    info->put_tx_holding_index = 0;
3989    info->tx_holding_count = 0;
3990
3991} /* end of mgsl_free_intermediate_txbuffer_memory() */
3992
3993
3994/*
3995 * load_next_tx_holding_buffer()
3996 *
3997 * attempts to load the next buffered tx request into the
3998 * tx dma buffers
3999 *
4000 * Arguments:
4001 *
4002 * info pointer to device instance data
4003 *
4004 * Return Value: true if next buffered tx request loaded
4005 * into adapter's tx dma buffer,
4006 * false otherwise
4007 */
4008static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4009{
4010    bool ret = false;
4011
4012    if ( info->tx_holding_count ) {
4013        /* determine if we have enough tx dma buffers
4014         * to accommodate the next tx frame
4015         */
4016        struct tx_holding_buffer *ptx =
4017            &info->tx_holding_buffers[info->get_tx_holding_index];
4018        int num_free = num_free_tx_dma_buffers(info);
4019        int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4020        if ( ptx->buffer_size % DMABUFFERSIZE )
4021            ++num_needed;
4022
4023        if (num_needed <= num_free) {
4024            info->xmit_cnt = ptx->buffer_size;
4025            mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4026
4027            --info->tx_holding_count;
4028            if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4029                info->get_tx_holding_index=0;
4030
4031            /* restart transmit timer */
4032            mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4033
4034            ret = true;
4035        }
4036    }
4037
4038    return ret;
4039}
4040
4041/*
4042 * save_tx_buffer_request()
4043 *
4044 * attempt to store transmit frame request for later transmission
4045 *
4046 * Arguments:
4047 *
4048 * info pointer to device instance data
4049 * Buffer pointer to buffer containing frame to load
4050 * BufferSize size in bytes of frame in Buffer
4051 *
4052 * Return Value: 1 if able to store, 0 otherwise
4053 */
4054static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4055{
4056    struct tx_holding_buffer *ptx;
4057
4058    if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4059        return 0; /* all buffers in use */
4060    }
4061
4062    ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4063    ptx->buffer_size = BufferSize;
4064    memcpy( ptx->buffer, Buffer, BufferSize);
4065
4066    ++info->tx_holding_count;
4067    if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4068        info->put_tx_holding_index=0;
4069
4070    return 1;
4071}
4072
4073static int mgsl_claim_resources(struct mgsl_struct *info)
4074{
4075    if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4076        printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4077            __FILE__,__LINE__,info->device_name, info->io_base);
4078        return -ENODEV;
4079    }
4080    info->io_addr_requested = true;
4081    
4082    if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4083        info->device_name, info ) < 0 ) {
4084        printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4085            __FILE__,__LINE__,info->device_name, info->irq_level );
4086        goto errout;
4087    }
4088    info->irq_requested = true;
4089    
4090    if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4091        if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4092            printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4093                __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4094            goto errout;
4095        }
4096        info->shared_mem_requested = true;
4097        if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4098            printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4099                __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4100            goto errout;
4101        }
4102        info->lcr_mem_requested = true;
4103
4104        info->memory_base = ioremap_nocache(info->phys_memory_base,
4105                                0x40000);
4106        if (!info->memory_base) {
4107            printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4108                __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4109            goto errout;
4110        }
4111        
4112        if ( !mgsl_memory_test(info) ) {
4113            printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4114                __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4115            goto errout;
4116        }
4117        
4118        info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4119                                PAGE_SIZE);
4120        if (!info->lcr_base) {
4121            printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4122                __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4123            goto errout;
4124        }
4125        info->lcr_base += info->lcr_offset;
4126        
4127    } else {
4128        /* claim DMA channel */
4129        
4130        if (request_dma(info->dma_level,info->device_name) < 0){
4131            printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4132                __FILE__,__LINE__,info->device_name, info->dma_level );
4133            mgsl_release_resources( info );
4134            return -ENODEV;
4135        }
4136        info->dma_requested = true;
4137
4138        /* ISA adapter uses bus master DMA */
4139        set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4140        enable_dma(info->dma_level);
4141    }
4142    
4143    if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4144        printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4145            __FILE__,__LINE__,info->device_name, info->dma_level );
4146        goto errout;
4147    }
4148    
4149    return 0;
4150errout:
4151    mgsl_release_resources(info);
4152    return -ENODEV;
4153
4154} /* end of mgsl_claim_resources() */
4155
4156static void mgsl_release_resources(struct mgsl_struct *info)
4157{
4158    if ( debug_level >= DEBUG_LEVEL_INFO )
4159        printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4160            __FILE__,__LINE__,info->device_name );
4161            
4162    if ( info->irq_requested ) {
4163        free_irq(info->irq_level, info);
4164        info->irq_requested = false;
4165    }
4166    if ( info->dma_requested ) {
4167        disable_dma(info->dma_level);
4168        free_dma(info->dma_level);
4169        info->dma_requested = false;
4170    }
4171    mgsl_free_dma_buffers(info);
4172    mgsl_free_intermediate_rxbuffer_memory(info);
4173         mgsl_free_intermediate_txbuffer_memory(info);
4174    
4175    if ( info->io_addr_requested ) {
4176        release_region(info->io_base,info->io_addr_size);
4177        info->io_addr_requested = false;
4178    }
4179    if ( info->shared_mem_requested ) {
4180        release_mem_region(info->phys_memory_base,0x40000);
4181        info->shared_mem_requested = false;
4182    }
4183    if ( info->lcr_mem_requested ) {
4184        release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4185        info->lcr_mem_requested = false;
4186    }
4187    if (info->memory_base){
4188        iounmap(info->memory_base);
4189        info->memory_base = NULL;
4190    }
4191    if (info->lcr_base){
4192        iounmap(info->lcr_base - info->lcr_offset);
4193        info->lcr_base = NULL;
4194    }
4195    
4196    if ( debug_level >= DEBUG_LEVEL_INFO )
4197        printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4198            __FILE__,__LINE__,info->device_name );
4199            
4200} /* end of mgsl_release_resources() */
4201
4202/* mgsl_add_device()
4203 *
4204 * Add the specified device instance data structure to the
4205 * global linked list of devices and increment the device count.
4206 *
4207 * Arguments: info pointer to device instance data
4208 * Return Value: None
4209 */
4210static void mgsl_add_device( struct mgsl_struct *info )
4211{
4212    info->next_device = NULL;
4213    info->line = mgsl_device_count;
4214    sprintf(info->device_name,"ttySL%d",info->line);
4215    
4216    if (info->line < MAX_TOTAL_DEVICES) {
4217        if (maxframe[info->line])
4218            info->max_frame_size = maxframe[info->line];
4219
4220        if (txdmabufs[info->line]) {
4221            info->num_tx_dma_buffers = txdmabufs[info->line];
4222            if (info->num_tx_dma_buffers < 1)
4223                info->num_tx_dma_buffers = 1;
4224        }
4225
4226        if (txholdbufs[info->line]) {
4227            info->num_tx_holding_buffers = txholdbufs[info->line];
4228            if (info->num_tx_holding_buffers < 1)
4229                info->num_tx_holding_buffers = 1;
4230            else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4231                info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4232        }
4233    }
4234
4235    mgsl_device_count++;
4236    
4237    if ( !mgsl_device_list )
4238        mgsl_device_list = info;
4239    else {
4240        struct mgsl_struct *current_dev = mgsl_device_list;
4241        while( current_dev->next_device )
4242            current_dev = current_dev->next_device;
4243        current_dev->next_device = info;
4244    }
4245    
4246    if ( info->max_frame_size < 4096 )
4247        info->max_frame_size = 4096;
4248    else if ( info->max_frame_size > 65535 )
4249        info->max_frame_size = 65535;
4250    
4251    if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4252        printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4253            info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4254            info->phys_memory_base, info->phys_lcr_base,
4255                 info->max_frame_size );
4256    } else {
4257        printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4258            info->device_name, info->io_base, info->irq_level, info->dma_level,
4259                 info->max_frame_size );
4260    }
4261
4262#if SYNCLINK_GENERIC_HDLC
4263    hdlcdev_init(info);
4264#endif
4265
4266} /* end of mgsl_add_device() */
4267
4268static const struct tty_port_operations mgsl_port_ops = {
4269    .carrier_raised = carrier_raised,
4270    .dtr_rts = dtr_rts,
4271};
4272
4273
4274/* mgsl_allocate_device()
4275 *
4276 * Allocate and initialize a device instance structure
4277 *
4278 * Arguments: none
4279 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4280 */
4281static struct mgsl_struct* mgsl_allocate_device(void)
4282{
4283    struct mgsl_struct *info;
4284    
4285    info = kzalloc(sizeof(struct mgsl_struct),
4286         GFP_KERNEL);
4287         
4288    if (!info) {
4289        printk("Error can't allocate device instance data\n");
4290    } else {
4291        tty_port_init(&info->port);
4292        info->port.ops = &mgsl_port_ops;
4293        info->magic = MGSL_MAGIC;
4294        INIT_WORK(&info->task, mgsl_bh_handler);
4295        info->max_frame_size = 4096;
4296        info->port.close_delay = 5*HZ/10;
4297        info->port.closing_wait = 30*HZ;
4298        init_waitqueue_head(&info->status_event_wait_q);
4299        init_waitqueue_head(&info->event_wait_q);
4300        spin_lock_init(&info->irq_spinlock);
4301        spin_lock_init(&info->netlock);
4302        memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4303        info->idle_mode = HDLC_TXIDLE_FLAGS;
4304        info->num_tx_dma_buffers = 1;
4305        info->num_tx_holding_buffers = 0;
4306    }
4307    
4308    return info;
4309
4310} /* end of mgsl_allocate_device()*/
4311
4312static const struct tty_operations mgsl_ops = {
4313    .install = mgsl_install,
4314    .open = mgsl_open,
4315    .close = mgsl_close,
4316    .write = mgsl_write,
4317    .put_char = mgsl_put_char,
4318    .flush_chars = mgsl_flush_chars,
4319    .write_room = mgsl_write_room,
4320    .chars_in_buffer = mgsl_chars_in_buffer,
4321    .flush_buffer = mgsl_flush_buffer,
4322    .ioctl = mgsl_ioctl,
4323    .throttle = mgsl_throttle,
4324    .unthrottle = mgsl_unthrottle,
4325    .send_xchar = mgsl_send_xchar,
4326    .break_ctl = mgsl_break,
4327    .wait_until_sent = mgsl_wait_until_sent,
4328    .set_termios = mgsl_set_termios,
4329    .stop = mgsl_stop,
4330    .start = mgsl_start,
4331    .hangup = mgsl_hangup,
4332    .tiocmget = tiocmget,
4333    .tiocmset = tiocmset,
4334    .get_icount = msgl_get_icount,
4335    .proc_fops = &mgsl_proc_fops,
4336};
4337
4338/*
4339 * perform tty device initialization
4340 */
4341static int mgsl_init_tty(void)
4342{
4343    int rc;
4344
4345    serial_driver = alloc_tty_driver(128);
4346    if (!serial_driver)
4347        return -ENOMEM;
4348    
4349    serial_driver->driver_name = "synclink";
4350    serial_driver->name = "ttySL";
4351    serial_driver->major = ttymajor;
4352    serial_driver->minor_start = 64;
4353    serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4354    serial_driver->subtype = SERIAL_TYPE_NORMAL;
4355    serial_driver->init_termios = tty_std_termios;
4356    serial_driver->init_termios.c_cflag =
4357        B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4358    serial_driver->init_termios.c_ispeed = 9600;
4359    serial_driver->init_termios.c_ospeed = 9600;
4360    serial_driver->flags = TTY_DRIVER_REAL_RAW;
4361    tty_set_operations(serial_driver, &mgsl_ops);
4362    if ((rc = tty_register_driver(serial_driver)) < 0) {
4363        printk("%s(%d):Couldn't register serial driver\n",
4364            __FILE__,__LINE__);
4365        put_tty_driver(serial_driver);
4366        serial_driver = NULL;
4367        return rc;
4368    }
4369            
4370     printk("%s %s, tty major#%d\n",
4371        driver_name, driver_version,
4372        serial_driver->major);
4373    return 0;
4374}
4375
4376/* enumerate user specified ISA adapters
4377 */
4378static void mgsl_enum_isa_devices(void)
4379{
4380    struct mgsl_struct *info;
4381    int i;
4382        
4383    /* Check for user specified ISA devices */
4384    
4385    for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4386        if ( debug_level >= DEBUG_LEVEL_INFO )
4387            printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4388                io[i], irq[i], dma[i] );
4389        
4390        info = mgsl_allocate_device();
4391        if ( !info ) {
4392            /* error allocating device instance data */
4393            if ( debug_level >= DEBUG_LEVEL_ERROR )
4394                printk( "can't allocate device instance data.\n");
4395            continue;
4396        }
4397        
4398        /* Copy user configuration info to device instance data */
4399        info->io_base = (unsigned int)io[i];
4400        info->irq_level = (unsigned int)irq[i];
4401        info->irq_level = irq_canonicalize(info->irq_level);
4402        info->dma_level = (unsigned int)dma[i];
4403        info->bus_type = MGSL_BUS_TYPE_ISA;
4404        info->io_addr_size = 16;
4405        info->irq_flags = 0;
4406        
4407        mgsl_add_device( info );
4408    }
4409}
4410
4411static void synclink_cleanup(void)
4412{
4413    int rc;
4414    struct mgsl_struct *info;
4415    struct mgsl_struct *tmp;
4416
4417    printk("Unloading %s: %s\n", driver_name, driver_version);
4418
4419    if (serial_driver) {
4420        if ((rc = tty_unregister_driver(serial_driver)))
4421            printk("%s(%d) failed to unregister tty driver err=%d\n",
4422                   __FILE__,__LINE__,rc);
4423        put_tty_driver(serial_driver);
4424    }
4425
4426    info = mgsl_device_list;
4427    while(info) {
4428#if SYNCLINK_GENERIC_HDLC
4429        hdlcdev_exit(info);
4430#endif
4431        mgsl_release_resources(info);
4432        tmp = info;
4433        info = info->next_device;
4434        tty_port_destroy(&tmp->port);
4435        kfree(tmp);
4436    }
4437    
4438    if (pci_registered)
4439        pci_unregister_driver(&synclink_pci_driver);
4440}
4441
4442static int __init synclink_init(void)
4443{
4444    int rc;
4445
4446    if (break_on_load) {
4447         mgsl_get_text_ptr();
4448          BREAKPOINT();
4449    }
4450
4451     printk("%s %s\n", driver_name, driver_version);
4452
4453    mgsl_enum_isa_devices();
4454    if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4455        printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4456    else
4457        pci_registered = true;
4458
4459    if ((rc = mgsl_init_tty()) < 0)
4460        goto error;
4461
4462    return 0;
4463
4464error:
4465    synclink_cleanup();
4466    return rc;
4467}
4468
4469static void __exit synclink_exit(void)
4470{
4471    synclink_cleanup();
4472}
4473
4474module_init(synclink_init);
4475module_exit(synclink_exit);
4476
4477/*
4478 * usc_RTCmd()
4479 *
4480 * Issue a USC Receive/Transmit command to the
4481 * Channel Command/Address Register (CCAR).
4482 *
4483 * Notes:
4484 *
4485 * The command is encoded in the most significant 5 bits <15..11>
4486 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4487 * and Bits <6..0> must be written as zeros.
4488 *
4489 * Arguments:
4490 *
4491 * info pointer to device information structure
4492 * Cmd command mask (use symbolic macros)
4493 *
4494 * Return Value:
4495 *
4496 * None
4497 */
4498static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4499{
4500    /* output command to CCAR in bits <15..11> */
4501    /* preserve bits <10..7>, bits <6..0> must be zero */
4502
4503    outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4504
4505    /* Read to flush write to CCAR */
4506    if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4507        inw( info->io_base + CCAR );
4508
4509} /* end of usc_RTCmd() */
4510
4511/*
4512 * usc_DmaCmd()
4513 *
4514 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4515 *
4516 * Arguments:
4517 *
4518 * info pointer to device information structure
4519 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4520 *
4521 * Return Value:
4522 *
4523 * None
4524 */
4525static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4526{
4527    /* write command mask to DCAR */
4528    outw( Cmd + info->mbre_bit, info->io_base );
4529
4530    /* Read to flush write to DCAR */
4531    if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4532        inw( info->io_base );
4533
4534} /* end of usc_DmaCmd() */
4535
4536/*
4537 * usc_OutDmaReg()
4538 *
4539 * Write a 16-bit value to a USC DMA register
4540 *
4541 * Arguments:
4542 *
4543 * info pointer to device info structure
4544 * RegAddr register address (number) for write
4545 * RegValue 16-bit value to write to register
4546 *
4547 * Return Value:
4548 *
4549 * None
4550 *
4551 */
4552static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4553{
4554    /* Note: The DCAR is located at the adapter base address */
4555    /* Note: must preserve state of BIT8 in DCAR */
4556
4557    outw( RegAddr + info->mbre_bit, info->io_base );
4558    outw( RegValue, info->io_base );
4559
4560    /* Read to flush write to DCAR */
4561    if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4562        inw( info->io_base );
4563
4564} /* end of usc_OutDmaReg() */
4565 
4566/*
4567 * usc_InDmaReg()
4568 *
4569 * Read a 16-bit value from a DMA register
4570 *
4571 * Arguments:
4572 *
4573 * info pointer to device info structure
4574 * RegAddr register address (number) to read from
4575 *
4576 * Return Value:
4577 *
4578 * The 16-bit value read from register
4579 *
4580 */
4581static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4582{
4583    /* Note: The DCAR is located at the adapter base address */
4584    /* Note: must preserve state of BIT8 in DCAR */
4585
4586    outw( RegAddr + info->mbre_bit, info->io_base );
4587    return inw( info->io_base );
4588
4589} /* end of usc_InDmaReg() */
4590
4591/*
4592 *
4593 * usc_OutReg()
4594 *
4595 * Write a 16-bit value to a USC serial channel register
4596 *
4597 * Arguments:
4598 *
4599 * info pointer to device info structure
4600 * RegAddr register address (number) to write to
4601 * RegValue 16-bit value to write to register
4602 *
4603 * Return Value:
4604 *
4605 * None
4606 *
4607 */
4608static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4609{
4610    outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4611    outw( RegValue, info->io_base + CCAR );
4612
4613    /* Read to flush write to CCAR */
4614    if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4615        inw( info->io_base + CCAR );
4616
4617} /* end of usc_OutReg() */
4618
4619/*
4620 * usc_InReg()
4621 *
4622 * Reads a 16-bit value from a USC serial channel register
4623 *
4624 * Arguments:
4625 *
4626 * info pointer to device extension
4627 * RegAddr register address (number) to read from
4628 *
4629 * Return Value:
4630 *
4631 * 16-bit value read from register
4632 */
4633static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4634{
4635    outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4636    return inw( info->io_base + CCAR );
4637
4638} /* end of usc_InReg() */
4639
4640/* usc_set_sdlc_mode()
4641 *
4642 * Set up the adapter for SDLC DMA communications.
4643 *
4644 * Arguments: info pointer to device instance data
4645 * Return Value: NONE
4646 */
4647static void usc_set_sdlc_mode( struct mgsl_struct *info )
4648{
4649    u16 RegValue;
4650    bool PreSL1660;
4651    
4652    /*
4653     * determine if the IUSC on the adapter is pre-SL1660. If
4654     * not, take advantage of the UnderWait feature of more
4655     * modern chips. If an underrun occurs and this bit is set,
4656     * the transmitter will idle the programmed idle pattern
4657     * until the driver has time to service the underrun. Otherwise,
4658     * the dma controller may get the cycles previously requested
4659     * and begin transmitting queued tx data.
4660     */
4661    usc_OutReg(info,TMCR,0x1f);
4662    RegValue=usc_InReg(info,TMDR);
4663    PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4664
4665     if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4666     {
4667        /*
4668        ** Channel Mode Register (CMR)
4669        **
4670        ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4671        ** <13> 0 0 = Transmit Disabled (initially)
4672        ** <12> 0 1 = Consecutive Idles share common 0
4673        ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4674        ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4675        ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4676        **
4677        ** 1000 1110 0000 0110 = 0x8e06
4678        */
4679        RegValue = 0x8e06;
4680 
4681        /*--------------------------------------------------
4682         * ignore user options for UnderRun Actions and
4683         * preambles
4684         *--------------------------------------------------*/
4685     }
4686     else
4687     {
4688        /* Channel mode Register (CMR)
4689         *
4690         * <15..14> 00 Tx Sub modes, Underrun Action
4691         * <13> 0 1 = Send Preamble before opening flag
4692         * <12> 0 1 = Consecutive Idles share common 0
4693         * <11..8> 0110 Transmitter mode = HDLC/SDLC
4694         * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4695         * <3..0> 0110 Receiver mode = HDLC/SDLC
4696         *
4697         * 0000 0110 0000 0110 = 0x0606
4698         */
4699        if (info->params.mode == MGSL_MODE_RAW) {
4700            RegValue = 0x0001; /* Set Receive mode = external sync */
4701
4702            usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4703                (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4704
4705            /*
4706             * TxSubMode:
4707             * CMR <15> 0 Don't send CRC on Tx Underrun
4708             * CMR <14> x undefined
4709             * CMR <13> 0 Send preamble before openning sync
4710             * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4711             *
4712             * TxMode:
4713             * CMR <11-8) 0100 MonoSync
4714             *
4715             * 0x00 0100 xxxx xxxx 04xx
4716             */
4717            RegValue |= 0x0400;
4718        }
4719        else {
4720
4721        RegValue = 0x0606;
4722
4723        if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4724            RegValue |= BIT14;
4725        else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4726            RegValue |= BIT15;
4727        else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4728            RegValue |= BIT15 + BIT14;
4729        }
4730
4731        if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4732            RegValue |= BIT13;
4733    }
4734
4735    if ( info->params.mode == MGSL_MODE_HDLC &&
4736        (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4737        RegValue |= BIT12;
4738
4739    if ( info->params.addr_filter != 0xff )
4740    {
4741        /* set up receive address filtering */
4742        usc_OutReg( info, RSR, info->params.addr_filter );
4743        RegValue |= BIT4;
4744    }
4745
4746    usc_OutReg( info, CMR, RegValue );
4747    info->cmr_value = RegValue;
4748
4749    /* Receiver mode Register (RMR)
4750     *
4751     * <15..13> 000 encoding
4752     * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4753     * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4754     * <9> 0 1 = Include Receive chars in CRC
4755     * <8> 1 1 = Use Abort/PE bit as abort indicator
4756     * <7..6> 00 Even parity
4757     * <5> 0 parity disabled
4758     * <4..2> 000 Receive Char Length = 8 bits
4759     * <1..0> 00 Disable Receiver
4760     *
4761     * 0000 0101 0000 0000 = 0x0500
4762     */
4763
4764    RegValue = 0x0500;
4765
4766    switch ( info->params.encoding ) {
4767    case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4768    case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4769    case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4770    case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4771    case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4772    case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4773    case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4774    }
4775
4776    if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4777        RegValue |= BIT9;
4778    else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4779        RegValue |= ( BIT12 | BIT10 | BIT9 );
4780
4781    usc_OutReg( info, RMR, RegValue );
4782
4783    /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4784    /* When an opening flag of an SDLC frame is recognized the */
4785    /* Receive Character count (RCC) is loaded with the value in */
4786    /* RCLR. The RCC is decremented for each received byte. The */
4787    /* value of RCC is stored after the closing flag of the frame */
4788    /* allowing the frame size to be computed. */
4789
4790    usc_OutReg( info, RCLR, RCLRVALUE );
4791
4792    usc_RCmd( info, RCmd_SelectRicrdma_level );
4793
4794    /* Receive Interrupt Control Register (RICR)
4795     *
4796     * <15..8> ? RxFIFO DMA Request Level
4797     * <7> 0 Exited Hunt IA (Interrupt Arm)
4798     * <6> 0 Idle Received IA
4799     * <5> 0 Break/Abort IA
4800     * <4> 0 Rx Bound IA
4801     * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4802     * <2> 0 Abort/PE IA
4803     * <1> 1 Rx Overrun IA
4804     * <0> 0 Select TC0 value for readback
4805     *
4806     * 0000 0000 0000 1000 = 0x000a
4807     */
4808
4809    /* Carry over the Exit Hunt and Idle Received bits */
4810    /* in case they have been armed by usc_ArmEvents. */
4811
4812    RegValue = usc_InReg( info, RICR ) & 0xc0;
4813
4814    if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4815        usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4816    else
4817        usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4818
4819    /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4820
4821    usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4822    usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4823
4824    /* Transmit mode Register (TMR)
4825     *
4826     * <15..13> 000 encoding
4827     * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4828     * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4829     * <9> 0 1 = Tx CRC Enabled
4830     * <8> 0 1 = Append CRC to end of transmit frame
4831     * <7..6> 00 Transmit parity Even
4832     * <5> 0 Transmit parity Disabled
4833     * <4..2> 000 Tx Char Length = 8 bits
4834     * <1..0> 00 Disable Transmitter
4835     *
4836     * 0000 0100 0000 0000 = 0x0400
4837     */
4838
4839    RegValue = 0x0400;
4840
4841    switch ( info->params.encoding ) {
4842    case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4843    case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4844    case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4845    case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4846    case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4847    case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4848    case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4849    }
4850
4851    if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4852        RegValue |= BIT9 + BIT8;
4853    else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4854        RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4855
4856    usc_OutReg( info, TMR, RegValue );
4857
4858    usc_set_txidle( info );
4859
4860
4861    usc_TCmd( info, TCmd_SelectTicrdma_level );
4862
4863    /* Transmit Interrupt Control Register (TICR)
4864     *
4865     * <15..8> ? Transmit FIFO DMA Level
4866     * <7> 0 Present IA (Interrupt Arm)
4867     * <6> 0 Idle Sent IA
4868     * <5> 1 Abort Sent IA
4869     * <4> 1 EOF/EOM Sent IA
4870     * <3> 0 CRC Sent IA
4871     * <2> 1 1 = Wait for SW Trigger to Start Frame
4872     * <1> 1 Tx Underrun IA
4873     * <0> 0 TC0 constant on read back
4874     *
4875     * 0000 0000 0011 0110 = 0x0036
4876     */
4877
4878    if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4879        usc_OutReg( info, TICR, 0x0736 );
4880    else
4881        usc_OutReg( info, TICR, 0x1436 );
4882
4883    usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4884    usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4885
4886    /*
4887    ** Transmit Command/Status Register (TCSR)
4888    **
4889    ** <15..12> 0000 TCmd
4890    ** <11> 0/1 UnderWait
4891    ** <10..08> 000 TxIdle
4892    ** <7> x PreSent
4893    ** <6> x IdleSent
4894    ** <5> x AbortSent
4895    ** <4> x EOF/EOM Sent
4896    ** <3> x CRC Sent
4897    ** <2> x All Sent
4898    ** <1> x TxUnder
4899    ** <0> x TxEmpty
4900    **
4901    ** 0000 0000 0000 0000 = 0x0000
4902    */
4903    info->tcsr_value = 0;
4904
4905    if ( !PreSL1660 )
4906        info->tcsr_value |= TCSR_UNDERWAIT;
4907        
4908    usc_OutReg( info, TCSR, info->tcsr_value );
4909
4910    /* Clock mode Control Register (CMCR)
4911     *
4912     * <15..14> 00 counter 1 Source = Disabled
4913     * <13..12> 00 counter 0 Source = Disabled
4914     * <11..10> 11 BRG1 Input is TxC Pin
4915     * <9..8> 11 BRG0 Input is TxC Pin
4916     * <7..6> 01 DPLL Input is BRG1 Output
4917     * <5..3> XXX TxCLK comes from Port 0
4918     * <2..0> XXX RxCLK comes from Port 1
4919     *
4920     * 0000 1111 0111 0111 = 0x0f77
4921     */
4922
4923    RegValue = 0x0f40;
4924
4925    if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4926        RegValue |= 0x0003; /* RxCLK from DPLL */
4927    else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4928        RegValue |= 0x0004; /* RxCLK from BRG0 */
4929     else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4930         RegValue |= 0x0006; /* RxCLK from TXC Input */
4931    else
4932        RegValue |= 0x0007; /* RxCLK from Port1 */
4933
4934    if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4935        RegValue |= 0x0018; /* TxCLK from DPLL */
4936    else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4937        RegValue |= 0x0020; /* TxCLK from BRG0 */
4938     else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4939         RegValue |= 0x0038; /* RxCLK from TXC Input */
4940    else
4941        RegValue |= 0x0030; /* TxCLK from Port0 */
4942
4943    usc_OutReg( info, CMCR, RegValue );
4944
4945
4946    /* Hardware Configuration Register (HCR)
4947     *
4948     * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4949     * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4950     * <12> 0 CVOK:0=report code violation in biphase
4951     * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4952     * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4953     * <7..6> 00 reserved
4954     * <5> 0 BRG1 mode:0=continuous,1=single cycle
4955     * <4> X BRG1 Enable
4956     * <3..2> 00 reserved
4957     * <1> 0 BRG0 mode:0=continuous,1=single cycle
4958     * <0> 0 BRG0 Enable
4959     */
4960
4961    RegValue = 0x0000;
4962
4963    if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4964        u32 XtalSpeed;
4965        u32 DpllDivisor;
4966        u16 Tc;
4967
4968        /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4969        /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4970
4971        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4972            XtalSpeed = 11059200;
4973        else
4974            XtalSpeed = 14745600;
4975
4976        if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4977            DpllDivisor = 16;
4978            RegValue |= BIT10;
4979        }
4980        else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4981            DpllDivisor = 8;
4982            RegValue |= BIT11;
4983        }
4984        else
4985            DpllDivisor = 32;
4986
4987        /* Tc = (Xtal/Speed) - 1 */
4988        /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4989        /* then rounding up gives a more precise time constant. Instead */
4990        /* of rounding up and then subtracting 1 we just don't subtract */
4991        /* the one in this case. */
4992
4993         /*--------------------------------------------------
4994          * ejz: for DPLL mode, application should use the
4995          * same clock speed as the partner system, even
4996          * though clocking is derived from the input RxData.
4997          * In case the user uses a 0 for the clock speed,
4998          * default to 0xffffffff and don't try to divide by
4999          * zero
5000          *--------------------------------------------------*/
5001         if ( info->params.clock_speed )
5002         {
5003            Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5004            if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5005                   / info->params.clock_speed) )
5006                Tc--;
5007         }
5008         else
5009             Tc = -1;
5010                   
5011
5012        /* Write 16-bit Time Constant for BRG1 */
5013        usc_OutReg( info, TC1R, Tc );
5014
5015        RegValue |= BIT4; /* enable BRG1 */
5016
5017        switch ( info->params.encoding ) {
5018        case HDLC_ENCODING_NRZ:
5019        case HDLC_ENCODING_NRZB:
5020        case HDLC_ENCODING_NRZI_MARK:
5021        case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5022        case HDLC_ENCODING_BIPHASE_MARK:
5023        case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5024        case HDLC_ENCODING_BIPHASE_LEVEL:
5025        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5026        }
5027    }
5028
5029    usc_OutReg( info, HCR, RegValue );
5030
5031
5032    /* Channel Control/status Register (CCSR)
5033     *
5034     * <15> X RCC FIFO Overflow status (RO)
5035     * <14> X RCC FIFO Not Empty status (RO)
5036     * <13> 0 1 = Clear RCC FIFO (WO)
5037     * <12> X DPLL Sync (RW)
5038     * <11> X DPLL 2 Missed Clocks status (RO)
5039     * <10> X DPLL 1 Missed Clock status (RO)
5040     * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5041     * <7> X SDLC Loop On status (RO)
5042     * <6> X SDLC Loop Send status (RO)
5043     * <5> 1 Bypass counters for TxClk and RxClk (RW)
5044     * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5045     * <1..0> 00 reserved
5046     *
5047     * 0000 0000 0010 0000 = 0x0020
5048     */
5049
5050    usc_OutReg( info, CCSR, 0x1020 );
5051
5052
5053    if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5054        usc_OutReg( info, SICR,
5055                (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5056    }
5057    
5058
5059    /* enable Master Interrupt Enable bit (MIE) */
5060    usc_EnableMasterIrqBit( info );
5061
5062    usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5063                TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5064
5065    /* arm RCC underflow interrupt */
5066    usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5067    usc_EnableInterrupts(info, MISC);
5068
5069    info->mbre_bit = 0;
5070    outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5071    usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5072    info->mbre_bit = BIT8;
5073    outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5074
5075    if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5076        /* Enable DMAEN (Port 7, Bit 14) */
5077        /* This connects the DMA request signal to the ISA bus */
5078        usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5079    }
5080
5081    /* DMA Control Register (DCR)
5082     *
5083     * <15..14> 10 Priority mode = Alternating Tx/Rx
5084     * 01 Rx has priority
5085     * 00 Tx has priority
5086     *
5087     * <13> 1 Enable Priority Preempt per DCR<15..14>
5088     * (WARNING DCR<11..10> must be 00 when this is 1)
5089     * 0 Choose activate channel per DCR<11..10>
5090     *
5091     * <12> 0 Little Endian for Array/List
5092     * <11..10> 00 Both Channels can use each bus grant
5093     * <9..6> 0000 reserved
5094     * <5> 0 7 CLK - Minimum Bus Re-request Interval
5095     * <4> 0 1 = drive D/C and S/D pins
5096     * <3> 1 1 = Add one wait state to all DMA cycles.
5097     * <2> 0 1 = Strobe /UAS on every transfer.
5098     * <1..0> 11 Addr incrementing only affects LS24 bits
5099     *
5100     * 0110 0000 0000 1011 = 0x600b
5101     */
5102
5103    if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5104        /* PCI adapter does not need DMA wait state */
5105        usc_OutDmaReg( info, DCR, 0xa00b );
5106    }
5107    else
5108        usc_OutDmaReg( info, DCR, 0x800b );
5109
5110
5111    /* Receive DMA mode Register (RDMR)
5112     *
5113     * <15..14> 11 DMA mode = Linked List Buffer mode
5114     * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5115     * <12> 1 Clear count of List Entry after fetching
5116     * <11..10> 00 Address mode = Increment
5117     * <9> 1 Terminate Buffer on RxBound
5118     * <8> 0 Bus Width = 16bits
5119     * <7..0> ? status Bits (write as 0s)
5120     *
5121     * 1111 0010 0000 0000 = 0xf200
5122     */
5123
5124    usc_OutDmaReg( info, RDMR, 0xf200 );
5125
5126
5127    /* Transmit DMA mode Register (TDMR)
5128     *
5129     * <15..14> 11 DMA mode = Linked List Buffer mode
5130     * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5131     * <12> 1 Clear count of List Entry after fetching
5132     * <11..10> 00 Address mode = Increment
5133     * <9> 1 Terminate Buffer on end of frame
5134     * <8> 0 Bus Width = 16bits
5135     * <7..0> ? status Bits (Read Only so write as 0)
5136     *
5137     * 1111 0010 0000 0000 = 0xf200
5138     */
5139
5140    usc_OutDmaReg( info, TDMR, 0xf200 );
5141
5142
5143    /* DMA Interrupt Control Register (DICR)
5144     *
5145     * <15> 1 DMA Interrupt Enable
5146     * <14> 0 1 = Disable IEO from USC
5147     * <13> 0 1 = Don't provide vector during IntAck
5148     * <12> 1 1 = Include status in Vector
5149     * <10..2> 0 reserved, Must be 0s
5150     * <1> 0 1 = Rx DMA Interrupt Enabled
5151     * <0> 0 1 = Tx DMA Interrupt Enabled
5152     *
5153     * 1001 0000 0000 0000 = 0x9000
5154     */
5155
5156    usc_OutDmaReg( info, DICR, 0x9000 );
5157
5158    usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5159    usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5160    usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5161
5162    /* Channel Control Register (CCR)
5163     *
5164     * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5165     * <13> 0 Trigger Tx on SW Command Disabled
5166     * <12> 0 Flag Preamble Disabled
5167     * <11..10> 00 Preamble Length
5168     * <9..8> 00 Preamble Pattern
5169     * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5170     * <5> 0 Trigger Rx on SW Command Disabled
5171     * <4..0> 0 reserved
5172     *
5173     * 1000 0000 1000 0000 = 0x8080
5174     */
5175
5176    RegValue = 0x8080;
5177
5178    switch ( info->params.preamble_length ) {
5179    case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5180    case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5181    case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5182    }
5183
5184    switch ( info->params.preamble ) {
5185    case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5186    case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5187    case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5188    case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5189    }
5190
5191    usc_OutReg( info, CCR, RegValue );
5192
5193
5194    /*
5195     * Burst/Dwell Control Register
5196     *
5197     * <15..8> 0x20 Maximum number of transfers per bus grant
5198     * <7..0> 0x00 Maximum number of clock cycles per bus grant
5199     */
5200
5201    if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5202        /* don't limit bus occupancy on PCI adapter */
5203        usc_OutDmaReg( info, BDCR, 0x0000 );
5204    }
5205    else
5206        usc_OutDmaReg( info, BDCR, 0x2000 );
5207
5208    usc_stop_transmitter(info);
5209    usc_stop_receiver(info);
5210    
5211} /* end of usc_set_sdlc_mode() */
5212
5213/* usc_enable_loopback()
5214 *
5215 * Set the 16C32 for internal loopback mode.
5216 * The TxCLK and RxCLK signals are generated from the BRG0 and
5217 * the TxD is looped back to the RxD internally.
5218 *
5219 * Arguments: info pointer to device instance data
5220 * enable 1 = enable loopback, 0 = disable
5221 * Return Value: None
5222 */
5223static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5224{
5225    if (enable) {
5226        /* blank external TXD output */
5227        usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5228    
5229        /* Clock mode Control Register (CMCR)
5230         *
5231         * <15..14> 00 counter 1 Disabled
5232         * <13..12> 00 counter 0 Disabled
5233         * <11..10> 11 BRG1 Input is TxC Pin
5234         * <9..8> 11 BRG0 Input is TxC Pin
5235         * <7..6> 01 DPLL Input is BRG1 Output
5236         * <5..3> 100 TxCLK comes from BRG0
5237         * <2..0> 100 RxCLK comes from BRG0
5238         *
5239         * 0000 1111 0110 0100 = 0x0f64
5240         */
5241
5242        usc_OutReg( info, CMCR, 0x0f64 );
5243
5244        /* Write 16-bit Time Constant for BRG0 */
5245        /* use clock speed if available, otherwise use 8 for diagnostics */
5246        if (info->params.clock_speed) {
5247            if (info->bus_type == MGSL_BUS_TYPE_PCI)
5248                usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5249            else
5250                usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5251        } else
5252            usc_OutReg(info, TC0R, (u16)8);
5253
5254        /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5255           mode = Continuous Set Bit 0 to enable BRG0. */
5256        usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5257
5258        /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5259        usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5260
5261        /* set Internal Data loopback mode */
5262        info->loopback_bits = 0x300;
5263        outw( 0x0300, info->io_base + CCAR );
5264    } else {
5265        /* enable external TXD output */
5266        usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5267    
5268        /* clear Internal Data loopback mode */
5269        info->loopback_bits = 0;
5270        outw( 0,info->io_base + CCAR );
5271    }
5272    
5273} /* end of usc_enable_loopback() */
5274
5275/* usc_enable_aux_clock()
5276 *
5277 * Enabled the AUX clock output at the specified frequency.
5278 *
5279 * Arguments:
5280 *
5281 * info pointer to device extension
5282 * data_rate data rate of clock in bits per second
5283 * A data rate of 0 disables the AUX clock.
5284 *
5285 * Return Value: None
5286 */
5287static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5288{
5289    u32 XtalSpeed;
5290    u16 Tc;
5291
5292    if ( data_rate ) {
5293        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5294            XtalSpeed = 11059200;
5295        else
5296            XtalSpeed = 14745600;
5297
5298
5299        /* Tc = (Xtal/Speed) - 1 */
5300        /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5301        /* then rounding up gives a more precise time constant. Instead */
5302        /* of rounding up and then subtracting 1 we just don't subtract */
5303        /* the one in this case. */
5304
5305
5306        Tc = (u16)(XtalSpeed/data_rate);
5307        if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5308            Tc--;
5309
5310        /* Write 16-bit Time Constant for BRG0 */
5311        usc_OutReg( info, TC0R, Tc );
5312
5313        /*
5314         * Hardware Configuration Register (HCR)
5315         * Clear Bit 1, BRG0 mode = Continuous
5316         * Set Bit 0 to enable BRG0.
5317         */
5318
5319        usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5320
5321        /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5322        usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5323    } else {
5324        /* data rate == 0 so turn off BRG0 */
5325        usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5326    }
5327
5328} /* end of usc_enable_aux_clock() */
5329
5330/*
5331 *
5332 * usc_process_rxoverrun_sync()
5333 *
5334 * This function processes a receive overrun by resetting the
5335 * receive DMA buffers and issuing a Purge Rx FIFO command
5336 * to allow the receiver to continue receiving.
5337 *
5338 * Arguments:
5339 *
5340 * info pointer to device extension
5341 *
5342 * Return Value: None
5343 */
5344static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5345{
5346    int start_index;
5347    int end_index;
5348    int frame_start_index;
5349    bool start_of_frame_found = false;
5350    bool end_of_frame_found = false;
5351    bool reprogram_dma = false;
5352
5353    DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5354    u32 phys_addr;
5355
5356    usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5357    usc_RCmd( info, RCmd_EnterHuntmode );
5358    usc_RTCmd( info, RTCmd_PurgeRxFifo );
5359
5360    /* CurrentRxBuffer points to the 1st buffer of the next */
5361    /* possibly available receive frame. */
5362    
5363    frame_start_index = start_index = end_index = info->current_rx_buffer;
5364
5365    /* Search for an unfinished string of buffers. This means */
5366    /* that a receive frame started (at least one buffer with */
5367    /* count set to zero) but there is no terminiting buffer */
5368    /* (status set to non-zero). */
5369
5370    while( !buffer_list[end_index].count )
5371    {
5372        /* Count field has been reset to zero by 16C32. */
5373        /* This buffer is currently in use. */
5374
5375        if ( !start_of_frame_found )
5376        {
5377            start_of_frame_found = true;
5378            frame_start_index = end_index;
5379            end_of_frame_found = false;
5380        }
5381
5382        if ( buffer_list[end_index].status )
5383        {
5384            /* Status field has been set by 16C32. */
5385            /* This is the last buffer of a received frame. */
5386
5387            /* We want to leave the buffers for this frame intact. */
5388            /* Move on to next possible frame. */
5389
5390            start_of_frame_found = false;
5391            end_of_frame_found = true;
5392        }
5393
5394          /* advance to next buffer entry in linked list */
5395          end_index++;
5396          if ( end_index == info->rx_buffer_count )
5397              end_index = 0;
5398
5399        if ( start_index == end_index )
5400        {
5401            /* The entire list has been searched with all Counts == 0 and */
5402            /* all Status == 0. The receive buffers are */
5403            /* completely screwed, reset all receive buffers! */
5404            mgsl_reset_rx_dma_buffers( info );
5405            frame_start_index = 0;
5406            start_of_frame_found = false;
5407            reprogram_dma = true;
5408            break;
5409        }
5410    }
5411
5412    if ( start_of_frame_found && !end_of_frame_found )
5413    {
5414        /* There is an unfinished string of receive DMA buffers */
5415        /* as a result of the receiver overrun. */
5416
5417        /* Reset the buffers for the unfinished frame */
5418        /* and reprogram the receive DMA controller to start */
5419        /* at the 1st buffer of unfinished frame. */
5420
5421        start_index = frame_start_index;
5422
5423        do
5424        {
5425            *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5426
5427              /* Adjust index for wrap around. */
5428              if ( start_index == info->rx_buffer_count )
5429                  start_index = 0;
5430
5431        } while( start_index != end_index );
5432
5433        reprogram_dma = true;
5434    }
5435
5436    if ( reprogram_dma )
5437    {
5438        usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5439        usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5440        usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5441        
5442        usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5443        
5444        /* This empties the receive FIFO and loads the RCC with RCLR */
5445        usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5446
5447        /* program 16C32 with physical address of 1st DMA buffer entry */
5448        phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5449        usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5450        usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5451
5452        usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5453        usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5454        usc_EnableInterrupts( info, RECEIVE_STATUS );
5455
5456        /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5457        /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5458
5459        usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5460        usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5461        usc_DmaCmd( info, DmaCmd_InitRxChannel );
5462        if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5463            usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5464        else
5465            usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5466    }
5467    else
5468    {
5469        /* This empties the receive FIFO and loads the RCC with RCLR */
5470        usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5471        usc_RTCmd( info, RTCmd_PurgeRxFifo );
5472    }
5473
5474} /* end of usc_process_rxoverrun_sync() */
5475
5476/* usc_stop_receiver()
5477 *
5478 * Disable USC receiver
5479 *
5480 * Arguments: info pointer to device instance data
5481 * Return Value: None
5482 */
5483static void usc_stop_receiver( struct mgsl_struct *info )
5484{
5485    if (debug_level >= DEBUG_LEVEL_ISR)
5486        printk("%s(%d):usc_stop_receiver(%s)\n",
5487             __FILE__,__LINE__, info->device_name );
5488             
5489    /* Disable receive DMA channel. */
5490    /* This also disables receive DMA channel interrupts */
5491    usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5492
5493    usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5494    usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5495    usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5496
5497    usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5498
5499    /* This empties the receive FIFO and loads the RCC with RCLR */
5500    usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5501    usc_RTCmd( info, RTCmd_PurgeRxFifo );
5502
5503    info->rx_enabled = false;
5504    info->rx_overflow = false;
5505    info->rx_rcc_underrun = false;
5506    
5507} /* end of stop_receiver() */
5508
5509/* usc_start_receiver()
5510 *
5511 * Enable the USC receiver
5512 *
5513 * Arguments: info pointer to device instance data
5514 * Return Value: None
5515 */
5516static void usc_start_receiver( struct mgsl_struct *info )
5517{
5518    u32 phys_addr;
5519    
5520    if (debug_level >= DEBUG_LEVEL_ISR)
5521        printk("%s(%d):usc_start_receiver(%s)\n",
5522             __FILE__,__LINE__, info->device_name );
5523
5524    mgsl_reset_rx_dma_buffers( info );
5525    usc_stop_receiver( info );
5526
5527    usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5528    usc_RTCmd( info, RTCmd_PurgeRxFifo );
5529
5530    if ( info->params.mode == MGSL_MODE_HDLC ||
5531        info->params.mode == MGSL_MODE_RAW ) {
5532        /* DMA mode Transfers */
5533        /* Program the DMA controller. */
5534        /* Enable the DMA controller end of buffer interrupt. */
5535
5536        /* program 16C32 with physical address of 1st DMA buffer entry */
5537        phys_addr = info->rx_buffer_list[0].phys_entry;
5538        usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5539        usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5540
5541        usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5542        usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5543        usc_EnableInterrupts( info, RECEIVE_STATUS );
5544
5545        /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5546        /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5547
5548        usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5549        usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5550        usc_DmaCmd( info, DmaCmd_InitRxChannel );
5551        if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5552            usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5553        else
5554            usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5555    } else {
5556        usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5557        usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5558        usc_EnableInterrupts(info, RECEIVE_DATA);
5559
5560        usc_RTCmd( info, RTCmd_PurgeRxFifo );
5561        usc_RCmd( info, RCmd_EnterHuntmode );
5562
5563        usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5564    }
5565
5566    usc_OutReg( info, CCSR, 0x1020 );
5567
5568    info->rx_enabled = true;
5569
5570} /* end of usc_start_receiver() */
5571
5572/* usc_start_transmitter()
5573 *
5574 * Enable the USC transmitter and send a transmit frame if
5575 * one is loaded in the DMA buffers.
5576 *
5577 * Arguments: info pointer to device instance data
5578 * Return Value: None
5579 */
5580static void usc_start_transmitter( struct mgsl_struct *info )
5581{
5582    u32 phys_addr;
5583    unsigned int FrameSize;
5584
5585    if (debug_level >= DEBUG_LEVEL_ISR)
5586        printk("%s(%d):usc_start_transmitter(%s)\n",
5587             __FILE__,__LINE__, info->device_name );
5588             
5589    if ( info->xmit_cnt ) {
5590
5591        /* If auto RTS enabled and RTS is inactive, then assert */
5592        /* RTS and set a flag indicating that the driver should */
5593        /* negate RTS when the transmission completes. */
5594
5595        info->drop_rts_on_tx_done = false;
5596
5597        if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5598            usc_get_serial_signals( info );
5599            if ( !(info->serial_signals & SerialSignal_RTS) ) {
5600                info->serial_signals |= SerialSignal_RTS;
5601                usc_set_serial_signals( info );
5602                info->drop_rts_on_tx_done = true;
5603            }
5604        }
5605
5606
5607        if ( info->params.mode == MGSL_MODE_ASYNC ) {
5608            if ( !info->tx_active ) {
5609                usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5610                usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5611                usc_EnableInterrupts(info, TRANSMIT_DATA);
5612                usc_load_txfifo(info);
5613            }
5614        } else {
5615            /* Disable transmit DMA controller while programming. */
5616            usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5617            
5618            /* Transmit DMA buffer is loaded, so program USC */
5619            /* to send the frame contained in the buffers. */
5620
5621            FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5622
5623            /* if operating in Raw sync mode, reset the rcc component
5624             * of the tx dma buffer entry, otherwise, the serial controller
5625             * will send a closing sync char after this count.
5626             */
5627                if ( info->params.mode == MGSL_MODE_RAW )
5628                info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5629
5630            /* Program the Transmit Character Length Register (TCLR) */
5631            /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5632            usc_OutReg( info, TCLR, (u16)FrameSize );
5633
5634            usc_RTCmd( info, RTCmd_PurgeTxFifo );
5635
5636            /* Program the address of the 1st DMA Buffer Entry in linked list */
5637            phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5638            usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5639            usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5640
5641            usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5642            usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5643            usc_EnableInterrupts( info, TRANSMIT_STATUS );
5644
5645            if ( info->params.mode == MGSL_MODE_RAW &&
5646                    info->num_tx_dma_buffers > 1 ) {
5647               /* When running external sync mode, attempt to 'stream' transmit */
5648               /* by filling tx dma buffers as they become available. To do this */
5649               /* we need to enable Tx DMA EOB Status interrupts : */
5650               /* */
5651               /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5652               /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5653
5654               usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5655               usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5656            }
5657
5658            /* Initialize Transmit DMA Channel */
5659            usc_DmaCmd( info, DmaCmd_InitTxChannel );
5660            
5661            usc_TCmd( info, TCmd_SendFrame );
5662            
5663            mod_timer(&info->tx_timer, jiffies +
5664                    msecs_to_jiffies(5000));
5665        }
5666        info->tx_active = true;
5667    }
5668
5669    if ( !info->tx_enabled ) {
5670        info->tx_enabled = true;
5671        if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5672            usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5673        else
5674            usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5675    }
5676
5677} /* end of usc_start_transmitter() */
5678
5679/* usc_stop_transmitter()
5680 *
5681 * Stops the transmitter and DMA
5682 *
5683 * Arguments: info pointer to device isntance data
5684 * Return Value: None
5685 */
5686static void usc_stop_transmitter( struct mgsl_struct *info )
5687{
5688    if (debug_level >= DEBUG_LEVEL_ISR)
5689        printk("%s(%d):usc_stop_transmitter(%s)\n",
5690             __FILE__,__LINE__, info->device_name );
5691             
5692    del_timer(&info->tx_timer);
5693             
5694    usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5695    usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5696    usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5697
5698    usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5699    usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5700    usc_RTCmd( info, RTCmd_PurgeTxFifo );
5701
5702    info->tx_enabled = false;
5703    info->tx_active = false;
5704
5705} /* end of usc_stop_transmitter() */
5706
5707/* usc_load_txfifo()
5708 *
5709 * Fill the transmit FIFO until the FIFO is full or
5710 * there is no more data to load.
5711 *
5712 * Arguments: info pointer to device extension (instance data)
5713 * Return Value: None
5714 */
5715static void usc_load_txfifo( struct mgsl_struct *info )
5716{
5717    int Fifocount;
5718    u8 TwoBytes[2];
5719    
5720    if ( !info->xmit_cnt && !info->x_char )
5721        return;
5722        
5723    /* Select transmit FIFO status readback in TICR */
5724    usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5725
5726    /* load the Transmit FIFO until FIFOs full or all data sent */
5727
5728    while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5729        /* there is more space in the transmit FIFO and */
5730        /* there is more data in transmit buffer */
5731
5732        if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5733             /* write a 16-bit word from transmit buffer to 16C32 */
5734                
5735            TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5736            info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5737            TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5738            info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5739            
5740            outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5741                
5742            info->xmit_cnt -= 2;
5743            info->icount.tx += 2;
5744        } else {
5745            /* only 1 byte left to transmit or 1 FIFO slot left */
5746            
5747            outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5748                info->io_base + CCAR );
5749            
5750            if (info->x_char) {
5751                /* transmit pending high priority char */
5752                outw( info->x_char,info->io_base + CCAR );
5753                info->x_char = 0;
5754            } else {
5755                outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5756                info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5757                info->xmit_cnt--;
5758            }
5759            info->icount.tx++;
5760        }
5761    }
5762
5763} /* end of usc_load_txfifo() */
5764
5765/* usc_reset()
5766 *
5767 * Reset the adapter to a known state and prepare it for further use.
5768 *
5769 * Arguments: info pointer to device instance data
5770 * Return Value: None
5771 */
5772static void usc_reset( struct mgsl_struct *info )
5773{
5774    if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5775        int i;
5776        u32 readval;
5777
5778        /* Set BIT30 of Misc Control Register */
5779        /* (Local Control Register 0x50) to force reset of USC. */
5780
5781        volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5782        u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5783
5784        info->misc_ctrl_value |= BIT30;
5785        *MiscCtrl = info->misc_ctrl_value;
5786
5787        /*
5788         * Force at least 170ns delay before clearing
5789         * reset bit. Each read from LCR takes at least
5790         * 30ns so 10 times for 300ns to be safe.
5791         */
5792        for(i=0;i<10;i++)
5793            readval = *MiscCtrl;
5794
5795        info->misc_ctrl_value &= ~BIT30;
5796        *MiscCtrl = info->misc_ctrl_value;
5797
5798        *LCR0BRDR = BUS_DESCRIPTOR(
5799            1, // Write Strobe Hold (0-3)
5800            2, // Write Strobe Delay (0-3)
5801            2, // Read Strobe Delay (0-3)
5802            0, // NWDD (Write data-data) (0-3)
5803            4, // NWAD (Write Addr-data)