2                       PCI Error Recovery
3                       ------------------
4                        February 2, 2006
6                 Current document maintainer:
7             Linas Vepstas <>
8          updated by Richard Lary <>
9       and Mike Mason <> on 27-Jul-2009
12Many PCI bus controllers are able to detect a variety of hardware
13PCI errors on the bus, such as parity errors on the data and address
14busses, as well as SERR and PERR errors. Some of the more advanced
15chipsets are able to deal with these errors; these include PCI-E chipsets,
16and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
17pSeries boxes. A typical action taken is to disconnect the affected device,
18halting all I/O to it. The goal of a disconnection is to avoid system
19corruption; for example, to halt system memory corruption due to DMA's
20to "wild" addresses. Typically, a reconnection mechanism is also
21offered, so that the affected PCI device(s) are reset and put back
22into working condition. The reset phase requires coordination
23between the affected device drivers and the PCI controller chip.
24This document describes a generic API for notifying device drivers
25of a bus disconnection, and then performing error recovery.
26This API is currently implemented in the 2.6.16 and later kernels.
28Reporting and recovery is performed in several steps. First, when
29a PCI hardware error has resulted in a bus disconnect, that event
30is reported as soon as possible to all affected device drivers,
31including multiple instances of a device driver on multi-function
32cards. This allows device drivers to avoid deadlocking in spinloops,
33waiting for some i/o-space register to change, when it never will.
34It also gives the drivers a chance to defer incoming I/O as
37Next, recovery is performed in several stages. Most of the complexity
38is forced by the need to handle multi-function devices, that is,
39devices that have multiple device drivers associated with them.
40In the first stage, each driver is allowed to indicate what type
41of reset it desires, the choices being a simple re-enabling of I/O
42or requesting a slot reset.
44If any driver requests a slot reset, that is what will be done.
46After a reset and/or a re-enabling of I/O, all drivers are
47again notified, so that they may then perform any device setup/config
48that may be required. After these have all completed, a final
49"resume normal operations" event is sent out.
51The biggest reason for choosing a kernel-based implementation rather
52than a user-space implementation was the need to deal with bus
53disconnects of PCI devices attached to storage media, and, in particular,
54disconnects from devices holding the root file system. If the root
55file system is disconnected, a user-space mechanism would have to go
56through a large number of contortions to complete recovery. Almost all
57of the current Linux file systems are not tolerant of disconnection
58from/reconnection to their underlying block device. By contrast,
59bus errors are easy to manage in the device driver. Indeed, most
60device drivers already handle very similar recovery procedures;
61for example, the SCSI-generic layer already provides significant
62mechanisms for dealing with SCSI bus errors and SCSI bus resets.
65Detailed Design
67Design and implementation details below, based on a chain of
68public email discussions with Ben Herrenschmidt, circa 5 April 2005.
70The error recovery API support is exposed to the driver in the form of
71a structure of function pointers pointed to by a new field in struct
72pci_driver. A driver that fails to provide the structure is "non-aware",
73and the actual recovery steps taken are platform dependent. The
74arch/powerpc implementation will simulate a PCI hotplug remove/add.
76This structure has the form:
77struct pci_error_handlers
79    int (*error_detected)(struct pci_dev *dev, enum pci_channel_state);
80    int (*mmio_enabled)(struct pci_dev *dev);
81    int (*link_reset)(struct pci_dev *dev);
82    int (*slot_reset)(struct pci_dev *dev);
83    void (*resume)(struct pci_dev *dev);
86The possible channel states are:
87enum pci_channel_state {
88    pci_channel_io_normal, /* I/O channel is in normal state */
89    pci_channel_io_frozen, /* I/O to channel is blocked */
90    pci_channel_io_perm_failure, /* PCI card is dead */
93Possible return values are:
94enum pci_ers_result {
95    PCI_ERS_RESULT_NONE, /* no result/none/not supported in device driver */
96    PCI_ERS_RESULT_CAN_RECOVER, /* Device driver can recover without slot reset */
97    PCI_ERS_RESULT_NEED_RESET, /* Device driver wants slot to be reset. */
98    PCI_ERS_RESULT_DISCONNECT, /* Device has completely failed, is unrecoverable */
99    PCI_ERS_RESULT_RECOVERED, /* Device driver is fully recovered and operational */
102A driver does not have to implement all of these callbacks; however,
103if it implements any, it must implement error_detected(). If a callback
104is not implemented, the corresponding feature is considered unsupported.
105For example, if mmio_enabled() and resume() aren't there, then it
106is assumed that the driver is not doing any direct recovery and requires
107a slot reset. If link_reset() is not implemented, the card is assumed to
108not care about link resets. Typically a driver will want to know about
109a slot_reset().
111The actual steps taken by a platform to recover from a PCI error
112event will be platform-dependent, but will follow the general
113sequence described below.
115STEP 0: Error Event
117A PCI bus error is detected by the PCI hardware. On powerpc, the slot
118is isolated, in that all I/O is blocked: all reads return 0xffffffff,
119all writes are ignored.
122STEP 1: Notification
124Platform calls the error_detected() callback on every instance of
125every driver affected by the error.
127At this point, the device might not be accessible anymore, depending on
128the platform (the slot will be isolated on powerpc). The driver may
129already have "noticed" the error because of a failing I/O, but this
130is the proper "synchronization point", that is, it gives the driver
131a chance to cleanup, waiting for pending stuff (timers, whatever, etc...)
132to complete; it can take semaphores, schedule, etc... everything but
133touch the device. Within this function and after it returns, the driver
134shouldn't do any new IOs. Called in task context. This is sort of a
135"quiesce" point. See note about interrupts at the end of this doc.
137All drivers participating in this system must implement this call.
138The driver must return one of the following result codes:
140          Driver returns this if it thinks it might be able to recover
141          the HW by just banging IOs or if it wants to be given
142          a chance to extract some diagnostic information (see
143          mmio_enable, below).
145          Driver returns this if it can't recover without a
146          slot reset.
148          Driver returns this if it doesn't want to recover at all.
150The next step taken will depend on the result codes returned by the
153If all drivers on the segment/slot return PCI_ERS_RESULT_CAN_RECOVER,
154then the platform should re-enable IOs on the slot (or do nothing in
155particular, if the platform doesn't isolate slots), and recovery
156proceeds to STEP 2 (MMIO Enable).
158If any driver requested a slot reset (by returning PCI_ERS_RESULT_NEED_RESET),
159then recovery proceeds to STEP 4 (Slot Reset).
161If the platform is unable to recover the slot, the next step
162is STEP 6 (Permanent Failure).
164>>> The current powerpc implementation assumes that a device driver will
165>>> *not* schedule or semaphore in this routine; the current powerpc
166>>> implementation uses one kernel thread to notify all devices;
167>>> thus, if one device sleeps/schedules, all devices are affected.
168>>> Doing better requires complex multi-threaded logic in the error
169>>> recovery implementation (e.g. waiting for all notification threads
170>>> to "join" before proceeding with recovery.) This seems excessively
171>>> complex and not worth implementing.
173>>> The current powerpc implementation doesn't much care if the device
174>>> attempts I/O at this point, or not. I/O's will fail, returning
175>>> a value of 0xff on read, and writes will be dropped. If more than
176>>> EEH_MAX_FAILS I/O's are attempted to a frozen adapter, EEH
177>>> assumes that the device driver has gone into an infinite loop
178>>> and prints an error to syslog. A reboot is then required to
179>>> get the device working again.
181STEP 2: MMIO Enabled
183The platform re-enables MMIO to the device (but typically not the
184DMA), and then calls the mmio_enabled() callback on all affected
185device drivers.
187This is the "early recovery" call. IOs are allowed again, but DMA is
188not, with some restrictions. This is NOT a callback for the driver to
189start operations again, only to peek/poke at the device, extract diagnostic
190information, if any, and eventually do things like trigger a device local
191reset or some such, but not restart operations. This callback is made if
192all drivers on a segment agree that they can try to recover and if no automatic
193link reset was performed by the HW. If the platform can't just re-enable IOs
194without a slot reset or a link reset, it will not call this callback, and
195instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)
197>>> The following is proposed; no platform implements this yet:
198>>> Proposal: All I/O's should be done _synchronously_ from within
199>>> this callback, errors triggered by them will be returned via
200>>> the normal pci_check_whatever() API, no new error_detected()
201>>> callback will be issued due to an error happening here. However,
202>>> such an error might cause IOs to be re-blocked for the whole
203>>> segment, and thus invalidate the recovery that other devices
204>>> on the same segment might have done, forcing the whole segment
205>>> into one of the next states, that is, link reset or slot reset.
207The driver should return one of the following result codes:
209          Driver returns this if it thinks the device is fully
210          functional and thinks it is ready to start
211          normal driver operations again. There is no
212          guarantee that the driver will actually be
213          allowed to proceed, as another driver on the
214          same segment might have failed and thus triggered a
215          slot reset on platforms that support it.
218          Driver returns this if it thinks the device is not
219          recoverable in its current state and it needs a slot
220          reset to proceed.
223          Same as above. Total failure, no recovery even after
224          reset driver dead. (To be defined more precisely)
226The next step taken depends on the results returned by the drivers.
227If all drivers returned PCI_ERS_RESULT_RECOVERED, then the platform
228proceeds to either STEP3 (Link Reset) or to STEP 5 (Resume Operations).
230If any driver returned PCI_ERS_RESULT_NEED_RESET, then the platform
231proceeds to STEP 4 (Slot Reset)
233STEP 3: Link Reset
235The platform resets the link, and then calls the link_reset() callback
236on all affected device drivers. This is a PCI-Express specific state
237and is done whenever a non-fatal error has been detected that can be
238"solved" by resetting the link. This call informs the driver of the
239reset and the driver should check to see if the device appears to be
240in working condition.
242The driver is not supposed to restart normal driver I/O operations
243at this point. It should limit itself to "probing" the device to
244check its recoverability status. If all is right, then the platform
245will call resume() once all drivers have ack'd link_reset().
247    Result codes:
248        (identical to STEP 3 (MMIO Enabled)
250The platform then proceeds to either STEP 4 (Slot Reset) or STEP 5
251(Resume Operations).
253>>> The current powerpc implementation does not implement this callback.
255STEP 4: Slot Reset
258In response to a return value of PCI_ERS_RESULT_NEED_RESET, the
259the platform will peform a slot reset on the requesting PCI device(s).
260The actual steps taken by a platform to perform a slot reset
261will be platform-dependent. Upon completion of slot reset, the
262platform will call the device slot_reset() callback.
264Powerpc platforms implement two levels of slot reset:
265soft reset(default) and fundamental(optional) reset.
267Powerpc soft reset consists of asserting the adapter #RST line and then
268restoring the PCI BAR's and PCI configuration header to a state
269that is equivalent to what it would be after a fresh system
270power-on followed by power-on BIOS/system firmware initialization.
271Soft reset is also known as hot-reset.
273Powerpc fundamental reset is supported by PCI Express cards only
274and results in device's state machines, hardware logic, port states and
275configuration registers to initialize to their default conditions.
277For most PCI devices, a soft reset will be sufficient for recovery.
278Optional fundamental reset is provided to support a limited number
279of PCI Express PCI devices for which a soft reset is not sufficient
280for recovery.
282If the platform supports PCI hotplug, then the reset might be
283performed by toggling the slot electrical power off/on.
285It is important for the platform to restore the PCI config space
286to the "fresh poweron" state, rather than the "last state". After
287a slot reset, the device driver will almost always use its standard
288device initialization routines, and an unusual config space setup
289may result in hung devices, kernel panics, or silent data corruption.
291This call gives drivers the chance to re-initialize the hardware
292(re-download firmware, etc.). At this point, the driver may assume
293that the card is in a fresh state and is fully functional. The slot
294is unfrozen and the driver has full access to PCI config space,
295memory mapped I/O space and DMA. Interrupts (Legacy, MSI, or MSI-X)
296will also be available.
298Drivers should not restart normal I/O processing operations
299at this point. If all device drivers report success on this
300callback, the platform will call resume() to complete the sequence,
301and let the driver restart normal I/O processing.
303A driver can still return a critical failure for this function if
304it can't get the device operational after reset. If the platform
305previously tried a soft reset, it might now try a hard reset (power
306cycle) and then call slot_reset() again. It the device still can't
307be recovered, there is nothing more that can be done; the platform
308will typically report a "permanent failure" in such a case. The
309device will be considered "dead" in this case.
311Drivers for multi-function cards will need to coordinate among
312themselves as to which driver instance will perform any "one-shot"
313or global device initialization. For example, the Symbios sym53cxx2
314driver performs device init only from PCI function 0:
316+ if (PCI_FUNC(pdev->devfn) == 0)
317+ sym_reset_scsi_bus(np, 0);
319    Result codes:
321        Same as above.
323Drivers for PCI Express cards that require a fundamental reset must
324set the needs_freset bit in the pci_dev structure in their probe function.
325For example, the QLogic qla2xxx driver sets the needs_freset bit for certain
326PCI card types:
328+ /* Set EEH reset type to fundamental if required by hba */
329+ if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha))
330+ pdev->needs_freset = 1;
333Platform proceeds either to STEP 5 (Resume Operations) or STEP 6 (Permanent
336>>> The current powerpc implementation does not try a power-cycle
337>>> reset if the driver returned PCI_ERS_RESULT_DISCONNECT.
338>>> However, it probably should.
341STEP 5: Resume Operations
343The platform will call the resume() callback on all affected device
344drivers if all drivers on the segment have returned
345PCI_ERS_RESULT_RECOVERED from one of the 3 previous callbacks.
346The goal of this callback is to tell the driver to restart activity,
347that everything is back and running. This callback does not return
348a result code.
350At this point, if a new error happens, the platform will restart
351a new error recovery sequence.
353STEP 6: Permanent Failure
355A "permanent failure" has occurred, and the platform cannot recover
356the device. The platform will call error_detected() with a
357pci_channel_state value of pci_channel_io_perm_failure.
359The device driver should, at this point, assume the worst. It should
360cancel all pending I/O, refuse all new I/O, returning -EIO to
361higher layers. The device driver should then clean up all of its
362memory and remove itself from kernel operations, much as it would
363during system shutdown.
365The platform will typically notify the system operator of the
366permanent failure in some way. If the device is hotplug-capable,
367the operator will probably want to remove and replace the device.
368Note, however, not all failures are truly "permanent". Some are
369caused by over-heating, some by a poorly seated card. Many
370PCI error events are caused by software bugs, e.g. DMA's to
371wild addresses or bogus split transactions due to programming
372errors. See the discussion in powerpc/eeh-pci-error-recovery.txt
373for additional detail on real-life experience of the causes of
374software errors.
377Conclusion; General Remarks
379The way the callbacks are called is platform policy. A platform with
380no slot reset capability may want to just "ignore" drivers that can't
381recover (disconnect them) and try to let other cards on the same segment
382recover. Keep in mind that in most real life cases, though, there will
383be only one driver per segment.
385Now, a note about interrupts. If you get an interrupt and your
386device is dead or has been isolated, there is a problem :)
387The current policy is to turn this into a platform policy.
388That is, the recovery API only requires that:
390 - There is no guarantee that interrupt delivery can proceed from any
391device on the segment starting from the error detection and until the
392slot_reset callback is called, at which point interrupts are expected
393to be fully operational.
395 - There is no guarantee that interrupt delivery is stopped, that is,
396a driver that gets an interrupt after detecting an error, or that detects
397an error within the interrupt handler such that it prevents proper
398ack'ing of the interrupt (and thus removal of the source) should just
399return IRQ_NOTHANDLED. It's up to the platform to deal with that
400condition, typically by masking the IRQ source during the duration of
401the error handling. It is expected that the platform "knows" which
402interrupts are routed to error-management capable slots and can deal
403with temporarily disabling that IRQ number during error processing (this
404isn't terribly complex). That means some IRQ latency for other devices
405sharing the interrupt, but there is simply no other way. High end
406platforms aren't supposed to share interrupts between many devices
407anyway :)
409>>> Implementation details for the powerpc platform are discussed in
410>>> the file Documentation/powerpc/eeh-pci-error-recovery.txt
412>>> As of this writing, there is a growing list of device drivers with
413>>> patches implementing error recovery. Not all of these patches are in
414>>> mainline yet. These may be used as "examples":
416>>> drivers/scsi/ipr
417>>> drivers/scsi/sym53c8xx_2
418>>> drivers/scsi/qla2xxx
419>>> drivers/scsi/lpfc
420>>> drivers/next/bnx2.c
421>>> drivers/next/e100.c
422>>> drivers/net/e1000
423>>> drivers/net/e1000e
424>>> drivers/net/ixgb
425>>> drivers/net/ixgbe
426>>> drivers/net/cxgb3
427>>> drivers/net/s2io.c
428>>> drivers/net/qlge
430The End

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