Root/Documentation/PCI/pcieaer-howto.txt

1   The PCI Express Advanced Error Reporting Driver Guide HOWTO
2        T. Long Nguyen <tom.l.nguyen@intel.com>
3        Yanmin Zhang <yanmin.zhang@intel.com>
4                07/29/2006
5
6
71. Overview
8
91.1 About this guide
10
11This guide describes the basics of the PCI Express Advanced Error
12Reporting (AER) driver and provides information on how to use it, as
13well as how to enable the drivers of endpoint devices to conform with
14PCI Express AER driver.
15
161.2 Copyright (C) Intel Corporation 2006.
17
181.3 What is the PCI Express AER Driver?
19
20PCI Express error signaling can occur on the PCI Express link itself
21or on behalf of transactions initiated on the link. PCI Express
22defines two error reporting paradigms: the baseline capability and
23the Advanced Error Reporting capability. The baseline capability is
24required of all PCI Express components providing a minimum defined
25set of error reporting requirements. Advanced Error Reporting
26capability is implemented with a PCI Express advanced error reporting
27extended capability structure providing more robust error reporting.
28
29The PCI Express AER driver provides the infrastructure to support PCI
30Express Advanced Error Reporting capability. The PCI Express AER
31driver provides three basic functions:
32
33- Gathers the comprehensive error information if errors occurred.
34- Reports error to the users.
35- Performs error recovery actions.
36
37AER driver only attaches root ports which support PCI-Express AER
38capability.
39
40
412. User Guide
42
432.1 Include the PCI Express AER Root Driver into the Linux Kernel
44
45The PCI Express AER Root driver is a Root Port service driver attached
46to the PCI Express Port Bus driver. If a user wants to use it, the driver
47has to be compiled. Option CONFIG_PCIEAER supports this capability. It
48depends on CONFIG_PCIEPORTBUS, so pls. set CONFIG_PCIEPORTBUS=y and
49CONFIG_PCIEAER = y.
50
512.2 Load PCI Express AER Root Driver
52There is a case where a system has AER support in BIOS. Enabling the AER
53Root driver and having AER support in BIOS may result unpredictable
54behavior. To avoid this conflict, a successful load of the AER Root driver
55requires ACPI _OSC support in the BIOS to allow the AER Root driver to
56request for native control of AER. See the PCI FW 3.0 Specification for
57details regarding OSC usage. Currently, lots of firmwares don't provide
58_OSC support while they use PCI Express. To support such firmwares,
59forceload, a parameter of type bool, could enable AER to continue to
60be initiated although firmwares have no _OSC support. To enable the
61walkaround, pls. add aerdriver.forceload=y to kernel boot parameter line
62when booting kernel. Note that forceload=n by default.
63
64nosourceid, another parameter of type bool, can be used when broken
65hardware (mostly chipsets) has root ports that cannot obtain the reporting
66source ID. nosourceid=n by default.
67
682.3 AER error output
69When a PCI-E AER error is captured, an error message will be outputed to
70console. If it's a correctable error, it is outputed as a warning.
71Otherwise, it is printed as an error. So users could choose different
72log level to filter out correctable error messages.
73
74Below shows an example:
750000:50:00.0: PCIe Bus Error: severity=Uncorrected (Fatal), type=Transaction Layer, id=0500(Requester ID)
760000:50:00.0: device [8086:0329] error status/mask=00100000/00000000
770000:50:00.0: [20] Unsupported Request (First)
780000:50:00.0: TLP Header: 04000001 00200a03 05010000 00050100
79
80In the example, 'Requester ID' means the ID of the device who sends
81the error message to root port. Pls. refer to pci express specs for
82other fields.
83
84
853. Developer Guide
86
87To enable AER aware support requires a software driver to configure
88the AER capability structure within its device and to provide callbacks.
89
90To support AER better, developers need understand how AER does work
91firstly.
92
93PCI Express errors are classified into two types: correctable errors
94and uncorrectable errors. This classification is based on the impacts
95of those errors, which may result in degraded performance or function
96failure.
97
98Correctable errors pose no impacts on the functionality of the
99interface. The PCI Express protocol can recover without any software
100intervention or any loss of data. These errors are detected and
101corrected by hardware. Unlike correctable errors, uncorrectable
102errors impact functionality of the interface. Uncorrectable errors
103can cause a particular transaction or a particular PCI Express link
104to be unreliable. Depending on those error conditions, uncorrectable
105errors are further classified into non-fatal errors and fatal errors.
106Non-fatal errors cause the particular transaction to be unreliable,
107but the PCI Express link itself is fully functional. Fatal errors, on
108the other hand, cause the link to be unreliable.
109
110When AER is enabled, a PCI Express device will automatically send an
111error message to the PCIe root port above it when the device captures
112an error. The Root Port, upon receiving an error reporting message,
113internally processes and logs the error message in its PCI Express
114capability structure. Error information being logged includes storing
115the error reporting agent's requestor ID into the Error Source
116Identification Registers and setting the error bits of the Root Error
117Status Register accordingly. If AER error reporting is enabled in Root
118Error Command Register, the Root Port generates an interrupt if an
119error is detected.
120
121Note that the errors as described above are related to the PCI Express
122hierarchy and links. These errors do not include any device specific
123errors because device specific errors will still get sent directly to
124the device driver.
125
1263.1 Configure the AER capability structure
127
128AER aware drivers of PCI Express component need change the device
129control registers to enable AER. They also could change AER registers,
130including mask and severity registers. Helper function
131pci_enable_pcie_error_reporting could be used to enable AER. See
132section 3.3.
133
1343.2. Provide callbacks
135
1363.2.1 callback reset_link to reset pci express link
137
138This callback is used to reset the pci express physical link when a
139fatal error happens. The root port aer service driver provides a
140default reset_link function, but different upstream ports might
141have different specifications to reset pci express link, so all
142upstream ports should provide their own reset_link functions.
143
144In struct pcie_port_service_driver, a new pointer, reset_link, is
145added.
146
147pci_ers_result_t (*reset_link) (struct pci_dev *dev);
148
149Section 3.2.2.2 provides more detailed info on when to call
150reset_link.
151
1523.2.2 PCI error-recovery callbacks
153
154The PCI Express AER Root driver uses error callbacks to coordinate
155with downstream device drivers associated with a hierarchy in question
156when performing error recovery actions.
157
158Data struct pci_driver has a pointer, err_handler, to point to
159pci_error_handlers who consists of a couple of callback function
160pointers. AER driver follows the rules defined in
161pci-error-recovery.txt except pci express specific parts (e.g.
162reset_link). Pls. refer to pci-error-recovery.txt for detailed
163definitions of the callbacks.
164
165Below sections specify when to call the error callback functions.
166
1673.2.2.1 Correctable errors
168
169Correctable errors pose no impacts on the functionality of
170the interface. The PCI Express protocol can recover without any
171software intervention or any loss of data. These errors do not
172require any recovery actions. The AER driver clears the device's
173correctable error status register accordingly and logs these errors.
174
1753.2.2.2 Non-correctable (non-fatal and fatal) errors
176
177If an error message indicates a non-fatal error, performing link reset
178at upstream is not required. The AER driver calls error_detected(dev,
179pci_channel_io_normal) to all drivers associated within a hierarchy in
180question. for example,
181EndPoint<==>DownstreamPort B<==>UpstreamPort A<==>RootPort.
182If Upstream port A captures an AER error, the hierarchy consists of
183Downstream port B and EndPoint.
184
185A driver may return PCI_ERS_RESULT_CAN_RECOVER,
186PCI_ERS_RESULT_DISCONNECT, or PCI_ERS_RESULT_NEED_RESET, depending on
187whether it can recover or the AER driver calls mmio_enabled as next.
188
189If an error message indicates a fatal error, kernel will broadcast
190error_detected(dev, pci_channel_io_frozen) to all drivers within
191a hierarchy in question. Then, performing link reset at upstream is
192necessary. As different kinds of devices might use different approaches
193to reset link, AER port service driver is required to provide the
194function to reset link. Firstly, kernel looks for if the upstream
195component has an aer driver. If it has, kernel uses the reset_link
196callback of the aer driver. If the upstream component has no aer driver
197and the port is downstream port, we will perform a hot reset as the
198default by setting the Secondary Bus Reset bit of the Bridge Control
199register associated with the downstream port. As for upstream ports,
200they should provide their own aer service drivers with reset_link
201function. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and
202reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes
203to mmio_enabled.
204
2053.3 helper functions
206
2073.3.1 int pci_enable_pcie_error_reporting(struct pci_dev *dev);
208pci_enable_pcie_error_reporting enables the device to send error
209messages to root port when an error is detected. Note that devices
210don't enable the error reporting by default, so device drivers need
211call this function to enable it.
212
2133.3.2 int pci_disable_pcie_error_reporting(struct pci_dev *dev);
214pci_disable_pcie_error_reporting disables the device to send error
215messages to root port when an error is detected.
216
2173.3.3 int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
218pci_cleanup_aer_uncorrect_error_status cleanups the uncorrectable
219error status register.
220
2213.4 Frequent Asked Questions
222
223Q: What happens if a PCI Express device driver does not provide an
224error recovery handler (pci_driver->err_handler is equal to NULL)?
225
226A: The devices attached with the driver won't be recovered. If the
227error is fatal, kernel will print out warning messages. Please refer
228to section 3 for more information.
229
230Q: What happens if an upstream port service driver does not provide
231callback reset_link?
232
233A: Fatal error recovery will fail if the errors are reported by the
234upstream ports who are attached by the service driver.
235
236Q: How does this infrastructure deal with driver that is not PCI
237Express aware?
238
239A: This infrastructure calls the error callback functions of the
240driver when an error happens. But if the driver is not aware of
241PCI Express, the device might not report its own errors to root
242port.
243
244Q: What modifications will that driver need to make it compatible
245with the PCI Express AER Root driver?
246
247A: It could call the helper functions to enable AER in devices and
248cleanup uncorrectable status register. Pls. refer to section 3.3.
249
250
2514. Software error injection
252
253Debugging PCIe AER error recovery code is quite difficult because it
254is hard to trigger real hardware errors. Software based error
255injection can be used to fake various kinds of PCIe errors.
256
257First you should enable PCIe AER software error injection in kernel
258configuration, that is, following item should be in your .config.
259
260CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m
261
262After reboot with new kernel or insert the module, a device file named
263/dev/aer_inject should be created.
264
265Then, you need a user space tool named aer-inject, which can be gotten
266from:
267    http://www.kernel.org/pub/linux/utils/pci/aer-inject/
268
269More information about aer-inject can be found in the document comes
270with its source code.
271

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