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1 | /* |
2 | * core routines for the asynchronous memory transfer/transform api |
3 | * |
4 | * Copyright © 2006, Intel Corporation. |
5 | * |
6 | * Dan Williams <dan.j.williams@intel.com> |
7 | * |
8 | * with architecture considerations by: |
9 | * Neil Brown <neilb@suse.de> |
10 | * Jeff Garzik <jeff@garzik.org> |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify it |
13 | * under the terms and conditions of the GNU General Public License, |
14 | * version 2, as published by the Free Software Foundation. |
15 | * |
16 | * This program is distributed in the hope it will be useful, but WITHOUT |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
19 | * more details. |
20 | * |
21 | * You should have received a copy of the GNU General Public License along with |
22 | * this program; if not, write to the Free Software Foundation, Inc., |
23 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
24 | * |
25 | */ |
26 | #include <linux/rculist.h> |
27 | #include <linux/kernel.h> |
28 | #include <linux/async_tx.h> |
29 | |
30 | #ifdef CONFIG_DMA_ENGINE |
31 | static int __init async_tx_init(void) |
32 | { |
33 | async_dmaengine_get(); |
34 | |
35 | printk(KERN_INFO "async_tx: api initialized (async)\n"); |
36 | |
37 | return 0; |
38 | } |
39 | |
40 | static void __exit async_tx_exit(void) |
41 | { |
42 | async_dmaengine_put(); |
43 | } |
44 | |
45 | module_init(async_tx_init); |
46 | module_exit(async_tx_exit); |
47 | |
48 | /** |
49 | * __async_tx_find_channel - find a channel to carry out the operation or let |
50 | * the transaction execute synchronously |
51 | * @submit: transaction dependency and submission modifiers |
52 | * @tx_type: transaction type |
53 | */ |
54 | struct dma_chan * |
55 | __async_tx_find_channel(struct async_submit_ctl *submit, |
56 | enum dma_transaction_type tx_type) |
57 | { |
58 | struct dma_async_tx_descriptor *depend_tx = submit->depend_tx; |
59 | |
60 | /* see if we can keep the chain on one channel */ |
61 | if (depend_tx && |
62 | dma_has_cap(tx_type, depend_tx->chan->device->cap_mask)) |
63 | return depend_tx->chan; |
64 | return async_dma_find_channel(tx_type); |
65 | } |
66 | EXPORT_SYMBOL_GPL(__async_tx_find_channel); |
67 | #endif |
68 | |
69 | |
70 | /** |
71 | * async_tx_channel_switch - queue an interrupt descriptor with a dependency |
72 | * pre-attached. |
73 | * @depend_tx: the operation that must finish before the new operation runs |
74 | * @tx: the new operation |
75 | */ |
76 | static void |
77 | async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx, |
78 | struct dma_async_tx_descriptor *tx) |
79 | { |
80 | struct dma_chan *chan = depend_tx->chan; |
81 | struct dma_device *device = chan->device; |
82 | struct dma_async_tx_descriptor *intr_tx = (void *) ~0; |
83 | |
84 | #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH |
85 | BUG(); |
86 | #endif |
87 | |
88 | /* first check to see if we can still append to depend_tx */ |
89 | spin_lock_bh(&depend_tx->lock); |
90 | if (depend_tx->parent && depend_tx->chan == tx->chan) { |
91 | tx->parent = depend_tx; |
92 | depend_tx->next = tx; |
93 | intr_tx = NULL; |
94 | } |
95 | spin_unlock_bh(&depend_tx->lock); |
96 | |
97 | /* attached dependency, flush the parent channel */ |
98 | if (!intr_tx) { |
99 | device->device_issue_pending(chan); |
100 | return; |
101 | } |
102 | |
103 | /* see if we can schedule an interrupt |
104 | * otherwise poll for completion |
105 | */ |
106 | if (dma_has_cap(DMA_INTERRUPT, device->cap_mask)) |
107 | intr_tx = device->device_prep_dma_interrupt(chan, 0); |
108 | else |
109 | intr_tx = NULL; |
110 | |
111 | if (intr_tx) { |
112 | intr_tx->callback = NULL; |
113 | intr_tx->callback_param = NULL; |
114 | tx->parent = intr_tx; |
115 | /* safe to set ->next outside the lock since we know we are |
116 | * not submitted yet |
117 | */ |
118 | intr_tx->next = tx; |
119 | |
120 | /* check if we need to append */ |
121 | spin_lock_bh(&depend_tx->lock); |
122 | if (depend_tx->parent) { |
123 | intr_tx->parent = depend_tx; |
124 | depend_tx->next = intr_tx; |
125 | async_tx_ack(intr_tx); |
126 | intr_tx = NULL; |
127 | } |
128 | spin_unlock_bh(&depend_tx->lock); |
129 | |
130 | if (intr_tx) { |
131 | intr_tx->parent = NULL; |
132 | intr_tx->tx_submit(intr_tx); |
133 | async_tx_ack(intr_tx); |
134 | } |
135 | device->device_issue_pending(chan); |
136 | } else { |
137 | if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR) |
138 | panic("%s: DMA_ERROR waiting for depend_tx\n", |
139 | __func__); |
140 | tx->tx_submit(tx); |
141 | } |
142 | } |
143 | |
144 | |
145 | /** |
146 | * submit_disposition - flags for routing an incoming operation |
147 | * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock |
148 | * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch |
149 | * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly |
150 | * |
151 | * while holding depend_tx->lock we must avoid submitting new operations |
152 | * to prevent a circular locking dependency with drivers that already |
153 | * hold a channel lock when calling async_tx_run_dependencies. |
154 | */ |
155 | enum submit_disposition { |
156 | ASYNC_TX_SUBMITTED, |
157 | ASYNC_TX_CHANNEL_SWITCH, |
158 | ASYNC_TX_DIRECT_SUBMIT, |
159 | }; |
160 | |
161 | void |
162 | async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, |
163 | struct async_submit_ctl *submit) |
164 | { |
165 | struct dma_async_tx_descriptor *depend_tx = submit->depend_tx; |
166 | |
167 | tx->callback = submit->cb_fn; |
168 | tx->callback_param = submit->cb_param; |
169 | |
170 | if (depend_tx) { |
171 | enum submit_disposition s; |
172 | |
173 | /* sanity check the dependency chain: |
174 | * 1/ if ack is already set then we cannot be sure |
175 | * we are referring to the correct operation |
176 | * 2/ dependencies are 1:1 i.e. two transactions can |
177 | * not depend on the same parent |
178 | */ |
179 | BUG_ON(async_tx_test_ack(depend_tx) || depend_tx->next || |
180 | tx->parent); |
181 | |
182 | /* the lock prevents async_tx_run_dependencies from missing |
183 | * the setting of ->next when ->parent != NULL |
184 | */ |
185 | spin_lock_bh(&depend_tx->lock); |
186 | if (depend_tx->parent) { |
187 | /* we have a parent so we can not submit directly |
188 | * if we are staying on the same channel: append |
189 | * else: channel switch |
190 | */ |
191 | if (depend_tx->chan == chan) { |
192 | tx->parent = depend_tx; |
193 | depend_tx->next = tx; |
194 | s = ASYNC_TX_SUBMITTED; |
195 | } else |
196 | s = ASYNC_TX_CHANNEL_SWITCH; |
197 | } else { |
198 | /* we do not have a parent so we may be able to submit |
199 | * directly if we are staying on the same channel |
200 | */ |
201 | if (depend_tx->chan == chan) |
202 | s = ASYNC_TX_DIRECT_SUBMIT; |
203 | else |
204 | s = ASYNC_TX_CHANNEL_SWITCH; |
205 | } |
206 | spin_unlock_bh(&depend_tx->lock); |
207 | |
208 | switch (s) { |
209 | case ASYNC_TX_SUBMITTED: |
210 | break; |
211 | case ASYNC_TX_CHANNEL_SWITCH: |
212 | async_tx_channel_switch(depend_tx, tx); |
213 | break; |
214 | case ASYNC_TX_DIRECT_SUBMIT: |
215 | tx->parent = NULL; |
216 | tx->tx_submit(tx); |
217 | break; |
218 | } |
219 | } else { |
220 | tx->parent = NULL; |
221 | tx->tx_submit(tx); |
222 | } |
223 | |
224 | if (submit->flags & ASYNC_TX_ACK) |
225 | async_tx_ack(tx); |
226 | |
227 | if (depend_tx) |
228 | async_tx_ack(depend_tx); |
229 | } |
230 | EXPORT_SYMBOL_GPL(async_tx_submit); |
231 | |
232 | /** |
233 | * async_trigger_callback - schedules the callback function to be run |
234 | * @submit: submission and completion parameters |
235 | * |
236 | * honored flags: ASYNC_TX_ACK |
237 | * |
238 | * The callback is run after any dependent operations have completed. |
239 | */ |
240 | struct dma_async_tx_descriptor * |
241 | async_trigger_callback(struct async_submit_ctl *submit) |
242 | { |
243 | struct dma_chan *chan; |
244 | struct dma_device *device; |
245 | struct dma_async_tx_descriptor *tx; |
246 | struct dma_async_tx_descriptor *depend_tx = submit->depend_tx; |
247 | |
248 | if (depend_tx) { |
249 | chan = depend_tx->chan; |
250 | device = chan->device; |
251 | |
252 | /* see if we can schedule an interrupt |
253 | * otherwise poll for completion |
254 | */ |
255 | if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask)) |
256 | device = NULL; |
257 | |
258 | tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL; |
259 | } else |
260 | tx = NULL; |
261 | |
262 | if (tx) { |
263 | pr_debug("%s: (async)\n", __func__); |
264 | |
265 | async_tx_submit(chan, tx, submit); |
266 | } else { |
267 | pr_debug("%s: (sync)\n", __func__); |
268 | |
269 | /* wait for any prerequisite operations */ |
270 | async_tx_quiesce(&submit->depend_tx); |
271 | |
272 | async_tx_sync_epilog(submit); |
273 | } |
274 | |
275 | return tx; |
276 | } |
277 | EXPORT_SYMBOL_GPL(async_trigger_callback); |
278 | |
279 | /** |
280 | * async_tx_quiesce - ensure tx is complete and freeable upon return |
281 | * @tx - transaction to quiesce |
282 | */ |
283 | void async_tx_quiesce(struct dma_async_tx_descriptor **tx) |
284 | { |
285 | if (*tx) { |
286 | /* if ack is already set then we cannot be sure |
287 | * we are referring to the correct operation |
288 | */ |
289 | BUG_ON(async_tx_test_ack(*tx)); |
290 | if (dma_wait_for_async_tx(*tx) == DMA_ERROR) |
291 | panic("DMA_ERROR waiting for transaction\n"); |
292 | async_tx_ack(*tx); |
293 | *tx = NULL; |
294 | } |
295 | } |
296 | EXPORT_SYMBOL_GPL(async_tx_quiesce); |
297 | |
298 | MODULE_AUTHOR("Intel Corporation"); |
299 | MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API"); |
300 | MODULE_LICENSE("GPL"); |
301 |
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