Root/drivers/dma/Kconfig

1#
2# DMA engine configuration
3#
4
5menuconfig DMADEVICES
6    bool "DMA Engine support"
7    depends on HAS_DMA
8    help
9      DMA engines can do asynchronous data transfers without
10      involving the host CPU. Currently, this framework can be
11      used to offload memory copies in the network stack and
12      RAID operations in the MD driver. This menu only presents
13      DMA Device drivers supported by the configured arch, it may
14      be empty in some cases.
15
16if DMADEVICES
17
18comment "DMA Devices"
19
20config ASYNC_TX_DISABLE_CHANNEL_SWITCH
21    bool
22
23config INTEL_IOATDMA
24    tristate "Intel I/OAT DMA support"
25    depends on PCI && X86
26    select DMA_ENGINE
27    select DCA
28    select ASYNC_TX_DISABLE_CHANNEL_SWITCH
29    select ASYNC_TX_DISABLE_PQ_VAL_DMA
30    select ASYNC_TX_DISABLE_XOR_VAL_DMA
31    help
32      Enable support for the Intel(R) I/OAT DMA engine present
33      in recent Intel Xeon chipsets.
34
35      Say Y here if you have such a chipset.
36
37      If unsure, say N.
38
39config INTEL_IOP_ADMA
40    tristate "Intel IOP ADMA support"
41    depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
42    select DMA_ENGINE
43    help
44      Enable support for the Intel(R) IOP Series RAID engines.
45
46config DW_DMAC
47    tristate "Synopsys DesignWare AHB DMA support"
48    depends on AVR32
49    select DMA_ENGINE
50    default y if CPU_AT32AP7000
51    help
52      Support the Synopsys DesignWare AHB DMA controller. This
53      can be integrated in chips such as the Atmel AT32ap7000.
54
55config AT_HDMAC
56    tristate "Atmel AHB DMA support"
57    depends on ARCH_AT91SAM9RL
58    select DMA_ENGINE
59    help
60      Support the Atmel AHB DMA controller. This can be integrated in
61      chips such as the Atmel AT91SAM9RL.
62
63config FSL_DMA
64    tristate "Freescale Elo and Elo Plus DMA support"
65    depends on FSL_SOC
66    select DMA_ENGINE
67    ---help---
68      Enable support for the Freescale Elo and Elo Plus DMA controllers.
69      The Elo is the DMA controller on some 82xx and 83xx parts, and the
70      Elo Plus is the DMA controller on 85xx and 86xx parts.
71
72config MV_XOR
73    bool "Marvell XOR engine support"
74    depends on PLAT_ORION
75    select DMA_ENGINE
76    ---help---
77      Enable support for the Marvell XOR engine.
78
79config MX3_IPU
80    bool "MX3x Image Processing Unit support"
81    depends on ARCH_MX3
82    select DMA_ENGINE
83    default y
84    help
85      If you plan to use the Image Processing unit in the i.MX3x, say
86      Y here. If unsure, select Y.
87
88config MX3_IPU_IRQS
89    int "Number of dynamically mapped interrupts for IPU"
90    depends on MX3_IPU
91    range 2 137
92    default 4
93    help
94      Out of 137 interrupt sources on i.MX31 IPU only very few are used.
95      To avoid bloating the irq_desc[] array we allocate a sufficient
96      number of IRQ slots and map them dynamically to specific sources.
97
98config TXX9_DMAC
99    tristate "Toshiba TXx9 SoC DMA support"
100    depends on MACH_TX49XX || MACH_TX39XX
101    select DMA_ENGINE
102    help
103      Support the TXx9 SoC internal DMA controller. This can be
104      integrated in chips such as the Toshiba TX4927/38/39.
105
106config SH_DMAE
107    tristate "Renesas SuperH DMAC support"
108    depends on SUPERH && SH_DMA
109    depends on !SH_DMA_API
110    select DMA_ENGINE
111    help
112      Enable support for the Renesas SuperH DMA controllers.
113
114config DMA_ENGINE
115    bool
116
117comment "DMA Clients"
118    depends on DMA_ENGINE
119
120config NET_DMA
121    bool "Network: TCP receive copy offload"
122    depends on DMA_ENGINE && NET
123    default (INTEL_IOATDMA || FSL_DMA)
124    help
125      This enables the use of DMA engines in the network stack to
126      offload receive copy-to-user operations, freeing CPU cycles.
127
128      Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
129      say N.
130
131config ASYNC_TX_DMA
132    bool "Async_tx: Offload support for the async_tx api"
133    depends on DMA_ENGINE
134    help
135      This allows the async_tx api to take advantage of offload engines for
136      memcpy, memset, xor, and raid6 p+q operations. If your platform has
137      a dma engine that can perform raid operations and you have enabled
138      MD_RAID456 say Y.
139
140      If unsure, say N.
141
142config DMATEST
143    tristate "DMA Test client"
144    depends on DMA_ENGINE
145    help
146      Simple DMA test client. Say N unless you're debugging a
147      DMA Device driver.
148
149endif
150

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