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1 | /* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $ |
2 | * linux/include/linux/cyclades.h |
3 | * |
4 | * This file was initially written by |
5 | * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by |
6 | * Ivan Passos <ivan@cyclades.com>. |
7 | * |
8 | * This file contains the general definitions for the cyclades.c driver |
9 | *$Log: cyclades.h,v $ |
10 | *Revision 3.1 2002/01/29 11:36:16 henrique |
11 | *added throttle field on struct cyclades_port to indicate whether the |
12 | *port is throttled or not |
13 | * |
14 | *Revision 3.1 2000/04/19 18:52:52 ivan |
15 | *converted address fields to unsigned long and added fields for physical |
16 | *addresses on cyclades_card structure; |
17 | * |
18 | *Revision 3.0 1998/11/02 14:20:59 ivan |
19 | *added nports field on cyclades_card structure; |
20 | * |
21 | *Revision 2.5 1998/08/03 16:57:01 ivan |
22 | *added cyclades_idle_stats structure; |
23 | * |
24 | *Revision 2.4 1998/06/01 12:09:53 ivan |
25 | *removed closing_wait2 from cyclades_port structure; |
26 | * |
27 | *Revision 2.3 1998/03/16 18:01:12 ivan |
28 | *changes in the cyclades_port structure to get it closer to the |
29 | *standard serial port structure; |
30 | *added constants for new ioctls; |
31 | * |
32 | *Revision 2.2 1998/02/17 16:50:00 ivan |
33 | *changes in the cyclades_port structure (addition of shutdown_wait and |
34 | *chip_rev variables); |
35 | *added constants for new ioctls and for CD1400 rev. numbers. |
36 | * |
37 | *Revision 2.1 1997/10/24 16:03:00 ivan |
38 | *added rflow (which allows enabling the CD1400 special flow control |
39 | *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to |
40 | *cyclades_port structure; |
41 | *added Alpha support |
42 | * |
43 | *Revision 2.0 1997/06/30 10:30:00 ivan |
44 | *added some new doorbell command constants related to IOCTLW and |
45 | *UART error signaling |
46 | * |
47 | *Revision 1.8 1997/06/03 15:30:00 ivan |
48 | *added constant ZFIRM_HLT |
49 | *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin) |
50 | * |
51 | *Revision 1.7 1997/03/26 10:30:00 daniel |
52 | *new entries at the end of cyclades_port struct to reallocate |
53 | *variables illegally allocated within card memory. |
54 | * |
55 | *Revision 1.6 1996/09/09 18:35:30 bentson |
56 | *fold in changes for Cyclom-Z -- including structures for |
57 | *communicating with board as well modest changes to original |
58 | *structures to support new features. |
59 | * |
60 | *Revision 1.5 1995/11/13 21:13:31 bentson |
61 | *changes suggested by Michael Chastain <mec@duracef.shout.net> |
62 | *to support use of this file in non-kernel applications |
63 | * |
64 | * |
65 | */ |
66 | |
67 | #ifndef _LINUX_CYCLADES_H |
68 | #define _LINUX_CYCLADES_H |
69 | |
70 | #include <linux/types.h> |
71 | |
72 | struct cyclades_monitor { |
73 | unsigned long int_count; |
74 | unsigned long char_count; |
75 | unsigned long char_max; |
76 | unsigned long char_last; |
77 | }; |
78 | |
79 | /* |
80 | * These stats all reflect activity since the device was last initialized. |
81 | * (i.e., since the port was opened with no other processes already having it |
82 | * open) |
83 | */ |
84 | struct cyclades_idle_stats { |
85 | __kernel_time_t in_use; /* Time device has been in use (secs) */ |
86 | __kernel_time_t recv_idle; /* Time since last char received (secs) */ |
87 | __kernel_time_t xmit_idle; /* Time since last char transmitted (secs) */ |
88 | unsigned long recv_bytes; /* Bytes received */ |
89 | unsigned long xmit_bytes; /* Bytes transmitted */ |
90 | unsigned long overruns; /* Input overruns */ |
91 | unsigned long frame_errs; /* Input framing errors */ |
92 | unsigned long parity_errs; /* Input parity errors */ |
93 | }; |
94 | |
95 | #define CYCLADES_MAGIC 0x4359 |
96 | |
97 | #define CYGETMON 0x435901 |
98 | #define CYGETTHRESH 0x435902 |
99 | #define CYSETTHRESH 0x435903 |
100 | #define CYGETDEFTHRESH 0x435904 |
101 | #define CYSETDEFTHRESH 0x435905 |
102 | #define CYGETTIMEOUT 0x435906 |
103 | #define CYSETTIMEOUT 0x435907 |
104 | #define CYGETDEFTIMEOUT 0x435908 |
105 | #define CYSETDEFTIMEOUT 0x435909 |
106 | #define CYSETRFLOW 0x43590a |
107 | #define CYGETRFLOW 0x43590b |
108 | #define CYSETRTSDTR_INV 0x43590c |
109 | #define CYGETRTSDTR_INV 0x43590d |
110 | #define CYZSETPOLLCYCLE 0x43590e |
111 | #define CYZGETPOLLCYCLE 0x43590f |
112 | #define CYGETCD1400VER 0x435910 |
113 | #define CYSETWAIT 0x435912 |
114 | #define CYGETWAIT 0x435913 |
115 | |
116 | /*************** CYCLOM-Z ADDITIONS ***************/ |
117 | |
118 | #define CZIOC ('M' << 8) |
119 | #define CZ_NBOARDS (CZIOC|0xfa) |
120 | #define CZ_BOOT_START (CZIOC|0xfb) |
121 | #define CZ_BOOT_DATA (CZIOC|0xfc) |
122 | #define CZ_BOOT_END (CZIOC|0xfd) |
123 | #define CZ_TEST (CZIOC|0xfe) |
124 | |
125 | #define CZ_DEF_POLL (HZ/25) |
126 | |
127 | #define MAX_BOARD 4 /* Max number of boards */ |
128 | #define MAX_DEV 256 /* Max number of ports total */ |
129 | #define CYZ_MAX_SPEED 921600 |
130 | |
131 | #define CYZ_FIFO_SIZE 16 |
132 | |
133 | #define CYZ_BOOT_NWORDS 0x100 |
134 | struct CYZ_BOOT_CTRL { |
135 | unsigned short nboard; |
136 | int status[MAX_BOARD]; |
137 | int nchannel[MAX_BOARD]; |
138 | int fw_rev[MAX_BOARD]; |
139 | unsigned long offset; |
140 | unsigned long data[CYZ_BOOT_NWORDS]; |
141 | }; |
142 | |
143 | |
144 | #ifndef DP_WINDOW_SIZE |
145 | /* |
146 | * Memory Window Sizes |
147 | */ |
148 | |
149 | #define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */ |
150 | #define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and |
151 | 8Zo V.2 */ |
152 | #define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */ |
153 | |
154 | /* |
155 | * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver |
156 | * normally will access only interested on the fpga_id, fpga_version, |
157 | * start_cpu and stop_cpu. |
158 | */ |
159 | |
160 | struct CUSTOM_REG { |
161 | __u32 fpga_id; /* FPGA Identification Register */ |
162 | __u32 fpga_version; /* FPGA Version Number Register */ |
163 | __u32 cpu_start; /* CPU start Register (write) */ |
164 | __u32 cpu_stop; /* CPU stop Register (write) */ |
165 | __u32 misc_reg; /* Miscellaneous Register */ |
166 | __u32 idt_mode; /* IDT mode Register */ |
167 | __u32 uart_irq_status; /* UART IRQ status Register */ |
168 | __u32 clear_timer0_irq; /* Clear timer interrupt Register */ |
169 | __u32 clear_timer1_irq; /* Clear timer interrupt Register */ |
170 | __u32 clear_timer2_irq; /* Clear timer interrupt Register */ |
171 | __u32 test_register; /* Test Register */ |
172 | __u32 test_count; /* Test Count Register */ |
173 | __u32 timer_select; /* Timer select register */ |
174 | __u32 pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */ |
175 | __u32 ram_wait_state; /* RAM wait-state Register */ |
176 | __u32 uart_wait_state; /* UART wait-state Register */ |
177 | __u32 timer_wait_state; /* timer wait-state Register */ |
178 | __u32 ack_wait_state; /* ACK wait State Register */ |
179 | }; |
180 | |
181 | /* |
182 | * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime |
183 | * registers. This structure can be used to access the 9060 registers |
184 | * (memory mapped). |
185 | */ |
186 | |
187 | struct RUNTIME_9060 { |
188 | __u32 loc_addr_range; /* 00h - Local Address Range */ |
189 | __u32 loc_addr_base; /* 04h - Local Address Base */ |
190 | __u32 loc_arbitr; /* 08h - Local Arbitration */ |
191 | __u32 endian_descr; /* 0Ch - Big/Little Endian Descriptor */ |
192 | __u32 loc_rom_range; /* 10h - Local ROM Range */ |
193 | __u32 loc_rom_base; /* 14h - Local ROM Base */ |
194 | __u32 loc_bus_descr; /* 18h - Local Bus descriptor */ |
195 | __u32 loc_range_mst; /* 1Ch - Local Range for Master to PCI */ |
196 | __u32 loc_base_mst; /* 20h - Local Base for Master PCI */ |
197 | __u32 loc_range_io; /* 24h - Local Range for Master IO */ |
198 | __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */ |
199 | __u32 pci_conf_io; /* 2Ch - PCI configuration for Master IO */ |
200 | __u32 filler1; /* 30h */ |
201 | __u32 filler2; /* 34h */ |
202 | __u32 filler3; /* 38h */ |
203 | __u32 filler4; /* 3Ch */ |
204 | __u32 mail_box_0; /* 40h - Mail Box 0 */ |
205 | __u32 mail_box_1; /* 44h - Mail Box 1 */ |
206 | __u32 mail_box_2; /* 48h - Mail Box 2 */ |
207 | __u32 mail_box_3; /* 4Ch - Mail Box 3 */ |
208 | __u32 filler5; /* 50h */ |
209 | __u32 filler6; /* 54h */ |
210 | __u32 filler7; /* 58h */ |
211 | __u32 filler8; /* 5Ch */ |
212 | __u32 pci_doorbell; /* 60h - PCI to Local Doorbell */ |
213 | __u32 loc_doorbell; /* 64h - Local to PCI Doorbell */ |
214 | __u32 intr_ctrl_stat; /* 68h - Interrupt Control/Status */ |
215 | __u32 init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */ |
216 | }; |
217 | |
218 | /* Values for the Local Base Address re-map register */ |
219 | |
220 | #define WIN_RAM 0x00000001L /* set the sliding window to RAM */ |
221 | #define WIN_CREG 0x14000001L /* set the window to custom Registers */ |
222 | |
223 | /* Values timer select registers */ |
224 | |
225 | #define TIMER_BY_1M 0x00 /* clock divided by 1M */ |
226 | #define TIMER_BY_256K 0x01 /* clock divided by 256k */ |
227 | #define TIMER_BY_128K 0x02 /* clock divided by 128k */ |
228 | #define TIMER_BY_32K 0x03 /* clock divided by 32k */ |
229 | |
230 | /****************** ****************** *******************/ |
231 | #endif |
232 | |
233 | #ifndef ZFIRM_ID |
234 | /* #include "zfwint.h" */ |
235 | /****************** ****************** *******************/ |
236 | /* |
237 | * This file contains the definitions for interfacing with the |
238 | * Cyclom-Z ZFIRM Firmware. |
239 | */ |
240 | |
241 | /* General Constant definitions */ |
242 | |
243 | #define MAX_CHAN 64 /* max number of channels per board */ |
244 | |
245 | /* firmware id structure (set after boot) */ |
246 | |
247 | #define ID_ADDRESS 0x00000180L /* signature/pointer address */ |
248 | #define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */ |
249 | #define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */ |
250 | #define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */ |
251 | |
252 | #define ZF_TINACT_DEF 1000 /* default inactivity timeout |
253 | (1000 ms) */ |
254 | #define ZF_TINACT ZF_TINACT_DEF |
255 | |
256 | struct FIRM_ID { |
257 | __u32 signature; /* ZFIRM/U signature */ |
258 | __u32 zfwctrl_addr; /* pointer to ZFW_CTRL structure */ |
259 | }; |
260 | |
261 | /* Op. System id */ |
262 | |
263 | #define C_OS_LINUX 0x00000030 /* generic Linux system */ |
264 | |
265 | /* channel op_mode */ |
266 | |
267 | #define C_CH_DISABLE 0x00000000 /* channel is disabled */ |
268 | #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */ |
269 | #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */ |
270 | #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */ |
271 | #define C_CH_LOOPBACK 0x00000004 /* Loopback mode */ |
272 | |
273 | /* comm_parity - parity */ |
274 | |
275 | #define C_PR_NONE 0x00000000 /* None */ |
276 | #define C_PR_ODD 0x00000001 /* Odd */ |
277 | #define C_PR_EVEN 0x00000002 /* Even */ |
278 | #define C_PR_MARK 0x00000004 /* Mark */ |
279 | #define C_PR_SPACE 0x00000008 /* Space */ |
280 | #define C_PR_PARITY 0x000000ff |
281 | |
282 | #define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */ |
283 | #define C_PR_IGNORE 0x00000200 /* ignore frame/par error */ |
284 | |
285 | /* comm_data_l - data length and stop bits */ |
286 | |
287 | #define C_DL_CS5 0x00000001 |
288 | #define C_DL_CS6 0x00000002 |
289 | #define C_DL_CS7 0x00000004 |
290 | #define C_DL_CS8 0x00000008 |
291 | #define C_DL_CS 0x0000000f |
292 | #define C_DL_1STOP 0x00000010 |
293 | #define C_DL_15STOP 0x00000020 |
294 | #define C_DL_2STOP 0x00000040 |
295 | #define C_DL_STOP 0x000000f0 |
296 | |
297 | /* interrupt enabling/status */ |
298 | |
299 | #define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */ |
300 | #define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */ |
301 | #define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */ |
302 | #define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */ |
303 | #define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */ |
304 | #define C_IN_MDCD 0x00000100 /* modem DCD change */ |
305 | #define C_IN_MDSR 0x00000200 /* modem DSR change */ |
306 | #define C_IN_MRI 0x00000400 /* modem RI change */ |
307 | #define C_IN_MCTS 0x00000800 /* modem CTS change */ |
308 | #define C_IN_RXBRK 0x00001000 /* Break received */ |
309 | #define C_IN_PR_ERROR 0x00002000 /* parity error */ |
310 | #define C_IN_FR_ERROR 0x00004000 /* frame error */ |
311 | #define C_IN_OVR_ERROR 0x00008000 /* overrun error */ |
312 | #define C_IN_RXOFL 0x00010000 /* RX buffer overflow */ |
313 | #define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */ |
314 | #define C_IN_MRTS 0x00040000 /* modem RTS drop */ |
315 | #define C_IN_ICHAR 0x00080000 |
316 | |
317 | /* flow control */ |
318 | |
319 | #define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */ |
320 | #define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */ |
321 | #define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */ |
322 | #define C_FL_SWFLOW 0x0000000f |
323 | |
324 | /* flow status */ |
325 | |
326 | #define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */ |
327 | #define C_FS_SENDING 0x00000001 /* UART is sending data */ |
328 | #define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */ |
329 | |
330 | /* rs_control/rs_status RS-232 signals */ |
331 | |
332 | #define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in |
333 | IOCTLM command */ |
334 | #define C_RS_RTS 0x00000001 /* RTS */ |
335 | #define C_RS_DTR 0x00000004 /* DTR */ |
336 | #define C_RS_DCD 0x00000100 /* CD */ |
337 | #define C_RS_DSR 0x00000200 /* DSR */ |
338 | #define C_RS_RI 0x00000400 /* RI */ |
339 | #define C_RS_CTS 0x00000800 /* CTS */ |
340 | |
341 | /* commands Host <-> Board */ |
342 | |
343 | #define C_CM_RESET 0x01 /* reset/flush buffers */ |
344 | #define C_CM_IOCTL 0x02 /* re-read CH_CTRL */ |
345 | #define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */ |
346 | #define C_CM_IOCTLM 0x04 /* RS-232 outputs change */ |
347 | #define C_CM_SENDXOFF 0x10 /* send Xoff */ |
348 | #define C_CM_SENDXON 0x11 /* send Xon */ |
349 | #define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */ |
350 | #define C_CM_SENDBRK 0x41 /* send break */ |
351 | #define C_CM_INTBACK 0x42 /* Interrupt back */ |
352 | #define C_CM_SET_BREAK 0x43 /* Tx break on */ |
353 | #define C_CM_CLR_BREAK 0x44 /* Tx break off */ |
354 | #define C_CM_CMD_DONE 0x45 /* Previous command done */ |
355 | #define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */ |
356 | #define C_CM_TINACT 0x51 /* set inactivity detection */ |
357 | #define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */ |
358 | #define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */ |
359 | #define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */ |
360 | #define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */ |
361 | #define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */ |
362 | #define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */ |
363 | #define C_CM_Q_ENABLE 0x58 /* enables queue access from the |
364 | driver */ |
365 | #define C_CM_Q_DISABLE 0x59 /* disables queue access from the |
366 | driver */ |
367 | |
368 | #define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */ |
369 | #define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */ |
370 | #define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */ |
371 | #define C_CM_RXNNDT 0x63 /* rx no new data timeout */ |
372 | #define C_CM_TXFEMPTY 0x64 |
373 | #define C_CM_ICHAR 0x65 |
374 | #define C_CM_MDCD 0x70 /* modem DCD change */ |
375 | #define C_CM_MDSR 0x71 /* modem DSR change */ |
376 | #define C_CM_MRI 0x72 /* modem RI change */ |
377 | #define C_CM_MCTS 0x73 /* modem CTS change */ |
378 | #define C_CM_MRTS 0x74 /* modem RTS drop */ |
379 | #define C_CM_RXBRK 0x84 /* Break received */ |
380 | #define C_CM_PR_ERROR 0x85 /* Parity error */ |
381 | #define C_CM_FR_ERROR 0x86 /* Frame error */ |
382 | #define C_CM_OVR_ERROR 0x87 /* Overrun error */ |
383 | #define C_CM_RXOFL 0x88 /* RX buffer overflow */ |
384 | #define C_CM_CMDERROR 0x90 /* command error */ |
385 | #define C_CM_FATAL 0x91 /* fatal error */ |
386 | #define C_CM_HW_RESET 0x92 /* reset board */ |
387 | |
388 | /* |
389 | * CH_CTRL - This per port structure contains all parameters |
390 | * that control an specific port. It can be seen as the |
391 | * configuration registers of a "super-serial-controller". |
392 | */ |
393 | |
394 | struct CH_CTRL { |
395 | __u32 op_mode; /* operation mode */ |
396 | __u32 intr_enable; /* interrupt masking */ |
397 | __u32 sw_flow; /* SW flow control */ |
398 | __u32 flow_status; /* output flow status */ |
399 | __u32 comm_baud; /* baud rate - numerically specified */ |
400 | __u32 comm_parity; /* parity */ |
401 | __u32 comm_data_l; /* data length/stop */ |
402 | __u32 comm_flags; /* other flags */ |
403 | __u32 hw_flow; /* HW flow control */ |
404 | __u32 rs_control; /* RS-232 outputs */ |
405 | __u32 rs_status; /* RS-232 inputs */ |
406 | __u32 flow_xon; /* xon char */ |
407 | __u32 flow_xoff; /* xoff char */ |
408 | __u32 hw_overflow; /* hw overflow counter */ |
409 | __u32 sw_overflow; /* sw overflow counter */ |
410 | __u32 comm_error; /* frame/parity error counter */ |
411 | __u32 ichar; |
412 | __u32 filler[7]; |
413 | }; |
414 | |
415 | |
416 | /* |
417 | * BUF_CTRL - This per channel structure contains |
418 | * all Tx and Rx buffer control for a given channel. |
419 | */ |
420 | |
421 | struct BUF_CTRL { |
422 | __u32 flag_dma; /* buffers are in Host memory */ |
423 | __u32 tx_bufaddr; /* address of the tx buffer */ |
424 | __u32 tx_bufsize; /* tx buffer size */ |
425 | __u32 tx_threshold; /* tx low water mark */ |
426 | __u32 tx_get; /* tail index tx buf */ |
427 | __u32 tx_put; /* head index tx buf */ |
428 | __u32 rx_bufaddr; /* address of the rx buffer */ |
429 | __u32 rx_bufsize; /* rx buffer size */ |
430 | __u32 rx_threshold; /* rx high water mark */ |
431 | __u32 rx_get; /* tail index rx buf */ |
432 | __u32 rx_put; /* head index rx buf */ |
433 | __u32 filler[5]; /* filler to align structures */ |
434 | }; |
435 | |
436 | /* |
437 | * BOARD_CTRL - This per board structure contains all global |
438 | * control fields related to the board. |
439 | */ |
440 | |
441 | struct BOARD_CTRL { |
442 | |
443 | /* static info provided by the on-board CPU */ |
444 | __u32 n_channel; /* number of channels */ |
445 | __u32 fw_version; /* firmware version */ |
446 | |
447 | /* static info provided by the driver */ |
448 | __u32 op_system; /* op_system id */ |
449 | __u32 dr_version; /* driver version */ |
450 | |
451 | /* board control area */ |
452 | __u32 inactivity; /* inactivity control */ |
453 | |
454 | /* host to FW commands */ |
455 | __u32 hcmd_channel; /* channel number */ |
456 | __u32 hcmd_param; /* pointer to parameters */ |
457 | |
458 | /* FW to Host commands */ |
459 | __u32 fwcmd_channel; /* channel number */ |
460 | __u32 fwcmd_param; /* pointer to parameters */ |
461 | __u32 zf_int_queue_addr; /* offset for INT_QUEUE structure */ |
462 | |
463 | /* filler so the structures are aligned */ |
464 | __u32 filler[6]; |
465 | }; |
466 | |
467 | /* Host Interrupt Queue */ |
468 | |
469 | #define QUEUE_SIZE (10*MAX_CHAN) |
470 | |
471 | struct INT_QUEUE { |
472 | unsigned char intr_code[QUEUE_SIZE]; |
473 | unsigned long channel[QUEUE_SIZE]; |
474 | unsigned long param[QUEUE_SIZE]; |
475 | unsigned long put; |
476 | unsigned long get; |
477 | }; |
478 | |
479 | /* |
480 | * ZFW_CTRL - This is the data structure that includes all other |
481 | * data structures used by the Firmware. |
482 | */ |
483 | |
484 | struct ZFW_CTRL { |
485 | struct BOARD_CTRL board_ctrl; |
486 | struct CH_CTRL ch_ctrl[MAX_CHAN]; |
487 | struct BUF_CTRL buf_ctrl[MAX_CHAN]; |
488 | }; |
489 | |
490 | /****************** ****************** *******************/ |
491 | #endif |
492 | |
493 | #ifdef __KERNEL__ |
494 | |
495 | /* Per card data structure */ |
496 | struct cyclades_card { |
497 | void __iomem *base_addr; |
498 | union { |
499 | void __iomem *p9050; |
500 | struct RUNTIME_9060 __iomem *p9060; |
501 | } ctl_addr; |
502 | struct BOARD_CTRL __iomem *board_ctrl; /* cyz specific */ |
503 | int irq; |
504 | unsigned int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */ |
505 | unsigned int first_line; /* minor number of first channel on card */ |
506 | unsigned int nports; /* Number of ports in the card */ |
507 | int bus_index; /* address shift - 0 for ISA, 1 for PCI */ |
508 | int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */ |
509 | u32 hw_ver; |
510 | spinlock_t card_lock; |
511 | struct cyclades_port *ports; |
512 | }; |
513 | |
514 | /*************************************** |
515 | * Memory access functions/macros * |
516 | * (required to support Alpha systems) * |
517 | ***************************************/ |
518 | |
519 | #define cy_writeb(port,val) do { writeb((val), (port)); mb(); } while (0) |
520 | #define cy_writew(port,val) do { writew((val), (port)); mb(); } while (0) |
521 | #define cy_writel(port,val) do { writel((val), (port)); mb(); } while (0) |
522 | |
523 | /* |
524 | * Statistics counters |
525 | */ |
526 | struct cyclades_icount { |
527 | __u32 cts, dsr, rng, dcd, tx, rx; |
528 | __u32 frame, parity, overrun, brk; |
529 | __u32 buf_overrun; |
530 | }; |
531 | |
532 | /* |
533 | * This is our internal structure for each serial port's state. |
534 | * |
535 | * Many fields are paralleled by the structure used by the serial_struct |
536 | * structure. |
537 | * |
538 | * For definitions of the flags field, see tty.h |
539 | */ |
540 | |
541 | struct cyclades_port { |
542 | int magic; |
543 | struct tty_port port; |
544 | struct cyclades_card *card; |
545 | union { |
546 | struct { |
547 | void __iomem *base_addr; |
548 | } cyy; |
549 | struct { |
550 | struct CH_CTRL __iomem *ch_ctrl; |
551 | struct BUF_CTRL __iomem *buf_ctrl; |
552 | } cyz; |
553 | } u; |
554 | int line; |
555 | int flags; /* defined in tty.h */ |
556 | int type; /* UART type */ |
557 | int read_status_mask; |
558 | int ignore_status_mask; |
559 | int timeout; |
560 | int xmit_fifo_size; |
561 | int cor1,cor2,cor3,cor4,cor5; |
562 | int tbpr,tco,rbpr,rco; |
563 | int baud; |
564 | int rflow; |
565 | int rtsdtr_inv; |
566 | int chip_rev; |
567 | int custom_divisor; |
568 | u8 x_char; /* to be pushed out ASAP */ |
569 | int breakon; |
570 | int breakoff; |
571 | int xmit_head; |
572 | int xmit_tail; |
573 | int xmit_cnt; |
574 | int default_threshold; |
575 | int default_timeout; |
576 | unsigned long rflush_count; |
577 | struct cyclades_monitor mon; |
578 | struct cyclades_idle_stats idle_stats; |
579 | struct cyclades_icount icount; |
580 | struct completion shutdown_wait; |
581 | int throttle; |
582 | }; |
583 | |
584 | #define CLOSING_WAIT_DELAY 30*HZ |
585 | #define CY_CLOSING_WAIT_NONE ASYNC_CLOSING_WAIT_NONE |
586 | #define CY_CLOSING_WAIT_INF ASYNC_CLOSING_WAIT_INF |
587 | |
588 | |
589 | #define CyMAX_CHIPS_PER_CARD 8 |
590 | #define CyMAX_CHAR_FIFO 12 |
591 | #define CyPORTS_PER_CHIP 4 |
592 | #define CD1400_MAX_SPEED 115200 |
593 | |
594 | #define CyISA_Ywin 0x2000 |
595 | |
596 | #define CyPCI_Ywin 0x4000 |
597 | #define CyPCI_Yctl 0x80 |
598 | #define CyPCI_Zctl CTRL_WINDOW_SIZE |
599 | #define CyPCI_Zwin 0x80000 |
600 | #define CyPCI_Ze_win (2 * CyPCI_Zwin) |
601 | |
602 | #define PCI_DEVICE_ID_MASK 0x06 |
603 | |
604 | /**** CD1400 registers ****/ |
605 | |
606 | #define CD1400_REV_G 0x46 |
607 | #define CD1400_REV_J 0x48 |
608 | |
609 | #define CyRegSize 0x0400 |
610 | #define Cy_HwReset 0x1400 |
611 | #define Cy_ClrIntr 0x1800 |
612 | #define Cy_EpldRev 0x1e00 |
613 | |
614 | /* Global Registers */ |
615 | |
616 | #define CyGFRCR (0x40*2) |
617 | #define CyRevE (44) |
618 | #define CyCAR (0x68*2) |
619 | #define CyCHAN_0 (0x00) |
620 | #define CyCHAN_1 (0x01) |
621 | #define CyCHAN_2 (0x02) |
622 | #define CyCHAN_3 (0x03) |
623 | #define CyGCR (0x4B*2) |
624 | #define CyCH0_SERIAL (0x00) |
625 | #define CyCH0_PARALLEL (0x80) |
626 | #define CySVRR (0x67*2) |
627 | #define CySRModem (0x04) |
628 | #define CySRTransmit (0x02) |
629 | #define CySRReceive (0x01) |
630 | #define CyRICR (0x44*2) |
631 | #define CyTICR (0x45*2) |
632 | #define CyMICR (0x46*2) |
633 | #define CyICR0 (0x00) |
634 | #define CyICR1 (0x01) |
635 | #define CyICR2 (0x02) |
636 | #define CyICR3 (0x03) |
637 | #define CyRIR (0x6B*2) |
638 | #define CyTIR (0x6A*2) |
639 | #define CyMIR (0x69*2) |
640 | #define CyIRDirEq (0x80) |
641 | #define CyIRBusy (0x40) |
642 | #define CyIRUnfair (0x20) |
643 | #define CyIRContext (0x1C) |
644 | #define CyIRChannel (0x03) |
645 | #define CyPPR (0x7E*2) |
646 | #define CyCLOCK_20_1MS (0x27) |
647 | #define CyCLOCK_25_1MS (0x31) |
648 | #define CyCLOCK_25_5MS (0xf4) |
649 | #define CyCLOCK_60_1MS (0x75) |
650 | #define CyCLOCK_60_2MS (0xea) |
651 | |
652 | /* Virtual Registers */ |
653 | |
654 | #define CyRIVR (0x43*2) |
655 | #define CyTIVR (0x42*2) |
656 | #define CyMIVR (0x41*2) |
657 | #define CyIVRMask (0x07) |
658 | #define CyIVRRxEx (0x07) |
659 | #define CyIVRRxOK (0x03) |
660 | #define CyIVRTxOK (0x02) |
661 | #define CyIVRMdmOK (0x01) |
662 | #define CyTDR (0x63*2) |
663 | #define CyRDSR (0x62*2) |
664 | #define CyTIMEOUT (0x80) |
665 | #define CySPECHAR (0x70) |
666 | #define CyBREAK (0x08) |
667 | #define CyPARITY (0x04) |
668 | #define CyFRAME (0x02) |
669 | #define CyOVERRUN (0x01) |
670 | #define CyMISR (0x4C*2) |
671 | /* see CyMCOR_ and CyMSVR_ for bits*/ |
672 | #define CyEOSRR (0x60*2) |
673 | |
674 | /* Channel Registers */ |
675 | |
676 | #define CyLIVR (0x18*2) |
677 | #define CyMscsr (0x01) |
678 | #define CyTdsr (0x02) |
679 | #define CyRgdsr (0x03) |
680 | #define CyRedsr (0x07) |
681 | #define CyCCR (0x05*2) |
682 | /* Format 1 */ |
683 | #define CyCHAN_RESET (0x80) |
684 | #define CyCHIP_RESET (0x81) |
685 | #define CyFlushTransFIFO (0x82) |
686 | /* Format 2 */ |
687 | #define CyCOR_CHANGE (0x40) |
688 | #define CyCOR1ch (0x02) |
689 | #define CyCOR2ch (0x04) |
690 | #define CyCOR3ch (0x08) |
691 | /* Format 3 */ |
692 | #define CySEND_SPEC_1 (0x21) |
693 | #define CySEND_SPEC_2 (0x22) |
694 | #define CySEND_SPEC_3 (0x23) |
695 | #define CySEND_SPEC_4 (0x24) |
696 | /* Format 4 */ |
697 | #define CyCHAN_CTL (0x10) |
698 | #define CyDIS_RCVR (0x01) |
699 | #define CyENB_RCVR (0x02) |
700 | #define CyDIS_XMTR (0x04) |
701 | #define CyENB_XMTR (0x08) |
702 | #define CySRER (0x06*2) |
703 | #define CyMdmCh (0x80) |
704 | #define CyRxData (0x10) |
705 | #define CyTxRdy (0x04) |
706 | #define CyTxMpty (0x02) |
707 | #define CyNNDT (0x01) |
708 | #define CyCOR1 (0x08*2) |
709 | #define CyPARITY_NONE (0x00) |
710 | #define CyPARITY_0 (0x20) |
711 | #define CyPARITY_1 (0xA0) |
712 | #define CyPARITY_E (0x40) |
713 | #define CyPARITY_O (0xC0) |
714 | #define Cy_1_STOP (0x00) |
715 | #define Cy_1_5_STOP (0x04) |
716 | #define Cy_2_STOP (0x08) |
717 | #define Cy_5_BITS (0x00) |
718 | #define Cy_6_BITS (0x01) |
719 | #define Cy_7_BITS (0x02) |
720 | #define Cy_8_BITS (0x03) |
721 | #define CyCOR2 (0x09*2) |
722 | #define CyIXM (0x80) |
723 | #define CyTxIBE (0x40) |
724 | #define CyETC (0x20) |
725 | #define CyAUTO_TXFL (0x60) |
726 | #define CyLLM (0x10) |
727 | #define CyRLM (0x08) |
728 | #define CyRtsAO (0x04) |
729 | #define CyCtsAE (0x02) |
730 | #define CyDsrAE (0x01) |
731 | #define CyCOR3 (0x0A*2) |
732 | #define CySPL_CH_DRANGE (0x80) /* special character detect range */ |
733 | #define CySPL_CH_DET1 (0x40) /* enable special character detection |
734 | on SCHR4-SCHR3 */ |
735 | #define CyFL_CTRL_TRNSP (0x20) /* Flow Control Transparency */ |
736 | #define CySPL_CH_DET2 (0x10) /* Enable special character detection |
737 | on SCHR2-SCHR1 */ |
738 | #define CyREC_FIFO (0x0F) /* Receive FIFO threshold */ |
739 | #define CyCOR4 (0x1E*2) |
740 | #define CyCOR5 (0x1F*2) |
741 | #define CyCCSR (0x0B*2) |
742 | #define CyRxEN (0x80) |
743 | #define CyRxFloff (0x40) |
744 | #define CyRxFlon (0x20) |
745 | #define CyTxEN (0x08) |
746 | #define CyTxFloff (0x04) |
747 | #define CyTxFlon (0x02) |
748 | #define CyRDCR (0x0E*2) |
749 | #define CySCHR1 (0x1A*2) |
750 | #define CySCHR2 (0x1B*2) |
751 | #define CySCHR3 (0x1C*2) |
752 | #define CySCHR4 (0x1D*2) |
753 | #define CySCRL (0x22*2) |
754 | #define CySCRH (0x23*2) |
755 | #define CyLNC (0x24*2) |
756 | #define CyMCOR1 (0x15*2) |
757 | #define CyMCOR2 (0x16*2) |
758 | #define CyRTPR (0x21*2) |
759 | #define CyMSVR1 (0x6C*2) |
760 | #define CyMSVR2 (0x6D*2) |
761 | #define CyANY_DELTA (0xF0) |
762 | #define CyDSR (0x80) |
763 | #define CyCTS (0x40) |
764 | #define CyRI (0x20) |
765 | #define CyDCD (0x10) |
766 | #define CyDTR (0x02) |
767 | #define CyRTS (0x01) |
768 | #define CyPVSR (0x6F*2) |
769 | #define CyRBPR (0x78*2) |
770 | #define CyRCOR (0x7C*2) |
771 | #define CyTBPR (0x72*2) |
772 | #define CyTCOR (0x76*2) |
773 | |
774 | /* Custom Registers */ |
775 | |
776 | #define CyPLX_VER (0x3400) |
777 | #define PLX_9050 0x0b |
778 | #define PLX_9060 0x0c |
779 | #define PLX_9080 0x0d |
780 | |
781 | /***************************************************************************/ |
782 | |
783 | #endif /* __KERNEL__ */ |
784 | #endif /* _LINUX_CYCLADES_H */ |
785 |
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