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1 | /* |
2 | * Copyright (C) 2006 Intel Corp. |
3 | * Tom Long Nguyen (tom.l.nguyen@intel.com) |
4 | * Zhang Yanmin (yanmin.zhang@intel.com) |
5 | */ |
6 | |
7 | #ifndef _AER_H_ |
8 | #define _AER_H_ |
9 | |
10 | struct aer_header_log_regs { |
11 | unsigned int dw0; |
12 | unsigned int dw1; |
13 | unsigned int dw2; |
14 | unsigned int dw3; |
15 | }; |
16 | |
17 | struct aer_capability_regs { |
18 | u32 header; |
19 | u32 uncor_status; |
20 | u32 uncor_mask; |
21 | u32 uncor_severity; |
22 | u32 cor_status; |
23 | u32 cor_mask; |
24 | u32 cap_control; |
25 | struct aer_header_log_regs header_log; |
26 | u32 root_command; |
27 | u32 root_status; |
28 | u16 cor_err_source; |
29 | u16 uncor_err_source; |
30 | }; |
31 | |
32 | #if defined(CONFIG_PCIEAER) |
33 | /* pci-e port driver needs this function to enable aer */ |
34 | extern int pci_enable_pcie_error_reporting(struct pci_dev *dev); |
35 | extern int pci_disable_pcie_error_reporting(struct pci_dev *dev); |
36 | extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev); |
37 | #else |
38 | static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) |
39 | { |
40 | return -EINVAL; |
41 | } |
42 | static inline int pci_disable_pcie_error_reporting(struct pci_dev *dev) |
43 | { |
44 | return -EINVAL; |
45 | } |
46 | static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev) |
47 | { |
48 | return -EINVAL; |
49 | } |
50 | #endif |
51 | |
52 | extern void cper_print_aer(const char *prefix, int cper_severity, |
53 | struct aer_capability_regs *aer); |
54 | #endif //_AER_H_ |
55 | |
56 |
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