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1 | /*****************************************************************************/ |
2 | |
3 | /* |
4 | * cd1400.h -- cd1400 UART hardware info. |
5 | * |
6 | * Copyright (C) 1996-1998 Stallion Technologies |
7 | * Copyright (C) 1994-1996 Greg Ungerer. |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or |
12 | * (at your option) any later version. |
13 | * |
14 | * This program is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
17 | * GNU General Public License for more details. |
18 | * |
19 | * You should have received a copy of the GNU General Public License |
20 | * along with this program; if not, write to the Free Software |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
22 | */ |
23 | |
24 | /*****************************************************************************/ |
25 | #ifndef _CD1400_H |
26 | #define _CD1400_H |
27 | /*****************************************************************************/ |
28 | |
29 | /* |
30 | * Define the number of async ports per cd1400 uart chip. |
31 | */ |
32 | #define CD1400_PORTS 4 |
33 | |
34 | /* |
35 | * Define the cd1400 uarts internal FIFO sizes. |
36 | */ |
37 | #define CD1400_TXFIFOSIZE 12 |
38 | #define CD1400_RXFIFOSIZE 12 |
39 | |
40 | /* |
41 | * Local RX FIFO thresh hold level. Also define the RTS thresh hold |
42 | * based on the RX thresh hold. |
43 | */ |
44 | #define FIFO_RXTHRESHOLD 6 |
45 | #define FIFO_RTSTHRESHOLD 7 |
46 | |
47 | /*****************************************************************************/ |
48 | |
49 | /* |
50 | * Define the cd1400 register addresses. These are all the valid |
51 | * registers with the cd1400. Some are global, some virtual, some |
52 | * per port. |
53 | */ |
54 | #define GFRCR 0x40 |
55 | #define CAR 0x68 |
56 | #define GCR 0x4b |
57 | #define SVRR 0x67 |
58 | #define RICR 0x44 |
59 | #define TICR 0x45 |
60 | #define MICR 0x46 |
61 | #define RIR 0x6b |
62 | #define TIR 0x6a |
63 | #define MIR 0x69 |
64 | #define PPR 0x7e |
65 | |
66 | #define RIVR 0x43 |
67 | #define TIVR 0x42 |
68 | #define MIVR 0x41 |
69 | #define TDR 0x63 |
70 | #define RDSR 0x62 |
71 | #define MISR 0x4c |
72 | #define EOSRR 0x60 |
73 | |
74 | #define LIVR 0x18 |
75 | #define CCR 0x05 |
76 | #define SRER 0x06 |
77 | #define COR1 0x08 |
78 | #define COR2 0x09 |
79 | #define COR3 0x0a |
80 | #define COR4 0x1e |
81 | #define COR5 0x1f |
82 | #define CCSR 0x0b |
83 | #define RDCR 0x0e |
84 | #define SCHR1 0x1a |
85 | #define SCHR2 0x1b |
86 | #define SCHR3 0x1c |
87 | #define SCHR4 0x1d |
88 | #define SCRL 0x22 |
89 | #define SCRH 0x23 |
90 | #define LNC 0x24 |
91 | #define MCOR1 0x15 |
92 | #define MCOR2 0x16 |
93 | #define RTPR 0x21 |
94 | #define MSVR1 0x6c |
95 | #define MSVR2 0x6d |
96 | #define PSVR 0x6f |
97 | #define RBPR 0x78 |
98 | #define RCOR 0x7c |
99 | #define TBPR 0x72 |
100 | #define TCOR 0x76 |
101 | |
102 | /*****************************************************************************/ |
103 | |
104 | /* |
105 | * Define the set of baud rate clock divisors. |
106 | */ |
107 | #define CD1400_CLK0 8 |
108 | #define CD1400_CLK1 32 |
109 | #define CD1400_CLK2 128 |
110 | #define CD1400_CLK3 512 |
111 | #define CD1400_CLK4 2048 |
112 | |
113 | #define CD1400_NUMCLKS 5 |
114 | |
115 | /*****************************************************************************/ |
116 | |
117 | /* |
118 | * Define the clock pre-scalar value to be a 5 ms clock. This should be |
119 | * OK for now. It would probably be better to make it 10 ms, but we |
120 | * can't fit that divisor into 8 bits! |
121 | */ |
122 | #define PPR_SCALAR 244 |
123 | |
124 | /*****************************************************************************/ |
125 | |
126 | /* |
127 | * Define values used to set character size options. |
128 | */ |
129 | #define COR1_CHL5 0x00 |
130 | #define COR1_CHL6 0x01 |
131 | #define COR1_CHL7 0x02 |
132 | #define COR1_CHL8 0x03 |
133 | |
134 | /* |
135 | * Define values used to set the number of stop bits. |
136 | */ |
137 | #define COR1_STOP1 0x00 |
138 | #define COR1_STOP15 0x04 |
139 | #define COR1_STOP2 0x08 |
140 | |
141 | /* |
142 | * Define values used to set the parity scheme in use. |
143 | */ |
144 | #define COR1_PARNONE 0x00 |
145 | #define COR1_PARFORCE 0x20 |
146 | #define COR1_PARENB 0x40 |
147 | #define COR1_PARIGNORE 0x10 |
148 | |
149 | #define COR1_PARODD 0x80 |
150 | #define COR1_PAREVEN 0x00 |
151 | |
152 | #define COR2_IXM 0x80 |
153 | #define COR2_TXIBE 0x40 |
154 | #define COR2_ETC 0x20 |
155 | #define COR2_LLM 0x10 |
156 | #define COR2_RLM 0x08 |
157 | #define COR2_RTSAO 0x04 |
158 | #define COR2_CTSAE 0x02 |
159 | |
160 | #define COR3_SCDRNG 0x80 |
161 | #define COR3_SCD34 0x40 |
162 | #define COR3_FCT 0x20 |
163 | #define COR3_SCD12 0x10 |
164 | |
165 | /* |
166 | * Define values used by COR4. |
167 | */ |
168 | #define COR4_BRKINT 0x08 |
169 | #define COR4_IGNBRK 0x18 |
170 | |
171 | /*****************************************************************************/ |
172 | |
173 | /* |
174 | * Define the modem control register values. |
175 | * Note that the actual hardware is a little different to the conventional |
176 | * pin names on the cd1400. |
177 | */ |
178 | #define MSVR1_DTR 0x01 |
179 | #define MSVR1_DSR 0x10 |
180 | #define MSVR1_RI 0x20 |
181 | #define MSVR1_CTS 0x40 |
182 | #define MSVR1_DCD 0x80 |
183 | |
184 | #define MSVR2_RTS 0x02 |
185 | #define MSVR2_DSR 0x10 |
186 | #define MSVR2_RI 0x20 |
187 | #define MSVR2_CTS 0x40 |
188 | #define MSVR2_DCD 0x80 |
189 | |
190 | #define MCOR1_DCD 0x80 |
191 | #define MCOR1_CTS 0x40 |
192 | #define MCOR1_RI 0x20 |
193 | #define MCOR1_DSR 0x10 |
194 | |
195 | #define MCOR2_DCD 0x80 |
196 | #define MCOR2_CTS 0x40 |
197 | #define MCOR2_RI 0x20 |
198 | #define MCOR2_DSR 0x10 |
199 | |
200 | /*****************************************************************************/ |
201 | |
202 | /* |
203 | * Define the bits used with the service (interrupt) enable register. |
204 | */ |
205 | #define SRER_NNDT 0x01 |
206 | #define SRER_TXEMPTY 0x02 |
207 | #define SRER_TXDATA 0x04 |
208 | #define SRER_RXDATA 0x10 |
209 | #define SRER_MODEM 0x80 |
210 | |
211 | /*****************************************************************************/ |
212 | |
213 | /* |
214 | * Define operational commands for the command register. |
215 | */ |
216 | #define CCR_RESET 0x80 |
217 | #define CCR_CORCHANGE 0x4e |
218 | #define CCR_SENDCH 0x20 |
219 | #define CCR_CHANCTRL 0x10 |
220 | |
221 | #define CCR_TXENABLE (CCR_CHANCTRL | 0x08) |
222 | #define CCR_TXDISABLE (CCR_CHANCTRL | 0x04) |
223 | #define CCR_RXENABLE (CCR_CHANCTRL | 0x02) |
224 | #define CCR_RXDISABLE (CCR_CHANCTRL | 0x01) |
225 | |
226 | #define CCR_SENDSCHR1 (CCR_SENDCH | 0x01) |
227 | #define CCR_SENDSCHR2 (CCR_SENDCH | 0x02) |
228 | #define CCR_SENDSCHR3 (CCR_SENDCH | 0x03) |
229 | #define CCR_SENDSCHR4 (CCR_SENDCH | 0x04) |
230 | |
231 | #define CCR_RESETCHAN (CCR_RESET | 0x00) |
232 | #define CCR_RESETFULL (CCR_RESET | 0x01) |
233 | #define CCR_TXFLUSHFIFO (CCR_RESET | 0x02) |
234 | |
235 | #define CCR_MAXWAIT 10000 |
236 | |
237 | /*****************************************************************************/ |
238 | |
239 | /* |
240 | * Define the valid acknowledgement types (for hw ack cycle). |
241 | */ |
242 | #define ACK_TYPMASK 0x07 |
243 | #define ACK_TYPTX 0x02 |
244 | #define ACK_TYPMDM 0x01 |
245 | #define ACK_TYPRXGOOD 0x03 |
246 | #define ACK_TYPRXBAD 0x07 |
247 | |
248 | #define SVRR_RX 0x01 |
249 | #define SVRR_TX 0x02 |
250 | #define SVRR_MDM 0x04 |
251 | |
252 | #define ST_OVERRUN 0x01 |
253 | #define ST_FRAMING 0x02 |
254 | #define ST_PARITY 0x04 |
255 | #define ST_BREAK 0x08 |
256 | #define ST_SCHAR1 0x10 |
257 | #define ST_SCHAR2 0x20 |
258 | #define ST_SCHAR3 0x30 |
259 | #define ST_SCHAR4 0x40 |
260 | #define ST_RANGE 0x70 |
261 | #define ST_SCHARMASK 0x70 |
262 | #define ST_TIMEOUT 0x80 |
263 | |
264 | #define MISR_DCD 0x80 |
265 | #define MISR_CTS 0x40 |
266 | #define MISR_RI 0x20 |
267 | #define MISR_DSR 0x10 |
268 | |
269 | /*****************************************************************************/ |
270 | |
271 | /* |
272 | * Defines for the CCSR status register. |
273 | */ |
274 | #define CCSR_RXENABLED 0x80 |
275 | #define CCSR_RXFLOWON 0x40 |
276 | #define CCSR_RXFLOWOFF 0x20 |
277 | #define CCSR_TXENABLED 0x08 |
278 | #define CCSR_TXFLOWON 0x04 |
279 | #define CCSR_TXFLOWOFF 0x02 |
280 | |
281 | /*****************************************************************************/ |
282 | |
283 | /* |
284 | * Define the embedded commands. |
285 | */ |
286 | #define ETC_CMD 0x00 |
287 | #define ETC_STARTBREAK 0x81 |
288 | #define ETC_DELAY 0x82 |
289 | #define ETC_STOPBREAK 0x83 |
290 | |
291 | /*****************************************************************************/ |
292 | #endif |
293 |
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