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1 | #ifndef __SOUND_CS4231_REGS_H |
2 | #define __SOUND_CS4231_REGS_H |
3 | |
4 | /* |
5 | * Copyright (c) by Jaroslav Kysela <perex@perex.cz> |
6 | * Definitions for CS4231 & InterWave chips & compatible chips registers |
7 | * |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or |
12 | * (at your option) any later version. |
13 | * |
14 | * This program is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
17 | * GNU General Public License for more details. |
18 | * |
19 | * You should have received a copy of the GNU General Public License |
20 | * along with this program; if not, write to the Free Software |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
22 | * |
23 | */ |
24 | |
25 | /* IO ports */ |
26 | |
27 | #define CS4231P(x) (c_d_c_CS4231##x) |
28 | |
29 | #define c_d_c_CS4231REGSEL 0 |
30 | #define c_d_c_CS4231REG 1 |
31 | #define c_d_c_CS4231STATUS 2 |
32 | #define c_d_c_CS4231PIO 3 |
33 | |
34 | /* codec registers */ |
35 | |
36 | #define CS4231_LEFT_INPUT 0x00 /* left input control */ |
37 | #define CS4231_RIGHT_INPUT 0x01 /* right input control */ |
38 | #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ |
39 | #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ |
40 | #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ |
41 | #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ |
42 | #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ |
43 | #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ |
44 | #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ |
45 | #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ |
46 | #define CS4231_PIN_CTRL 0x0a /* pin control */ |
47 | #define CS4231_TEST_INIT 0x0b /* test and initialization */ |
48 | #define CS4231_MISC_INFO 0x0c /* miscellaneous information */ |
49 | #define CS4231_LOOPBACK 0x0d /* loopback control */ |
50 | #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ |
51 | #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ |
52 | #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ |
53 | #define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */ |
54 | #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ |
55 | #define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */ |
56 | #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ |
57 | #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ |
58 | #define CS4231_TIMER_LOW 0x14 /* timer low byte */ |
59 | #define CS4231_TIMER_HIGH 0x15 /* timer high byte */ |
60 | #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ |
61 | #define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */ |
62 | #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ |
63 | #define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */ |
64 | #define CS4236_EXT_REG 0x17 /* extended register access */ |
65 | #define CS4231_IRQ_STATUS 0x18 /* irq status register */ |
66 | #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ |
67 | #define CS4231_VERSION 0x19 /* CS4231(A) - version values */ |
68 | #define CS4231_MONO_CTRL 0x1a /* mono input/output control */ |
69 | #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ |
70 | #define AD1845_PWR_DOWN 0x1b /* power down control */ |
71 | #define CS4235_LEFT_MASTER 0x1b /* left master output control */ |
72 | #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ |
73 | #define AD1845_CLOCK 0x1d /* crystal clock select and total power down */ |
74 | #define CS4235_RIGHT_MASTER 0x1d /* right master output control */ |
75 | #define CS4231_REC_UPR_CNT 0x1e /* record upper count */ |
76 | #define CS4231_REC_LWR_CNT 0x1f /* record lower count */ |
77 | |
78 | /* definitions for codec register select port - CODECP( REGSEL ) */ |
79 | |
80 | #define CS4231_INIT 0x80 /* CODEC is initializing */ |
81 | #define CS4231_MCE 0x40 /* mode change enable */ |
82 | #define CS4231_TRD 0x20 /* transfer request disable */ |
83 | |
84 | /* definitions for codec status register - CODECP( STATUS ) */ |
85 | |
86 | #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ |
87 | |
88 | /* definitions for codec irq status */ |
89 | |
90 | #define CS4231_PLAYBACK_IRQ 0x10 |
91 | #define CS4231_RECORD_IRQ 0x20 |
92 | #define CS4231_TIMER_IRQ 0x40 |
93 | #define CS4231_ALL_IRQS 0x70 |
94 | #define CS4231_REC_UNDERRUN 0x08 |
95 | #define CS4231_REC_OVERRUN 0x04 |
96 | #define CS4231_PLY_OVERRUN 0x02 |
97 | #define CS4231_PLY_UNDERRUN 0x01 |
98 | |
99 | /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ |
100 | |
101 | #define CS4231_ENABLE_MIC_GAIN 0x20 |
102 | |
103 | #define CS4231_MIXS_LINE 0x00 |
104 | #define CS4231_MIXS_AUX1 0x40 |
105 | #define CS4231_MIXS_MIC 0x80 |
106 | #define CS4231_MIXS_ALL 0xc0 |
107 | |
108 | /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ |
109 | |
110 | #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ |
111 | #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ |
112 | #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ |
113 | #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ |
114 | #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ |
115 | #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ |
116 | #define CS4231_STEREO 0x10 /* stereo mode */ |
117 | /* bits 3-1 define frequency divisor */ |
118 | #define CS4231_XTAL1 0x00 /* 24.576 crystal */ |
119 | #define CS4231_XTAL2 0x01 /* 16.9344 crystal */ |
120 | |
121 | /* definitions for interface control register - CS4231_IFACE_CTRL */ |
122 | |
123 | #define CS4231_RECORD_PIO 0x80 /* record PIO enable */ |
124 | #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ |
125 | #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ |
126 | #define CS4231_AUTOCALIB 0x08 /* auto calibrate */ |
127 | #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ |
128 | #define CS4231_RECORD_ENABLE 0x02 /* record enable */ |
129 | #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ |
130 | |
131 | /* definitions for pin control register - CS4231_PIN_CTRL */ |
132 | |
133 | #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ |
134 | #define CS4231_XCTL1 0x40 /* external control #1 */ |
135 | #define CS4231_XCTL0 0x80 /* external control #0 */ |
136 | |
137 | /* definitions for test and init register - CS4231_TEST_INIT */ |
138 | |
139 | #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ |
140 | #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ |
141 | |
142 | /* definitions for misc control register - CS4231_MISC_INFO */ |
143 | |
144 | #define CS4231_MODE2 0x40 /* MODE 2 */ |
145 | #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ |
146 | #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ |
147 | |
148 | /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ |
149 | |
150 | #define CS4231_DACZ 0x01 /* zero DAC when underrun */ |
151 | #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ |
152 | #define CS4231_OLB 0x80 /* output level bit */ |
153 | |
154 | /* definitions for Extended Registers - CS4236+ */ |
155 | |
156 | #define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f)) |
157 | #define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8) |
158 | |
159 | #define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */ |
160 | #define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */ |
161 | #define CS4236_LEFT_MIC 0x28 /* left MIC volume */ |
162 | #define CS4236_RIGHT_MIC 0x38 /* right MIC volume */ |
163 | #define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */ |
164 | #define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */ |
165 | #define CS4236_LEFT_FM 0x68 /* left FM volume */ |
166 | #define CS4236_RIGHT_FM 0x78 /* right FM volume */ |
167 | #define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */ |
168 | #define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */ |
169 | #define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */ |
170 | #define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */ |
171 | #define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */ |
172 | #define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */ |
173 | #define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */ |
174 | #define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */ |
175 | #define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */ |
176 | #define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */ |
177 | #define CS4236_VERSION 0x9c /* chip version and ID */ |
178 | |
179 | /* definitions for extended registers - OPTI93X */ |
180 | #define OPTi931_AUX_LEFT_INPUT 0x10 |
181 | #define OPTi931_AUX_RIGHT_INPUT 0x11 |
182 | #define OPTi93X_MIC_LEFT_INPUT 0x14 |
183 | #define OPTi93X_MIC_RIGHT_INPUT 0x15 |
184 | #define OPTi93X_OUT_LEFT 0x16 |
185 | #define OPTi93X_OUT_RIGHT 0x17 |
186 | |
187 | #endif /* __SOUND_CS4231_REGS_H */ |
188 |
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