Root/
1 | menu "Processor features" |
2 | |
3 | choice |
4 | prompt "Endianess selection" |
5 | default CPU_LITTLE_ENDIAN |
6 | help |
7 | Some SuperH machines can be configured for either little or big |
8 | endian byte order. These modes require different kernels. |
9 | |
10 | config CPU_LITTLE_ENDIAN |
11 | bool "Little Endian" |
12 | |
13 | config CPU_BIG_ENDIAN |
14 | bool "Big Endian" |
15 | depends on !CPU_SH5 |
16 | |
17 | endchoice |
18 | |
19 | config SH_FPU |
20 | def_bool y |
21 | prompt "FPU support" |
22 | depends on CPU_HAS_FPU |
23 | help |
24 | Selecting this option will enable support for SH processors that |
25 | have FPU units (ie, SH77xx). |
26 | |
27 | This option must be set in order to enable the FPU. |
28 | |
29 | config SH64_FPU_DENORM_FLUSH |
30 | bool "Flush floating point denorms to zero" |
31 | depends on SH_FPU && SUPERH64 |
32 | |
33 | config SH_FPU_EMU |
34 | def_bool n |
35 | prompt "FPU emulation support" |
36 | depends on !SH_FPU && EXPERIMENTAL |
37 | help |
38 | Selecting this option will enable support for software FPU emulation. |
39 | Most SH-3 users will want to say Y here, whereas most SH-4 users will |
40 | want to say N. |
41 | |
42 | config SH_DSP |
43 | def_bool y |
44 | prompt "DSP support" |
45 | depends on CPU_HAS_DSP |
46 | help |
47 | Selecting this option will enable support for SH processors that |
48 | have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP). |
49 | |
50 | This option must be set in order to enable the DSP. |
51 | |
52 | config SH_ADC |
53 | def_bool y |
54 | prompt "ADC support" |
55 | depends on CPU_SH3 |
56 | help |
57 | Selecting this option will allow the Linux kernel to use SH3 on-chip |
58 | ADC module. |
59 | |
60 | If unsure, say N. |
61 | |
62 | config SH_STORE_QUEUES |
63 | bool "Support for Store Queues" |
64 | depends on CPU_SH4 |
65 | help |
66 | Selecting this option will enable an in-kernel API for manipulating |
67 | the store queues integrated in the SH-4 processors. |
68 | |
69 | config SPECULATIVE_EXECUTION |
70 | bool "Speculative subroutine return" |
71 | depends on EXPERIMENTAL |
72 | depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786 |
73 | help |
74 | This enables support for a speculative instruction fetch for |
75 | subroutine return. There are various pitfalls associated with |
76 | this, as outlined in the SH7780 hardware manual. |
77 | |
78 | If unsure, say N. |
79 | |
80 | config SH64_ID2815_WORKAROUND |
81 | bool "Include workaround for SH5-101 cut2 silicon defect ID2815" |
82 | depends on CPU_SUBTYPE_SH5_101 |
83 | |
84 | config CPU_HAS_INTEVT |
85 | bool |
86 | |
87 | config CPU_HAS_IPR_IRQ |
88 | bool |
89 | |
90 | config CPU_HAS_SR_RB |
91 | bool |
92 | help |
93 | This will enable the use of SR.RB register bank usage. Processors |
94 | that are lacking this bit must have another method in place for |
95 | accomplishing what is taken care of by the banked registers. |
96 | |
97 | See <file:Documentation/sh/register-banks.txt> for further |
98 | information on SR.RB and register banking in the kernel in general. |
99 | |
100 | config CPU_HAS_PTEAEX |
101 | bool |
102 | |
103 | config CPU_HAS_DSP |
104 | bool |
105 | |
106 | config CPU_HAS_FPU |
107 | bool |
108 | |
109 | endmenu |
110 |
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