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1 | /* |
2 | * linux/drivers/char/8250.c |
3 | * |
4 | * Driver for 8250/16550-type serial ports |
5 | * |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. |
7 | * |
8 | * Copyright (C) 2001 Russell King. |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by |
12 | * the Free Software Foundation; either version 2 of the License, or |
13 | * (at your option) any later version. |
14 | * |
15 | * A note about mapbase / membase |
16 | * |
17 | * mapbase is the physical address of the IO port. |
18 | * membase is an 'ioremapped' cookie. |
19 | */ |
20 | |
21 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
22 | #define SUPPORT_SYSRQ |
23 | #endif |
24 | |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> |
27 | #include <linux/ioport.h> |
28 | #include <linux/init.h> |
29 | #include <linux/console.h> |
30 | #include <linux/sysrq.h> |
31 | #include <linux/delay.h> |
32 | #include <linux/platform_device.h> |
33 | #include <linux/tty.h> |
34 | #include <linux/tty_flip.h> |
35 | #include <linux/serial_reg.h> |
36 | #include <linux/serial_core.h> |
37 | #include <linux/serial.h> |
38 | #include <linux/serial_8250.h> |
39 | #include <linux/nmi.h> |
40 | #include <linux/mutex.h> |
41 | #include <linux/slab.h> |
42 | |
43 | #include <asm/io.h> |
44 | #include <asm/irq.h> |
45 | |
46 | #include "8250.h" |
47 | |
48 | #ifdef CONFIG_SPARC |
49 | #include "suncore.h" |
50 | #endif |
51 | |
52 | /* |
53 | * Configuration: |
54 | * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option |
55 | * is unsafe when used on edge-triggered interrupts. |
56 | */ |
57 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; |
58 | |
59 | static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; |
60 | |
61 | static struct uart_driver serial8250_reg; |
62 | |
63 | static int serial_index(struct uart_port *port) |
64 | { |
65 | return (serial8250_reg.minor - 64) + port->line; |
66 | } |
67 | |
68 | static unsigned int skip_txen_test; /* force skip of txen test at init time */ |
69 | |
70 | /* |
71 | * Debugging. |
72 | */ |
73 | #if 0 |
74 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) |
75 | #else |
76 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) |
77 | #endif |
78 | |
79 | #if 0 |
80 | #define DEBUG_INTR(fmt...) printk(fmt) |
81 | #else |
82 | #define DEBUG_INTR(fmt...) do { } while (0) |
83 | #endif |
84 | |
85 | #define PASS_LIMIT 256 |
86 | |
87 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
88 | |
89 | |
90 | /* |
91 | * We default to IRQ0 for the "no irq" hack. Some |
92 | * machine types want others as well - they're free |
93 | * to redefine this in their header file. |
94 | */ |
95 | #define is_real_interrupt(irq) ((irq) != 0) |
96 | |
97 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ |
98 | #define CONFIG_SERIAL_DETECT_IRQ 1 |
99 | #endif |
100 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS |
101 | #define CONFIG_SERIAL_MANY_PORTS 1 |
102 | #endif |
103 | |
104 | /* |
105 | * HUB6 is always on. This will be removed once the header |
106 | * files have been cleaned. |
107 | */ |
108 | #define CONFIG_HUB6 1 |
109 | |
110 | #include <asm/serial.h> |
111 | /* |
112 | * SERIAL_PORT_DFNS tells us about built-in ports that have no |
113 | * standard enumeration mechanism. Platforms that can find all |
114 | * serial ports via mechanisms like ACPI or PCI need not supply it. |
115 | */ |
116 | #ifndef SERIAL_PORT_DFNS |
117 | #define SERIAL_PORT_DFNS |
118 | #endif |
119 | |
120 | static const struct old_serial_port old_serial_port[] = { |
121 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ |
122 | }; |
123 | |
124 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS |
125 | |
126 | #ifdef CONFIG_SERIAL_8250_RSA |
127 | |
128 | #define PORT_RSA_MAX 4 |
129 | static unsigned long probe_rsa[PORT_RSA_MAX]; |
130 | static unsigned int probe_rsa_count; |
131 | #endif /* CONFIG_SERIAL_8250_RSA */ |
132 | |
133 | struct uart_8250_port { |
134 | struct uart_port port; |
135 | struct timer_list timer; /* "no irq" timer */ |
136 | struct list_head list; /* ports on this IRQ */ |
137 | unsigned short capabilities; /* port capabilities */ |
138 | unsigned short bugs; /* port bugs */ |
139 | unsigned int tx_loadsz; /* transmit fifo load size */ |
140 | unsigned char acr; |
141 | unsigned char ier; |
142 | unsigned char lcr; |
143 | unsigned char mcr; |
144 | unsigned char mcr_mask; /* mask of user bits */ |
145 | unsigned char mcr_force; /* mask of forced bits */ |
146 | unsigned char cur_iotype; /* Running I/O type */ |
147 | |
148 | /* |
149 | * Some bits in registers are cleared on a read, so they must |
150 | * be saved whenever the register is read but the bits will not |
151 | * be immediately processed. |
152 | */ |
153 | #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS |
154 | unsigned char lsr_saved_flags; |
155 | #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA |
156 | unsigned char msr_saved_flags; |
157 | |
158 | /* |
159 | * We provide a per-port pm hook. |
160 | */ |
161 | void (*pm)(struct uart_port *port, |
162 | unsigned int state, unsigned int old); |
163 | }; |
164 | |
165 | struct irq_info { |
166 | struct hlist_node node; |
167 | int irq; |
168 | spinlock_t lock; /* Protects list not the hash */ |
169 | struct list_head *head; |
170 | }; |
171 | |
172 | #define NR_IRQ_HASH 32 /* Can be adjusted later */ |
173 | static struct hlist_head irq_lists[NR_IRQ_HASH]; |
174 | static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */ |
175 | |
176 | /* |
177 | * Here we define the default xmit fifo size used for each type of UART. |
178 | */ |
179 | static const struct serial8250_config uart_config[] = { |
180 | [PORT_UNKNOWN] = { |
181 | .name = "unknown", |
182 | .fifo_size = 1, |
183 | .tx_loadsz = 1, |
184 | }, |
185 | [PORT_8250] = { |
186 | .name = "8250", |
187 | .fifo_size = 1, |
188 | .tx_loadsz = 1, |
189 | }, |
190 | [PORT_16450] = { |
191 | .name = "16450", |
192 | .fifo_size = 1, |
193 | .tx_loadsz = 1, |
194 | }, |
195 | [PORT_16550] = { |
196 | .name = "16550", |
197 | .fifo_size = 1, |
198 | .tx_loadsz = 1, |
199 | }, |
200 | [PORT_16550A] = { |
201 | .name = "16550A", |
202 | .fifo_size = 16, |
203 | .tx_loadsz = 16, |
204 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
205 | .flags = UART_CAP_FIFO, |
206 | }, |
207 | [PORT_CIRRUS] = { |
208 | .name = "Cirrus", |
209 | .fifo_size = 1, |
210 | .tx_loadsz = 1, |
211 | }, |
212 | [PORT_16650] = { |
213 | .name = "ST16650", |
214 | .fifo_size = 1, |
215 | .tx_loadsz = 1, |
216 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
217 | }, |
218 | [PORT_16650V2] = { |
219 | .name = "ST16650V2", |
220 | .fifo_size = 32, |
221 | .tx_loadsz = 16, |
222 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | |
223 | UART_FCR_T_TRIG_00, |
224 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
225 | }, |
226 | [PORT_16750] = { |
227 | .name = "TI16750", |
228 | .fifo_size = 64, |
229 | .tx_loadsz = 64, |
230 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | |
231 | UART_FCR7_64BYTE, |
232 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, |
233 | }, |
234 | [PORT_STARTECH] = { |
235 | .name = "Startech", |
236 | .fifo_size = 1, |
237 | .tx_loadsz = 1, |
238 | }, |
239 | [PORT_16C950] = { |
240 | .name = "16C950/954", |
241 | .fifo_size = 128, |
242 | .tx_loadsz = 128, |
243 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
244 | .flags = UART_CAP_FIFO, |
245 | }, |
246 | [PORT_16654] = { |
247 | .name = "ST16654", |
248 | .fifo_size = 64, |
249 | .tx_loadsz = 32, |
250 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | |
251 | UART_FCR_T_TRIG_10, |
252 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
253 | }, |
254 | [PORT_16850] = { |
255 | .name = "XR16850", |
256 | .fifo_size = 128, |
257 | .tx_loadsz = 128, |
258 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
259 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
260 | }, |
261 | [PORT_RSA] = { |
262 | .name = "RSA", |
263 | .fifo_size = 2048, |
264 | .tx_loadsz = 2048, |
265 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, |
266 | .flags = UART_CAP_FIFO, |
267 | }, |
268 | [PORT_NS16550A] = { |
269 | .name = "NS16550A", |
270 | .fifo_size = 16, |
271 | .tx_loadsz = 16, |
272 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
273 | .flags = UART_CAP_FIFO | UART_NATSEMI, |
274 | }, |
275 | [PORT_XSCALE] = { |
276 | .name = "XScale", |
277 | .fifo_size = 32, |
278 | .tx_loadsz = 32, |
279 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
280 | .flags = UART_CAP_FIFO | UART_CAP_UUE, |
281 | }, |
282 | [PORT_RM9000] = { |
283 | .name = "RM9000", |
284 | .fifo_size = 16, |
285 | .tx_loadsz = 16, |
286 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
287 | .flags = UART_CAP_FIFO, |
288 | }, |
289 | [PORT_OCTEON] = { |
290 | .name = "OCTEON", |
291 | .fifo_size = 64, |
292 | .tx_loadsz = 64, |
293 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
294 | .flags = UART_CAP_FIFO, |
295 | }, |
296 | [PORT_AR7] = { |
297 | .name = "AR7", |
298 | .fifo_size = 16, |
299 | .tx_loadsz = 16, |
300 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, |
301 | .flags = UART_CAP_FIFO | UART_CAP_AFE, |
302 | }, |
303 | }; |
304 | |
305 | #if defined (CONFIG_SERIAL_8250_AU1X00) |
306 | |
307 | /* Au1x00 UART hardware has a weird register layout */ |
308 | static const u8 au_io_in_map[] = { |
309 | [UART_RX] = 0, |
310 | [UART_IER] = 2, |
311 | [UART_IIR] = 3, |
312 | [UART_LCR] = 5, |
313 | [UART_MCR] = 6, |
314 | [UART_LSR] = 7, |
315 | [UART_MSR] = 8, |
316 | }; |
317 | |
318 | static const u8 au_io_out_map[] = { |
319 | [UART_TX] = 1, |
320 | [UART_IER] = 2, |
321 | [UART_FCR] = 4, |
322 | [UART_LCR] = 5, |
323 | [UART_MCR] = 6, |
324 | }; |
325 | |
326 | /* sane hardware needs no mapping */ |
327 | static inline int map_8250_in_reg(struct uart_port *p, int offset) |
328 | { |
329 | if (p->iotype != UPIO_AU) |
330 | return offset; |
331 | return au_io_in_map[offset]; |
332 | } |
333 | |
334 | static inline int map_8250_out_reg(struct uart_port *p, int offset) |
335 | { |
336 | if (p->iotype != UPIO_AU) |
337 | return offset; |
338 | return au_io_out_map[offset]; |
339 | } |
340 | |
341 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
342 | |
343 | static const u8 |
344 | regmap_in[8] = { |
345 | [UART_RX] = 0x00, |
346 | [UART_IER] = 0x0c, |
347 | [UART_IIR] = 0x14, |
348 | [UART_LCR] = 0x1c, |
349 | [UART_MCR] = 0x20, |
350 | [UART_LSR] = 0x24, |
351 | [UART_MSR] = 0x28, |
352 | [UART_SCR] = 0x2c |
353 | }, |
354 | regmap_out[8] = { |
355 | [UART_TX] = 0x04, |
356 | [UART_IER] = 0x0c, |
357 | [UART_FCR] = 0x18, |
358 | [UART_LCR] = 0x1c, |
359 | [UART_MCR] = 0x20, |
360 | [UART_LSR] = 0x24, |
361 | [UART_MSR] = 0x28, |
362 | [UART_SCR] = 0x2c |
363 | }; |
364 | |
365 | static inline int map_8250_in_reg(struct uart_port *p, int offset) |
366 | { |
367 | if (p->iotype != UPIO_RM9000) |
368 | return offset; |
369 | return regmap_in[offset]; |
370 | } |
371 | |
372 | static inline int map_8250_out_reg(struct uart_port *p, int offset) |
373 | { |
374 | if (p->iotype != UPIO_RM9000) |
375 | return offset; |
376 | return regmap_out[offset]; |
377 | } |
378 | |
379 | #else |
380 | |
381 | /* sane hardware needs no mapping */ |
382 | #define map_8250_in_reg(up, offset) (offset) |
383 | #define map_8250_out_reg(up, offset) (offset) |
384 | |
385 | #endif |
386 | |
387 | static unsigned int hub6_serial_in(struct uart_port *p, int offset) |
388 | { |
389 | offset = map_8250_in_reg(p, offset) << p->regshift; |
390 | outb(p->hub6 - 1 + offset, p->iobase); |
391 | return inb(p->iobase + 1); |
392 | } |
393 | |
394 | static void hub6_serial_out(struct uart_port *p, int offset, int value) |
395 | { |
396 | offset = map_8250_out_reg(p, offset) << p->regshift; |
397 | outb(p->hub6 - 1 + offset, p->iobase); |
398 | outb(value, p->iobase + 1); |
399 | } |
400 | |
401 | static unsigned int mem_serial_in(struct uart_port *p, int offset) |
402 | { |
403 | offset = map_8250_in_reg(p, offset) << p->regshift; |
404 | return readb(p->membase + offset); |
405 | } |
406 | |
407 | static void mem_serial_out(struct uart_port *p, int offset, int value) |
408 | { |
409 | offset = map_8250_out_reg(p, offset) << p->regshift; |
410 | writeb(value, p->membase + offset); |
411 | } |
412 | |
413 | static void mem32_serial_out(struct uart_port *p, int offset, int value) |
414 | { |
415 | offset = map_8250_out_reg(p, offset) << p->regshift; |
416 | writel(value, p->membase + offset); |
417 | } |
418 | |
419 | static unsigned int mem32_serial_in(struct uart_port *p, int offset) |
420 | { |
421 | offset = map_8250_in_reg(p, offset) << p->regshift; |
422 | return readl(p->membase + offset); |
423 | } |
424 | |
425 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
426 | static unsigned int au_serial_in(struct uart_port *p, int offset) |
427 | { |
428 | offset = map_8250_in_reg(p, offset) << p->regshift; |
429 | return __raw_readl(p->membase + offset); |
430 | } |
431 | |
432 | static void au_serial_out(struct uart_port *p, int offset, int value) |
433 | { |
434 | offset = map_8250_out_reg(p, offset) << p->regshift; |
435 | __raw_writel(value, p->membase + offset); |
436 | } |
437 | #endif |
438 | |
439 | static unsigned int tsi_serial_in(struct uart_port *p, int offset) |
440 | { |
441 | unsigned int tmp; |
442 | offset = map_8250_in_reg(p, offset) << p->regshift; |
443 | if (offset == UART_IIR) { |
444 | tmp = readl(p->membase + (UART_IIR & ~3)); |
445 | return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */ |
446 | } else |
447 | return readb(p->membase + offset); |
448 | } |
449 | |
450 | static void tsi_serial_out(struct uart_port *p, int offset, int value) |
451 | { |
452 | offset = map_8250_out_reg(p, offset) << p->regshift; |
453 | if (!((offset == UART_IER) && (value & UART_IER_UUE))) |
454 | writeb(value, p->membase + offset); |
455 | } |
456 | |
457 | static void dwapb_serial_out(struct uart_port *p, int offset, int value) |
458 | { |
459 | int save_offset = offset; |
460 | offset = map_8250_out_reg(p, offset) << p->regshift; |
461 | /* Save the LCR value so it can be re-written when a |
462 | * Busy Detect interrupt occurs. */ |
463 | if (save_offset == UART_LCR) { |
464 | struct uart_8250_port *up = (struct uart_8250_port *)p; |
465 | up->lcr = value; |
466 | } |
467 | writeb(value, p->membase + offset); |
468 | /* Read the IER to ensure any interrupt is cleared before |
469 | * returning from ISR. */ |
470 | if (save_offset == UART_TX || save_offset == UART_IER) |
471 | value = p->serial_in(p, UART_IER); |
472 | } |
473 | |
474 | static unsigned int io_serial_in(struct uart_port *p, int offset) |
475 | { |
476 | offset = map_8250_in_reg(p, offset) << p->regshift; |
477 | return inb(p->iobase + offset); |
478 | } |
479 | |
480 | static void io_serial_out(struct uart_port *p, int offset, int value) |
481 | { |
482 | offset = map_8250_out_reg(p, offset) << p->regshift; |
483 | outb(value, p->iobase + offset); |
484 | } |
485 | |
486 | static void set_io_from_upio(struct uart_port *p) |
487 | { |
488 | struct uart_8250_port *up = (struct uart_8250_port *)p; |
489 | switch (p->iotype) { |
490 | case UPIO_HUB6: |
491 | p->serial_in = hub6_serial_in; |
492 | p->serial_out = hub6_serial_out; |
493 | break; |
494 | |
495 | case UPIO_MEM: |
496 | p->serial_in = mem_serial_in; |
497 | p->serial_out = mem_serial_out; |
498 | break; |
499 | |
500 | case UPIO_RM9000: |
501 | case UPIO_MEM32: |
502 | p->serial_in = mem32_serial_in; |
503 | p->serial_out = mem32_serial_out; |
504 | break; |
505 | |
506 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
507 | case UPIO_AU: |
508 | p->serial_in = au_serial_in; |
509 | p->serial_out = au_serial_out; |
510 | break; |
511 | #endif |
512 | case UPIO_TSI: |
513 | p->serial_in = tsi_serial_in; |
514 | p->serial_out = tsi_serial_out; |
515 | break; |
516 | |
517 | case UPIO_DWAPB: |
518 | p->serial_in = mem_serial_in; |
519 | p->serial_out = dwapb_serial_out; |
520 | break; |
521 | |
522 | default: |
523 | p->serial_in = io_serial_in; |
524 | p->serial_out = io_serial_out; |
525 | break; |
526 | } |
527 | /* Remember loaded iotype */ |
528 | up->cur_iotype = p->iotype; |
529 | } |
530 | |
531 | static void |
532 | serial_out_sync(struct uart_8250_port *up, int offset, int value) |
533 | { |
534 | struct uart_port *p = &up->port; |
535 | switch (p->iotype) { |
536 | case UPIO_MEM: |
537 | case UPIO_MEM32: |
538 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
539 | case UPIO_AU: |
540 | #endif |
541 | case UPIO_DWAPB: |
542 | p->serial_out(p, offset, value); |
543 | p->serial_in(p, UART_LCR); /* safe, no side-effects */ |
544 | break; |
545 | default: |
546 | p->serial_out(p, offset, value); |
547 | } |
548 | } |
549 | |
550 | #define serial_in(up, offset) \ |
551 | (up->port.serial_in(&(up)->port, (offset))) |
552 | #define serial_out(up, offset, value) \ |
553 | (up->port.serial_out(&(up)->port, (offset), (value))) |
554 | /* |
555 | * We used to support using pause I/O for certain machines. We |
556 | * haven't supported this for a while, but just in case it's badly |
557 | * needed for certain old 386 machines, I've left these #define's |
558 | * in.... |
559 | */ |
560 | #define serial_inp(up, offset) serial_in(up, offset) |
561 | #define serial_outp(up, offset, value) serial_out(up, offset, value) |
562 | |
563 | /* Uart divisor latch read */ |
564 | static inline int _serial_dl_read(struct uart_8250_port *up) |
565 | { |
566 | return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8; |
567 | } |
568 | |
569 | /* Uart divisor latch write */ |
570 | static inline void _serial_dl_write(struct uart_8250_port *up, int value) |
571 | { |
572 | serial_outp(up, UART_DLL, value & 0xff); |
573 | serial_outp(up, UART_DLM, value >> 8 & 0xff); |
574 | } |
575 | |
576 | #if defined(CONFIG_SERIAL_8250_AU1X00) |
577 | /* Au1x00 haven't got a standard divisor latch */ |
578 | static int serial_dl_read(struct uart_8250_port *up) |
579 | { |
580 | if (up->port.iotype == UPIO_AU) |
581 | return __raw_readl(up->port.membase + 0x28); |
582 | else |
583 | return _serial_dl_read(up); |
584 | } |
585 | |
586 | static void serial_dl_write(struct uart_8250_port *up, int value) |
587 | { |
588 | if (up->port.iotype == UPIO_AU) |
589 | __raw_writel(value, up->port.membase + 0x28); |
590 | else |
591 | _serial_dl_write(up, value); |
592 | } |
593 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
594 | static int serial_dl_read(struct uart_8250_port *up) |
595 | { |
596 | return (up->port.iotype == UPIO_RM9000) ? |
597 | (((__raw_readl(up->port.membase + 0x10) << 8) | |
598 | (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) : |
599 | _serial_dl_read(up); |
600 | } |
601 | |
602 | static void serial_dl_write(struct uart_8250_port *up, int value) |
603 | { |
604 | if (up->port.iotype == UPIO_RM9000) { |
605 | __raw_writel(value, up->port.membase + 0x08); |
606 | __raw_writel(value >> 8, up->port.membase + 0x10); |
607 | } else { |
608 | _serial_dl_write(up, value); |
609 | } |
610 | } |
611 | #else |
612 | #define serial_dl_read(up) _serial_dl_read(up) |
613 | #define serial_dl_write(up, value) _serial_dl_write(up, value) |
614 | #endif |
615 | |
616 | /* |
617 | * For the 16C950 |
618 | */ |
619 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) |
620 | { |
621 | serial_out(up, UART_SCR, offset); |
622 | serial_out(up, UART_ICR, value); |
623 | } |
624 | |
625 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) |
626 | { |
627 | unsigned int value; |
628 | |
629 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); |
630 | serial_out(up, UART_SCR, offset); |
631 | value = serial_in(up, UART_ICR); |
632 | serial_icr_write(up, UART_ACR, up->acr); |
633 | |
634 | return value; |
635 | } |
636 | |
637 | /* |
638 | * FIFO support. |
639 | */ |
640 | static void serial8250_clear_fifos(struct uart_8250_port *p) |
641 | { |
642 | if (p->capabilities & UART_CAP_FIFO) { |
643 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO); |
644 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO | |
645 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
646 | serial_outp(p, UART_FCR, 0); |
647 | } |
648 | } |
649 | |
650 | /* |
651 | * IER sleep support. UARTs which have EFRs need the "extended |
652 | * capability" bit enabled. Note that on XR16C850s, we need to |
653 | * reset LCR to write to IER. |
654 | */ |
655 | static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) |
656 | { |
657 | if (p->capabilities & UART_CAP_SLEEP) { |
658 | if (p->capabilities & UART_CAP_EFR) { |
659 | serial_outp(p, UART_LCR, 0xBF); |
660 | serial_outp(p, UART_EFR, UART_EFR_ECB); |
661 | serial_outp(p, UART_LCR, 0); |
662 | } |
663 | serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); |
664 | if (p->capabilities & UART_CAP_EFR) { |
665 | serial_outp(p, UART_LCR, 0xBF); |
666 | serial_outp(p, UART_EFR, 0); |
667 | serial_outp(p, UART_LCR, 0); |
668 | } |
669 | } |
670 | } |
671 | |
672 | #ifdef CONFIG_SERIAL_8250_RSA |
673 | /* |
674 | * Attempts to turn on the RSA FIFO. Returns zero on failure. |
675 | * We set the port uart clock rate if we succeed. |
676 | */ |
677 | static int __enable_rsa(struct uart_8250_port *up) |
678 | { |
679 | unsigned char mode; |
680 | int result; |
681 | |
682 | mode = serial_inp(up, UART_RSA_MSR); |
683 | result = mode & UART_RSA_MSR_FIFO; |
684 | |
685 | if (!result) { |
686 | serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); |
687 | mode = serial_inp(up, UART_RSA_MSR); |
688 | result = mode & UART_RSA_MSR_FIFO; |
689 | } |
690 | |
691 | if (result) |
692 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; |
693 | |
694 | return result; |
695 | } |
696 | |
697 | static void enable_rsa(struct uart_8250_port *up) |
698 | { |
699 | if (up->port.type == PORT_RSA) { |
700 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { |
701 | spin_lock_irq(&up->port.lock); |
702 | __enable_rsa(up); |
703 | spin_unlock_irq(&up->port.lock); |
704 | } |
705 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) |
706 | serial_outp(up, UART_RSA_FRR, 0); |
707 | } |
708 | } |
709 | |
710 | /* |
711 | * Attempts to turn off the RSA FIFO. Returns zero on failure. |
712 | * It is unknown why interrupts were disabled in here. However, |
713 | * the caller is expected to preserve this behaviour by grabbing |
714 | * the spinlock before calling this function. |
715 | */ |
716 | static void disable_rsa(struct uart_8250_port *up) |
717 | { |
718 | unsigned char mode; |
719 | int result; |
720 | |
721 | if (up->port.type == PORT_RSA && |
722 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { |
723 | spin_lock_irq(&up->port.lock); |
724 | |
725 | mode = serial_inp(up, UART_RSA_MSR); |
726 | result = !(mode & UART_RSA_MSR_FIFO); |
727 | |
728 | if (!result) { |
729 | serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); |
730 | mode = serial_inp(up, UART_RSA_MSR); |
731 | result = !(mode & UART_RSA_MSR_FIFO); |
732 | } |
733 | |
734 | if (result) |
735 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; |
736 | spin_unlock_irq(&up->port.lock); |
737 | } |
738 | } |
739 | #endif /* CONFIG_SERIAL_8250_RSA */ |
740 | |
741 | /* |
742 | * This is a quickie test to see how big the FIFO is. |
743 | * It doesn't work at all the time, more's the pity. |
744 | */ |
745 | static int size_fifo(struct uart_8250_port *up) |
746 | { |
747 | unsigned char old_fcr, old_mcr, old_lcr; |
748 | unsigned short old_dl; |
749 | int count; |
750 | |
751 | old_lcr = serial_inp(up, UART_LCR); |
752 | serial_outp(up, UART_LCR, 0); |
753 | old_fcr = serial_inp(up, UART_FCR); |
754 | old_mcr = serial_inp(up, UART_MCR); |
755 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | |
756 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
757 | serial_outp(up, UART_MCR, UART_MCR_LOOP); |
758 | serial_outp(up, UART_LCR, UART_LCR_DLAB); |
759 | old_dl = serial_dl_read(up); |
760 | serial_dl_write(up, 0x0001); |
761 | serial_outp(up, UART_LCR, 0x03); |
762 | for (count = 0; count < 256; count++) |
763 | serial_outp(up, UART_TX, count); |
764 | mdelay(20);/* FIXME - schedule_timeout */ |
765 | for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) && |
766 | (count < 256); count++) |
767 | serial_inp(up, UART_RX); |
768 | serial_outp(up, UART_FCR, old_fcr); |
769 | serial_outp(up, UART_MCR, old_mcr); |
770 | serial_outp(up, UART_LCR, UART_LCR_DLAB); |
771 | serial_dl_write(up, old_dl); |
772 | serial_outp(up, UART_LCR, old_lcr); |
773 | |
774 | return count; |
775 | } |
776 | |
777 | /* |
778 | * Read UART ID using the divisor method - set DLL and DLM to zero |
779 | * and the revision will be in DLL and device type in DLM. We |
780 | * preserve the device state across this. |
781 | */ |
782 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) |
783 | { |
784 | unsigned char old_dll, old_dlm, old_lcr; |
785 | unsigned int id; |
786 | |
787 | old_lcr = serial_inp(p, UART_LCR); |
788 | serial_outp(p, UART_LCR, UART_LCR_DLAB); |
789 | |
790 | old_dll = serial_inp(p, UART_DLL); |
791 | old_dlm = serial_inp(p, UART_DLM); |
792 | |
793 | serial_outp(p, UART_DLL, 0); |
794 | serial_outp(p, UART_DLM, 0); |
795 | |
796 | id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; |
797 | |
798 | serial_outp(p, UART_DLL, old_dll); |
799 | serial_outp(p, UART_DLM, old_dlm); |
800 | serial_outp(p, UART_LCR, old_lcr); |
801 | |
802 | return id; |
803 | } |
804 | |
805 | /* |
806 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. |
807 | * When this function is called we know it is at least a StarTech |
808 | * 16650 V2, but it might be one of several StarTech UARTs, or one of |
809 | * its clones. (We treat the broken original StarTech 16650 V1 as a |
810 | * 16550, and why not? Startech doesn't seem to even acknowledge its |
811 | * existence.) |
812 | * |
813 | * What evil have men's minds wrought... |
814 | */ |
815 | static void autoconfig_has_efr(struct uart_8250_port *up) |
816 | { |
817 | unsigned int id1, id2, id3, rev; |
818 | |
819 | /* |
820 | * Everything with an EFR has SLEEP |
821 | */ |
822 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; |
823 | |
824 | /* |
825 | * First we check to see if it's an Oxford Semiconductor UART. |
826 | * |
827 | * If we have to do this here because some non-National |
828 | * Semiconductor clone chips lock up if you try writing to the |
829 | * LSR register (which serial_icr_read does) |
830 | */ |
831 | |
832 | /* |
833 | * Check for Oxford Semiconductor 16C950. |
834 | * |
835 | * EFR [4] must be set else this test fails. |
836 | * |
837 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) |
838 | * claims that it's needed for 952 dual UART's (which are not |
839 | * recommended for new designs). |
840 | */ |
841 | up->acr = 0; |
842 | serial_out(up, UART_LCR, 0xBF); |
843 | serial_out(up, UART_EFR, UART_EFR_ECB); |
844 | serial_out(up, UART_LCR, 0x00); |
845 | id1 = serial_icr_read(up, UART_ID1); |
846 | id2 = serial_icr_read(up, UART_ID2); |
847 | id3 = serial_icr_read(up, UART_ID3); |
848 | rev = serial_icr_read(up, UART_REV); |
849 | |
850 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); |
851 | |
852 | if (id1 == 0x16 && id2 == 0xC9 && |
853 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { |
854 | up->port.type = PORT_16C950; |
855 | |
856 | /* |
857 | * Enable work around for the Oxford Semiconductor 952 rev B |
858 | * chip which causes it to seriously miscalculate baud rates |
859 | * when DLL is 0. |
860 | */ |
861 | if (id3 == 0x52 && rev == 0x01) |
862 | up->bugs |= UART_BUG_QUOT; |
863 | return; |
864 | } |
865 | |
866 | /* |
867 | * We check for a XR16C850 by setting DLL and DLM to 0, and then |
868 | * reading back DLL and DLM. The chip type depends on the DLM |
869 | * value read back: |
870 | * 0x10 - XR16C850 and the DLL contains the chip revision. |
871 | * 0x12 - XR16C2850. |
872 | * 0x14 - XR16C854. |
873 | */ |
874 | id1 = autoconfig_read_divisor_id(up); |
875 | DEBUG_AUTOCONF("850id=%04x ", id1); |
876 | |
877 | id2 = id1 >> 8; |
878 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { |
879 | up->port.type = PORT_16850; |
880 | return; |
881 | } |
882 | |
883 | /* |
884 | * It wasn't an XR16C850. |
885 | * |
886 | * We distinguish between the '654 and the '650 by counting |
887 | * how many bytes are in the FIFO. I'm using this for now, |
888 | * since that's the technique that was sent to me in the |
889 | * serial driver update, but I'm not convinced this works. |
890 | * I've had problems doing this in the past. -TYT |
891 | */ |
892 | if (size_fifo(up) == 64) |
893 | up->port.type = PORT_16654; |
894 | else |
895 | up->port.type = PORT_16650V2; |
896 | } |
897 | |
898 | /* |
899 | * We detected a chip without a FIFO. Only two fall into |
900 | * this category - the original 8250 and the 16450. The |
901 | * 16450 has a scratch register (accessible with LCR=0) |
902 | */ |
903 | static void autoconfig_8250(struct uart_8250_port *up) |
904 | { |
905 | unsigned char scratch, status1, status2; |
906 | |
907 | up->port.type = PORT_8250; |
908 | |
909 | scratch = serial_in(up, UART_SCR); |
910 | serial_outp(up, UART_SCR, 0xa5); |
911 | status1 = serial_in(up, UART_SCR); |
912 | serial_outp(up, UART_SCR, 0x5a); |
913 | status2 = serial_in(up, UART_SCR); |
914 | serial_outp(up, UART_SCR, scratch); |
915 | |
916 | if (status1 == 0xa5 && status2 == 0x5a) |
917 | up->port.type = PORT_16450; |
918 | } |
919 | |
920 | static int broken_efr(struct uart_8250_port *up) |
921 | { |
922 | /* |
923 | * Exar ST16C2550 "A2" devices incorrectly detect as |
924 | * having an EFR, and report an ID of 0x0201. See |
925 | * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf |
926 | */ |
927 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) |
928 | return 1; |
929 | |
930 | return 0; |
931 | } |
932 | |
933 | /* |
934 | * We know that the chip has FIFOs. Does it have an EFR? The |
935 | * EFR is located in the same register position as the IIR and |
936 | * we know the top two bits of the IIR are currently set. The |
937 | * EFR should contain zero. Try to read the EFR. |
938 | */ |
939 | static void autoconfig_16550a(struct uart_8250_port *up) |
940 | { |
941 | unsigned char status1, status2; |
942 | unsigned int iersave; |
943 | |
944 | up->port.type = PORT_16550A; |
945 | up->capabilities |= UART_CAP_FIFO; |
946 | |
947 | /* |
948 | * Check for presence of the EFR when DLAB is set. |
949 | * Only ST16C650V1 UARTs pass this test. |
950 | */ |
951 | serial_outp(up, UART_LCR, UART_LCR_DLAB); |
952 | if (serial_in(up, UART_EFR) == 0) { |
953 | serial_outp(up, UART_EFR, 0xA8); |
954 | if (serial_in(up, UART_EFR) != 0) { |
955 | DEBUG_AUTOCONF("EFRv1 "); |
956 | up->port.type = PORT_16650; |
957 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; |
958 | } else { |
959 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); |
960 | } |
961 | serial_outp(up, UART_EFR, 0); |
962 | return; |
963 | } |
964 | |
965 | /* |
966 | * Maybe it requires 0xbf to be written to the LCR. |
967 | * (other ST16C650V2 UARTs, TI16C752A, etc) |
968 | */ |
969 | serial_outp(up, UART_LCR, 0xBF); |
970 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { |
971 | DEBUG_AUTOCONF("EFRv2 "); |
972 | autoconfig_has_efr(up); |
973 | return; |
974 | } |
975 | |
976 | /* |
977 | * Check for a National Semiconductor SuperIO chip. |
978 | * Attempt to switch to bank 2, read the value of the LOOP bit |
979 | * from EXCR1. Switch back to bank 0, change it in MCR. Then |
980 | * switch back to bank 2, read it from EXCR1 again and check |
981 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 |
982 | */ |
983 | serial_outp(up, UART_LCR, 0); |
984 | status1 = serial_in(up, UART_MCR); |
985 | serial_outp(up, UART_LCR, 0xE0); |
986 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
987 | |
988 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { |
989 | serial_outp(up, UART_LCR, 0); |
990 | serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP); |
991 | serial_outp(up, UART_LCR, 0xE0); |
992 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
993 | serial_outp(up, UART_LCR, 0); |
994 | serial_outp(up, UART_MCR, status1); |
995 | |
996 | if ((status2 ^ status1) & UART_MCR_LOOP) { |
997 | unsigned short quot; |
998 | |
999 | serial_outp(up, UART_LCR, 0xE0); |
1000 | |
1001 | quot = serial_dl_read(up); |
1002 | quot <<= 3; |
1003 | |
1004 | status1 = serial_in(up, 0x04); /* EXCR2 */ |
1005 | status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ |
1006 | status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ |
1007 | serial_outp(up, 0x04, status1); |
1008 | |
1009 | serial_dl_write(up, quot); |
1010 | |
1011 | serial_outp(up, UART_LCR, 0); |
1012 | |
1013 | up->port.uartclk = 921600*16; |
1014 | up->port.type = PORT_NS16550A; |
1015 | up->capabilities |= UART_NATSEMI; |
1016 | return; |
1017 | } |
1018 | } |
1019 | |
1020 | /* |
1021 | * No EFR. Try to detect a TI16750, which only sets bit 5 of |
1022 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. |
1023 | * Try setting it with and without DLAB set. Cheap clones |
1024 | * set bit 5 without DLAB set. |
1025 | */ |
1026 | serial_outp(up, UART_LCR, 0); |
1027 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); |
1028 | status1 = serial_in(up, UART_IIR) >> 5; |
1029 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1030 | serial_outp(up, UART_LCR, UART_LCR_DLAB); |
1031 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); |
1032 | status2 = serial_in(up, UART_IIR) >> 5; |
1033 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1034 | serial_outp(up, UART_LCR, 0); |
1035 | |
1036 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); |
1037 | |
1038 | if (status1 == 6 && status2 == 7) { |
1039 | up->port.type = PORT_16750; |
1040 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; |
1041 | return; |
1042 | } |
1043 | |
1044 | /* |
1045 | * Try writing and reading the UART_IER_UUE bit (b6). |
1046 | * If it works, this is probably one of the Xscale platform's |
1047 | * internal UARTs. |
1048 | * We're going to explicitly set the UUE bit to 0 before |
1049 | * trying to write and read a 1 just to make sure it's not |
1050 | * already a 1 and maybe locked there before we even start start. |
1051 | */ |
1052 | iersave = serial_in(up, UART_IER); |
1053 | serial_outp(up, UART_IER, iersave & ~UART_IER_UUE); |
1054 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { |
1055 | /* |
1056 | * OK it's in a known zero state, try writing and reading |
1057 | * without disturbing the current state of the other bits. |
1058 | */ |
1059 | serial_outp(up, UART_IER, iersave | UART_IER_UUE); |
1060 | if (serial_in(up, UART_IER) & UART_IER_UUE) { |
1061 | /* |
1062 | * It's an Xscale. |
1063 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). |
1064 | */ |
1065 | DEBUG_AUTOCONF("Xscale "); |
1066 | up->port.type = PORT_XSCALE; |
1067 | up->capabilities |= UART_CAP_UUE; |
1068 | return; |
1069 | } |
1070 | } else { |
1071 | /* |
1072 | * If we got here we couldn't force the IER_UUE bit to 0. |
1073 | * Log it and continue. |
1074 | */ |
1075 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); |
1076 | } |
1077 | serial_outp(up, UART_IER, iersave); |
1078 | } |
1079 | |
1080 | /* |
1081 | * This routine is called by rs_init() to initialize a specific serial |
1082 | * port. It determines what type of UART chip this serial port is |
1083 | * using: 8250, 16450, 16550, 16550A. The important question is |
1084 | * whether or not this UART is a 16550A or not, since this will |
1085 | * determine whether or not we can use its FIFO features or not. |
1086 | */ |
1087 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) |
1088 | { |
1089 | unsigned char status1, scratch, scratch2, scratch3; |
1090 | unsigned char save_lcr, save_mcr; |
1091 | unsigned long flags; |
1092 | |
1093 | if (!up->port.iobase && !up->port.mapbase && !up->port.membase) |
1094 | return; |
1095 | |
1096 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", |
1097 | serial_index(&up->port), up->port.iobase, up->port.membase); |
1098 | |
1099 | /* |
1100 | * We really do need global IRQs disabled here - we're going to |
1101 | * be frobbing the chips IRQ enable register to see if it exists. |
1102 | */ |
1103 | spin_lock_irqsave(&up->port.lock, flags); |
1104 | |
1105 | up->capabilities = 0; |
1106 | up->bugs = 0; |
1107 | |
1108 | if (!(up->port.flags & UPF_BUGGY_UART)) { |
1109 | /* |
1110 | * Do a simple existence test first; if we fail this, |
1111 | * there's no point trying anything else. |
1112 | * |
1113 | * 0x80 is used as a nonsense port to prevent against |
1114 | * false positives due to ISA bus float. The |
1115 | * assumption is that 0x80 is a non-existent port; |
1116 | * which should be safe since include/asm/io.h also |
1117 | * makes this assumption. |
1118 | * |
1119 | * Note: this is safe as long as MCR bit 4 is clear |
1120 | * and the device is in "PC" mode. |
1121 | */ |
1122 | scratch = serial_inp(up, UART_IER); |
1123 | serial_outp(up, UART_IER, 0); |
1124 | #ifdef __i386__ |
1125 | outb(0xff, 0x080); |
1126 | #endif |
1127 | /* |
1128 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL |
1129 | * 16C754B) allow only to modify them if an EFR bit is set. |
1130 | */ |
1131 | scratch2 = serial_inp(up, UART_IER) & 0x0f; |
1132 | serial_outp(up, UART_IER, 0x0F); |
1133 | #ifdef __i386__ |
1134 | outb(0, 0x080); |
1135 | #endif |
1136 | scratch3 = serial_inp(up, UART_IER) & 0x0f; |
1137 | serial_outp(up, UART_IER, scratch); |
1138 | if (scratch2 != 0 || scratch3 != 0x0F) { |
1139 | /* |
1140 | * We failed; there's nothing here |
1141 | */ |
1142 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", |
1143 | scratch2, scratch3); |
1144 | goto out; |
1145 | } |
1146 | } |
1147 | |
1148 | save_mcr = serial_in(up, UART_MCR); |
1149 | save_lcr = serial_in(up, UART_LCR); |
1150 | |
1151 | /* |
1152 | * Check to see if a UART is really there. Certain broken |
1153 | * internal modems based on the Rockwell chipset fail this |
1154 | * test, because they apparently don't implement the loopback |
1155 | * test mode. So this test is skipped on the COM 1 through |
1156 | * COM 4 ports. This *should* be safe, since no board |
1157 | * manufacturer would be stupid enough to design a board |
1158 | * that conflicts with COM 1-4 --- we hope! |
1159 | */ |
1160 | if (!(up->port.flags & UPF_SKIP_TEST)) { |
1161 | serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); |
1162 | status1 = serial_inp(up, UART_MSR) & 0xF0; |
1163 | serial_outp(up, UART_MCR, save_mcr); |
1164 | if (status1 != 0x90) { |
1165 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", |
1166 | status1); |
1167 | goto out; |
1168 | } |
1169 | } |
1170 | |
1171 | /* |
1172 | * We're pretty sure there's a port here. Lets find out what |
1173 | * type of port it is. The IIR top two bits allows us to find |
1174 | * out if it's 8250 or 16450, 16550, 16550A or later. This |
1175 | * determines what we test for next. |
1176 | * |
1177 | * We also initialise the EFR (if any) to zero for later. The |
1178 | * EFR occupies the same register location as the FCR and IIR. |
1179 | */ |
1180 | serial_outp(up, UART_LCR, 0xBF); |
1181 | serial_outp(up, UART_EFR, 0); |
1182 | serial_outp(up, UART_LCR, 0); |
1183 | |
1184 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1185 | scratch = serial_in(up, UART_IIR) >> 6; |
1186 | |
1187 | DEBUG_AUTOCONF("iir=%d ", scratch); |
1188 | |
1189 | switch (scratch) { |
1190 | case 0: |
1191 | autoconfig_8250(up); |
1192 | break; |
1193 | case 1: |
1194 | up->port.type = PORT_UNKNOWN; |
1195 | break; |
1196 | case 2: |
1197 | up->port.type = PORT_16550; |
1198 | break; |
1199 | case 3: |
1200 | autoconfig_16550a(up); |
1201 | break; |
1202 | } |
1203 | |
1204 | #ifdef CONFIG_SERIAL_8250_RSA |
1205 | /* |
1206 | * Only probe for RSA ports if we got the region. |
1207 | */ |
1208 | if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) { |
1209 | int i; |
1210 | |
1211 | for (i = 0 ; i < probe_rsa_count; ++i) { |
1212 | if (probe_rsa[i] == up->port.iobase && |
1213 | __enable_rsa(up)) { |
1214 | up->port.type = PORT_RSA; |
1215 | break; |
1216 | } |
1217 | } |
1218 | } |
1219 | #endif |
1220 | |
1221 | serial_outp(up, UART_LCR, save_lcr); |
1222 | |
1223 | if (up->capabilities != uart_config[up->port.type].flags) { |
1224 | printk(KERN_WARNING |
1225 | "ttyS%d: detected caps %08x should be %08x\n", |
1226 | serial_index(&up->port), up->capabilities, |
1227 | uart_config[up->port.type].flags); |
1228 | } |
1229 | |
1230 | up->port.fifosize = uart_config[up->port.type].fifo_size; |
1231 | up->capabilities = uart_config[up->port.type].flags; |
1232 | up->tx_loadsz = uart_config[up->port.type].tx_loadsz; |
1233 | |
1234 | if (up->port.type == PORT_UNKNOWN) |
1235 | goto out; |
1236 | |
1237 | /* |
1238 | * Reset the UART. |
1239 | */ |
1240 | #ifdef CONFIG_SERIAL_8250_RSA |
1241 | if (up->port.type == PORT_RSA) |
1242 | serial_outp(up, UART_RSA_FRR, 0); |
1243 | #endif |
1244 | serial_outp(up, UART_MCR, save_mcr); |
1245 | serial8250_clear_fifos(up); |
1246 | serial_in(up, UART_RX); |
1247 | if (up->capabilities & UART_CAP_UUE) |
1248 | serial_outp(up, UART_IER, UART_IER_UUE); |
1249 | else |
1250 | serial_outp(up, UART_IER, 0); |
1251 | |
1252 | out: |
1253 | spin_unlock_irqrestore(&up->port.lock, flags); |
1254 | DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name); |
1255 | } |
1256 | |
1257 | static void autoconfig_irq(struct uart_8250_port *up) |
1258 | { |
1259 | unsigned char save_mcr, save_ier; |
1260 | unsigned char save_ICP = 0; |
1261 | unsigned int ICP = 0; |
1262 | unsigned long irqs; |
1263 | int irq; |
1264 | |
1265 | if (up->port.flags & UPF_FOURPORT) { |
1266 | ICP = (up->port.iobase & 0xfe0) | 0x1f; |
1267 | save_ICP = inb_p(ICP); |
1268 | outb_p(0x80, ICP); |
1269 | (void) inb_p(ICP); |
1270 | } |
1271 | |
1272 | /* forget possible initially masked and pending IRQ */ |
1273 | probe_irq_off(probe_irq_on()); |
1274 | save_mcr = serial_inp(up, UART_MCR); |
1275 | save_ier = serial_inp(up, UART_IER); |
1276 | serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); |
1277 | |
1278 | irqs = probe_irq_on(); |
1279 | serial_outp(up, UART_MCR, 0); |
1280 | udelay(10); |
1281 | if (up->port.flags & UPF_FOURPORT) { |
1282 | serial_outp(up, UART_MCR, |
1283 | UART_MCR_DTR | UART_MCR_RTS); |
1284 | } else { |
1285 | serial_outp(up, UART_MCR, |
1286 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); |
1287 | } |
1288 | serial_outp(up, UART_IER, 0x0f); /* enable all intrs */ |
1289 | (void)serial_inp(up, UART_LSR); |
1290 | (void)serial_inp(up, UART_RX); |
1291 | (void)serial_inp(up, UART_IIR); |
1292 | (void)serial_inp(up, UART_MSR); |
1293 | serial_outp(up, UART_TX, 0xFF); |
1294 | udelay(20); |
1295 | irq = probe_irq_off(irqs); |
1296 | |
1297 | serial_outp(up, UART_MCR, save_mcr); |
1298 | serial_outp(up, UART_IER, save_ier); |
1299 | |
1300 | if (up->port.flags & UPF_FOURPORT) |
1301 | outb_p(save_ICP, ICP); |
1302 | |
1303 | up->port.irq = (irq > 0) ? irq : 0; |
1304 | } |
1305 | |
1306 | static inline void __stop_tx(struct uart_8250_port *p) |
1307 | { |
1308 | if (p->ier & UART_IER_THRI) { |
1309 | p->ier &= ~UART_IER_THRI; |
1310 | serial_out(p, UART_IER, p->ier); |
1311 | } |
1312 | } |
1313 | |
1314 | static void serial8250_stop_tx(struct uart_port *port) |
1315 | { |
1316 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1317 | |
1318 | __stop_tx(up); |
1319 | |
1320 | /* |
1321 | * We really want to stop the transmitter from sending. |
1322 | */ |
1323 | if (up->port.type == PORT_16C950) { |
1324 | up->acr |= UART_ACR_TXDIS; |
1325 | serial_icr_write(up, UART_ACR, up->acr); |
1326 | } |
1327 | } |
1328 | |
1329 | static void transmit_chars(struct uart_8250_port *up); |
1330 | |
1331 | static void serial8250_start_tx(struct uart_port *port) |
1332 | { |
1333 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1334 | |
1335 | if (!(up->ier & UART_IER_THRI)) { |
1336 | up->ier |= UART_IER_THRI; |
1337 | serial_out(up, UART_IER, up->ier); |
1338 | |
1339 | if (up->bugs & UART_BUG_TXEN) { |
1340 | unsigned char lsr; |
1341 | lsr = serial_in(up, UART_LSR); |
1342 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
1343 | if ((up->port.type == PORT_RM9000) ? |
1344 | (lsr & UART_LSR_THRE) : |
1345 | (lsr & UART_LSR_TEMT)) |
1346 | transmit_chars(up); |
1347 | } |
1348 | } |
1349 | |
1350 | /* |
1351 | * Re-enable the transmitter if we disabled it. |
1352 | */ |
1353 | if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { |
1354 | up->acr &= ~UART_ACR_TXDIS; |
1355 | serial_icr_write(up, UART_ACR, up->acr); |
1356 | } |
1357 | } |
1358 | |
1359 | static void serial8250_stop_rx(struct uart_port *port) |
1360 | { |
1361 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1362 | |
1363 | up->ier &= ~UART_IER_RLSI; |
1364 | up->port.read_status_mask &= ~UART_LSR_DR; |
1365 | serial_out(up, UART_IER, up->ier); |
1366 | } |
1367 | |
1368 | static void serial8250_enable_ms(struct uart_port *port) |
1369 | { |
1370 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1371 | |
1372 | /* no MSR capabilities */ |
1373 | if (up->bugs & UART_BUG_NOMSR) |
1374 | return; |
1375 | |
1376 | up->ier |= UART_IER_MSI; |
1377 | serial_out(up, UART_IER, up->ier); |
1378 | } |
1379 | |
1380 | static void |
1381 | receive_chars(struct uart_8250_port *up, unsigned int *status) |
1382 | { |
1383 | struct tty_struct *tty = up->port.state->port.tty; |
1384 | unsigned char ch, lsr = *status; |
1385 | int max_count = 256; |
1386 | char flag; |
1387 | |
1388 | do { |
1389 | if (likely(lsr & UART_LSR_DR)) |
1390 | ch = serial_inp(up, UART_RX); |
1391 | else |
1392 | /* |
1393 | * Intel 82571 has a Serial Over Lan device that will |
1394 | * set UART_LSR_BI without setting UART_LSR_DR when |
1395 | * it receives a break. To avoid reading from the |
1396 | * receive buffer without UART_LSR_DR bit set, we |
1397 | * just force the read character to be 0 |
1398 | */ |
1399 | ch = 0; |
1400 | |
1401 | flag = TTY_NORMAL; |
1402 | up->port.icount.rx++; |
1403 | |
1404 | lsr |= up->lsr_saved_flags; |
1405 | up->lsr_saved_flags = 0; |
1406 | |
1407 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { |
1408 | /* |
1409 | * For statistics only |
1410 | */ |
1411 | if (lsr & UART_LSR_BI) { |
1412 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); |
1413 | up->port.icount.brk++; |
1414 | /* |
1415 | * We do the SysRQ and SAK checking |
1416 | * here because otherwise the break |
1417 | * may get masked by ignore_status_mask |
1418 | * or read_status_mask. |
1419 | */ |
1420 | if (uart_handle_break(&up->port)) |
1421 | goto ignore_char; |
1422 | } else if (lsr & UART_LSR_PE) |
1423 | up->port.icount.parity++; |
1424 | else if (lsr & UART_LSR_FE) |
1425 | up->port.icount.frame++; |
1426 | if (lsr & UART_LSR_OE) |
1427 | up->port.icount.overrun++; |
1428 | |
1429 | /* |
1430 | * Mask off conditions which should be ignored. |
1431 | */ |
1432 | lsr &= up->port.read_status_mask; |
1433 | |
1434 | if (lsr & UART_LSR_BI) { |
1435 | DEBUG_INTR("handling break...."); |
1436 | flag = TTY_BREAK; |
1437 | } else if (lsr & UART_LSR_PE) |
1438 | flag = TTY_PARITY; |
1439 | else if (lsr & UART_LSR_FE) |
1440 | flag = TTY_FRAME; |
1441 | } |
1442 | if (uart_handle_sysrq_char(&up->port, ch)) |
1443 | goto ignore_char; |
1444 | |
1445 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); |
1446 | |
1447 | ignore_char: |
1448 | lsr = serial_inp(up, UART_LSR); |
1449 | } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); |
1450 | spin_unlock(&up->port.lock); |
1451 | tty_flip_buffer_push(tty); |
1452 | spin_lock(&up->port.lock); |
1453 | *status = lsr; |
1454 | } |
1455 | |
1456 | static void transmit_chars(struct uart_8250_port *up) |
1457 | { |
1458 | struct circ_buf *xmit = &up->port.state->xmit; |
1459 | int count; |
1460 | |
1461 | if (up->port.x_char) { |
1462 | serial_outp(up, UART_TX, up->port.x_char); |
1463 | up->port.icount.tx++; |
1464 | up->port.x_char = 0; |
1465 | return; |
1466 | } |
1467 | if (uart_tx_stopped(&up->port)) { |
1468 | serial8250_stop_tx(&up->port); |
1469 | return; |
1470 | } |
1471 | if (uart_circ_empty(xmit)) { |
1472 | __stop_tx(up); |
1473 | return; |
1474 | } |
1475 | |
1476 | count = up->tx_loadsz; |
1477 | do { |
1478 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); |
1479 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1480 | up->port.icount.tx++; |
1481 | if (uart_circ_empty(xmit)) |
1482 | break; |
1483 | } while (--count > 0); |
1484 | |
1485 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
1486 | uart_write_wakeup(&up->port); |
1487 | |
1488 | DEBUG_INTR("THRE..."); |
1489 | |
1490 | if (uart_circ_empty(xmit)) |
1491 | __stop_tx(up); |
1492 | } |
1493 | |
1494 | static unsigned int check_modem_status(struct uart_8250_port *up) |
1495 | { |
1496 | unsigned int status = serial_in(up, UART_MSR); |
1497 | |
1498 | status |= up->msr_saved_flags; |
1499 | up->msr_saved_flags = 0; |
1500 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && |
1501 | up->port.state != NULL) { |
1502 | if (status & UART_MSR_TERI) |
1503 | up->port.icount.rng++; |
1504 | if (status & UART_MSR_DDSR) |
1505 | up->port.icount.dsr++; |
1506 | if (status & UART_MSR_DDCD) |
1507 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); |
1508 | if (status & UART_MSR_DCTS) |
1509 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); |
1510 | |
1511 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
1512 | } |
1513 | |
1514 | return status; |
1515 | } |
1516 | |
1517 | /* |
1518 | * This handles the interrupt from one port. |
1519 | */ |
1520 | static void serial8250_handle_port(struct uart_8250_port *up) |
1521 | { |
1522 | unsigned int status; |
1523 | unsigned long flags; |
1524 | |
1525 | spin_lock_irqsave(&up->port.lock, flags); |
1526 | |
1527 | status = serial_inp(up, UART_LSR); |
1528 | |
1529 | DEBUG_INTR("status = %x...", status); |
1530 | |
1531 | if (status & (UART_LSR_DR | UART_LSR_BI)) |
1532 | receive_chars(up, &status); |
1533 | check_modem_status(up); |
1534 | if (status & UART_LSR_THRE) |
1535 | transmit_chars(up); |
1536 | |
1537 | spin_unlock_irqrestore(&up->port.lock, flags); |
1538 | } |
1539 | |
1540 | /* |
1541 | * This is the serial driver's interrupt routine. |
1542 | * |
1543 | * Arjan thinks the old way was overly complex, so it got simplified. |
1544 | * Alan disagrees, saying that need the complexity to handle the weird |
1545 | * nature of ISA shared interrupts. (This is a special exception.) |
1546 | * |
1547 | * In order to handle ISA shared interrupts properly, we need to check |
1548 | * that all ports have been serviced, and therefore the ISA interrupt |
1549 | * line has been de-asserted. |
1550 | * |
1551 | * This means we need to loop through all ports. checking that they |
1552 | * don't have an interrupt pending. |
1553 | */ |
1554 | static irqreturn_t serial8250_interrupt(int irq, void *dev_id) |
1555 | { |
1556 | struct irq_info *i = dev_id; |
1557 | struct list_head *l, *end = NULL; |
1558 | int pass_counter = 0, handled = 0; |
1559 | |
1560 | DEBUG_INTR("serial8250_interrupt(%d)...", irq); |
1561 | |
1562 | spin_lock(&i->lock); |
1563 | |
1564 | l = i->head; |
1565 | do { |
1566 | struct uart_8250_port *up; |
1567 | unsigned int iir; |
1568 | |
1569 | up = list_entry(l, struct uart_8250_port, list); |
1570 | |
1571 | iir = serial_in(up, UART_IIR); |
1572 | if (!(iir & UART_IIR_NO_INT)) { |
1573 | serial8250_handle_port(up); |
1574 | |
1575 | handled = 1; |
1576 | |
1577 | end = NULL; |
1578 | } else if (up->port.iotype == UPIO_DWAPB && |
1579 | (iir & UART_IIR_BUSY) == UART_IIR_BUSY) { |
1580 | /* The DesignWare APB UART has an Busy Detect (0x07) |
1581 | * interrupt meaning an LCR write attempt occured while the |
1582 | * UART was busy. The interrupt must be cleared by reading |
1583 | * the UART status register (USR) and the LCR re-written. */ |
1584 | unsigned int status; |
1585 | status = *(volatile u32 *)up->port.private_data; |
1586 | serial_out(up, UART_LCR, up->lcr); |
1587 | |
1588 | handled = 1; |
1589 | |
1590 | end = NULL; |
1591 | } else if (end == NULL) |
1592 | end = l; |
1593 | |
1594 | l = l->next; |
1595 | |
1596 | if (l == i->head && pass_counter++ > PASS_LIMIT) { |
1597 | /* If we hit this, we're dead. */ |
1598 | printk(KERN_ERR "serial8250: too much work for " |
1599 | "irq%d\n", irq); |
1600 | break; |
1601 | } |
1602 | } while (l != end); |
1603 | |
1604 | spin_unlock(&i->lock); |
1605 | |
1606 | DEBUG_INTR("end.\n"); |
1607 | |
1608 | return IRQ_RETVAL(handled); |
1609 | } |
1610 | |
1611 | /* |
1612 | * To support ISA shared interrupts, we need to have one interrupt |
1613 | * handler that ensures that the IRQ line has been deasserted |
1614 | * before returning. Failing to do this will result in the IRQ |
1615 | * line being stuck active, and, since ISA irqs are edge triggered, |
1616 | * no more IRQs will be seen. |
1617 | */ |
1618 | static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) |
1619 | { |
1620 | spin_lock_irq(&i->lock); |
1621 | |
1622 | if (!list_empty(i->head)) { |
1623 | if (i->head == &up->list) |
1624 | i->head = i->head->next; |
1625 | list_del(&up->list); |
1626 | } else { |
1627 | BUG_ON(i->head != &up->list); |
1628 | i->head = NULL; |
1629 | } |
1630 | spin_unlock_irq(&i->lock); |
1631 | /* List empty so throw away the hash node */ |
1632 | if (i->head == NULL) { |
1633 | hlist_del(&i->node); |
1634 | kfree(i); |
1635 | } |
1636 | } |
1637 | |
1638 | static int serial_link_irq_chain(struct uart_8250_port *up) |
1639 | { |
1640 | struct hlist_head *h; |
1641 | struct hlist_node *n; |
1642 | struct irq_info *i; |
1643 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; |
1644 | |
1645 | mutex_lock(&hash_mutex); |
1646 | |
1647 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; |
1648 | |
1649 | hlist_for_each(n, h) { |
1650 | i = hlist_entry(n, struct irq_info, node); |
1651 | if (i->irq == up->port.irq) |
1652 | break; |
1653 | } |
1654 | |
1655 | if (n == NULL) { |
1656 | i = kzalloc(sizeof(struct irq_info), GFP_KERNEL); |
1657 | if (i == NULL) { |
1658 | mutex_unlock(&hash_mutex); |
1659 | return -ENOMEM; |
1660 | } |
1661 | spin_lock_init(&i->lock); |
1662 | i->irq = up->port.irq; |
1663 | hlist_add_head(&i->node, h); |
1664 | } |
1665 | mutex_unlock(&hash_mutex); |
1666 | |
1667 | spin_lock_irq(&i->lock); |
1668 | |
1669 | if (i->head) { |
1670 | list_add(&up->list, i->head); |
1671 | spin_unlock_irq(&i->lock); |
1672 | |
1673 | ret = 0; |
1674 | } else { |
1675 | INIT_LIST_HEAD(&up->list); |
1676 | i->head = &up->list; |
1677 | spin_unlock_irq(&i->lock); |
1678 | irq_flags |= up->port.irqflags; |
1679 | ret = request_irq(up->port.irq, serial8250_interrupt, |
1680 | irq_flags, "serial", i); |
1681 | if (ret < 0) |
1682 | serial_do_unlink(i, up); |
1683 | } |
1684 | |
1685 | return ret; |
1686 | } |
1687 | |
1688 | static void serial_unlink_irq_chain(struct uart_8250_port *up) |
1689 | { |
1690 | struct irq_info *i; |
1691 | struct hlist_node *n; |
1692 | struct hlist_head *h; |
1693 | |
1694 | mutex_lock(&hash_mutex); |
1695 | |
1696 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; |
1697 | |
1698 | hlist_for_each(n, h) { |
1699 | i = hlist_entry(n, struct irq_info, node); |
1700 | if (i->irq == up->port.irq) |
1701 | break; |
1702 | } |
1703 | |
1704 | BUG_ON(n == NULL); |
1705 | BUG_ON(i->head == NULL); |
1706 | |
1707 | if (list_empty(i->head)) |
1708 | free_irq(up->port.irq, i); |
1709 | |
1710 | serial_do_unlink(i, up); |
1711 | mutex_unlock(&hash_mutex); |
1712 | } |
1713 | |
1714 | /* Base timer interval for polling */ |
1715 | static inline int poll_timeout(int timeout) |
1716 | { |
1717 | return timeout > 6 ? (timeout / 2 - 2) : 1; |
1718 | } |
1719 | |
1720 | /* |
1721 | * This function is used to handle ports that do not have an |
1722 | * interrupt. This doesn't work very well for 16450's, but gives |
1723 | * barely passable results for a 16550A. (Although at the expense |
1724 | * of much CPU overhead). |
1725 | */ |
1726 | static void serial8250_timeout(unsigned long data) |
1727 | { |
1728 | struct uart_8250_port *up = (struct uart_8250_port *)data; |
1729 | unsigned int iir; |
1730 | |
1731 | iir = serial_in(up, UART_IIR); |
1732 | if (!(iir & UART_IIR_NO_INT)) |
1733 | serial8250_handle_port(up); |
1734 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
1735 | } |
1736 | |
1737 | static void serial8250_backup_timeout(unsigned long data) |
1738 | { |
1739 | struct uart_8250_port *up = (struct uart_8250_port *)data; |
1740 | unsigned int iir, ier = 0, lsr; |
1741 | unsigned long flags; |
1742 | |
1743 | /* |
1744 | * Must disable interrupts or else we risk racing with the interrupt |
1745 | * based handler. |
1746 | */ |
1747 | if (is_real_interrupt(up->port.irq)) { |
1748 | ier = serial_in(up, UART_IER); |
1749 | serial_out(up, UART_IER, 0); |
1750 | } |
1751 | |
1752 | iir = serial_in(up, UART_IIR); |
1753 | |
1754 | /* |
1755 | * This should be a safe test for anyone who doesn't trust the |
1756 | * IIR bits on their UART, but it's specifically designed for |
1757 | * the "Diva" UART used on the management processor on many HP |
1758 | * ia64 and parisc boxes. |
1759 | */ |
1760 | spin_lock_irqsave(&up->port.lock, flags); |
1761 | lsr = serial_in(up, UART_LSR); |
1762 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
1763 | spin_unlock_irqrestore(&up->port.lock, flags); |
1764 | if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && |
1765 | (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && |
1766 | (lsr & UART_LSR_THRE)) { |
1767 | iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); |
1768 | iir |= UART_IIR_THRI; |
1769 | } |
1770 | |
1771 | if (!(iir & UART_IIR_NO_INT)) |
1772 | serial8250_handle_port(up); |
1773 | |
1774 | if (is_real_interrupt(up->port.irq)) |
1775 | serial_out(up, UART_IER, ier); |
1776 | |
1777 | /* Standard timer interval plus 0.2s to keep the port running */ |
1778 | mod_timer(&up->timer, |
1779 | jiffies + poll_timeout(up->port.timeout) + HZ / 5); |
1780 | } |
1781 | |
1782 | static unsigned int serial8250_tx_empty(struct uart_port *port) |
1783 | { |
1784 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1785 | unsigned long flags; |
1786 | unsigned int lsr; |
1787 | |
1788 | spin_lock_irqsave(&up->port.lock, flags); |
1789 | lsr = serial_in(up, UART_LSR); |
1790 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
1791 | spin_unlock_irqrestore(&up->port.lock, flags); |
1792 | |
1793 | return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; |
1794 | } |
1795 | |
1796 | static unsigned int serial8250_get_mctrl(struct uart_port *port) |
1797 | { |
1798 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1799 | unsigned int status; |
1800 | unsigned int ret; |
1801 | |
1802 | status = check_modem_status(up); |
1803 | |
1804 | ret = 0; |
1805 | if (status & UART_MSR_DCD) |
1806 | ret |= TIOCM_CAR; |
1807 | if (status & UART_MSR_RI) |
1808 | ret |= TIOCM_RNG; |
1809 | if (status & UART_MSR_DSR) |
1810 | ret |= TIOCM_DSR; |
1811 | if (status & UART_MSR_CTS) |
1812 | ret |= TIOCM_CTS; |
1813 | return ret; |
1814 | } |
1815 | |
1816 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1817 | { |
1818 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1819 | unsigned char mcr = 0; |
1820 | |
1821 | if (mctrl & TIOCM_RTS) |
1822 | mcr |= UART_MCR_RTS; |
1823 | if (mctrl & TIOCM_DTR) |
1824 | mcr |= UART_MCR_DTR; |
1825 | if (mctrl & TIOCM_OUT1) |
1826 | mcr |= UART_MCR_OUT1; |
1827 | if (mctrl & TIOCM_OUT2) |
1828 | mcr |= UART_MCR_OUT2; |
1829 | if (mctrl & TIOCM_LOOP) |
1830 | mcr |= UART_MCR_LOOP; |
1831 | |
1832 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; |
1833 | |
1834 | serial_out(up, UART_MCR, mcr); |
1835 | } |
1836 | |
1837 | static void serial8250_break_ctl(struct uart_port *port, int break_state) |
1838 | { |
1839 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1840 | unsigned long flags; |
1841 | |
1842 | spin_lock_irqsave(&up->port.lock, flags); |
1843 | if (break_state == -1) |
1844 | up->lcr |= UART_LCR_SBC; |
1845 | else |
1846 | up->lcr &= ~UART_LCR_SBC; |
1847 | serial_out(up, UART_LCR, up->lcr); |
1848 | spin_unlock_irqrestore(&up->port.lock, flags); |
1849 | } |
1850 | |
1851 | /* |
1852 | * Wait for transmitter & holding register to empty |
1853 | */ |
1854 | static void wait_for_xmitr(struct uart_8250_port *up, int bits) |
1855 | { |
1856 | unsigned int status, tmout = 10000; |
1857 | |
1858 | /* Wait up to 10ms for the character(s) to be sent. */ |
1859 | do { |
1860 | status = serial_in(up, UART_LSR); |
1861 | |
1862 | up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; |
1863 | |
1864 | if (--tmout == 0) |
1865 | break; |
1866 | udelay(1); |
1867 | } while ((status & bits) != bits); |
1868 | |
1869 | /* Wait up to 1s for flow control if necessary */ |
1870 | if (up->port.flags & UPF_CONS_FLOW) { |
1871 | unsigned int tmout; |
1872 | for (tmout = 1000000; tmout; tmout--) { |
1873 | unsigned int msr = serial_in(up, UART_MSR); |
1874 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; |
1875 | if (msr & UART_MSR_CTS) |
1876 | break; |
1877 | udelay(1); |
1878 | touch_nmi_watchdog(); |
1879 | } |
1880 | } |
1881 | } |
1882 | |
1883 | #ifdef CONFIG_CONSOLE_POLL |
1884 | /* |
1885 | * Console polling routines for writing and reading from the uart while |
1886 | * in an interrupt or debug context. |
1887 | */ |
1888 | |
1889 | static int serial8250_get_poll_char(struct uart_port *port) |
1890 | { |
1891 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1892 | unsigned char lsr = serial_inp(up, UART_LSR); |
1893 | |
1894 | while (!(lsr & UART_LSR_DR)) |
1895 | lsr = serial_inp(up, UART_LSR); |
1896 | |
1897 | return serial_inp(up, UART_RX); |
1898 | } |
1899 | |
1900 | |
1901 | static void serial8250_put_poll_char(struct uart_port *port, |
1902 | unsigned char c) |
1903 | { |
1904 | unsigned int ier; |
1905 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1906 | |
1907 | /* |
1908 | * First save the IER then disable the interrupts |
1909 | */ |
1910 | ier = serial_in(up, UART_IER); |
1911 | if (up->capabilities & UART_CAP_UUE) |
1912 | serial_out(up, UART_IER, UART_IER_UUE); |
1913 | else |
1914 | serial_out(up, UART_IER, 0); |
1915 | |
1916 | wait_for_xmitr(up, BOTH_EMPTY); |
1917 | /* |
1918 | * Send the character out. |
1919 | * If a LF, also do CR... |
1920 | */ |
1921 | serial_out(up, UART_TX, c); |
1922 | if (c == 10) { |
1923 | wait_for_xmitr(up, BOTH_EMPTY); |
1924 | serial_out(up, UART_TX, 13); |
1925 | } |
1926 | |
1927 | /* |
1928 | * Finally, wait for transmitter to become empty |
1929 | * and restore the IER |
1930 | */ |
1931 | wait_for_xmitr(up, BOTH_EMPTY); |
1932 | serial_out(up, UART_IER, ier); |
1933 | } |
1934 | |
1935 | #endif /* CONFIG_CONSOLE_POLL */ |
1936 | |
1937 | static int serial8250_startup(struct uart_port *port) |
1938 | { |
1939 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1940 | unsigned long flags; |
1941 | unsigned char lsr, iir; |
1942 | int retval; |
1943 | |
1944 | up->capabilities = uart_config[up->port.type].flags; |
1945 | up->mcr = 0; |
1946 | |
1947 | if (up->port.iotype != up->cur_iotype) |
1948 | set_io_from_upio(port); |
1949 | |
1950 | if (up->port.type == PORT_16C950) { |
1951 | /* Wake up and initialize UART */ |
1952 | up->acr = 0; |
1953 | serial_outp(up, UART_LCR, 0xBF); |
1954 | serial_outp(up, UART_EFR, UART_EFR_ECB); |
1955 | serial_outp(up, UART_IER, 0); |
1956 | serial_outp(up, UART_LCR, 0); |
1957 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ |
1958 | serial_outp(up, UART_LCR, 0xBF); |
1959 | serial_outp(up, UART_EFR, UART_EFR_ECB); |
1960 | serial_outp(up, UART_LCR, 0); |
1961 | } |
1962 | |
1963 | #ifdef CONFIG_SERIAL_8250_RSA |
1964 | /* |
1965 | * If this is an RSA port, see if we can kick it up to the |
1966 | * higher speed clock. |
1967 | */ |
1968 | enable_rsa(up); |
1969 | #endif |
1970 | |
1971 | /* |
1972 | * Clear the FIFO buffers and disable them. |
1973 | * (they will be reenabled in set_termios()) |
1974 | */ |
1975 | serial8250_clear_fifos(up); |
1976 | |
1977 | /* |
1978 | * Clear the interrupt registers. |
1979 | */ |
1980 | (void) serial_inp(up, UART_LSR); |
1981 | (void) serial_inp(up, UART_RX); |
1982 | (void) serial_inp(up, UART_IIR); |
1983 | (void) serial_inp(up, UART_MSR); |
1984 | |
1985 | /* |
1986 | * At this point, there's no way the LSR could still be 0xff; |
1987 | * if it is, then bail out, because there's likely no UART |
1988 | * here. |
1989 | */ |
1990 | if (!(up->port.flags & UPF_BUGGY_UART) && |
1991 | (serial_inp(up, UART_LSR) == 0xff)) { |
1992 | printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n", |
1993 | serial_index(&up->port)); |
1994 | return -ENODEV; |
1995 | } |
1996 | |
1997 | /* |
1998 | * For a XR16C850, we need to set the trigger levels |
1999 | */ |
2000 | if (up->port.type == PORT_16850) { |
2001 | unsigned char fctr; |
2002 | |
2003 | serial_outp(up, UART_LCR, 0xbf); |
2004 | |
2005 | fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); |
2006 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX); |
2007 | serial_outp(up, UART_TRG, UART_TRG_96); |
2008 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX); |
2009 | serial_outp(up, UART_TRG, UART_TRG_96); |
2010 | |
2011 | serial_outp(up, UART_LCR, 0); |
2012 | } |
2013 | |
2014 | if (is_real_interrupt(up->port.irq)) { |
2015 | unsigned char iir1; |
2016 | /* |
2017 | * Test for UARTs that do not reassert THRE when the |
2018 | * transmitter is idle and the interrupt has already |
2019 | * been cleared. Real 16550s should always reassert |
2020 | * this interrupt whenever the transmitter is idle and |
2021 | * the interrupt is enabled. Delays are necessary to |
2022 | * allow register changes to become visible. |
2023 | */ |
2024 | spin_lock_irqsave(&up->port.lock, flags); |
2025 | if (up->port.irqflags & IRQF_SHARED) |
2026 | disable_irq_nosync(up->port.irq); |
2027 | |
2028 | wait_for_xmitr(up, UART_LSR_THRE); |
2029 | serial_out_sync(up, UART_IER, UART_IER_THRI); |
2030 | udelay(1); /* allow THRE to set */ |
2031 | iir1 = serial_in(up, UART_IIR); |
2032 | serial_out(up, UART_IER, 0); |
2033 | serial_out_sync(up, UART_IER, UART_IER_THRI); |
2034 | udelay(1); /* allow a working UART time to re-assert THRE */ |
2035 | iir = serial_in(up, UART_IIR); |
2036 | serial_out(up, UART_IER, 0); |
2037 | |
2038 | if (up->port.irqflags & IRQF_SHARED) |
2039 | enable_irq(up->port.irq); |
2040 | spin_unlock_irqrestore(&up->port.lock, flags); |
2041 | |
2042 | /* |
2043 | * If the interrupt is not reasserted, setup a timer to |
2044 | * kick the UART on a regular basis. |
2045 | */ |
2046 | if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) { |
2047 | up->bugs |= UART_BUG_THRE; |
2048 | pr_debug("ttyS%d - using backup timer\n", |
2049 | serial_index(port)); |
2050 | } |
2051 | } |
2052 | |
2053 | /* |
2054 | * The above check will only give an accurate result the first time |
2055 | * the port is opened so this value needs to be preserved. |
2056 | */ |
2057 | if (up->bugs & UART_BUG_THRE) { |
2058 | up->timer.function = serial8250_backup_timeout; |
2059 | up->timer.data = (unsigned long)up; |
2060 | mod_timer(&up->timer, jiffies + |
2061 | poll_timeout(up->port.timeout) + HZ / 5); |
2062 | } |
2063 | |
2064 | /* |
2065 | * If the "interrupt" for this port doesn't correspond with any |
2066 | * hardware interrupt, we use a timer-based system. The original |
2067 | * driver used to do this with IRQ0. |
2068 | */ |
2069 | if (!is_real_interrupt(up->port.irq)) { |
2070 | up->timer.data = (unsigned long)up; |
2071 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
2072 | } else { |
2073 | retval = serial_link_irq_chain(up); |
2074 | if (retval) |
2075 | return retval; |
2076 | } |
2077 | |
2078 | /* |
2079 | * Now, initialize the UART |
2080 | */ |
2081 | serial_outp(up, UART_LCR, UART_LCR_WLEN8); |
2082 | |
2083 | spin_lock_irqsave(&up->port.lock, flags); |
2084 | if (up->port.flags & UPF_FOURPORT) { |
2085 | if (!is_real_interrupt(up->port.irq)) |
2086 | up->port.mctrl |= TIOCM_OUT1; |
2087 | } else |
2088 | /* |
2089 | * Most PC uarts need OUT2 raised to enable interrupts. |
2090 | */ |
2091 | if (is_real_interrupt(up->port.irq)) |
2092 | up->port.mctrl |= TIOCM_OUT2; |
2093 | |
2094 | serial8250_set_mctrl(&up->port, up->port.mctrl); |
2095 | |
2096 | /* Serial over Lan (SoL) hack: |
2097 | Intel 8257x Gigabit ethernet chips have a |
2098 | 16550 emulation, to be used for Serial Over Lan. |
2099 | Those chips take a longer time than a normal |
2100 | serial device to signalize that a transmission |
2101 | data was queued. Due to that, the above test generally |
2102 | fails. One solution would be to delay the reading of |
2103 | iir. However, this is not reliable, since the timeout |
2104 | is variable. So, let's just don't test if we receive |
2105 | TX irq. This way, we'll never enable UART_BUG_TXEN. |
2106 | */ |
2107 | if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) |
2108 | goto dont_test_tx_en; |
2109 | |
2110 | /* |
2111 | * Do a quick test to see if we receive an |
2112 | * interrupt when we enable the TX irq. |
2113 | */ |
2114 | serial_outp(up, UART_IER, UART_IER_THRI); |
2115 | lsr = serial_in(up, UART_LSR); |
2116 | iir = serial_in(up, UART_IIR); |
2117 | serial_outp(up, UART_IER, 0); |
2118 | |
2119 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { |
2120 | if (!(up->bugs & UART_BUG_TXEN)) { |
2121 | up->bugs |= UART_BUG_TXEN; |
2122 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", |
2123 | serial_index(port)); |
2124 | } |
2125 | } else { |
2126 | up->bugs &= ~UART_BUG_TXEN; |
2127 | } |
2128 | |
2129 | dont_test_tx_en: |
2130 | spin_unlock_irqrestore(&up->port.lock, flags); |
2131 | |
2132 | /* |
2133 | * Clear the interrupt registers again for luck, and clear the |
2134 | * saved flags to avoid getting false values from polling |
2135 | * routines or the previous session. |
2136 | */ |
2137 | serial_inp(up, UART_LSR); |
2138 | serial_inp(up, UART_RX); |
2139 | serial_inp(up, UART_IIR); |
2140 | serial_inp(up, UART_MSR); |
2141 | up->lsr_saved_flags = 0; |
2142 | up->msr_saved_flags = 0; |
2143 | |
2144 | /* |
2145 | * Finally, enable interrupts. Note: Modem status interrupts |
2146 | * are set via set_termios(), which will be occurring imminently |
2147 | * anyway, so we don't enable them here. |
2148 | */ |
2149 | up->ier = UART_IER_RLSI | UART_IER_RDI; |
2150 | serial_outp(up, UART_IER, up->ier); |
2151 | |
2152 | if (up->port.flags & UPF_FOURPORT) { |
2153 | unsigned int icp; |
2154 | /* |
2155 | * Enable interrupts on the AST Fourport board |
2156 | */ |
2157 | icp = (up->port.iobase & 0xfe0) | 0x01f; |
2158 | outb_p(0x80, icp); |
2159 | (void) inb_p(icp); |
2160 | } |
2161 | |
2162 | return 0; |
2163 | } |
2164 | |
2165 | static void serial8250_shutdown(struct uart_port *port) |
2166 | { |
2167 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2168 | unsigned long flags; |
2169 | |
2170 | /* |
2171 | * Disable interrupts from this port |
2172 | */ |
2173 | up->ier = 0; |
2174 | serial_outp(up, UART_IER, 0); |
2175 | |
2176 | spin_lock_irqsave(&up->port.lock, flags); |
2177 | if (up->port.flags & UPF_FOURPORT) { |
2178 | /* reset interrupts on the AST Fourport board */ |
2179 | inb((up->port.iobase & 0xfe0) | 0x1f); |
2180 | up->port.mctrl |= TIOCM_OUT1; |
2181 | } else |
2182 | up->port.mctrl &= ~TIOCM_OUT2; |
2183 | |
2184 | serial8250_set_mctrl(&up->port, up->port.mctrl); |
2185 | spin_unlock_irqrestore(&up->port.lock, flags); |
2186 | |
2187 | /* |
2188 | * Disable break condition and FIFOs |
2189 | */ |
2190 | serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); |
2191 | serial8250_clear_fifos(up); |
2192 | |
2193 | #ifdef CONFIG_SERIAL_8250_RSA |
2194 | /* |
2195 | * Reset the RSA board back to 115kbps compat mode. |
2196 | */ |
2197 | disable_rsa(up); |
2198 | #endif |
2199 | |
2200 | /* |
2201 | * Read data port to reset things, and then unlink from |
2202 | * the IRQ chain. |
2203 | */ |
2204 | (void) serial_in(up, UART_RX); |
2205 | |
2206 | del_timer_sync(&up->timer); |
2207 | up->timer.function = serial8250_timeout; |
2208 | if (is_real_interrupt(up->port.irq)) |
2209 | serial_unlink_irq_chain(up); |
2210 | } |
2211 | |
2212 | static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) |
2213 | { |
2214 | unsigned int quot; |
2215 | |
2216 | /* |
2217 | * Handle magic divisors for baud rates above baud_base on |
2218 | * SMSC SuperIO chips. |
2219 | */ |
2220 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && |
2221 | baud == (port->uartclk/4)) |
2222 | quot = 0x8001; |
2223 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && |
2224 | baud == (port->uartclk/8)) |
2225 | quot = 0x8002; |
2226 | else |
2227 | quot = uart_get_divisor(port, baud); |
2228 | |
2229 | return quot; |
2230 | } |
2231 | |
2232 | static void |
2233 | serial8250_set_termios(struct uart_port *port, struct ktermios *termios, |
2234 | struct ktermios *old) |
2235 | { |
2236 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2237 | unsigned char cval, fcr = 0; |
2238 | unsigned long flags; |
2239 | unsigned int baud, quot; |
2240 | |
2241 | switch (termios->c_cflag & CSIZE) { |
2242 | case CS5: |
2243 | cval = UART_LCR_WLEN5; |
2244 | break; |
2245 | case CS6: |
2246 | cval = UART_LCR_WLEN6; |
2247 | break; |
2248 | case CS7: |
2249 | cval = UART_LCR_WLEN7; |
2250 | break; |
2251 | default: |
2252 | case CS8: |
2253 | cval = UART_LCR_WLEN8; |
2254 | break; |
2255 | } |
2256 | |
2257 | if (termios->c_cflag & CSTOPB) |
2258 | cval |= UART_LCR_STOP; |
2259 | if (termios->c_cflag & PARENB) |
2260 | cval |= UART_LCR_PARITY; |
2261 | if (!(termios->c_cflag & PARODD)) |
2262 | cval |= UART_LCR_EPAR; |
2263 | #ifdef CMSPAR |
2264 | if (termios->c_cflag & CMSPAR) |
2265 | cval |= UART_LCR_SPAR; |
2266 | #endif |
2267 | |
2268 | /* |
2269 | * Ask the core to calculate the divisor for us. |
2270 | */ |
2271 | baud = uart_get_baud_rate(port, termios, old, |
2272 | port->uartclk / 16 / 0xffff, |
2273 | port->uartclk / 16); |
2274 | quot = serial8250_get_divisor(port, baud); |
2275 | |
2276 | /* |
2277 | * Oxford Semi 952 rev B workaround |
2278 | */ |
2279 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) |
2280 | quot++; |
2281 | |
2282 | if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) { |
2283 | if (baud < 2400) |
2284 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; |
2285 | else |
2286 | fcr = uart_config[up->port.type].fcr; |
2287 | } |
2288 | |
2289 | /* |
2290 | * MCR-based auto flow control. When AFE is enabled, RTS will be |
2291 | * deasserted when the receive FIFO contains more characters than |
2292 | * the trigger, or the MCR RTS bit is cleared. In the case where |
2293 | * the remote UART is not using CTS auto flow control, we must |
2294 | * have sufficient FIFO entries for the latency of the remote |
2295 | * UART to respond. IOW, at least 32 bytes of FIFO. |
2296 | */ |
2297 | if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) { |
2298 | up->mcr &= ~UART_MCR_AFE; |
2299 | if (termios->c_cflag & CRTSCTS) |
2300 | up->mcr |= UART_MCR_AFE; |
2301 | } |
2302 | |
2303 | /* |
2304 | * Ok, we're now changing the port state. Do it with |
2305 | * interrupts disabled. |
2306 | */ |
2307 | spin_lock_irqsave(&up->port.lock, flags); |
2308 | |
2309 | /* |
2310 | * Update the per-port timeout. |
2311 | */ |
2312 | uart_update_timeout(port, termios->c_cflag, baud); |
2313 | |
2314 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
2315 | if (termios->c_iflag & INPCK) |
2316 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
2317 | if (termios->c_iflag & (BRKINT | PARMRK)) |
2318 | up->port.read_status_mask |= UART_LSR_BI; |
2319 | |
2320 | /* |
2321 | * Characteres to ignore |
2322 | */ |
2323 | up->port.ignore_status_mask = 0; |
2324 | if (termios->c_iflag & IGNPAR) |
2325 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; |
2326 | if (termios->c_iflag & IGNBRK) { |
2327 | up->port.ignore_status_mask |= UART_LSR_BI; |
2328 | /* |
2329 | * If we're ignoring parity and break indicators, |
2330 | * ignore overruns too (for real raw support). |
2331 | */ |
2332 | if (termios->c_iflag & IGNPAR) |
2333 | up->port.ignore_status_mask |= UART_LSR_OE; |
2334 | } |
2335 | |
2336 | /* |
2337 | * ignore all characters if CREAD is not set |
2338 | */ |
2339 | if ((termios->c_cflag & CREAD) == 0) |
2340 | up->port.ignore_status_mask |= UART_LSR_DR; |
2341 | |
2342 | /* |
2343 | * CTS flow control flag and modem status interrupts |
2344 | */ |
2345 | up->ier &= ~UART_IER_MSI; |
2346 | if (!(up->bugs & UART_BUG_NOMSR) && |
2347 | UART_ENABLE_MS(&up->port, termios->c_cflag)) |
2348 | up->ier |= UART_IER_MSI; |
2349 | if (up->capabilities & UART_CAP_UUE) |
2350 | up->ier |= UART_IER_UUE | UART_IER_RTOIE; |
2351 | |
2352 | serial_out(up, UART_IER, up->ier); |
2353 | |
2354 | if (up->capabilities & UART_CAP_EFR) { |
2355 | unsigned char efr = 0; |
2356 | /* |
2357 | * TI16C752/Startech hardware flow control. FIXME: |
2358 | * - TI16C752 requires control thresholds to be set. |
2359 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. |
2360 | */ |
2361 | if (termios->c_cflag & CRTSCTS) |
2362 | efr |= UART_EFR_CTS; |
2363 | |
2364 | serial_outp(up, UART_LCR, 0xBF); |
2365 | serial_outp(up, UART_EFR, efr); |
2366 | } |
2367 | |
2368 | #ifdef CONFIG_ARCH_OMAP |
2369 | /* Workaround to enable 115200 baud on OMAP1510 internal ports */ |
2370 | if (cpu_is_omap1510() && is_omap_port(up)) { |
2371 | if (baud == 115200) { |
2372 | quot = 1; |
2373 | serial_out(up, UART_OMAP_OSC_12M_SEL, 1); |
2374 | } else |
2375 | serial_out(up, UART_OMAP_OSC_12M_SEL, 0); |
2376 | } |
2377 | #endif |
2378 | |
2379 | if (up->capabilities & UART_NATSEMI) { |
2380 | /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */ |
2381 | serial_outp(up, UART_LCR, 0xe0); |
2382 | } else { |
2383 | serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ |
2384 | } |
2385 | |
2386 | serial_dl_write(up, quot); |
2387 | |
2388 | /* |
2389 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR |
2390 | * is written without DLAB set, this mode will be disabled. |
2391 | */ |
2392 | if (up->port.type == PORT_16750) |
2393 | serial_outp(up, UART_FCR, fcr); |
2394 | |
2395 | serial_outp(up, UART_LCR, cval); /* reset DLAB */ |
2396 | up->lcr = cval; /* Save LCR */ |
2397 | if (up->port.type != PORT_16750) { |
2398 | if (fcr & UART_FCR_ENABLE_FIFO) { |
2399 | /* emulated UARTs (Lucent Venus 167x) need two steps */ |
2400 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
2401 | } |
2402 | serial_outp(up, UART_FCR, fcr); /* set fcr */ |
2403 | } |
2404 | serial8250_set_mctrl(&up->port, up->port.mctrl); |
2405 | spin_unlock_irqrestore(&up->port.lock, flags); |
2406 | /* Don't rewrite B0 */ |
2407 | if (tty_termios_baud_rate(termios)) |
2408 | tty_termios_encode_baud_rate(termios, baud, baud); |
2409 | } |
2410 | |
2411 | static void |
2412 | serial8250_set_ldisc(struct uart_port *port) |
2413 | { |
2414 | int line = port->line; |
2415 | |
2416 | if (line >= port->state->port.tty->driver->num) |
2417 | return; |
2418 | |
2419 | if (port->state->port.tty->ldisc->ops->num == N_PPS) { |
2420 | port->flags |= UPF_HARDPPS_CD; |
2421 | serial8250_enable_ms(port); |
2422 | } else |
2423 | port->flags &= ~UPF_HARDPPS_CD; |
2424 | } |
2425 | |
2426 | static void |
2427 | serial8250_pm(struct uart_port *port, unsigned int state, |
2428 | unsigned int oldstate) |
2429 | { |
2430 | struct uart_8250_port *p = (struct uart_8250_port *)port; |
2431 | |
2432 | serial8250_set_sleep(p, state != 0); |
2433 | |
2434 | if (p->pm) |
2435 | p->pm(port, state, oldstate); |
2436 | } |
2437 | |
2438 | static unsigned int serial8250_port_size(struct uart_8250_port *pt) |
2439 | { |
2440 | if (pt->port.iotype == UPIO_AU) |
2441 | return 0x1000; |
2442 | #ifdef CONFIG_ARCH_OMAP |
2443 | if (is_omap_port(pt)) |
2444 | return 0x16 << pt->port.regshift; |
2445 | #endif |
2446 | return 8 << pt->port.regshift; |
2447 | } |
2448 | |
2449 | /* |
2450 | * Resource handling. |
2451 | */ |
2452 | static int serial8250_request_std_resource(struct uart_8250_port *up) |
2453 | { |
2454 | unsigned int size = serial8250_port_size(up); |
2455 | int ret = 0; |
2456 | |
2457 | switch (up->port.iotype) { |
2458 | case UPIO_AU: |
2459 | case UPIO_TSI: |
2460 | case UPIO_MEM32: |
2461 | case UPIO_MEM: |
2462 | case UPIO_DWAPB: |
2463 | if (!up->port.mapbase) |
2464 | break; |
2465 | |
2466 | if (!request_mem_region(up->port.mapbase, size, "serial")) { |
2467 | ret = -EBUSY; |
2468 | break; |
2469 | } |
2470 | |
2471 | if (up->port.flags & UPF_IOREMAP) { |
2472 | up->port.membase = ioremap_nocache(up->port.mapbase, |
2473 | size); |
2474 | if (!up->port.membase) { |
2475 | release_mem_region(up->port.mapbase, size); |
2476 | ret = -ENOMEM; |
2477 | } |
2478 | } |
2479 | break; |
2480 | |
2481 | case UPIO_HUB6: |
2482 | case UPIO_PORT: |
2483 | if (!request_region(up->port.iobase, size, "serial")) |
2484 | ret = -EBUSY; |
2485 | break; |
2486 | } |
2487 | return ret; |
2488 | } |
2489 | |
2490 | static void serial8250_release_std_resource(struct uart_8250_port *up) |
2491 | { |
2492 | unsigned int size = serial8250_port_size(up); |
2493 | |
2494 | switch (up->port.iotype) { |
2495 | case UPIO_AU: |
2496 | case UPIO_TSI: |
2497 | case UPIO_MEM32: |
2498 | case UPIO_MEM: |
2499 | case UPIO_DWAPB: |
2500 | if (!up->port.mapbase) |
2501 | break; |
2502 | |
2503 | if (up->port.flags & UPF_IOREMAP) { |
2504 | iounmap(up->port.membase); |
2505 | up->port.membase = NULL; |
2506 | } |
2507 | |
2508 | release_mem_region(up->port.mapbase, size); |
2509 | break; |
2510 | |
2511 | case UPIO_HUB6: |
2512 | case UPIO_PORT: |
2513 | release_region(up->port.iobase, size); |
2514 | break; |
2515 | } |
2516 | } |
2517 | |
2518 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) |
2519 | { |
2520 | unsigned long start = UART_RSA_BASE << up->port.regshift; |
2521 | unsigned int size = 8 << up->port.regshift; |
2522 | int ret = -EINVAL; |
2523 | |
2524 | switch (up->port.iotype) { |
2525 | case UPIO_HUB6: |
2526 | case UPIO_PORT: |
2527 | start += up->port.iobase; |
2528 | if (request_region(start, size, "serial-rsa")) |
2529 | ret = 0; |
2530 | else |
2531 | ret = -EBUSY; |
2532 | break; |
2533 | } |
2534 | |
2535 | return ret; |
2536 | } |
2537 | |
2538 | static void serial8250_release_rsa_resource(struct uart_8250_port *up) |
2539 | { |
2540 | unsigned long offset = UART_RSA_BASE << up->port.regshift; |
2541 | unsigned int size = 8 << up->port.regshift; |
2542 | |
2543 | switch (up->port.iotype) { |
2544 | case UPIO_HUB6: |
2545 | case UPIO_PORT: |
2546 | release_region(up->port.iobase + offset, size); |
2547 | break; |
2548 | } |
2549 | } |
2550 | |
2551 | static void serial8250_release_port(struct uart_port *port) |
2552 | { |
2553 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2554 | |
2555 | serial8250_release_std_resource(up); |
2556 | if (up->port.type == PORT_RSA) |
2557 | serial8250_release_rsa_resource(up); |
2558 | } |
2559 | |
2560 | static int serial8250_request_port(struct uart_port *port) |
2561 | { |
2562 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2563 | int ret = 0; |
2564 | |
2565 | ret = serial8250_request_std_resource(up); |
2566 | if (ret == 0 && up->port.type == PORT_RSA) { |
2567 | ret = serial8250_request_rsa_resource(up); |
2568 | if (ret < 0) |
2569 | serial8250_release_std_resource(up); |
2570 | } |
2571 | |
2572 | return ret; |
2573 | } |
2574 | |
2575 | static void serial8250_config_port(struct uart_port *port, int flags) |
2576 | { |
2577 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2578 | int probeflags = PROBE_ANY; |
2579 | int ret; |
2580 | |
2581 | /* |
2582 | * Find the region that we can probe for. This in turn |
2583 | * tells us whether we can probe for the type of port. |
2584 | */ |
2585 | ret = serial8250_request_std_resource(up); |
2586 | if (ret < 0) |
2587 | return; |
2588 | |
2589 | ret = serial8250_request_rsa_resource(up); |
2590 | if (ret < 0) |
2591 | probeflags &= ~PROBE_RSA; |
2592 | |
2593 | if (up->port.iotype != up->cur_iotype) |
2594 | set_io_from_upio(port); |
2595 | |
2596 | if (flags & UART_CONFIG_TYPE) |
2597 | autoconfig(up, probeflags); |
2598 | |
2599 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
2600 | /* if access method is AU, it is a 16550 with a quirk */ |
2601 | if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU) |
2602 | up->bugs |= UART_BUG_NOMSR; |
2603 | #endif |
2604 | |
2605 | if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) |
2606 | autoconfig_irq(up); |
2607 | |
2608 | if (up->port.type != PORT_RSA && probeflags & PROBE_RSA) |
2609 | serial8250_release_rsa_resource(up); |
2610 | if (up->port.type == PORT_UNKNOWN) |
2611 | serial8250_release_std_resource(up); |
2612 | } |
2613 | |
2614 | static int |
2615 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) |
2616 | { |
2617 | if (ser->irq >= nr_irqs || ser->irq < 0 || |
2618 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || |
2619 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || |
2620 | ser->type == PORT_STARTECH) |
2621 | return -EINVAL; |
2622 | return 0; |
2623 | } |
2624 | |
2625 | static const char * |
2626 | serial8250_type(struct uart_port *port) |
2627 | { |
2628 | int type = port->type; |
2629 | |
2630 | if (type >= ARRAY_SIZE(uart_config)) |
2631 | type = 0; |
2632 | return uart_config[type].name; |
2633 | } |
2634 | |
2635 | static struct uart_ops serial8250_pops = { |
2636 | .tx_empty = serial8250_tx_empty, |
2637 | .set_mctrl = serial8250_set_mctrl, |
2638 | .get_mctrl = serial8250_get_mctrl, |
2639 | .stop_tx = serial8250_stop_tx, |
2640 | .start_tx = serial8250_start_tx, |
2641 | .stop_rx = serial8250_stop_rx, |
2642 | .enable_ms = serial8250_enable_ms, |
2643 | .break_ctl = serial8250_break_ctl, |
2644 | .startup = serial8250_startup, |
2645 | .shutdown = serial8250_shutdown, |
2646 | .set_termios = serial8250_set_termios, |
2647 | .set_ldisc = serial8250_set_ldisc, |
2648 | .pm = serial8250_pm, |
2649 | .type = serial8250_type, |
2650 | .release_port = serial8250_release_port, |
2651 | .request_port = serial8250_request_port, |
2652 | .config_port = serial8250_config_port, |
2653 | .verify_port = serial8250_verify_port, |
2654 | #ifdef CONFIG_CONSOLE_POLL |
2655 | .poll_get_char = serial8250_get_poll_char, |
2656 | .poll_put_char = serial8250_put_poll_char, |
2657 | #endif |
2658 | }; |
2659 | |
2660 | static struct uart_8250_port serial8250_ports[UART_NR]; |
2661 | |
2662 | static void __init serial8250_isa_init_ports(void) |
2663 | { |
2664 | struct uart_8250_port *up; |
2665 | static int first = 1; |
2666 | int i, irqflag = 0; |
2667 | |
2668 | if (!first) |
2669 | return; |
2670 | first = 0; |
2671 | |
2672 | for (i = 0; i < nr_uarts; i++) { |
2673 | struct uart_8250_port *up = &serial8250_ports[i]; |
2674 | |
2675 | up->port.line = i; |
2676 | spin_lock_init(&up->port.lock); |
2677 | |
2678 | init_timer(&up->timer); |
2679 | up->timer.function = serial8250_timeout; |
2680 | |
2681 | /* |
2682 | * ALPHA_KLUDGE_MCR needs to be killed. |
2683 | */ |
2684 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; |
2685 | up->mcr_force = ALPHA_KLUDGE_MCR; |
2686 | |
2687 | up->port.ops = &serial8250_pops; |
2688 | } |
2689 | |
2690 | if (share_irqs) |
2691 | irqflag = IRQF_SHARED; |
2692 | |
2693 | for (i = 0, up = serial8250_ports; |
2694 | i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; |
2695 | i++, up++) { |
2696 | up->port.iobase = old_serial_port[i].port; |
2697 | up->port.irq = irq_canonicalize(old_serial_port[i].irq); |
2698 | up->port.irqflags = old_serial_port[i].irqflags; |
2699 | up->port.uartclk = old_serial_port[i].baud_base * 16; |
2700 | up->port.flags = old_serial_port[i].flags; |
2701 | up->port.hub6 = old_serial_port[i].hub6; |
2702 | up->port.membase = old_serial_port[i].iomem_base; |
2703 | up->port.iotype = old_serial_port[i].io_type; |
2704 | up->port.regshift = old_serial_port[i].iomem_reg_shift; |
2705 | set_io_from_upio(&up->port); |
2706 | up->port.irqflags |= irqflag; |
2707 | } |
2708 | } |
2709 | |
2710 | static void |
2711 | serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type) |
2712 | { |
2713 | up->port.type = type; |
2714 | up->port.fifosize = uart_config[type].fifo_size; |
2715 | up->capabilities = uart_config[type].flags; |
2716 | up->tx_loadsz = uart_config[type].tx_loadsz; |
2717 | } |
2718 | |
2719 | static void __init |
2720 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) |
2721 | { |
2722 | int i; |
2723 | |
2724 | for (i = 0; i < nr_uarts; i++) { |
2725 | struct uart_8250_port *up = &serial8250_ports[i]; |
2726 | up->cur_iotype = 0xFF; |
2727 | } |
2728 | |
2729 | serial8250_isa_init_ports(); |
2730 | |
2731 | for (i = 0; i < nr_uarts; i++) { |
2732 | struct uart_8250_port *up = &serial8250_ports[i]; |
2733 | |
2734 | up->port.dev = dev; |
2735 | |
2736 | if (up->port.flags & UPF_FIXED_TYPE) |
2737 | serial8250_init_fixed_type_port(up, up->port.type); |
2738 | |
2739 | uart_add_one_port(drv, &up->port); |
2740 | } |
2741 | } |
2742 | |
2743 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
2744 | |
2745 | static void serial8250_console_putchar(struct uart_port *port, int ch) |
2746 | { |
2747 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2748 | |
2749 | wait_for_xmitr(up, UART_LSR_THRE); |
2750 | serial_out(up, UART_TX, ch); |
2751 | } |
2752 | |
2753 | /* |
2754 | * Print a string to the serial port trying not to disturb |
2755 | * any possible real use of the port... |
2756 | * |
2757 | * The console_lock must be held when we get here. |
2758 | */ |
2759 | static void |
2760 | serial8250_console_write(struct console *co, const char *s, unsigned int count) |
2761 | { |
2762 | struct uart_8250_port *up = &serial8250_ports[co->index]; |
2763 | unsigned long flags; |
2764 | unsigned int ier; |
2765 | int locked = 1; |
2766 | |
2767 | touch_nmi_watchdog(); |
2768 | |
2769 | local_irq_save(flags); |
2770 | if (up->port.sysrq) { |
2771 | /* serial8250_handle_port() already took the lock */ |
2772 | locked = 0; |
2773 | } else if (oops_in_progress) { |
2774 | locked = spin_trylock(&up->port.lock); |
2775 | } else |
2776 | spin_lock(&up->port.lock); |
2777 | |
2778 | /* |
2779 | * First save the IER then disable the interrupts |
2780 | */ |
2781 | ier = serial_in(up, UART_IER); |
2782 | |
2783 | if (up->capabilities & UART_CAP_UUE) |
2784 | serial_out(up, UART_IER, UART_IER_UUE); |
2785 | else |
2786 | serial_out(up, UART_IER, 0); |
2787 | |
2788 | uart_console_write(&up->port, s, count, serial8250_console_putchar); |
2789 | |
2790 | /* |
2791 | * Finally, wait for transmitter to become empty |
2792 | * and restore the IER |
2793 | */ |
2794 | wait_for_xmitr(up, BOTH_EMPTY); |
2795 | serial_out(up, UART_IER, ier); |
2796 | |
2797 | /* |
2798 | * The receive handling will happen properly because the |
2799 | * receive ready bit will still be set; it is not cleared |
2800 | * on read. However, modem control will not, we must |
2801 | * call it if we have saved something in the saved flags |
2802 | * while processing with interrupts off. |
2803 | */ |
2804 | if (up->msr_saved_flags) |
2805 | check_modem_status(up); |
2806 | |
2807 | if (locked) |
2808 | spin_unlock(&up->port.lock); |
2809 | local_irq_restore(flags); |
2810 | } |
2811 | |
2812 | static int __init serial8250_console_setup(struct console *co, char *options) |
2813 | { |
2814 | struct uart_port *port; |
2815 | int baud = 9600; |
2816 | int bits = 8; |
2817 | int parity = 'n'; |
2818 | int flow = 'n'; |
2819 | |
2820 | /* |
2821 | * Check whether an invalid uart number has been specified, and |
2822 | * if so, search for the first available port that does have |
2823 | * console support. |
2824 | */ |
2825 | if (co->index >= nr_uarts) |
2826 | co->index = 0; |
2827 | port = &serial8250_ports[co->index].port; |
2828 | if (!port->iobase && !port->membase) |
2829 | return -ENODEV; |
2830 | |
2831 | if (options) |
2832 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
2833 | |
2834 | return uart_set_options(port, co, baud, parity, bits, flow); |
2835 | } |
2836 | |
2837 | static int serial8250_console_early_setup(void) |
2838 | { |
2839 | return serial8250_find_port_for_earlycon(); |
2840 | } |
2841 | |
2842 | static struct console serial8250_console = { |
2843 | .name = "ttyS", |
2844 | .write = serial8250_console_write, |
2845 | .device = uart_console_device, |
2846 | .setup = serial8250_console_setup, |
2847 | .early_setup = serial8250_console_early_setup, |
2848 | .flags = CON_PRINTBUFFER, |
2849 | .index = -1, |
2850 | .data = &serial8250_reg, |
2851 | }; |
2852 | |
2853 | static int __init serial8250_console_init(void) |
2854 | { |
2855 | if (nr_uarts > UART_NR) |
2856 | nr_uarts = UART_NR; |
2857 | |
2858 | serial8250_isa_init_ports(); |
2859 | register_console(&serial8250_console); |
2860 | return 0; |
2861 | } |
2862 | console_initcall(serial8250_console_init); |
2863 | |
2864 | int serial8250_find_port(struct uart_port *p) |
2865 | { |
2866 | int line; |
2867 | struct uart_port *port; |
2868 | |
2869 | for (line = 0; line < nr_uarts; line++) { |
2870 | port = &serial8250_ports[line].port; |
2871 | if (uart_match_port(p, port)) |
2872 | return line; |
2873 | } |
2874 | return -ENODEV; |
2875 | } |
2876 | |
2877 | #define SERIAL8250_CONSOLE &serial8250_console |
2878 | #else |
2879 | #define SERIAL8250_CONSOLE NULL |
2880 | #endif |
2881 | |
2882 | static struct uart_driver serial8250_reg = { |
2883 | .owner = THIS_MODULE, |
2884 | .driver_name = "serial", |
2885 | .dev_name = "ttyS", |
2886 | .major = TTY_MAJOR, |
2887 | .minor = 64, |
2888 | .cons = SERIAL8250_CONSOLE, |
2889 | }; |
2890 | |
2891 | /* |
2892 | * early_serial_setup - early registration for 8250 ports |
2893 | * |
2894 | * Setup an 8250 port structure prior to console initialisation. Use |
2895 | * after console initialisation will cause undefined behaviour. |
2896 | */ |
2897 | int __init early_serial_setup(struct uart_port *port) |
2898 | { |
2899 | struct uart_port *p; |
2900 | |
2901 | if (port->line >= ARRAY_SIZE(serial8250_ports)) |
2902 | return -ENODEV; |
2903 | |
2904 | serial8250_isa_init_ports(); |
2905 | p = &serial8250_ports[port->line].port; |
2906 | p->iobase = port->iobase; |
2907 | p->membase = port->membase; |
2908 | p->irq = port->irq; |
2909 | p->irqflags = port->irqflags; |
2910 | p->uartclk = port->uartclk; |
2911 | p->fifosize = port->fifosize; |
2912 | p->regshift = port->regshift; |
2913 | p->iotype = port->iotype; |
2914 | p->flags = port->flags; |
2915 | p->mapbase = port->mapbase; |
2916 | p->private_data = port->private_data; |
2917 | p->type = port->type; |
2918 | p->line = port->line; |
2919 | |
2920 | set_io_from_upio(p); |
2921 | if (port->serial_in) |
2922 | p->serial_in = port->serial_in; |
2923 | if (port->serial_out) |
2924 | p->serial_out = port->serial_out; |
2925 | |
2926 | return 0; |
2927 | } |
2928 | |
2929 | /** |
2930 | * serial8250_suspend_port - suspend one serial port |
2931 | * @line: serial line number |
2932 | * |
2933 | * Suspend one serial port. |
2934 | */ |
2935 | void serial8250_suspend_port(int line) |
2936 | { |
2937 | uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); |
2938 | } |
2939 | |
2940 | /** |
2941 | * serial8250_resume_port - resume one serial port |
2942 | * @line: serial line number |
2943 | * |
2944 | * Resume one serial port. |
2945 | */ |
2946 | void serial8250_resume_port(int line) |
2947 | { |
2948 | struct uart_8250_port *up = &serial8250_ports[line]; |
2949 | |
2950 | if (up->capabilities & UART_NATSEMI) { |
2951 | unsigned char tmp; |
2952 | |
2953 | /* Ensure it's still in high speed mode */ |
2954 | serial_outp(up, UART_LCR, 0xE0); |
2955 | |
2956 | tmp = serial_in(up, 0x04); /* EXCR2 */ |
2957 | tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ |
2958 | tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ |
2959 | serial_outp(up, 0x04, tmp); |
2960 | |
2961 | serial_outp(up, UART_LCR, 0); |
2962 | } |
2963 | uart_resume_port(&serial8250_reg, &up->port); |
2964 | } |
2965 | |
2966 | /* |
2967 | * Register a set of serial devices attached to a platform device. The |
2968 | * list is terminated with a zero flags entry, which means we expect |
2969 | * all entries to have at least UPF_BOOT_AUTOCONF set. |
2970 | */ |
2971 | static int __devinit serial8250_probe(struct platform_device *dev) |
2972 | { |
2973 | struct plat_serial8250_port *p = dev->dev.platform_data; |
2974 | struct uart_port port; |
2975 | int ret, i, irqflag = 0; |
2976 | |
2977 | memset(&port, 0, sizeof(struct uart_port)); |
2978 | |
2979 | if (share_irqs) |
2980 | irqflag = IRQF_SHARED; |
2981 | |
2982 | for (i = 0; p && p->flags != 0; p++, i++) { |
2983 | port.iobase = p->iobase; |
2984 | port.membase = p->membase; |
2985 | port.irq = p->irq; |
2986 | port.irqflags = p->irqflags; |
2987 | port.uartclk = p->uartclk; |
2988 | port.regshift = p->regshift; |
2989 | port.iotype = p->iotype; |
2990 | port.flags = p->flags; |
2991 | port.mapbase = p->mapbase; |
2992 | port.hub6 = p->hub6; |
2993 | port.private_data = p->private_data; |
2994 | port.type = p->type; |
2995 | port.serial_in = p->serial_in; |
2996 | port.serial_out = p->serial_out; |
2997 | port.dev = &dev->dev; |
2998 | port.irqflags |= irqflag; |
2999 | ret = serial8250_register_port(&port); |
3000 | if (ret < 0) { |
3001 | dev_err(&dev->dev, "unable to register port at index %d " |
3002 | "(IO%lx MEM%llx IRQ%d): %d\n", i, |
3003 | p->iobase, (unsigned long long)p->mapbase, |
3004 | p->irq, ret); |
3005 | } |
3006 | } |
3007 | return 0; |
3008 | } |
3009 | |
3010 | /* |
3011 | * Remove serial ports registered against a platform device. |
3012 | */ |
3013 | static int __devexit serial8250_remove(struct platform_device *dev) |
3014 | { |
3015 | int i; |
3016 | |
3017 | for (i = 0; i < nr_uarts; i++) { |
3018 | struct uart_8250_port *up = &serial8250_ports[i]; |
3019 | |
3020 | if (up->port.dev == &dev->dev) |
3021 | serial8250_unregister_port(i); |
3022 | } |
3023 | return 0; |
3024 | } |
3025 | |
3026 | static int serial8250_suspend(struct platform_device *dev, pm_message_t state) |
3027 | { |
3028 | int i; |
3029 | |
3030 | for (i = 0; i < UART_NR; i++) { |
3031 | struct uart_8250_port *up = &serial8250_ports[i]; |
3032 | |
3033 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
3034 | uart_suspend_port(&serial8250_reg, &up->port); |
3035 | } |
3036 | |
3037 | return 0; |
3038 | } |
3039 | |
3040 | static int serial8250_resume(struct platform_device *dev) |
3041 | { |
3042 | int i; |
3043 | |
3044 | for (i = 0; i < UART_NR; i++) { |
3045 | struct uart_8250_port *up = &serial8250_ports[i]; |
3046 | |
3047 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
3048 | serial8250_resume_port(i); |
3049 | } |
3050 | |
3051 | return 0; |
3052 | } |
3053 | |
3054 | static struct platform_driver serial8250_isa_driver = { |
3055 | .probe = serial8250_probe, |
3056 | .remove = __devexit_p(serial8250_remove), |
3057 | .suspend = serial8250_suspend, |
3058 | .resume = serial8250_resume, |
3059 | .driver = { |
3060 | .name = "serial8250", |
3061 | .owner = THIS_MODULE, |
3062 | }, |
3063 | }; |
3064 | |
3065 | /* |
3066 | * This "device" covers _all_ ISA 8250-compatible serial devices listed |
3067 | * in the table in include/asm/serial.h |
3068 | */ |
3069 | static struct platform_device *serial8250_isa_devs; |
3070 | |
3071 | /* |
3072 | * serial8250_register_port and serial8250_unregister_port allows for |
3073 | * 16x50 serial ports to be configured at run-time, to support PCMCIA |
3074 | * modems and PCI multiport cards. |
3075 | */ |
3076 | static DEFINE_MUTEX(serial_mutex); |
3077 | |
3078 | static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) |
3079 | { |
3080 | int i; |
3081 | |
3082 | /* |
3083 | * First, find a port entry which matches. |
3084 | */ |
3085 | for (i = 0; i < nr_uarts; i++) |
3086 | if (uart_match_port(&serial8250_ports[i].port, port)) |
3087 | return &serial8250_ports[i]; |
3088 | |
3089 | /* |
3090 | * We didn't find a matching entry, so look for the first |
3091 | * free entry. We look for one which hasn't been previously |
3092 | * used (indicated by zero iobase). |
3093 | */ |
3094 | for (i = 0; i < nr_uarts; i++) |
3095 | if (serial8250_ports[i].port.type == PORT_UNKNOWN && |
3096 | serial8250_ports[i].port.iobase == 0) |
3097 | return &serial8250_ports[i]; |
3098 | |
3099 | /* |
3100 | * That also failed. Last resort is to find any entry which |
3101 | * doesn't have a real port associated with it. |
3102 | */ |
3103 | for (i = 0; i < nr_uarts; i++) |
3104 | if (serial8250_ports[i].port.type == PORT_UNKNOWN) |
3105 | return &serial8250_ports[i]; |
3106 | |
3107 | return NULL; |
3108 | } |
3109 | |
3110 | /** |
3111 | * serial8250_register_port - register a serial port |
3112 | * @port: serial port template |
3113 | * |
3114 | * Configure the serial port specified by the request. If the |
3115 | * port exists and is in use, it is hung up and unregistered |
3116 | * first. |
3117 | * |
3118 | * The port is then probed and if necessary the IRQ is autodetected |
3119 | * If this fails an error is returned. |
3120 | * |
3121 | * On success the port is ready to use and the line number is returned. |
3122 | */ |
3123 | int serial8250_register_port(struct uart_port *port) |
3124 | { |
3125 | struct uart_8250_port *uart; |
3126 | int ret = -ENOSPC; |
3127 | |
3128 | if (port->uartclk == 0) |
3129 | return -EINVAL; |
3130 | |
3131 | mutex_lock(&serial_mutex); |
3132 | |
3133 | uart = serial8250_find_match_or_unused(port); |
3134 | if (uart) { |
3135 | uart_remove_one_port(&serial8250_reg, &uart->port); |
3136 | |
3137 | uart->port.iobase = port->iobase; |
3138 | uart->port.membase = port->membase; |
3139 | uart->port.irq = port->irq; |
3140 | uart->port.irqflags = port->irqflags; |
3141 | uart->port.uartclk = port->uartclk; |
3142 | uart->port.fifosize = port->fifosize; |
3143 | uart->port.regshift = port->regshift; |
3144 | uart->port.iotype = port->iotype; |
3145 | uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; |
3146 | uart->port.mapbase = port->mapbase; |
3147 | uart->port.private_data = port->private_data; |
3148 | if (port->dev) |
3149 | uart->port.dev = port->dev; |
3150 | |
3151 | if (port->flags & UPF_FIXED_TYPE) |
3152 | serial8250_init_fixed_type_port(uart, port->type); |
3153 | |
3154 | set_io_from_upio(&uart->port); |
3155 | /* Possibly override default I/O functions. */ |
3156 | if (port->serial_in) |
3157 | uart->port.serial_in = port->serial_in; |
3158 | if (port->serial_out) |
3159 | uart->port.serial_out = port->serial_out; |
3160 | |
3161 | ret = uart_add_one_port(&serial8250_reg, &uart->port); |
3162 | if (ret == 0) |
3163 | ret = uart->port.line; |
3164 | } |
3165 | mutex_unlock(&serial_mutex); |
3166 | |
3167 | return ret; |
3168 | } |
3169 | EXPORT_SYMBOL(serial8250_register_port); |
3170 | |
3171 | /** |
3172 | * serial8250_unregister_port - remove a 16x50 serial port at runtime |
3173 | * @line: serial line number |
3174 | * |
3175 | * Remove one serial port. This may not be called from interrupt |
3176 | * context. We hand the port back to the our control. |
3177 | */ |
3178 | void serial8250_unregister_port(int line) |
3179 | { |
3180 | struct uart_8250_port *uart = &serial8250_ports[line]; |
3181 | |
3182 | mutex_lock(&serial_mutex); |
3183 | uart_remove_one_port(&serial8250_reg, &uart->port); |
3184 | if (serial8250_isa_devs) { |
3185 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; |
3186 | uart->port.type = PORT_UNKNOWN; |
3187 | uart->port.dev = &serial8250_isa_devs->dev; |
3188 | uart_add_one_port(&serial8250_reg, &uart->port); |
3189 | } else { |
3190 | uart->port.dev = NULL; |
3191 | } |
3192 | mutex_unlock(&serial_mutex); |
3193 | } |
3194 | EXPORT_SYMBOL(serial8250_unregister_port); |
3195 | |
3196 | static int __init serial8250_init(void) |
3197 | { |
3198 | int ret; |
3199 | |
3200 | if (nr_uarts > UART_NR) |
3201 | nr_uarts = UART_NR; |
3202 | |
3203 | printk(KERN_INFO "Serial: 8250/16550 driver, " |
3204 | "%d ports, IRQ sharing %sabled\n", nr_uarts, |
3205 | share_irqs ? "en" : "dis"); |
3206 | |
3207 | #ifdef CONFIG_SPARC |
3208 | ret = sunserial_register_minors(&serial8250_reg, UART_NR); |
3209 | #else |
3210 | serial8250_reg.nr = UART_NR; |
3211 | ret = uart_register_driver(&serial8250_reg); |
3212 | #endif |
3213 | if (ret) |
3214 | goto out; |
3215 | |
3216 | serial8250_isa_devs = platform_device_alloc("serial8250", |
3217 | PLAT8250_DEV_LEGACY); |
3218 | if (!serial8250_isa_devs) { |
3219 | ret = -ENOMEM; |
3220 | goto unreg_uart_drv; |
3221 | } |
3222 | |
3223 | ret = platform_device_add(serial8250_isa_devs); |
3224 | if (ret) |
3225 | goto put_dev; |
3226 | |
3227 | serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); |
3228 | |
3229 | ret = platform_driver_register(&serial8250_isa_driver); |
3230 | if (ret == 0) |
3231 | goto out; |
3232 | |
3233 | platform_device_del(serial8250_isa_devs); |
3234 | put_dev: |
3235 | platform_device_put(serial8250_isa_devs); |
3236 | unreg_uart_drv: |
3237 | #ifdef CONFIG_SPARC |
3238 | sunserial_unregister_minors(&serial8250_reg, UART_NR); |
3239 | #else |
3240 | uart_unregister_driver(&serial8250_reg); |
3241 | #endif |
3242 | out: |
3243 | return ret; |
3244 | } |
3245 | |
3246 | static void __exit serial8250_exit(void) |
3247 | { |
3248 | struct platform_device *isa_dev = serial8250_isa_devs; |
3249 | |
3250 | /* |
3251 | * This tells serial8250_unregister_port() not to re-register |
3252 | * the ports (thereby making serial8250_isa_driver permanently |
3253 | * in use.) |
3254 | */ |
3255 | serial8250_isa_devs = NULL; |
3256 | |
3257 | platform_driver_unregister(&serial8250_isa_driver); |
3258 | platform_device_unregister(isa_dev); |
3259 | |
3260 | #ifdef CONFIG_SPARC |
3261 | sunserial_unregister_minors(&serial8250_reg, UART_NR); |
3262 | #else |
3263 | uart_unregister_driver(&serial8250_reg); |
3264 | #endif |
3265 | } |
3266 | |
3267 | module_init(serial8250_init); |
3268 | module_exit(serial8250_exit); |
3269 | |
3270 | EXPORT_SYMBOL(serial8250_suspend_port); |
3271 | EXPORT_SYMBOL(serial8250_resume_port); |
3272 | |
3273 | MODULE_LICENSE("GPL"); |
3274 | MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); |
3275 | |
3276 | module_param(share_irqs, uint, 0644); |
3277 | MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" |
3278 | " (unsafe)"); |
3279 | |
3280 | module_param(nr_uarts, uint, 0644); |
3281 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); |
3282 | |
3283 | module_param(skip_txen_test, uint, 0644); |
3284 | MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); |
3285 | |
3286 | #ifdef CONFIG_SERIAL_8250_RSA |
3287 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); |
3288 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); |
3289 | #endif |
3290 | MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); |
3291 |
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