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1 | /* |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 |
4 | * |
5 | * License Terms: GNU General Public License v2 |
6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
7 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> |
8 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> |
9 | * |
10 | * U8500 PRCM Unit interface driver |
11 | * |
12 | */ |
13 | #include <linux/module.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/delay.h> |
16 | #include <linux/errno.h> |
17 | #include <linux/err.h> |
18 | #include <linux/spinlock.h> |
19 | #include <linux/io.h> |
20 | #include <linux/slab.h> |
21 | #include <linux/mutex.h> |
22 | #include <linux/completion.h> |
23 | #include <linux/irq.h> |
24 | #include <linux/jiffies.h> |
25 | #include <linux/bitops.h> |
26 | #include <linux/fs.h> |
27 | #include <linux/platform_device.h> |
28 | #include <linux/uaccess.h> |
29 | #include <linux/irqchip/arm-gic.h> |
30 | #include <linux/mfd/core.h> |
31 | #include <linux/mfd/dbx500-prcmu.h> |
32 | #include <linux/mfd/abx500/ab8500.h> |
33 | #include <linux/regulator/db8500-prcmu.h> |
34 | #include <linux/regulator/machine.h> |
35 | #include <linux/cpufreq.h> |
36 | #include <linux/platform_data/ux500_wdt.h> |
37 | #include <mach/hardware.h> |
38 | #include <mach/irqs.h> |
39 | #include <mach/db8500-regs.h> |
40 | #include "dbx500-prcmu-regs.h" |
41 | |
42 | /* Index of different voltages to be used when accessing AVSData */ |
43 | #define PRCM_AVS_BASE 0x2FC |
44 | #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) |
45 | #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) |
46 | #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) |
47 | #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) |
48 | #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) |
49 | #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) |
50 | #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) |
51 | #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) |
52 | #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) |
53 | #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) |
54 | #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) |
55 | #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) |
56 | #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) |
57 | |
58 | #define PRCM_AVS_VOLTAGE 0 |
59 | #define PRCM_AVS_VOLTAGE_MASK 0x3f |
60 | #define PRCM_AVS_ISSLOWSTARTUP 6 |
61 | #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) |
62 | #define PRCM_AVS_ISMODEENABLE 7 |
63 | #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) |
64 | |
65 | #define PRCM_BOOT_STATUS 0xFFF |
66 | #define PRCM_ROMCODE_A2P 0xFFE |
67 | #define PRCM_ROMCODE_P2A 0xFFD |
68 | #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ |
69 | |
70 | #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ |
71 | |
72 | #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ |
73 | #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) |
74 | #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) |
75 | #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) |
76 | #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) |
77 | #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) |
78 | #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) |
79 | #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) |
80 | |
81 | /* Req Mailboxes */ |
82 | #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ |
83 | #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ |
84 | #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ |
85 | #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ |
86 | #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ |
87 | #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ |
88 | |
89 | /* Ack Mailboxes */ |
90 | #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ |
91 | #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ |
92 | #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ |
93 | #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ |
94 | #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ |
95 | #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ |
96 | |
97 | /* Mailbox 0 headers */ |
98 | #define MB0H_POWER_STATE_TRANS 0 |
99 | #define MB0H_CONFIG_WAKEUPS_EXE 1 |
100 | #define MB0H_READ_WAKEUP_ACK 3 |
101 | #define MB0H_CONFIG_WAKEUPS_SLEEP 4 |
102 | |
103 | #define MB0H_WAKEUP_EXE 2 |
104 | #define MB0H_WAKEUP_SLEEP 5 |
105 | |
106 | /* Mailbox 0 REQs */ |
107 | #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) |
108 | #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) |
109 | #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) |
110 | #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) |
111 | #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) |
112 | #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) |
113 | |
114 | /* Mailbox 0 ACKs */ |
115 | #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) |
116 | #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) |
117 | #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) |
118 | #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) |
119 | #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) |
120 | #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) |
121 | #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 |
122 | |
123 | /* Mailbox 1 headers */ |
124 | #define MB1H_ARM_APE_OPP 0x0 |
125 | #define MB1H_RESET_MODEM 0x2 |
126 | #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 |
127 | #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 |
128 | #define MB1H_RELEASE_USB_WAKEUP 0x5 |
129 | #define MB1H_PLL_ON_OFF 0x6 |
130 | |
131 | /* Mailbox 1 Requests */ |
132 | #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) |
133 | #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) |
134 | #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) |
135 | #define PLL_SOC0_OFF 0x1 |
136 | #define PLL_SOC0_ON 0x2 |
137 | #define PLL_SOC1_OFF 0x4 |
138 | #define PLL_SOC1_ON 0x8 |
139 | |
140 | /* Mailbox 1 ACKs */ |
141 | #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) |
142 | #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) |
143 | #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) |
144 | #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) |
145 | |
146 | /* Mailbox 2 headers */ |
147 | #define MB2H_DPS 0x0 |
148 | #define MB2H_AUTO_PWR 0x1 |
149 | |
150 | /* Mailbox 2 REQs */ |
151 | #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) |
152 | #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) |
153 | #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) |
154 | #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) |
155 | #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) |
156 | #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) |
157 | #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) |
158 | #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) |
159 | #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) |
160 | #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) |
161 | |
162 | /* Mailbox 2 ACKs */ |
163 | #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) |
164 | #define HWACC_PWR_ST_OK 0xFE |
165 | |
166 | /* Mailbox 3 headers */ |
167 | #define MB3H_ANC 0x0 |
168 | #define MB3H_SIDETONE 0x1 |
169 | #define MB3H_SYSCLK 0xE |
170 | |
171 | /* Mailbox 3 Requests */ |
172 | #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) |
173 | #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) |
174 | #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) |
175 | #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) |
176 | #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) |
177 | #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) |
178 | #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) |
179 | |
180 | /* Mailbox 4 headers */ |
181 | #define MB4H_DDR_INIT 0x0 |
182 | #define MB4H_MEM_ST 0x1 |
183 | #define MB4H_HOTDOG 0x12 |
184 | #define MB4H_HOTMON 0x13 |
185 | #define MB4H_HOT_PERIOD 0x14 |
186 | #define MB4H_A9WDOG_CONF 0x16 |
187 | #define MB4H_A9WDOG_EN 0x17 |
188 | #define MB4H_A9WDOG_DIS 0x18 |
189 | #define MB4H_A9WDOG_LOAD 0x19 |
190 | #define MB4H_A9WDOG_KICK 0x20 |
191 | |
192 | /* Mailbox 4 Requests */ |
193 | #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) |
194 | #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) |
195 | #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) |
196 | #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) |
197 | #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) |
198 | #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) |
199 | #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) |
200 | #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) |
201 | #define HOTMON_CONFIG_LOW BIT(0) |
202 | #define HOTMON_CONFIG_HIGH BIT(1) |
203 | #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) |
204 | #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) |
205 | #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) |
206 | #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) |
207 | #define A9WDOG_AUTO_OFF_EN BIT(7) |
208 | #define A9WDOG_AUTO_OFF_DIS 0 |
209 | #define A9WDOG_ID_MASK 0xf |
210 | |
211 | /* Mailbox 5 Requests */ |
212 | #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) |
213 | #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) |
214 | #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) |
215 | #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) |
216 | #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6)) |
217 | #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6)) |
218 | #define PRCMU_I2C_STOP_EN BIT(3) |
219 | |
220 | /* Mailbox 5 ACKs */ |
221 | #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) |
222 | #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) |
223 | #define I2C_WR_OK 0x1 |
224 | #define I2C_RD_OK 0x2 |
225 | |
226 | #define NUM_MB 8 |
227 | #define MBOX_BIT BIT |
228 | #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) |
229 | |
230 | /* |
231 | * Wakeups/IRQs |
232 | */ |
233 | |
234 | #define WAKEUP_BIT_RTC BIT(0) |
235 | #define WAKEUP_BIT_RTT0 BIT(1) |
236 | #define WAKEUP_BIT_RTT1 BIT(2) |
237 | #define WAKEUP_BIT_HSI0 BIT(3) |
238 | #define WAKEUP_BIT_HSI1 BIT(4) |
239 | #define WAKEUP_BIT_CA_WAKE BIT(5) |
240 | #define WAKEUP_BIT_USB BIT(6) |
241 | #define WAKEUP_BIT_ABB BIT(7) |
242 | #define WAKEUP_BIT_ABB_FIFO BIT(8) |
243 | #define WAKEUP_BIT_SYSCLK_OK BIT(9) |
244 | #define WAKEUP_BIT_CA_SLEEP BIT(10) |
245 | #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) |
246 | #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) |
247 | #define WAKEUP_BIT_ANC_OK BIT(13) |
248 | #define WAKEUP_BIT_SW_ERROR BIT(14) |
249 | #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) |
250 | #define WAKEUP_BIT_ARM BIT(17) |
251 | #define WAKEUP_BIT_HOTMON_LOW BIT(18) |
252 | #define WAKEUP_BIT_HOTMON_HIGH BIT(19) |
253 | #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) |
254 | #define WAKEUP_BIT_GPIO0 BIT(23) |
255 | #define WAKEUP_BIT_GPIO1 BIT(24) |
256 | #define WAKEUP_BIT_GPIO2 BIT(25) |
257 | #define WAKEUP_BIT_GPIO3 BIT(26) |
258 | #define WAKEUP_BIT_GPIO4 BIT(27) |
259 | #define WAKEUP_BIT_GPIO5 BIT(28) |
260 | #define WAKEUP_BIT_GPIO6 BIT(29) |
261 | #define WAKEUP_BIT_GPIO7 BIT(30) |
262 | #define WAKEUP_BIT_GPIO8 BIT(31) |
263 | |
264 | static struct { |
265 | bool valid; |
266 | struct prcmu_fw_version version; |
267 | } fw_info; |
268 | |
269 | static struct irq_domain *db8500_irq_domain; |
270 | |
271 | /* |
272 | * This vector maps irq numbers to the bits in the bit field used in |
273 | * communication with the PRCMU firmware. |
274 | * |
275 | * The reason for having this is to keep the irq numbers contiguous even though |
276 | * the bits in the bit field are not. (The bits also have a tendency to move |
277 | * around, to further complicate matters.) |
278 | */ |
279 | #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) |
280 | #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) |
281 | static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { |
282 | IRQ_ENTRY(RTC), |
283 | IRQ_ENTRY(RTT0), |
284 | IRQ_ENTRY(RTT1), |
285 | IRQ_ENTRY(HSI0), |
286 | IRQ_ENTRY(HSI1), |
287 | IRQ_ENTRY(CA_WAKE), |
288 | IRQ_ENTRY(USB), |
289 | IRQ_ENTRY(ABB), |
290 | IRQ_ENTRY(ABB_FIFO), |
291 | IRQ_ENTRY(CA_SLEEP), |
292 | IRQ_ENTRY(ARM), |
293 | IRQ_ENTRY(HOTMON_LOW), |
294 | IRQ_ENTRY(HOTMON_HIGH), |
295 | IRQ_ENTRY(MODEM_SW_RESET_REQ), |
296 | IRQ_ENTRY(GPIO0), |
297 | IRQ_ENTRY(GPIO1), |
298 | IRQ_ENTRY(GPIO2), |
299 | IRQ_ENTRY(GPIO3), |
300 | IRQ_ENTRY(GPIO4), |
301 | IRQ_ENTRY(GPIO5), |
302 | IRQ_ENTRY(GPIO6), |
303 | IRQ_ENTRY(GPIO7), |
304 | IRQ_ENTRY(GPIO8) |
305 | }; |
306 | |
307 | #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) |
308 | #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) |
309 | static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { |
310 | WAKEUP_ENTRY(RTC), |
311 | WAKEUP_ENTRY(RTT0), |
312 | WAKEUP_ENTRY(RTT1), |
313 | WAKEUP_ENTRY(HSI0), |
314 | WAKEUP_ENTRY(HSI1), |
315 | WAKEUP_ENTRY(USB), |
316 | WAKEUP_ENTRY(ABB), |
317 | WAKEUP_ENTRY(ABB_FIFO), |
318 | WAKEUP_ENTRY(ARM) |
319 | }; |
320 | |
321 | /* |
322 | * mb0_transfer - state needed for mailbox 0 communication. |
323 | * @lock: The transaction lock. |
324 | * @dbb_events_lock: A lock used to handle concurrent access to (parts of) |
325 | * the request data. |
326 | * @mask_work: Work structure used for (un)masking wakeup interrupts. |
327 | * @req: Request data that need to persist between requests. |
328 | */ |
329 | static struct { |
330 | spinlock_t lock; |
331 | spinlock_t dbb_irqs_lock; |
332 | struct work_struct mask_work; |
333 | struct mutex ac_wake_lock; |
334 | struct completion ac_wake_work; |
335 | struct { |
336 | u32 dbb_irqs; |
337 | u32 dbb_wakeups; |
338 | u32 abb_events; |
339 | } req; |
340 | } mb0_transfer; |
341 | |
342 | /* |
343 | * mb1_transfer - state needed for mailbox 1 communication. |
344 | * @lock: The transaction lock. |
345 | * @work: The transaction completion structure. |
346 | * @ape_opp: The current APE OPP. |
347 | * @ack: Reply ("acknowledge") data. |
348 | */ |
349 | static struct { |
350 | struct mutex lock; |
351 | struct completion work; |
352 | u8 ape_opp; |
353 | struct { |
354 | u8 header; |
355 | u8 arm_opp; |
356 | u8 ape_opp; |
357 | u8 ape_voltage_status; |
358 | } ack; |
359 | } mb1_transfer; |
360 | |
361 | /* |
362 | * mb2_transfer - state needed for mailbox 2 communication. |
363 | * @lock: The transaction lock. |
364 | * @work: The transaction completion structure. |
365 | * @auto_pm_lock: The autonomous power management configuration lock. |
366 | * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. |
367 | * @req: Request data that need to persist between requests. |
368 | * @ack: Reply ("acknowledge") data. |
369 | */ |
370 | static struct { |
371 | struct mutex lock; |
372 | struct completion work; |
373 | spinlock_t auto_pm_lock; |
374 | bool auto_pm_enabled; |
375 | struct { |
376 | u8 status; |
377 | } ack; |
378 | } mb2_transfer; |
379 | |
380 | /* |
381 | * mb3_transfer - state needed for mailbox 3 communication. |
382 | * @lock: The request lock. |
383 | * @sysclk_lock: A lock used to handle concurrent sysclk requests. |
384 | * @sysclk_work: Work structure used for sysclk requests. |
385 | */ |
386 | static struct { |
387 | spinlock_t lock; |
388 | struct mutex sysclk_lock; |
389 | struct completion sysclk_work; |
390 | } mb3_transfer; |
391 | |
392 | /* |
393 | * mb4_transfer - state needed for mailbox 4 communication. |
394 | * @lock: The transaction lock. |
395 | * @work: The transaction completion structure. |
396 | */ |
397 | static struct { |
398 | struct mutex lock; |
399 | struct completion work; |
400 | } mb4_transfer; |
401 | |
402 | /* |
403 | * mb5_transfer - state needed for mailbox 5 communication. |
404 | * @lock: The transaction lock. |
405 | * @work: The transaction completion structure. |
406 | * @ack: Reply ("acknowledge") data. |
407 | */ |
408 | static struct { |
409 | struct mutex lock; |
410 | struct completion work; |
411 | struct { |
412 | u8 status; |
413 | u8 value; |
414 | } ack; |
415 | } mb5_transfer; |
416 | |
417 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); |
418 | |
419 | /* Spinlocks */ |
420 | static DEFINE_SPINLOCK(prcmu_lock); |
421 | static DEFINE_SPINLOCK(clkout_lock); |
422 | |
423 | /* Global var to runtime determine TCDM base for v2 or v1 */ |
424 | static __iomem void *tcdm_base; |
425 | |
426 | struct clk_mgt { |
427 | void __iomem *reg; |
428 | u32 pllsw; |
429 | int branch; |
430 | bool clk38div; |
431 | }; |
432 | |
433 | enum { |
434 | PLL_RAW, |
435 | PLL_FIX, |
436 | PLL_DIV |
437 | }; |
438 | |
439 | static DEFINE_SPINLOCK(clk_mgt_lock); |
440 | |
441 | #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ |
442 | { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} |
443 | struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { |
444 | CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), |
445 | CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), |
446 | CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), |
447 | CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), |
448 | CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), |
449 | CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), |
450 | CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), |
451 | CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), |
452 | CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), |
453 | CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), |
454 | CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), |
455 | CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), |
456 | CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), |
457 | CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), |
458 | CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), |
459 | CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), |
460 | CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), |
461 | CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), |
462 | CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), |
463 | CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), |
464 | CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), |
465 | CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), |
466 | CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), |
467 | CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), |
468 | CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), |
469 | CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), |
470 | CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), |
471 | CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), |
472 | CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), |
473 | }; |
474 | |
475 | struct dsiclk { |
476 | u32 divsel_mask; |
477 | u32 divsel_shift; |
478 | u32 divsel; |
479 | }; |
480 | |
481 | static struct dsiclk dsiclk[2] = { |
482 | { |
483 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, |
484 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, |
485 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, |
486 | }, |
487 | { |
488 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, |
489 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, |
490 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, |
491 | } |
492 | }; |
493 | |
494 | struct dsiescclk { |
495 | u32 en; |
496 | u32 div_mask; |
497 | u32 div_shift; |
498 | }; |
499 | |
500 | static struct dsiescclk dsiescclk[3] = { |
501 | { |
502 | .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, |
503 | .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, |
504 | .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, |
505 | }, |
506 | { |
507 | .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, |
508 | .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, |
509 | .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, |
510 | }, |
511 | { |
512 | .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, |
513 | .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, |
514 | .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, |
515 | } |
516 | }; |
517 | |
518 | |
519 | /* |
520 | * Used by MCDE to setup all necessary PRCMU registers |
521 | */ |
522 | #define PRCMU_RESET_DSIPLL 0x00004000 |
523 | #define PRCMU_UNCLAMP_DSIPLL 0x00400800 |
524 | |
525 | #define PRCMU_CLK_PLL_DIV_SHIFT 0 |
526 | #define PRCMU_CLK_PLL_SW_SHIFT 5 |
527 | #define PRCMU_CLK_38 (1 << 9) |
528 | #define PRCMU_CLK_38_SRC (1 << 10) |
529 | #define PRCMU_CLK_38_DIV (1 << 11) |
530 | |
531 | /* PLLDIV=12, PLLSW=4 (PLLDDR) */ |
532 | #define PRCMU_DSI_CLOCK_SETTING 0x0000008C |
533 | |
534 | /* DPI 50000000 Hz */ |
535 | #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ |
536 | (16 << PRCMU_CLK_PLL_DIV_SHIFT)) |
537 | #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 |
538 | |
539 | /* D=101, N=1, R=4, SELDIV2=0 */ |
540 | #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 |
541 | |
542 | #define PRCMU_ENABLE_PLLDSI 0x00000001 |
543 | #define PRCMU_DISABLE_PLLDSI 0x00000000 |
544 | #define PRCMU_RELEASE_RESET_DSS 0x0000400C |
545 | #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 |
546 | /* ESC clk, div0=1, div1=1, div2=3 */ |
547 | #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 |
548 | #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 |
549 | #define PRCMU_DSI_RESET_SW 0x00000007 |
550 | |
551 | #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 |
552 | |
553 | int db8500_prcmu_enable_dsipll(void) |
554 | { |
555 | int i; |
556 | |
557 | /* Clear DSIPLL_RESETN */ |
558 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); |
559 | /* Unclamp DSIPLL in/out */ |
560 | writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); |
561 | |
562 | /* Set DSI PLL FREQ */ |
563 | writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); |
564 | writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); |
565 | /* Enable Escape clocks */ |
566 | writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
567 | |
568 | /* Start DSI PLL */ |
569 | writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
570 | /* Reset DSI PLL */ |
571 | writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); |
572 | for (i = 0; i < 10; i++) { |
573 | if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) |
574 | == PRCMU_PLLDSI_LOCKP_LOCKED) |
575 | break; |
576 | udelay(100); |
577 | } |
578 | /* Set DSIPLL_RESETN */ |
579 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); |
580 | return 0; |
581 | } |
582 | |
583 | int db8500_prcmu_disable_dsipll(void) |
584 | { |
585 | /* Disable dsi pll */ |
586 | writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
587 | /* Disable escapeclock */ |
588 | writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
589 | return 0; |
590 | } |
591 | |
592 | int db8500_prcmu_set_display_clocks(void) |
593 | { |
594 | unsigned long flags; |
595 | |
596 | spin_lock_irqsave(&clk_mgt_lock, flags); |
597 | |
598 | /* Grab the HW semaphore. */ |
599 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
600 | cpu_relax(); |
601 | |
602 | writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); |
603 | writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); |
604 | writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); |
605 | |
606 | /* Release the HW semaphore. */ |
607 | writel(0, PRCM_SEM); |
608 | |
609 | spin_unlock_irqrestore(&clk_mgt_lock, flags); |
610 | |
611 | return 0; |
612 | } |
613 | |
614 | u32 db8500_prcmu_read(unsigned int reg) |
615 | { |
616 | return readl(_PRCMU_BASE + reg); |
617 | } |
618 | |
619 | void db8500_prcmu_write(unsigned int reg, u32 value) |
620 | { |
621 | unsigned long flags; |
622 | |
623 | spin_lock_irqsave(&prcmu_lock, flags); |
624 | writel(value, (_PRCMU_BASE + reg)); |
625 | spin_unlock_irqrestore(&prcmu_lock, flags); |
626 | } |
627 | |
628 | void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) |
629 | { |
630 | u32 val; |
631 | unsigned long flags; |
632 | |
633 | spin_lock_irqsave(&prcmu_lock, flags); |
634 | val = readl(_PRCMU_BASE + reg); |
635 | val = ((val & ~mask) | (value & mask)); |
636 | writel(val, (_PRCMU_BASE + reg)); |
637 | spin_unlock_irqrestore(&prcmu_lock, flags); |
638 | } |
639 | |
640 | struct prcmu_fw_version *prcmu_get_fw_version(void) |
641 | { |
642 | return fw_info.valid ? &fw_info.version : NULL; |
643 | } |
644 | |
645 | bool prcmu_has_arm_maxopp(void) |
646 | { |
647 | return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & |
648 | PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; |
649 | } |
650 | |
651 | /** |
652 | * prcmu_get_boot_status - PRCMU boot status checking |
653 | * Returns: the current PRCMU boot status |
654 | */ |
655 | int prcmu_get_boot_status(void) |
656 | { |
657 | return readb(tcdm_base + PRCM_BOOT_STATUS); |
658 | } |
659 | |
660 | /** |
661 | * prcmu_set_rc_a2p - This function is used to run few power state sequences |
662 | * @val: Value to be set, i.e. transition requested |
663 | * Returns: 0 on success, -EINVAL on invalid argument |
664 | * |
665 | * This function is used to run the following power state sequences - |
666 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep |
667 | */ |
668 | int prcmu_set_rc_a2p(enum romcode_write val) |
669 | { |
670 | if (val < RDY_2_DS || val > RDY_2_XP70_RST) |
671 | return -EINVAL; |
672 | writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); |
673 | return 0; |
674 | } |
675 | |
676 | /** |
677 | * prcmu_get_rc_p2a - This function is used to get power state sequences |
678 | * Returns: the power transition that has last happened |
679 | * |
680 | * This function can return the following transitions- |
681 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep |
682 | */ |
683 | enum romcode_read prcmu_get_rc_p2a(void) |
684 | { |
685 | return readb(tcdm_base + PRCM_ROMCODE_P2A); |
686 | } |
687 | |
688 | /** |
689 | * prcmu_get_current_mode - Return the current XP70 power mode |
690 | * Returns: Returns the current AP(ARM) power mode: init, |
691 | * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset |
692 | */ |
693 | enum ap_pwrst prcmu_get_xp70_current_state(void) |
694 | { |
695 | return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); |
696 | } |
697 | |
698 | /** |
699 | * prcmu_config_clkout - Configure one of the programmable clock outputs. |
700 | * @clkout: The CLKOUT number (0 or 1). |
701 | * @source: The clock to be used (one of the PRCMU_CLKSRC_*). |
702 | * @div: The divider to be applied. |
703 | * |
704 | * Configures one of the programmable clock outputs (CLKOUTs). |
705 | * @div should be in the range [1,63] to request a configuration, or 0 to |
706 | * inform that the configuration is no longer requested. |
707 | */ |
708 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div) |
709 | { |
710 | static int requests[2]; |
711 | int r = 0; |
712 | unsigned long flags; |
713 | u32 val; |
714 | u32 bits; |
715 | u32 mask; |
716 | u32 div_mask; |
717 | |
718 | BUG_ON(clkout > 1); |
719 | BUG_ON(div > 63); |
720 | BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); |
721 | |
722 | if (!div && !requests[clkout]) |
723 | return -EINVAL; |
724 | |
725 | switch (clkout) { |
726 | case 0: |
727 | div_mask = PRCM_CLKOCR_CLKODIV0_MASK; |
728 | mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); |
729 | bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | |
730 | (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); |
731 | break; |
732 | case 1: |
733 | div_mask = PRCM_CLKOCR_CLKODIV1_MASK; |
734 | mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | |
735 | PRCM_CLKOCR_CLK1TYPE); |
736 | bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | |
737 | (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); |
738 | break; |
739 | } |
740 | bits &= mask; |
741 | |
742 | spin_lock_irqsave(&clkout_lock, flags); |
743 | |
744 | val = readl(PRCM_CLKOCR); |
745 | if (val & div_mask) { |
746 | if (div) { |
747 | if ((val & mask) != bits) { |
748 | r = -EBUSY; |
749 | goto unlock_and_return; |
750 | } |
751 | } else { |
752 | if ((val & mask & ~div_mask) != bits) { |
753 | r = -EINVAL; |
754 | goto unlock_and_return; |
755 | } |
756 | } |
757 | } |
758 | writel((bits | (val & ~mask)), PRCM_CLKOCR); |
759 | requests[clkout] += (div ? 1 : -1); |
760 | |
761 | unlock_and_return: |
762 | spin_unlock_irqrestore(&clkout_lock, flags); |
763 | |
764 | return r; |
765 | } |
766 | |
767 | int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) |
768 | { |
769 | unsigned long flags; |
770 | |
771 | BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); |
772 | |
773 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
774 | |
775 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
776 | cpu_relax(); |
777 | |
778 | writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); |
779 | writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); |
780 | writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); |
781 | writeb((keep_ulp_clk ? 1 : 0), |
782 | (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); |
783 | writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); |
784 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
785 | |
786 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
787 | |
788 | return 0; |
789 | } |
790 | |
791 | u8 db8500_prcmu_get_power_state_result(void) |
792 | { |
793 | return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); |
794 | } |
795 | |
796 | /* This function decouple the gic from the prcmu */ |
797 | int db8500_prcmu_gic_decouple(void) |
798 | { |
799 | u32 val = readl(PRCM_A9_MASK_REQ); |
800 | |
801 | /* Set bit 0 register value to 1 */ |
802 | writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, |
803 | PRCM_A9_MASK_REQ); |
804 | |
805 | /* Make sure the register is updated */ |
806 | readl(PRCM_A9_MASK_REQ); |
807 | |
808 | /* Wait a few cycles for the gic mask completion */ |
809 | udelay(1); |
810 | |
811 | return 0; |
812 | } |
813 | |
814 | /* This function recouple the gic with the prcmu */ |
815 | int db8500_prcmu_gic_recouple(void) |
816 | { |
817 | u32 val = readl(PRCM_A9_MASK_REQ); |
818 | |
819 | /* Set bit 0 register value to 0 */ |
820 | writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); |
821 | |
822 | return 0; |
823 | } |
824 | |
825 | #define PRCMU_GIC_NUMBER_REGS 5 |
826 | |
827 | /* |
828 | * This function checks if there are pending irq on the gic. It only |
829 | * makes sense if the gic has been decoupled before with the |
830 | * db8500_prcmu_gic_decouple function. Disabling an interrupt only |
831 | * disables the forwarding of the interrupt to any CPU interface. It |
832 | * does not prevent the interrupt from changing state, for example |
833 | * becoming pending, or active and pending if it is already |
834 | * active. Hence, we have to check the interrupt is pending *and* is |
835 | * active. |
836 | */ |
837 | bool db8500_prcmu_gic_pending_irq(void) |
838 | { |
839 | u32 pr; /* Pending register */ |
840 | u32 er; /* Enable register */ |
841 | void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); |
842 | int i; |
843 | |
844 | /* 5 registers. STI & PPI not skipped */ |
845 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { |
846 | |
847 | pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); |
848 | er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
849 | |
850 | if (pr & er) |
851 | return true; /* There is a pending interrupt */ |
852 | } |
853 | |
854 | return false; |
855 | } |
856 | |
857 | /* |
858 | * This function checks if there are pending interrupt on the |
859 | * prcmu which has been delegated to monitor the irqs with the |
860 | * db8500_prcmu_copy_gic_settings function. |
861 | */ |
862 | bool db8500_prcmu_pending_irq(void) |
863 | { |
864 | u32 it, im; |
865 | int i; |
866 | |
867 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { |
868 | it = readl(PRCM_ARMITVAL31TO0 + i * 4); |
869 | im = readl(PRCM_ARMITMSK31TO0 + i * 4); |
870 | if (it & im) |
871 | return true; /* There is a pending interrupt */ |
872 | } |
873 | |
874 | return false; |
875 | } |
876 | |
877 | /* |
878 | * This function checks if the specified cpu is in in WFI. It's usage |
879 | * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple |
880 | * function. Of course passing smp_processor_id() to this function will |
881 | * always return false... |
882 | */ |
883 | bool db8500_prcmu_is_cpu_in_wfi(int cpu) |
884 | { |
885 | return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : |
886 | PRCM_ARM_WFI_STANDBY_WFI0; |
887 | } |
888 | |
889 | /* |
890 | * This function copies the gic SPI settings to the prcmu in order to |
891 | * monitor them and abort/finish the retention/off sequence or state. |
892 | */ |
893 | int db8500_prcmu_copy_gic_settings(void) |
894 | { |
895 | u32 er; /* Enable register */ |
896 | void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); |
897 | int i; |
898 | |
899 | /* We skip the STI and PPI */ |
900 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { |
901 | er = readl_relaxed(dist_base + |
902 | GIC_DIST_ENABLE_SET + (i + 1) * 4); |
903 | writel(er, PRCM_ARMITMSK31TO0 + i * 4); |
904 | } |
905 | |
906 | return 0; |
907 | } |
908 | |
909 | /* This function should only be called while mb0_transfer.lock is held. */ |
910 | static void config_wakeups(void) |
911 | { |
912 | const u8 header[2] = { |
913 | MB0H_CONFIG_WAKEUPS_EXE, |
914 | MB0H_CONFIG_WAKEUPS_SLEEP |
915 | }; |
916 | static u32 last_dbb_events; |
917 | static u32 last_abb_events; |
918 | u32 dbb_events; |
919 | u32 abb_events; |
920 | unsigned int i; |
921 | |
922 | dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; |
923 | dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); |
924 | |
925 | abb_events = mb0_transfer.req.abb_events; |
926 | |
927 | if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) |
928 | return; |
929 | |
930 | for (i = 0; i < 2; i++) { |
931 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
932 | cpu_relax(); |
933 | writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); |
934 | writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); |
935 | writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); |
936 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
937 | } |
938 | last_dbb_events = dbb_events; |
939 | last_abb_events = abb_events; |
940 | } |
941 | |
942 | void db8500_prcmu_enable_wakeups(u32 wakeups) |
943 | { |
944 | unsigned long flags; |
945 | u32 bits; |
946 | int i; |
947 | |
948 | BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); |
949 | |
950 | for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { |
951 | if (wakeups & BIT(i)) |
952 | bits |= prcmu_wakeup_bit[i]; |
953 | } |
954 | |
955 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
956 | |
957 | mb0_transfer.req.dbb_wakeups = bits; |
958 | config_wakeups(); |
959 | |
960 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
961 | } |
962 | |
963 | void db8500_prcmu_config_abb_event_readout(u32 abb_events) |
964 | { |
965 | unsigned long flags; |
966 | |
967 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
968 | |
969 | mb0_transfer.req.abb_events = abb_events; |
970 | config_wakeups(); |
971 | |
972 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
973 | } |
974 | |
975 | void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) |
976 | { |
977 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) |
978 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); |
979 | else |
980 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); |
981 | } |
982 | |
983 | /** |
984 | * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP |
985 | * @opp: The new ARM operating point to which transition is to be made |
986 | * Returns: 0 on success, non-zero on failure |
987 | * |
988 | * This function sets the the operating point of the ARM. |
989 | */ |
990 | int db8500_prcmu_set_arm_opp(u8 opp) |
991 | { |
992 | int r; |
993 | |
994 | if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) |
995 | return -EINVAL; |
996 | |
997 | r = 0; |
998 | |
999 | mutex_lock(&mb1_transfer.lock); |
1000 | |
1001 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
1002 | cpu_relax(); |
1003 | |
1004 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
1005 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); |
1006 | writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); |
1007 | |
1008 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
1009 | wait_for_completion(&mb1_transfer.work); |
1010 | |
1011 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || |
1012 | (mb1_transfer.ack.arm_opp != opp)) |
1013 | r = -EIO; |
1014 | |
1015 | mutex_unlock(&mb1_transfer.lock); |
1016 | |
1017 | return r; |
1018 | } |
1019 | |
1020 | /** |
1021 | * db8500_prcmu_get_arm_opp - get the current ARM OPP |
1022 | * |
1023 | * Returns: the current ARM OPP |
1024 | */ |
1025 | int db8500_prcmu_get_arm_opp(void) |
1026 | { |
1027 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); |
1028 | } |
1029 | |
1030 | /** |
1031 | * db8500_prcmu_get_ddr_opp - get the current DDR OPP |
1032 | * |
1033 | * Returns: the current DDR OPP |
1034 | */ |
1035 | int db8500_prcmu_get_ddr_opp(void) |
1036 | { |
1037 | return readb(PRCM_DDR_SUBSYS_APE_MINBW); |
1038 | } |
1039 | |
1040 | /** |
1041 | * db8500_set_ddr_opp - set the appropriate DDR OPP |
1042 | * @opp: The new DDR operating point to which transition is to be made |
1043 | * Returns: 0 on success, non-zero on failure |
1044 | * |
1045 | * This function sets the operating point of the DDR. |
1046 | */ |
1047 | static bool enable_set_ddr_opp; |
1048 | int db8500_prcmu_set_ddr_opp(u8 opp) |
1049 | { |
1050 | if (opp < DDR_100_OPP || opp > DDR_25_OPP) |
1051 | return -EINVAL; |
1052 | /* Changing the DDR OPP can hang the hardware pre-v21 */ |
1053 | if (enable_set_ddr_opp) |
1054 | writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); |
1055 | |
1056 | return 0; |
1057 | } |
1058 | |
1059 | /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ |
1060 | static void request_even_slower_clocks(bool enable) |
1061 | { |
1062 | void __iomem *clock_reg[] = { |
1063 | PRCM_ACLK_MGT, |
1064 | PRCM_DMACLK_MGT |
1065 | }; |
1066 | unsigned long flags; |
1067 | unsigned int i; |
1068 | |
1069 | spin_lock_irqsave(&clk_mgt_lock, flags); |
1070 | |
1071 | /* Grab the HW semaphore. */ |
1072 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
1073 | cpu_relax(); |
1074 | |
1075 | for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { |
1076 | u32 val; |
1077 | u32 div; |
1078 | |
1079 | val = readl(clock_reg[i]); |
1080 | div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); |
1081 | if (enable) { |
1082 | if ((div <= 1) || (div > 15)) { |
1083 | pr_err("prcmu: Bad clock divider %d in %s\n", |
1084 | div, __func__); |
1085 | goto unlock_and_return; |
1086 | } |
1087 | div <<= 1; |
1088 | } else { |
1089 | if (div <= 2) |
1090 | goto unlock_and_return; |
1091 | div >>= 1; |
1092 | } |
1093 | val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | |
1094 | (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); |
1095 | writel(val, clock_reg[i]); |
1096 | } |
1097 | |
1098 | unlock_and_return: |
1099 | /* Release the HW semaphore. */ |
1100 | writel(0, PRCM_SEM); |
1101 | |
1102 | spin_unlock_irqrestore(&clk_mgt_lock, flags); |
1103 | } |
1104 | |
1105 | /** |
1106 | * db8500_set_ape_opp - set the appropriate APE OPP |
1107 | * @opp: The new APE operating point to which transition is to be made |
1108 | * Returns: 0 on success, non-zero on failure |
1109 | * |
1110 | * This function sets the operating point of the APE. |
1111 | */ |
1112 | int db8500_prcmu_set_ape_opp(u8 opp) |
1113 | { |
1114 | int r = 0; |
1115 | |
1116 | if (opp == mb1_transfer.ape_opp) |
1117 | return 0; |
1118 | |
1119 | mutex_lock(&mb1_transfer.lock); |
1120 | |
1121 | if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) |
1122 | request_even_slower_clocks(false); |
1123 | |
1124 | if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) |
1125 | goto skip_message; |
1126 | |
1127 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
1128 | cpu_relax(); |
1129 | |
1130 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
1131 | writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); |
1132 | writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), |
1133 | (tcdm_base + PRCM_REQ_MB1_APE_OPP)); |
1134 | |
1135 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
1136 | wait_for_completion(&mb1_transfer.work); |
1137 | |
1138 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || |
1139 | (mb1_transfer.ack.ape_opp != opp)) |
1140 | r = -EIO; |
1141 | |
1142 | skip_message: |
1143 | if ((!r && (opp == APE_50_PARTLY_25_OPP)) || |
1144 | (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) |
1145 | request_even_slower_clocks(true); |
1146 | if (!r) |
1147 | mb1_transfer.ape_opp = opp; |
1148 | |
1149 | mutex_unlock(&mb1_transfer.lock); |
1150 | |
1151 | return r; |
1152 | } |
1153 | |
1154 | /** |
1155 | * db8500_prcmu_get_ape_opp - get the current APE OPP |
1156 | * |
1157 | * Returns: the current APE OPP |
1158 | */ |
1159 | int db8500_prcmu_get_ape_opp(void) |
1160 | { |
1161 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); |
1162 | } |
1163 | |
1164 | /** |
1165 | * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage |
1166 | * @enable: true to request the higher voltage, false to drop a request. |
1167 | * |
1168 | * Calls to this function to enable and disable requests must be balanced. |
1169 | */ |
1170 | int db8500_prcmu_request_ape_opp_100_voltage(bool enable) |
1171 | { |
1172 | int r = 0; |
1173 | u8 header; |
1174 | static unsigned int requests; |
1175 | |
1176 | mutex_lock(&mb1_transfer.lock); |
1177 | |
1178 | if (enable) { |
1179 | if (0 != requests++) |
1180 | goto unlock_and_return; |
1181 | header = MB1H_REQUEST_APE_OPP_100_VOLT; |
1182 | } else { |
1183 | if (requests == 0) { |
1184 | r = -EIO; |
1185 | goto unlock_and_return; |
1186 | } else if (1 != requests--) { |
1187 | goto unlock_and_return; |
1188 | } |
1189 | header = MB1H_RELEASE_APE_OPP_100_VOLT; |
1190 | } |
1191 | |
1192 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
1193 | cpu_relax(); |
1194 | |
1195 | writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
1196 | |
1197 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
1198 | wait_for_completion(&mb1_transfer.work); |
1199 | |
1200 | if ((mb1_transfer.ack.header != header) || |
1201 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) |
1202 | r = -EIO; |
1203 | |
1204 | unlock_and_return: |
1205 | mutex_unlock(&mb1_transfer.lock); |
1206 | |
1207 | return r; |
1208 | } |
1209 | |
1210 | /** |
1211 | * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup |
1212 | * |
1213 | * This function releases the power state requirements of a USB wakeup. |
1214 | */ |
1215 | int prcmu_release_usb_wakeup_state(void) |
1216 | { |
1217 | int r = 0; |
1218 | |
1219 | mutex_lock(&mb1_transfer.lock); |
1220 | |
1221 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
1222 | cpu_relax(); |
1223 | |
1224 | writeb(MB1H_RELEASE_USB_WAKEUP, |
1225 | (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
1226 | |
1227 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
1228 | wait_for_completion(&mb1_transfer.work); |
1229 | |
1230 | if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || |
1231 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) |
1232 | r = -EIO; |
1233 | |
1234 | mutex_unlock(&mb1_transfer.lock); |
1235 | |
1236 | return r; |
1237 | } |
1238 | |
1239 | static int request_pll(u8 clock, bool enable) |
1240 | { |
1241 | int r = 0; |
1242 | |
1243 | if (clock == PRCMU_PLLSOC0) |
1244 | clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); |
1245 | else if (clock == PRCMU_PLLSOC1) |
1246 | clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); |
1247 | else |
1248 | return -EINVAL; |
1249 | |
1250 | mutex_lock(&mb1_transfer.lock); |
1251 | |
1252 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
1253 | cpu_relax(); |
1254 | |
1255 | writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
1256 | writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); |
1257 | |
1258 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
1259 | wait_for_completion(&mb1_transfer.work); |
1260 | |
1261 | if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) |
1262 | r = -EIO; |
1263 | |
1264 | mutex_unlock(&mb1_transfer.lock); |
1265 | |
1266 | return r; |
1267 | } |
1268 | |
1269 | /** |
1270 | * db8500_prcmu_set_epod - set the state of a EPOD (power domain) |
1271 | * @epod_id: The EPOD to set |
1272 | * @epod_state: The new EPOD state |
1273 | * |
1274 | * This function sets the state of a EPOD (power domain). It may not be called |
1275 | * from interrupt context. |
1276 | */ |
1277 | int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) |
1278 | { |
1279 | int r = 0; |
1280 | bool ram_retention = false; |
1281 | int i; |
1282 | |
1283 | /* check argument */ |
1284 | BUG_ON(epod_id >= NUM_EPOD_ID); |
1285 | |
1286 | /* set flag if retention is possible */ |
1287 | switch (epod_id) { |
1288 | case EPOD_ID_SVAMMDSP: |
1289 | case EPOD_ID_SIAMMDSP: |
1290 | case EPOD_ID_ESRAM12: |
1291 | case EPOD_ID_ESRAM34: |
1292 | ram_retention = true; |
1293 | break; |
1294 | } |
1295 | |
1296 | /* check argument */ |
1297 | BUG_ON(epod_state > EPOD_STATE_ON); |
1298 | BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); |
1299 | |
1300 | /* get lock */ |
1301 | mutex_lock(&mb2_transfer.lock); |
1302 | |
1303 | /* wait for mailbox */ |
1304 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) |
1305 | cpu_relax(); |
1306 | |
1307 | /* fill in mailbox */ |
1308 | for (i = 0; i < NUM_EPOD_ID; i++) |
1309 | writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); |
1310 | writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); |
1311 | |
1312 | writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); |
1313 | |
1314 | writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); |
1315 | |
1316 | /* |
1317 | * The current firmware version does not handle errors correctly, |
1318 | * and we cannot recover if there is an error. |
1319 | * This is expected to change when the firmware is updated. |
1320 | */ |
1321 | if (!wait_for_completion_timeout(&mb2_transfer.work, |
1322 | msecs_to_jiffies(20000))) { |
1323 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", |
1324 | __func__); |
1325 | r = -EIO; |
1326 | goto unlock_and_return; |
1327 | } |
1328 | |
1329 | if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) |
1330 | r = -EIO; |
1331 | |
1332 | unlock_and_return: |
1333 | mutex_unlock(&mb2_transfer.lock); |
1334 | return r; |
1335 | } |
1336 | |
1337 | /** |
1338 | * prcmu_configure_auto_pm - Configure autonomous power management. |
1339 | * @sleep: Configuration for ApSleep. |
1340 | * @idle: Configuration for ApIdle. |
1341 | */ |
1342 | void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, |
1343 | struct prcmu_auto_pm_config *idle) |
1344 | { |
1345 | u32 sleep_cfg; |
1346 | u32 idle_cfg; |
1347 | unsigned long flags; |
1348 | |
1349 | BUG_ON((sleep == NULL) || (idle == NULL)); |
1350 | |
1351 | sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); |
1352 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); |
1353 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); |
1354 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); |
1355 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); |
1356 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); |
1357 | |
1358 | idle_cfg = (idle->sva_auto_pm_enable & 0xF); |
1359 | idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); |
1360 | idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); |
1361 | idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); |
1362 | idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); |
1363 | idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); |
1364 | |
1365 | spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); |
1366 | |
1367 | /* |
1368 | * The autonomous power management configuration is done through |
1369 | * fields in mailbox 2, but these fields are only used as shared |
1370 | * variables - i.e. there is no need to send a message. |
1371 | */ |
1372 | writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); |
1373 | writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); |
1374 | |
1375 | mb2_transfer.auto_pm_enabled = |
1376 | ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || |
1377 | (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || |
1378 | (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || |
1379 | (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); |
1380 | |
1381 | spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); |
1382 | } |
1383 | EXPORT_SYMBOL(prcmu_configure_auto_pm); |
1384 | |
1385 | bool prcmu_is_auto_pm_enabled(void) |
1386 | { |
1387 | return mb2_transfer.auto_pm_enabled; |
1388 | } |
1389 | |
1390 | static int request_sysclk(bool enable) |
1391 | { |
1392 | int r; |
1393 | unsigned long flags; |
1394 | |
1395 | r = 0; |
1396 | |
1397 | mutex_lock(&mb3_transfer.sysclk_lock); |
1398 | |
1399 | spin_lock_irqsave(&mb3_transfer.lock, flags); |
1400 | |
1401 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) |
1402 | cpu_relax(); |
1403 | |
1404 | writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); |
1405 | |
1406 | writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); |
1407 | writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); |
1408 | |
1409 | spin_unlock_irqrestore(&mb3_transfer.lock, flags); |
1410 | |
1411 | /* |
1412 | * The firmware only sends an ACK if we want to enable the |
1413 | * SysClk, and it succeeds. |
1414 | */ |
1415 | if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, |
1416 | msecs_to_jiffies(20000))) { |
1417 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", |
1418 | __func__); |
1419 | r = -EIO; |
1420 | } |
1421 | |
1422 | mutex_unlock(&mb3_transfer.sysclk_lock); |
1423 | |
1424 | return r; |
1425 | } |
1426 | |
1427 | static int request_timclk(bool enable) |
1428 | { |
1429 | u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); |
1430 | |
1431 | if (!enable) |
1432 | val |= PRCM_TCR_STOP_TIMERS; |
1433 | writel(val, PRCM_TCR); |
1434 | |
1435 | return 0; |
1436 | } |
1437 | |
1438 | static int request_clock(u8 clock, bool enable) |
1439 | { |
1440 | u32 val; |
1441 | unsigned long flags; |
1442 | |
1443 | spin_lock_irqsave(&clk_mgt_lock, flags); |
1444 | |
1445 | /* Grab the HW semaphore. */ |
1446 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
1447 | cpu_relax(); |
1448 | |
1449 | val = readl(clk_mgt[clock].reg); |
1450 | if (enable) { |
1451 | val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); |
1452 | } else { |
1453 | clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); |
1454 | val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); |
1455 | } |
1456 | writel(val, clk_mgt[clock].reg); |
1457 | |
1458 | /* Release the HW semaphore. */ |
1459 | writel(0, PRCM_SEM); |
1460 | |
1461 | spin_unlock_irqrestore(&clk_mgt_lock, flags); |
1462 | |
1463 | return 0; |
1464 | } |
1465 | |
1466 | static int request_sga_clock(u8 clock, bool enable) |
1467 | { |
1468 | u32 val; |
1469 | int ret; |
1470 | |
1471 | if (enable) { |
1472 | val = readl(PRCM_CGATING_BYPASS); |
1473 | writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); |
1474 | } |
1475 | |
1476 | ret = request_clock(clock, enable); |
1477 | |
1478 | if (!ret && !enable) { |
1479 | val = readl(PRCM_CGATING_BYPASS); |
1480 | writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); |
1481 | } |
1482 | |
1483 | return ret; |
1484 | } |
1485 | |
1486 | static inline bool plldsi_locked(void) |
1487 | { |
1488 | return (readl(PRCM_PLLDSI_LOCKP) & |
1489 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | |
1490 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == |
1491 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | |
1492 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); |
1493 | } |
1494 | |
1495 | static int request_plldsi(bool enable) |
1496 | { |
1497 | int r = 0; |
1498 | u32 val; |
1499 | |
1500 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | |
1501 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? |
1502 | PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); |
1503 | |
1504 | val = readl(PRCM_PLLDSI_ENABLE); |
1505 | if (enable) |
1506 | val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; |
1507 | else |
1508 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; |
1509 | writel(val, PRCM_PLLDSI_ENABLE); |
1510 | |
1511 | if (enable) { |
1512 | unsigned int i; |
1513 | bool locked = plldsi_locked(); |
1514 | |
1515 | for (i = 10; !locked && (i > 0); --i) { |
1516 | udelay(100); |
1517 | locked = plldsi_locked(); |
1518 | } |
1519 | if (locked) { |
1520 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, |
1521 | PRCM_APE_RESETN_SET); |
1522 | } else { |
1523 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | |
1524 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), |
1525 | PRCM_MMIP_LS_CLAMP_SET); |
1526 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; |
1527 | writel(val, PRCM_PLLDSI_ENABLE); |
1528 | r = -EAGAIN; |
1529 | } |
1530 | } else { |
1531 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); |
1532 | } |
1533 | return r; |
1534 | } |
1535 | |
1536 | static int request_dsiclk(u8 n, bool enable) |
1537 | { |
1538 | u32 val; |
1539 | |
1540 | val = readl(PRCM_DSI_PLLOUT_SEL); |
1541 | val &= ~dsiclk[n].divsel_mask; |
1542 | val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << |
1543 | dsiclk[n].divsel_shift); |
1544 | writel(val, PRCM_DSI_PLLOUT_SEL); |
1545 | return 0; |
1546 | } |
1547 | |
1548 | static int request_dsiescclk(u8 n, bool enable) |
1549 | { |
1550 | u32 val; |
1551 | |
1552 | val = readl(PRCM_DSITVCLK_DIV); |
1553 | enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); |
1554 | writel(val, PRCM_DSITVCLK_DIV); |
1555 | return 0; |
1556 | } |
1557 | |
1558 | /** |
1559 | * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. |
1560 | * @clock: The clock for which the request is made. |
1561 | * @enable: Whether the clock should be enabled (true) or disabled (false). |
1562 | * |
1563 | * This function should only be used by the clock implementation. |
1564 | * Do not use it from any other place! |
1565 | */ |
1566 | int db8500_prcmu_request_clock(u8 clock, bool enable) |
1567 | { |
1568 | if (clock == PRCMU_SGACLK) |
1569 | return request_sga_clock(clock, enable); |
1570 | else if (clock < PRCMU_NUM_REG_CLOCKS) |
1571 | return request_clock(clock, enable); |
1572 | else if (clock == PRCMU_TIMCLK) |
1573 | return request_timclk(enable); |
1574 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
1575 | return request_dsiclk((clock - PRCMU_DSI0CLK), enable); |
1576 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) |
1577 | return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); |
1578 | else if (clock == PRCMU_PLLDSI) |
1579 | return request_plldsi(enable); |
1580 | else if (clock == PRCMU_SYSCLK) |
1581 | return request_sysclk(enable); |
1582 | else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) |
1583 | return request_pll(clock, enable); |
1584 | else |
1585 | return -EINVAL; |
1586 | } |
1587 | |
1588 | static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, |
1589 | int branch) |
1590 | { |
1591 | u64 rate; |
1592 | u32 val; |
1593 | u32 d; |
1594 | u32 div = 1; |
1595 | |
1596 | val = readl(reg); |
1597 | |
1598 | rate = src_rate; |
1599 | rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); |
1600 | |
1601 | d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); |
1602 | if (d > 1) |
1603 | div *= d; |
1604 | |
1605 | d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); |
1606 | if (d > 1) |
1607 | div *= d; |
1608 | |
1609 | if (val & PRCM_PLL_FREQ_SELDIV2) |
1610 | div *= 2; |
1611 | |
1612 | if ((branch == PLL_FIX) || ((branch == PLL_DIV) && |
1613 | (val & PRCM_PLL_FREQ_DIV2EN) && |
1614 | ((reg == PRCM_PLLSOC0_FREQ) || |
1615 | (reg == PRCM_PLLARM_FREQ) || |
1616 | (reg == PRCM_PLLDDR_FREQ)))) |
1617 | div *= 2; |
1618 | |
1619 | (void)do_div(rate, div); |
1620 | |
1621 | return (unsigned long)rate; |
1622 | } |
1623 | |
1624 | #define ROOT_CLOCK_RATE 38400000 |
1625 | |
1626 | static unsigned long clock_rate(u8 clock) |
1627 | { |
1628 | u32 val; |
1629 | u32 pllsw; |
1630 | unsigned long rate = ROOT_CLOCK_RATE; |
1631 | |
1632 | val = readl(clk_mgt[clock].reg); |
1633 | |
1634 | if (val & PRCM_CLK_MGT_CLK38) { |
1635 | if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) |
1636 | rate /= 2; |
1637 | return rate; |
1638 | } |
1639 | |
1640 | val |= clk_mgt[clock].pllsw; |
1641 | pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); |
1642 | |
1643 | if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) |
1644 | rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); |
1645 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) |
1646 | rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); |
1647 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) |
1648 | rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); |
1649 | else |
1650 | return 0; |
1651 | |
1652 | if ((clock == PRCMU_SGACLK) && |
1653 | (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { |
1654 | u64 r = (rate * 10); |
1655 | |
1656 | (void)do_div(r, 25); |
1657 | return (unsigned long)r; |
1658 | } |
1659 | val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; |
1660 | if (val) |
1661 | return rate / val; |
1662 | else |
1663 | return 0; |
1664 | } |
1665 | |
1666 | static unsigned long armss_rate(void) |
1667 | { |
1668 | u32 r; |
1669 | unsigned long rate; |
1670 | |
1671 | r = readl(PRCM_ARM_CHGCLKREQ); |
1672 | |
1673 | if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { |
1674 | /* External ARMCLKFIX clock */ |
1675 | |
1676 | rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); |
1677 | |
1678 | /* Check PRCM_ARM_CHGCLKREQ divider */ |
1679 | if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) |
1680 | rate /= 2; |
1681 | |
1682 | /* Check PRCM_ARMCLKFIX_MGT divider */ |
1683 | r = readl(PRCM_ARMCLKFIX_MGT); |
1684 | r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; |
1685 | rate /= r; |
1686 | |
1687 | } else {/* ARM PLL */ |
1688 | rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); |
1689 | } |
1690 | |
1691 | return rate; |
1692 | } |
1693 | |
1694 | static unsigned long dsiclk_rate(u8 n) |
1695 | { |
1696 | u32 divsel; |
1697 | u32 div = 1; |
1698 | |
1699 | divsel = readl(PRCM_DSI_PLLOUT_SEL); |
1700 | divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); |
1701 | |
1702 | if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) |
1703 | divsel = dsiclk[n].divsel; |
1704 | |
1705 | switch (divsel) { |
1706 | case PRCM_DSI_PLLOUT_SEL_PHI_4: |
1707 | div *= 2; |
1708 | case PRCM_DSI_PLLOUT_SEL_PHI_2: |
1709 | div *= 2; |
1710 | case PRCM_DSI_PLLOUT_SEL_PHI: |
1711 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), |
1712 | PLL_RAW) / div; |
1713 | default: |
1714 | return 0; |
1715 | } |
1716 | } |
1717 | |
1718 | static unsigned long dsiescclk_rate(u8 n) |
1719 | { |
1720 | u32 div; |
1721 | |
1722 | div = readl(PRCM_DSITVCLK_DIV); |
1723 | div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); |
1724 | return clock_rate(PRCMU_TVCLK) / max((u32)1, div); |
1725 | } |
1726 | |
1727 | unsigned long prcmu_clock_rate(u8 clock) |
1728 | { |
1729 | if (clock < PRCMU_NUM_REG_CLOCKS) |
1730 | return clock_rate(clock); |
1731 | else if (clock == PRCMU_TIMCLK) |
1732 | return ROOT_CLOCK_RATE / 16; |
1733 | else if (clock == PRCMU_SYSCLK) |
1734 | return ROOT_CLOCK_RATE; |
1735 | else if (clock == PRCMU_PLLSOC0) |
1736 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); |
1737 | else if (clock == PRCMU_PLLSOC1) |
1738 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); |
1739 | else if (clock == PRCMU_ARMSS) |
1740 | return armss_rate(); |
1741 | else if (clock == PRCMU_PLLDDR) |
1742 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); |
1743 | else if (clock == PRCMU_PLLDSI) |
1744 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), |
1745 | PLL_RAW); |
1746 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
1747 | return dsiclk_rate(clock - PRCMU_DSI0CLK); |
1748 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) |
1749 | return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); |
1750 | else |
1751 | return 0; |
1752 | } |
1753 | |
1754 | static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) |
1755 | { |
1756 | if (clk_mgt_val & PRCM_CLK_MGT_CLK38) |
1757 | return ROOT_CLOCK_RATE; |
1758 | clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; |
1759 | if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) |
1760 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); |
1761 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) |
1762 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); |
1763 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) |
1764 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); |
1765 | else |
1766 | return 0; |
1767 | } |
1768 | |
1769 | static u32 clock_divider(unsigned long src_rate, unsigned long rate) |
1770 | { |
1771 | u32 div; |
1772 | |
1773 | div = (src_rate / rate); |
1774 | if (div == 0) |
1775 | return 1; |
1776 | if (rate < (src_rate / div)) |
1777 | div++; |
1778 | return div; |
1779 | } |
1780 | |
1781 | static long round_clock_rate(u8 clock, unsigned long rate) |
1782 | { |
1783 | u32 val; |
1784 | u32 div; |
1785 | unsigned long src_rate; |
1786 | long rounded_rate; |
1787 | |
1788 | val = readl(clk_mgt[clock].reg); |
1789 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), |
1790 | clk_mgt[clock].branch); |
1791 | div = clock_divider(src_rate, rate); |
1792 | if (val & PRCM_CLK_MGT_CLK38) { |
1793 | if (clk_mgt[clock].clk38div) { |
1794 | if (div > 2) |
1795 | div = 2; |
1796 | } else { |
1797 | div = 1; |
1798 | } |
1799 | } else if ((clock == PRCMU_SGACLK) && (div == 3)) { |
1800 | u64 r = (src_rate * 10); |
1801 | |
1802 | (void)do_div(r, 25); |
1803 | if (r <= rate) |
1804 | return (unsigned long)r; |
1805 | } |
1806 | rounded_rate = (src_rate / min(div, (u32)31)); |
1807 | |
1808 | return rounded_rate; |
1809 | } |
1810 | |
1811 | /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */ |
1812 | static struct cpufreq_frequency_table db8500_cpufreq_table[] = { |
1813 | { .frequency = 200000, .index = ARM_EXTCLK,}, |
1814 | { .frequency = 400000, .index = ARM_50_OPP,}, |
1815 | { .frequency = 800000, .index = ARM_100_OPP,}, |
1816 | { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */ |
1817 | { .frequency = CPUFREQ_TABLE_END,}, |
1818 | }; |
1819 | |
1820 | static long round_armss_rate(unsigned long rate) |
1821 | { |
1822 | long freq = 0; |
1823 | int i = 0; |
1824 | |
1825 | /* cpufreq table frequencies is in KHz. */ |
1826 | rate = rate / 1000; |
1827 | |
1828 | /* Find the corresponding arm opp from the cpufreq table. */ |
1829 | while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) { |
1830 | freq = db8500_cpufreq_table[i].frequency; |
1831 | if (freq == rate) |
1832 | break; |
1833 | i++; |
1834 | } |
1835 | |
1836 | /* Return the last valid value, even if a match was not found. */ |
1837 | return freq * 1000; |
1838 | } |
1839 | |
1840 | #define MIN_PLL_VCO_RATE 600000000ULL |
1841 | #define MAX_PLL_VCO_RATE 1680640000ULL |
1842 | |
1843 | static long round_plldsi_rate(unsigned long rate) |
1844 | { |
1845 | long rounded_rate = 0; |
1846 | unsigned long src_rate; |
1847 | unsigned long rem; |
1848 | u32 r; |
1849 | |
1850 | src_rate = clock_rate(PRCMU_HDMICLK); |
1851 | rem = rate; |
1852 | |
1853 | for (r = 7; (rem > 0) && (r > 0); r--) { |
1854 | u64 d; |
1855 | |
1856 | d = (r * rate); |
1857 | (void)do_div(d, src_rate); |
1858 | if (d < 6) |
1859 | d = 6; |
1860 | else if (d > 255) |
1861 | d = 255; |
1862 | d *= src_rate; |
1863 | if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || |
1864 | ((r * MAX_PLL_VCO_RATE) < (2 * d))) |
1865 | continue; |
1866 | (void)do_div(d, r); |
1867 | if (rate < d) { |
1868 | if (rounded_rate == 0) |
1869 | rounded_rate = (long)d; |
1870 | break; |
1871 | } |
1872 | if ((rate - d) < rem) { |
1873 | rem = (rate - d); |
1874 | rounded_rate = (long)d; |
1875 | } |
1876 | } |
1877 | return rounded_rate; |
1878 | } |
1879 | |
1880 | static long round_dsiclk_rate(unsigned long rate) |
1881 | { |
1882 | u32 div; |
1883 | unsigned long src_rate; |
1884 | long rounded_rate; |
1885 | |
1886 | src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), |
1887 | PLL_RAW); |
1888 | div = clock_divider(src_rate, rate); |
1889 | rounded_rate = (src_rate / ((div > 2) ? 4 : div)); |
1890 | |
1891 | return rounded_rate; |
1892 | } |
1893 | |
1894 | static long round_dsiescclk_rate(unsigned long rate) |
1895 | { |
1896 | u32 div; |
1897 | unsigned long src_rate; |
1898 | long rounded_rate; |
1899 | |
1900 | src_rate = clock_rate(PRCMU_TVCLK); |
1901 | div = clock_divider(src_rate, rate); |
1902 | rounded_rate = (src_rate / min(div, (u32)255)); |
1903 | |
1904 | return rounded_rate; |
1905 | } |
1906 | |
1907 | long prcmu_round_clock_rate(u8 clock, unsigned long rate) |
1908 | { |
1909 | if (clock < PRCMU_NUM_REG_CLOCKS) |
1910 | return round_clock_rate(clock, rate); |
1911 | else if (clock == PRCMU_ARMSS) |
1912 | return round_armss_rate(rate); |
1913 | else if (clock == PRCMU_PLLDSI) |
1914 | return round_plldsi_rate(rate); |
1915 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
1916 | return round_dsiclk_rate(rate); |
1917 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) |
1918 | return round_dsiescclk_rate(rate); |
1919 | else |
1920 | return (long)prcmu_clock_rate(clock); |
1921 | } |
1922 | |
1923 | static void set_clock_rate(u8 clock, unsigned long rate) |
1924 | { |
1925 | u32 val; |
1926 | u32 div; |
1927 | unsigned long src_rate; |
1928 | unsigned long flags; |
1929 | |
1930 | spin_lock_irqsave(&clk_mgt_lock, flags); |
1931 | |
1932 | /* Grab the HW semaphore. */ |
1933 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
1934 | cpu_relax(); |
1935 | |
1936 | val = readl(clk_mgt[clock].reg); |
1937 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), |
1938 | clk_mgt[clock].branch); |
1939 | div = clock_divider(src_rate, rate); |
1940 | if (val & PRCM_CLK_MGT_CLK38) { |
1941 | if (clk_mgt[clock].clk38div) { |
1942 | if (div > 1) |
1943 | val |= PRCM_CLK_MGT_CLK38DIV; |
1944 | else |
1945 | val &= ~PRCM_CLK_MGT_CLK38DIV; |
1946 | } |
1947 | } else if (clock == PRCMU_SGACLK) { |
1948 | val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | |
1949 | PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); |
1950 | if (div == 3) { |
1951 | u64 r = (src_rate * 10); |
1952 | |
1953 | (void)do_div(r, 25); |
1954 | if (r <= rate) { |
1955 | val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; |
1956 | div = 0; |
1957 | } |
1958 | } |
1959 | val |= min(div, (u32)31); |
1960 | } else { |
1961 | val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; |
1962 | val |= min(div, (u32)31); |
1963 | } |
1964 | writel(val, clk_mgt[clock].reg); |
1965 | |
1966 | /* Release the HW semaphore. */ |
1967 | writel(0, PRCM_SEM); |
1968 | |
1969 | spin_unlock_irqrestore(&clk_mgt_lock, flags); |
1970 | } |
1971 | |
1972 | static int set_armss_rate(unsigned long rate) |
1973 | { |
1974 | int i = 0; |
1975 | |
1976 | /* cpufreq table frequencies is in KHz. */ |
1977 | rate = rate / 1000; |
1978 | |
1979 | /* Find the corresponding arm opp from the cpufreq table. */ |
1980 | while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) { |
1981 | if (db8500_cpufreq_table[i].frequency == rate) |
1982 | break; |
1983 | i++; |
1984 | } |
1985 | |
1986 | if (db8500_cpufreq_table[i].frequency != rate) |
1987 | return -EINVAL; |
1988 | |
1989 | /* Set the new arm opp. */ |
1990 | return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index); |
1991 | } |
1992 | |
1993 | static int set_plldsi_rate(unsigned long rate) |
1994 | { |
1995 | unsigned long src_rate; |
1996 | unsigned long rem; |
1997 | u32 pll_freq = 0; |
1998 | u32 r; |
1999 | |
2000 | src_rate = clock_rate(PRCMU_HDMICLK); |
2001 | rem = rate; |
2002 | |
2003 | for (r = 7; (rem > 0) && (r > 0); r--) { |
2004 | u64 d; |
2005 | u64 hwrate; |
2006 | |
2007 | d = (r * rate); |
2008 | (void)do_div(d, src_rate); |
2009 | if (d < 6) |
2010 | d = 6; |
2011 | else if (d > 255) |
2012 | d = 255; |
2013 | hwrate = (d * src_rate); |
2014 | if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || |
2015 | ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) |
2016 | continue; |
2017 | (void)do_div(hwrate, r); |
2018 | if (rate < hwrate) { |
2019 | if (pll_freq == 0) |
2020 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | |
2021 | (r << PRCM_PLL_FREQ_R_SHIFT)); |
2022 | break; |
2023 | } |
2024 | if ((rate - hwrate) < rem) { |
2025 | rem = (rate - hwrate); |
2026 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | |
2027 | (r << PRCM_PLL_FREQ_R_SHIFT)); |
2028 | } |
2029 | } |
2030 | if (pll_freq == 0) |
2031 | return -EINVAL; |
2032 | |
2033 | pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); |
2034 | writel(pll_freq, PRCM_PLLDSI_FREQ); |
2035 | |
2036 | return 0; |
2037 | } |
2038 | |
2039 | static void set_dsiclk_rate(u8 n, unsigned long rate) |
2040 | { |
2041 | u32 val; |
2042 | u32 div; |
2043 | |
2044 | div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, |
2045 | clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); |
2046 | |
2047 | dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : |
2048 | (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : |
2049 | /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; |
2050 | |
2051 | val = readl(PRCM_DSI_PLLOUT_SEL); |
2052 | val &= ~dsiclk[n].divsel_mask; |
2053 | val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); |
2054 | writel(val, PRCM_DSI_PLLOUT_SEL); |
2055 | } |
2056 | |
2057 | static void set_dsiescclk_rate(u8 n, unsigned long rate) |
2058 | { |
2059 | u32 val; |
2060 | u32 div; |
2061 | |
2062 | div = clock_divider(clock_rate(PRCMU_TVCLK), rate); |
2063 | val = readl(PRCM_DSITVCLK_DIV); |
2064 | val &= ~dsiescclk[n].div_mask; |
2065 | val |= (min(div, (u32)255) << dsiescclk[n].div_shift); |
2066 | writel(val, PRCM_DSITVCLK_DIV); |
2067 | } |
2068 | |
2069 | int prcmu_set_clock_rate(u8 clock, unsigned long rate) |
2070 | { |
2071 | if (clock < PRCMU_NUM_REG_CLOCKS) |
2072 | set_clock_rate(clock, rate); |
2073 | else if (clock == PRCMU_ARMSS) |
2074 | return set_armss_rate(rate); |
2075 | else if (clock == PRCMU_PLLDSI) |
2076 | return set_plldsi_rate(rate); |
2077 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
2078 | set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); |
2079 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) |
2080 | set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); |
2081 | return 0; |
2082 | } |
2083 | |
2084 | int db8500_prcmu_config_esram0_deep_sleep(u8 state) |
2085 | { |
2086 | if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || |
2087 | (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) |
2088 | return -EINVAL; |
2089 | |
2090 | mutex_lock(&mb4_transfer.lock); |
2091 | |
2092 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
2093 | cpu_relax(); |
2094 | |
2095 | writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
2096 | writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), |
2097 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); |
2098 | writeb(DDR_PWR_STATE_ON, |
2099 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); |
2100 | writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); |
2101 | |
2102 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
2103 | wait_for_completion(&mb4_transfer.work); |
2104 | |
2105 | mutex_unlock(&mb4_transfer.lock); |
2106 | |
2107 | return 0; |
2108 | } |
2109 | |
2110 | int db8500_prcmu_config_hotdog(u8 threshold) |
2111 | { |
2112 | mutex_lock(&mb4_transfer.lock); |
2113 | |
2114 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
2115 | cpu_relax(); |
2116 | |
2117 | writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); |
2118 | writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
2119 | |
2120 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
2121 | wait_for_completion(&mb4_transfer.work); |
2122 | |
2123 | mutex_unlock(&mb4_transfer.lock); |
2124 | |
2125 | return 0; |
2126 | } |
2127 | |
2128 | int db8500_prcmu_config_hotmon(u8 low, u8 high) |
2129 | { |
2130 | mutex_lock(&mb4_transfer.lock); |
2131 | |
2132 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
2133 | cpu_relax(); |
2134 | |
2135 | writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); |
2136 | writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); |
2137 | writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), |
2138 | (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); |
2139 | writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
2140 | |
2141 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
2142 | wait_for_completion(&mb4_transfer.work); |
2143 | |
2144 | mutex_unlock(&mb4_transfer.lock); |
2145 | |
2146 | return 0; |
2147 | } |
2148 | |
2149 | static int config_hot_period(u16 val) |
2150 | { |
2151 | mutex_lock(&mb4_transfer.lock); |
2152 | |
2153 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
2154 | cpu_relax(); |
2155 | |
2156 | writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); |
2157 | writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
2158 | |
2159 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
2160 | wait_for_completion(&mb4_transfer.work); |
2161 | |
2162 | mutex_unlock(&mb4_transfer.lock); |
2163 | |
2164 | return 0; |
2165 | } |
2166 | |
2167 | int db8500_prcmu_start_temp_sense(u16 cycles32k) |
2168 | { |
2169 | if (cycles32k == 0xFFFF) |
2170 | return -EINVAL; |
2171 | |
2172 | return config_hot_period(cycles32k); |
2173 | } |
2174 | |
2175 | int db8500_prcmu_stop_temp_sense(void) |
2176 | { |
2177 | return config_hot_period(0xFFFF); |
2178 | } |
2179 | |
2180 | static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) |
2181 | { |
2182 | |
2183 | mutex_lock(&mb4_transfer.lock); |
2184 | |
2185 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
2186 | cpu_relax(); |
2187 | |
2188 | writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); |
2189 | writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); |
2190 | writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); |
2191 | writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); |
2192 | |
2193 | writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); |
2194 | |
2195 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
2196 | wait_for_completion(&mb4_transfer.work); |
2197 | |
2198 | mutex_unlock(&mb4_transfer.lock); |
2199 | |
2200 | return 0; |
2201 | |
2202 | } |
2203 | |
2204 | int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) |
2205 | { |
2206 | BUG_ON(num == 0 || num > 0xf); |
2207 | return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, |
2208 | sleep_auto_off ? A9WDOG_AUTO_OFF_EN : |
2209 | A9WDOG_AUTO_OFF_DIS); |
2210 | } |
2211 | EXPORT_SYMBOL(db8500_prcmu_config_a9wdog); |
2212 | |
2213 | int db8500_prcmu_enable_a9wdog(u8 id) |
2214 | { |
2215 | return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); |
2216 | } |
2217 | EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog); |
2218 | |
2219 | int db8500_prcmu_disable_a9wdog(u8 id) |
2220 | { |
2221 | return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); |
2222 | } |
2223 | EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog); |
2224 | |
2225 | int db8500_prcmu_kick_a9wdog(u8 id) |
2226 | { |
2227 | return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); |
2228 | } |
2229 | EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog); |
2230 | |
2231 | /* |
2232 | * timeout is 28 bit, in ms. |
2233 | */ |
2234 | int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) |
2235 | { |
2236 | return prcmu_a9wdog(MB4H_A9WDOG_LOAD, |
2237 | (id & A9WDOG_ID_MASK) | |
2238 | /* |
2239 | * Put the lowest 28 bits of timeout at |
2240 | * offset 4. Four first bits are used for id. |
2241 | */ |
2242 | (u8)((timeout << 4) & 0xf0), |
2243 | (u8)((timeout >> 4) & 0xff), |
2244 | (u8)((timeout >> 12) & 0xff), |
2245 | (u8)((timeout >> 20) & 0xff)); |
2246 | } |
2247 | EXPORT_SYMBOL(db8500_prcmu_load_a9wdog); |
2248 | |
2249 | /** |
2250 | * prcmu_abb_read() - Read register value(s) from the ABB. |
2251 | * @slave: The I2C slave address. |
2252 | * @reg: The (start) register address. |
2253 | * @value: The read out value(s). |
2254 | * @size: The number of registers to read. |
2255 | * |
2256 | * Reads register value(s) from the ABB. |
2257 | * @size has to be 1 for the current firmware version. |
2258 | */ |
2259 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) |
2260 | { |
2261 | int r; |
2262 | |
2263 | if (size != 1) |
2264 | return -EINVAL; |
2265 | |
2266 | mutex_lock(&mb5_transfer.lock); |
2267 | |
2268 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
2269 | cpu_relax(); |
2270 | |
2271 | writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
2272 | writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2273 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); |
2274 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); |
2275 | writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); |
2276 | |
2277 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
2278 | |
2279 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
2280 | msecs_to_jiffies(20000))) { |
2281 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", |
2282 | __func__); |
2283 | r = -EIO; |
2284 | } else { |
2285 | r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); |
2286 | } |
2287 | |
2288 | if (!r) |
2289 | *value = mb5_transfer.ack.value; |
2290 | |
2291 | mutex_unlock(&mb5_transfer.lock); |
2292 | |
2293 | return r; |
2294 | } |
2295 | |
2296 | /** |
2297 | * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. |
2298 | * @slave: The I2C slave address. |
2299 | * @reg: The (start) register address. |
2300 | * @value: The value(s) to write. |
2301 | * @mask: The mask(s) to use. |
2302 | * @size: The number of registers to write. |
2303 | * |
2304 | * Writes masked register value(s) to the ABB. |
2305 | * For each @value, only the bits set to 1 in the corresponding @mask |
2306 | * will be written. The other bits are not changed. |
2307 | * @size has to be 1 for the current firmware version. |
2308 | */ |
2309 | int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) |
2310 | { |
2311 | int r; |
2312 | |
2313 | if (size != 1) |
2314 | return -EINVAL; |
2315 | |
2316 | mutex_lock(&mb5_transfer.lock); |
2317 | |
2318 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
2319 | cpu_relax(); |
2320 | |
2321 | writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
2322 | writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2323 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); |
2324 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); |
2325 | writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); |
2326 | |
2327 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
2328 | |
2329 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
2330 | msecs_to_jiffies(20000))) { |
2331 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", |
2332 | __func__); |
2333 | r = -EIO; |
2334 | } else { |
2335 | r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); |
2336 | } |
2337 | |
2338 | mutex_unlock(&mb5_transfer.lock); |
2339 | |
2340 | return r; |
2341 | } |
2342 | |
2343 | /** |
2344 | * prcmu_abb_write() - Write register value(s) to the ABB. |
2345 | * @slave: The I2C slave address. |
2346 | * @reg: The (start) register address. |
2347 | * @value: The value(s) to write. |
2348 | * @size: The number of registers to write. |
2349 | * |
2350 | * Writes register value(s) to the ABB. |
2351 | * @size has to be 1 for the current firmware version. |
2352 | */ |
2353 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) |
2354 | { |
2355 | u8 mask = ~0; |
2356 | |
2357 | return prcmu_abb_write_masked(slave, reg, value, &mask, size); |
2358 | } |
2359 | |
2360 | /** |
2361 | * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem |
2362 | */ |
2363 | int prcmu_ac_wake_req(void) |
2364 | { |
2365 | u32 val; |
2366 | int ret = 0; |
2367 | |
2368 | mutex_lock(&mb0_transfer.ac_wake_lock); |
2369 | |
2370 | val = readl(PRCM_HOSTACCESS_REQ); |
2371 | if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) |
2372 | goto unlock_and_return; |
2373 | |
2374 | atomic_set(&ac_wake_req_state, 1); |
2375 | |
2376 | /* |
2377 | * Force Modem Wake-up before hostaccess_req ping-pong. |
2378 | * It prevents Modem to enter in Sleep while acking the hostaccess |
2379 | * request. The 31us delay has been calculated by HWI. |
2380 | */ |
2381 | val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; |
2382 | writel(val, PRCM_HOSTACCESS_REQ); |
2383 | |
2384 | udelay(31); |
2385 | |
2386 | val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; |
2387 | writel(val, PRCM_HOSTACCESS_REQ); |
2388 | |
2389 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
2390 | msecs_to_jiffies(5000))) { |
2391 | #if defined(CONFIG_DBX500_PRCMU_DEBUG) |
2392 | db8500_prcmu_debug_dump(__func__, true, true); |
2393 | #endif |
2394 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
2395 | __func__); |
2396 | ret = -EFAULT; |
2397 | } |
2398 | |
2399 | unlock_and_return: |
2400 | mutex_unlock(&mb0_transfer.ac_wake_lock); |
2401 | return ret; |
2402 | } |
2403 | |
2404 | /** |
2405 | * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem |
2406 | */ |
2407 | void prcmu_ac_sleep_req() |
2408 | { |
2409 | u32 val; |
2410 | |
2411 | mutex_lock(&mb0_transfer.ac_wake_lock); |
2412 | |
2413 | val = readl(PRCM_HOSTACCESS_REQ); |
2414 | if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) |
2415 | goto unlock_and_return; |
2416 | |
2417 | writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), |
2418 | PRCM_HOSTACCESS_REQ); |
2419 | |
2420 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
2421 | msecs_to_jiffies(5000))) { |
2422 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
2423 | __func__); |
2424 | } |
2425 | |
2426 | atomic_set(&ac_wake_req_state, 0); |
2427 | |
2428 | unlock_and_return: |
2429 | mutex_unlock(&mb0_transfer.ac_wake_lock); |
2430 | } |
2431 | |
2432 | bool db8500_prcmu_is_ac_wake_requested(void) |
2433 | { |
2434 | return (atomic_read(&ac_wake_req_state) != 0); |
2435 | } |
2436 | |
2437 | /** |
2438 | * db8500_prcmu_system_reset - System reset |
2439 | * |
2440 | * Saves the reset reason code and then sets the APE_SOFTRST register which |
2441 | * fires interrupt to fw |
2442 | */ |
2443 | void db8500_prcmu_system_reset(u16 reset_code) |
2444 | { |
2445 | writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); |
2446 | writel(1, PRCM_APE_SOFTRST); |
2447 | } |
2448 | |
2449 | /** |
2450 | * db8500_prcmu_get_reset_code - Retrieve SW reset reason code |
2451 | * |
2452 | * Retrieves the reset reason code stored by prcmu_system_reset() before |
2453 | * last restart. |
2454 | */ |
2455 | u16 db8500_prcmu_get_reset_code(void) |
2456 | { |
2457 | return readw(tcdm_base + PRCM_SW_RST_REASON); |
2458 | } |
2459 | |
2460 | /** |
2461 | * db8500_prcmu_reset_modem - ask the PRCMU to reset modem |
2462 | */ |
2463 | void db8500_prcmu_modem_reset(void) |
2464 | { |
2465 | mutex_lock(&mb1_transfer.lock); |
2466 | |
2467 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
2468 | cpu_relax(); |
2469 | |
2470 | writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); |
2471 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
2472 | wait_for_completion(&mb1_transfer.work); |
2473 | |
2474 | /* |
2475 | * No need to check return from PRCMU as modem should go in reset state |
2476 | * This state is already managed by upper layer |
2477 | */ |
2478 | |
2479 | mutex_unlock(&mb1_transfer.lock); |
2480 | } |
2481 | |
2482 | static void ack_dbb_wakeup(void) |
2483 | { |
2484 | unsigned long flags; |
2485 | |
2486 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
2487 | |
2488 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
2489 | cpu_relax(); |
2490 | |
2491 | writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); |
2492 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
2493 | |
2494 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
2495 | } |
2496 | |
2497 | static inline void print_unknown_header_warning(u8 n, u8 header) |
2498 | { |
2499 | pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", |
2500 | header, n); |
2501 | } |
2502 | |
2503 | static bool read_mailbox_0(void) |
2504 | { |
2505 | bool r; |
2506 | u32 ev; |
2507 | unsigned int n; |
2508 | u8 header; |
2509 | |
2510 | header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); |
2511 | switch (header) { |
2512 | case MB0H_WAKEUP_EXE: |
2513 | case MB0H_WAKEUP_SLEEP: |
2514 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) |
2515 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); |
2516 | else |
2517 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); |
2518 | |
2519 | if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) |
2520 | complete(&mb0_transfer.ac_wake_work); |
2521 | if (ev & WAKEUP_BIT_SYSCLK_OK) |
2522 | complete(&mb3_transfer.sysclk_work); |
2523 | |
2524 | ev &= mb0_transfer.req.dbb_irqs; |
2525 | |
2526 | for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { |
2527 | if (ev & prcmu_irq_bit[n]) |
2528 | generic_handle_irq(irq_find_mapping(db8500_irq_domain, n)); |
2529 | } |
2530 | r = true; |
2531 | break; |
2532 | default: |
2533 | print_unknown_header_warning(0, header); |
2534 | r = false; |
2535 | break; |
2536 | } |
2537 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); |
2538 | return r; |
2539 | } |
2540 | |
2541 | static bool read_mailbox_1(void) |
2542 | { |
2543 | mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); |
2544 | mb1_transfer.ack.arm_opp = readb(tcdm_base + |
2545 | PRCM_ACK_MB1_CURRENT_ARM_OPP); |
2546 | mb1_transfer.ack.ape_opp = readb(tcdm_base + |
2547 | PRCM_ACK_MB1_CURRENT_APE_OPP); |
2548 | mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + |
2549 | PRCM_ACK_MB1_APE_VOLTAGE_STATUS); |
2550 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); |
2551 | complete(&mb1_transfer.work); |
2552 | return false; |
2553 | } |
2554 | |
2555 | static bool read_mailbox_2(void) |
2556 | { |
2557 | mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); |
2558 | writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); |
2559 | complete(&mb2_transfer.work); |
2560 | return false; |
2561 | } |
2562 | |
2563 | static bool read_mailbox_3(void) |
2564 | { |
2565 | writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); |
2566 | return false; |
2567 | } |
2568 | |
2569 | static bool read_mailbox_4(void) |
2570 | { |
2571 | u8 header; |
2572 | bool do_complete = true; |
2573 | |
2574 | header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); |
2575 | switch (header) { |
2576 | case MB4H_MEM_ST: |
2577 | case MB4H_HOTDOG: |
2578 | case MB4H_HOTMON: |
2579 | case MB4H_HOT_PERIOD: |
2580 | case MB4H_A9WDOG_CONF: |
2581 | case MB4H_A9WDOG_EN: |
2582 | case MB4H_A9WDOG_DIS: |
2583 | case MB4H_A9WDOG_LOAD: |
2584 | case MB4H_A9WDOG_KICK: |
2585 | break; |
2586 | default: |
2587 | print_unknown_header_warning(4, header); |
2588 | do_complete = false; |
2589 | break; |
2590 | } |
2591 | |
2592 | writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); |
2593 | |
2594 | if (do_complete) |
2595 | complete(&mb4_transfer.work); |
2596 | |
2597 | return false; |
2598 | } |
2599 | |
2600 | static bool read_mailbox_5(void) |
2601 | { |
2602 | mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); |
2603 | mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); |
2604 | writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); |
2605 | complete(&mb5_transfer.work); |
2606 | return false; |
2607 | } |
2608 | |
2609 | static bool read_mailbox_6(void) |
2610 | { |
2611 | writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); |
2612 | return false; |
2613 | } |
2614 | |
2615 | static bool read_mailbox_7(void) |
2616 | { |
2617 | writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); |
2618 | return false; |
2619 | } |
2620 | |
2621 | static bool (* const read_mailbox[NUM_MB])(void) = { |
2622 | read_mailbox_0, |
2623 | read_mailbox_1, |
2624 | read_mailbox_2, |
2625 | read_mailbox_3, |
2626 | read_mailbox_4, |
2627 | read_mailbox_5, |
2628 | read_mailbox_6, |
2629 | read_mailbox_7 |
2630 | }; |
2631 | |
2632 | static irqreturn_t prcmu_irq_handler(int irq, void *data) |
2633 | { |
2634 | u32 bits; |
2635 | u8 n; |
2636 | irqreturn_t r; |
2637 | |
2638 | bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); |
2639 | if (unlikely(!bits)) |
2640 | return IRQ_NONE; |
2641 | |
2642 | r = IRQ_HANDLED; |
2643 | for (n = 0; bits; n++) { |
2644 | if (bits & MBOX_BIT(n)) { |
2645 | bits -= MBOX_BIT(n); |
2646 | if (read_mailbox[n]()) |
2647 | r = IRQ_WAKE_THREAD; |
2648 | } |
2649 | } |
2650 | return r; |
2651 | } |
2652 | |
2653 | static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) |
2654 | { |
2655 | ack_dbb_wakeup(); |
2656 | return IRQ_HANDLED; |
2657 | } |
2658 | |
2659 | static void prcmu_mask_work(struct work_struct *work) |
2660 | { |
2661 | unsigned long flags; |
2662 | |
2663 | spin_lock_irqsave(&mb0_transfer.lock, flags); |
2664 | |
2665 | config_wakeups(); |
2666 | |
2667 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); |
2668 | } |
2669 | |
2670 | static void prcmu_irq_mask(struct irq_data *d) |
2671 | { |
2672 | unsigned long flags; |
2673 | |
2674 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); |
2675 | |
2676 | mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; |
2677 | |
2678 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); |
2679 | |
2680 | if (d->irq != IRQ_PRCMU_CA_SLEEP) |
2681 | schedule_work(&mb0_transfer.mask_work); |
2682 | } |
2683 | |
2684 | static void prcmu_irq_unmask(struct irq_data *d) |
2685 | { |
2686 | unsigned long flags; |
2687 | |
2688 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); |
2689 | |
2690 | mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; |
2691 | |
2692 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); |
2693 | |
2694 | if (d->irq != IRQ_PRCMU_CA_SLEEP) |
2695 | schedule_work(&mb0_transfer.mask_work); |
2696 | } |
2697 | |
2698 | static void noop(struct irq_data *d) |
2699 | { |
2700 | } |
2701 | |
2702 | static struct irq_chip prcmu_irq_chip = { |
2703 | .name = "prcmu", |
2704 | .irq_disable = prcmu_irq_mask, |
2705 | .irq_ack = noop, |
2706 | .irq_mask = prcmu_irq_mask, |
2707 | .irq_unmask = prcmu_irq_unmask, |
2708 | }; |
2709 | |
2710 | static __init char *fw_project_name(u32 project) |
2711 | { |
2712 | switch (project) { |
2713 | case PRCMU_FW_PROJECT_U8500: |
2714 | return "U8500"; |
2715 | case PRCMU_FW_PROJECT_U8400: |
2716 | return "U8400"; |
2717 | case PRCMU_FW_PROJECT_U9500: |
2718 | return "U9500"; |
2719 | case PRCMU_FW_PROJECT_U8500_MBB: |
2720 | return "U8500 MBB"; |
2721 | case PRCMU_FW_PROJECT_U8500_C1: |
2722 | return "U8500 C1"; |
2723 | case PRCMU_FW_PROJECT_U8500_C2: |
2724 | return "U8500 C2"; |
2725 | case PRCMU_FW_PROJECT_U8500_C3: |
2726 | return "U8500 C3"; |
2727 | case PRCMU_FW_PROJECT_U8500_C4: |
2728 | return "U8500 C4"; |
2729 | case PRCMU_FW_PROJECT_U9500_MBL: |
2730 | return "U9500 MBL"; |
2731 | case PRCMU_FW_PROJECT_U8500_MBL: |
2732 | return "U8500 MBL"; |
2733 | case PRCMU_FW_PROJECT_U8500_MBL2: |
2734 | return "U8500 MBL2"; |
2735 | case PRCMU_FW_PROJECT_U8520: |
2736 | return "U8520 MBL"; |
2737 | case PRCMU_FW_PROJECT_U8420: |
2738 | return "U8420"; |
2739 | case PRCMU_FW_PROJECT_U9540: |
2740 | return "U9540"; |
2741 | case PRCMU_FW_PROJECT_A9420: |
2742 | return "A9420"; |
2743 | case PRCMU_FW_PROJECT_L8540: |
2744 | return "L8540"; |
2745 | case PRCMU_FW_PROJECT_L8580: |
2746 | return "L8580"; |
2747 | default: |
2748 | return "Unknown"; |
2749 | } |
2750 | } |
2751 | |
2752 | static int db8500_irq_map(struct irq_domain *d, unsigned int virq, |
2753 | irq_hw_number_t hwirq) |
2754 | { |
2755 | irq_set_chip_and_handler(virq, &prcmu_irq_chip, |
2756 | handle_simple_irq); |
2757 | set_irq_flags(virq, IRQF_VALID); |
2758 | |
2759 | return 0; |
2760 | } |
2761 | |
2762 | static struct irq_domain_ops db8500_irq_ops = { |
2763 | .map = db8500_irq_map, |
2764 | .xlate = irq_domain_xlate_twocell, |
2765 | }; |
2766 | |
2767 | static int db8500_irq_init(struct device_node *np) |
2768 | { |
2769 | int irq_base = 0; |
2770 | int i; |
2771 | |
2772 | /* In the device tree case, just take some IRQs */ |
2773 | if (!np) |
2774 | irq_base = IRQ_PRCMU_BASE; |
2775 | |
2776 | db8500_irq_domain = irq_domain_add_simple( |
2777 | np, NUM_PRCMU_WAKEUPS, irq_base, |
2778 | &db8500_irq_ops, NULL); |
2779 | |
2780 | if (!db8500_irq_domain) { |
2781 | pr_err("Failed to create irqdomain\n"); |
2782 | return -ENOSYS; |
2783 | } |
2784 | |
2785 | /* All wakeups will be used, so create mappings for all */ |
2786 | for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) |
2787 | irq_create_mapping(db8500_irq_domain, i); |
2788 | |
2789 | return 0; |
2790 | } |
2791 | |
2792 | static void dbx500_fw_version_init(struct platform_device *pdev, |
2793 | u32 version_offset) |
2794 | { |
2795 | struct resource *res; |
2796 | void __iomem *tcpm_base; |
2797 | |
2798 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2799 | "prcmu-tcpm"); |
2800 | if (!res) { |
2801 | dev_err(&pdev->dev, |
2802 | "Error: no prcmu tcpm memory region provided\n"); |
2803 | return; |
2804 | } |
2805 | tcpm_base = ioremap(res->start, resource_size(res)); |
2806 | if (tcpm_base != NULL) { |
2807 | u32 version; |
2808 | |
2809 | version = readl(tcpm_base + version_offset); |
2810 | fw_info.version.project = (version & 0xFF); |
2811 | fw_info.version.api_version = (version >> 8) & 0xFF; |
2812 | fw_info.version.func_version = (version >> 16) & 0xFF; |
2813 | fw_info.version.errata = (version >> 24) & 0xFF; |
2814 | strncpy(fw_info.version.project_name, |
2815 | fw_project_name(fw_info.version.project), |
2816 | PRCMU_FW_PROJECT_NAME_LEN); |
2817 | fw_info.valid = true; |
2818 | pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n", |
2819 | fw_info.version.project_name, |
2820 | fw_info.version.project, |
2821 | fw_info.version.api_version, |
2822 | fw_info.version.func_version, |
2823 | fw_info.version.errata); |
2824 | iounmap(tcpm_base); |
2825 | } |
2826 | } |
2827 | |
2828 | void __init db8500_prcmu_early_init(void) |
2829 | { |
2830 | spin_lock_init(&mb0_transfer.lock); |
2831 | spin_lock_init(&mb0_transfer.dbb_irqs_lock); |
2832 | mutex_init(&mb0_transfer.ac_wake_lock); |
2833 | init_completion(&mb0_transfer.ac_wake_work); |
2834 | mutex_init(&mb1_transfer.lock); |
2835 | init_completion(&mb1_transfer.work); |
2836 | mb1_transfer.ape_opp = APE_NO_CHANGE; |
2837 | mutex_init(&mb2_transfer.lock); |
2838 | init_completion(&mb2_transfer.work); |
2839 | spin_lock_init(&mb2_transfer.auto_pm_lock); |
2840 | spin_lock_init(&mb3_transfer.lock); |
2841 | mutex_init(&mb3_transfer.sysclk_lock); |
2842 | init_completion(&mb3_transfer.sysclk_work); |
2843 | mutex_init(&mb4_transfer.lock); |
2844 | init_completion(&mb4_transfer.work); |
2845 | mutex_init(&mb5_transfer.lock); |
2846 | init_completion(&mb5_transfer.work); |
2847 | |
2848 | INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); |
2849 | } |
2850 | |
2851 | static void __init init_prcm_registers(void) |
2852 | { |
2853 | u32 val; |
2854 | |
2855 | val = readl(PRCM_A9PL_FORCE_CLKEN); |
2856 | val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | |
2857 | PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); |
2858 | writel(val, (PRCM_A9PL_FORCE_CLKEN)); |
2859 | } |
2860 | |
2861 | /* |
2862 | * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC |
2863 | */ |
2864 | static struct regulator_consumer_supply db8500_vape_consumers[] = { |
2865 | REGULATOR_SUPPLY("v-ape", NULL), |
2866 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), |
2867 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), |
2868 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), |
2869 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), |
2870 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), |
2871 | /* "v-mmc" changed to "vcore" in the mainline kernel */ |
2872 | REGULATOR_SUPPLY("vcore", "sdi0"), |
2873 | REGULATOR_SUPPLY("vcore", "sdi1"), |
2874 | REGULATOR_SUPPLY("vcore", "sdi2"), |
2875 | REGULATOR_SUPPLY("vcore", "sdi3"), |
2876 | REGULATOR_SUPPLY("vcore", "sdi4"), |
2877 | REGULATOR_SUPPLY("v-dma", "dma40.0"), |
2878 | REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), |
2879 | /* "v-uart" changed to "vcore" in the mainline kernel */ |
2880 | REGULATOR_SUPPLY("vcore", "uart0"), |
2881 | REGULATOR_SUPPLY("vcore", "uart1"), |
2882 | REGULATOR_SUPPLY("vcore", "uart2"), |
2883 | REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), |
2884 | REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), |
2885 | REGULATOR_SUPPLY("vddvario", "smsc911x.0"), |
2886 | }; |
2887 | |
2888 | static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { |
2889 | REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), |
2890 | /* AV8100 regulator */ |
2891 | REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), |
2892 | }; |
2893 | |
2894 | static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { |
2895 | REGULATOR_SUPPLY("vsupply", "b2r2_bus"), |
2896 | REGULATOR_SUPPLY("vsupply", "mcde"), |
2897 | }; |
2898 | |
2899 | /* SVA MMDSP regulator switch */ |
2900 | static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { |
2901 | REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), |
2902 | }; |
2903 | |
2904 | /* SVA pipe regulator switch */ |
2905 | static struct regulator_consumer_supply db8500_svapipe_consumers[] = { |
2906 | REGULATOR_SUPPLY("sva-pipe", "cm_control"), |
2907 | }; |
2908 | |
2909 | /* SIA MMDSP regulator switch */ |
2910 | static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { |
2911 | REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), |
2912 | }; |
2913 | |
2914 | /* SIA pipe regulator switch */ |
2915 | static struct regulator_consumer_supply db8500_siapipe_consumers[] = { |
2916 | REGULATOR_SUPPLY("sia-pipe", "cm_control"), |
2917 | }; |
2918 | |
2919 | static struct regulator_consumer_supply db8500_sga_consumers[] = { |
2920 | REGULATOR_SUPPLY("v-mali", NULL), |
2921 | }; |
2922 | |
2923 | /* ESRAM1 and 2 regulator switch */ |
2924 | static struct regulator_consumer_supply db8500_esram12_consumers[] = { |
2925 | REGULATOR_SUPPLY("esram12", "cm_control"), |
2926 | }; |
2927 | |
2928 | /* ESRAM3 and 4 regulator switch */ |
2929 | static struct regulator_consumer_supply db8500_esram34_consumers[] = { |
2930 | REGULATOR_SUPPLY("v-esram34", "mcde"), |
2931 | REGULATOR_SUPPLY("esram34", "cm_control"), |
2932 | REGULATOR_SUPPLY("lcla_esram", "dma40.0"), |
2933 | }; |
2934 | |
2935 | static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { |
2936 | [DB8500_REGULATOR_VAPE] = { |
2937 | .constraints = { |
2938 | .name = "db8500-vape", |
2939 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
2940 | .always_on = true, |
2941 | }, |
2942 | .consumer_supplies = db8500_vape_consumers, |
2943 | .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), |
2944 | }, |
2945 | [DB8500_REGULATOR_VARM] = { |
2946 | .constraints = { |
2947 | .name = "db8500-varm", |
2948 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
2949 | }, |
2950 | }, |
2951 | [DB8500_REGULATOR_VMODEM] = { |
2952 | .constraints = { |
2953 | .name = "db8500-vmodem", |
2954 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
2955 | }, |
2956 | }, |
2957 | [DB8500_REGULATOR_VPLL] = { |
2958 | .constraints = { |
2959 | .name = "db8500-vpll", |
2960 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
2961 | }, |
2962 | }, |
2963 | [DB8500_REGULATOR_VSMPS1] = { |
2964 | .constraints = { |
2965 | .name = "db8500-vsmps1", |
2966 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
2967 | }, |
2968 | }, |
2969 | [DB8500_REGULATOR_VSMPS2] = { |
2970 | .constraints = { |
2971 | .name = "db8500-vsmps2", |
2972 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
2973 | }, |
2974 | .consumer_supplies = db8500_vsmps2_consumers, |
2975 | .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), |
2976 | }, |
2977 | [DB8500_REGULATOR_VSMPS3] = { |
2978 | .constraints = { |
2979 | .name = "db8500-vsmps3", |
2980 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
2981 | }, |
2982 | }, |
2983 | [DB8500_REGULATOR_VRF1] = { |
2984 | .constraints = { |
2985 | .name = "db8500-vrf1", |
2986 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
2987 | }, |
2988 | }, |
2989 | [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { |
2990 | /* dependency to u8500-vape is handled outside regulator framework */ |
2991 | .constraints = { |
2992 | .name = "db8500-sva-mmdsp", |
2993 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
2994 | }, |
2995 | .consumer_supplies = db8500_svammdsp_consumers, |
2996 | .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), |
2997 | }, |
2998 | [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { |
2999 | .constraints = { |
3000 | /* "ret" means "retention" */ |
3001 | .name = "db8500-sva-mmdsp-ret", |
3002 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3003 | }, |
3004 | }, |
3005 | [DB8500_REGULATOR_SWITCH_SVAPIPE] = { |
3006 | /* dependency to u8500-vape is handled outside regulator framework */ |
3007 | .constraints = { |
3008 | .name = "db8500-sva-pipe", |
3009 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3010 | }, |
3011 | .consumer_supplies = db8500_svapipe_consumers, |
3012 | .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), |
3013 | }, |
3014 | [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { |
3015 | /* dependency to u8500-vape is handled outside regulator framework */ |
3016 | .constraints = { |
3017 | .name = "db8500-sia-mmdsp", |
3018 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3019 | }, |
3020 | .consumer_supplies = db8500_siammdsp_consumers, |
3021 | .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), |
3022 | }, |
3023 | [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { |
3024 | .constraints = { |
3025 | .name = "db8500-sia-mmdsp-ret", |
3026 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3027 | }, |
3028 | }, |
3029 | [DB8500_REGULATOR_SWITCH_SIAPIPE] = { |
3030 | /* dependency to u8500-vape is handled outside regulator framework */ |
3031 | .constraints = { |
3032 | .name = "db8500-sia-pipe", |
3033 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3034 | }, |
3035 | .consumer_supplies = db8500_siapipe_consumers, |
3036 | .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), |
3037 | }, |
3038 | [DB8500_REGULATOR_SWITCH_SGA] = { |
3039 | .supply_regulator = "db8500-vape", |
3040 | .constraints = { |
3041 | .name = "db8500-sga", |
3042 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3043 | }, |
3044 | .consumer_supplies = db8500_sga_consumers, |
3045 | .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), |
3046 | |
3047 | }, |
3048 | [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { |
3049 | .supply_regulator = "db8500-vape", |
3050 | .constraints = { |
3051 | .name = "db8500-b2r2-mcde", |
3052 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3053 | }, |
3054 | .consumer_supplies = db8500_b2r2_mcde_consumers, |
3055 | .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), |
3056 | }, |
3057 | [DB8500_REGULATOR_SWITCH_ESRAM12] = { |
3058 | /* |
3059 | * esram12 is set in retention and supplied by Vsafe when Vape is off, |
3060 | * no need to hold Vape |
3061 | */ |
3062 | .constraints = { |
3063 | .name = "db8500-esram12", |
3064 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3065 | }, |
3066 | .consumer_supplies = db8500_esram12_consumers, |
3067 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), |
3068 | }, |
3069 | [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { |
3070 | .constraints = { |
3071 | .name = "db8500-esram12-ret", |
3072 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3073 | }, |
3074 | }, |
3075 | [DB8500_REGULATOR_SWITCH_ESRAM34] = { |
3076 | /* |
3077 | * esram34 is set in retention and supplied by Vsafe when Vape is off, |
3078 | * no need to hold Vape |
3079 | */ |
3080 | .constraints = { |
3081 | .name = "db8500-esram34", |
3082 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3083 | }, |
3084 | .consumer_supplies = db8500_esram34_consumers, |
3085 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), |
3086 | }, |
3087 | [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { |
3088 | .constraints = { |
3089 | .name = "db8500-esram34-ret", |
3090 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
3091 | }, |
3092 | }, |
3093 | }; |
3094 | |
3095 | static struct resource ab8500_resources[] = { |
3096 | [0] = { |
3097 | .start = IRQ_DB8500_AB8500, |
3098 | .end = IRQ_DB8500_AB8500, |
3099 | .flags = IORESOURCE_IRQ |
3100 | } |
3101 | }; |
3102 | |
3103 | static struct ux500_wdt_data db8500_wdt_pdata = { |
3104 | .timeout = 600, /* 10 minutes */ |
3105 | .has_28_bits_resolution = true, |
3106 | }; |
3107 | |
3108 | static struct mfd_cell db8500_prcmu_devs[] = { |
3109 | { |
3110 | .name = "db8500-prcmu-regulators", |
3111 | .of_compatible = "stericsson,db8500-prcmu-regulator", |
3112 | .platform_data = &db8500_regulators, |
3113 | .pdata_size = sizeof(db8500_regulators), |
3114 | }, |
3115 | { |
3116 | .name = "cpufreq-ux500", |
3117 | .of_compatible = "stericsson,cpufreq-ux500", |
3118 | .platform_data = &db8500_cpufreq_table, |
3119 | .pdata_size = sizeof(db8500_cpufreq_table), |
3120 | }, |
3121 | { |
3122 | .name = "ux500_wdt", |
3123 | .platform_data = &db8500_wdt_pdata, |
3124 | .pdata_size = sizeof(db8500_wdt_pdata), |
3125 | .id = -1, |
3126 | }, |
3127 | { |
3128 | .name = "ab8500-core", |
3129 | .of_compatible = "stericsson,ab8500", |
3130 | .num_resources = ARRAY_SIZE(ab8500_resources), |
3131 | .resources = ab8500_resources, |
3132 | .id = AB8500_VERSION_AB8500, |
3133 | }, |
3134 | }; |
3135 | |
3136 | static void db8500_prcmu_update_cpufreq(void) |
3137 | { |
3138 | if (prcmu_has_arm_maxopp()) { |
3139 | db8500_cpufreq_table[3].frequency = 1000000; |
3140 | db8500_cpufreq_table[3].index = ARM_MAX_OPP; |
3141 | } |
3142 | } |
3143 | |
3144 | /** |
3145 | * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic |
3146 | * |
3147 | */ |
3148 | static int db8500_prcmu_probe(struct platform_device *pdev) |
3149 | { |
3150 | struct device_node *np = pdev->dev.of_node; |
3151 | struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev); |
3152 | int irq = 0, err = 0, i; |
3153 | struct resource *res; |
3154 | |
3155 | init_prcm_registers(); |
3156 | |
3157 | dbx500_fw_version_init(pdev, pdata->version_offset); |
3158 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); |
3159 | if (!res) { |
3160 | dev_err(&pdev->dev, "no prcmu tcdm region provided\n"); |
3161 | return -ENOENT; |
3162 | } |
3163 | tcdm_base = devm_ioremap(&pdev->dev, res->start, |
3164 | resource_size(res)); |
3165 | |
3166 | /* Clean up the mailbox interrupts after pre-kernel code. */ |
3167 | writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); |
3168 | |
3169 | irq = platform_get_irq(pdev, 0); |
3170 | if (irq <= 0) { |
3171 | dev_err(&pdev->dev, "no prcmu irq provided\n"); |
3172 | return -ENOENT; |
3173 | } |
3174 | |
3175 | err = request_threaded_irq(irq, prcmu_irq_handler, |
3176 | prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); |
3177 | if (err < 0) { |
3178 | pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); |
3179 | err = -EBUSY; |
3180 | goto no_irq_return; |
3181 | } |
3182 | |
3183 | db8500_irq_init(np); |
3184 | |
3185 | for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) { |
3186 | if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) { |
3187 | db8500_prcmu_devs[i].platform_data = pdata->ab_platdata; |
3188 | db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data); |
3189 | } |
3190 | } |
3191 | |
3192 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); |
3193 | |
3194 | db8500_prcmu_update_cpufreq(); |
3195 | |
3196 | err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, |
3197 | ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL); |
3198 | if (err) { |
3199 | pr_err("prcmu: Failed to add subdevices\n"); |
3200 | return err; |
3201 | } |
3202 | |
3203 | pr_info("DB8500 PRCMU initialized\n"); |
3204 | |
3205 | no_irq_return: |
3206 | return err; |
3207 | } |
3208 | static const struct of_device_id db8500_prcmu_match[] = { |
3209 | { .compatible = "stericsson,db8500-prcmu"}, |
3210 | { }, |
3211 | }; |
3212 | |
3213 | static struct platform_driver db8500_prcmu_driver = { |
3214 | .driver = { |
3215 | .name = "db8500-prcmu", |
3216 | .owner = THIS_MODULE, |
3217 | .of_match_table = db8500_prcmu_match, |
3218 | }, |
3219 | .probe = db8500_prcmu_probe, |
3220 | }; |
3221 | |
3222 | static int __init db8500_prcmu_init(void) |
3223 | { |
3224 | return platform_driver_register(&db8500_prcmu_driver); |
3225 | } |
3226 | |
3227 | core_initcall(db8500_prcmu_init); |
3228 | |
3229 | MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); |
3230 | MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); |
3231 | MODULE_LICENSE("GPL v2"); |
3232 |
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