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Source at commit 0345656 created 13 years 4 months ago. By Erwin Lopez, Pins corrected again | |
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1 | Release 12.2 Map M.63c (lin64) |
2 | Xilinx Map Application Log File for Design 'beta' |
3 | |
4 | Design Information |
5 | ------------------ |
6 | Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd |
7 | Target Device : xc3s500e |
8 | Target Package : vq100 |
9 | Target Speed : -4 |
10 | Mapper Version : spartan3e -- $Revision: 1.52 $ |
11 | Mapped Date : Sun Oct 31 14:11:28 2010 |
12 | |
13 | Mapping design into LUTs... |
14 | Writing file project.ngm... |
15 | Running directed packing... |
16 | Running delay-based LUT packing... |
17 | Running related packing... |
18 | Updating timing models... |
19 | Writing design file "project.ncd"... |
20 | |
21 | Design Summary |
22 | -------------- |
23 | |
24 | Design Summary: |
25 | Number of errors: 0 |
26 | Number of warnings: 0 |
27 | Logic Utilization: |
28 | Number of Slice Flip Flops: 131 out of 9,312 1% |
29 | Number of 4 input LUTs: 112 out of 9,312 1% |
30 | Logic Distribution: |
31 | Number of occupied Slices: 118 out of 4,656 2% |
32 | Number of Slices containing only related logic: 118 out of 118 100% |
33 | Number of Slices containing unrelated logic: 0 out of 118 0% |
34 | *See NOTES below for an explanation of the effects of unrelated logic. |
35 | Total Number of 4 input LUTs: 140 out of 9,312 1% |
36 | Number used as logic: 112 |
37 | Number used as a route-thru: 28 |
38 | |
39 | The Slice Logic Distribution report is not meaningful if the design is |
40 | over-mapped for a non-slice resource or if Placement fails. |
41 | |
42 | Number of bonded IOBs: 34 out of 66 51% |
43 | IOB Flip Flops: 27 |
44 | Number of RAMB16s: 4 out of 20 20% |
45 | Number of BUFGMUXs: 1 out of 24 4% |
46 | |
47 | Average Fanout of Non-Clock Nets: 2.51 |
48 | |
49 | Peak Memory Usage: 367 MB |
50 | Total REAL time to MAP completion: 5 secs |
51 | Total CPU time to MAP completion: 2 secs |
52 | |
53 | NOTES: |
54 | |
55 | Related logic is defined as being logic that shares connectivity - e.g. two |
56 | LUTs are "related" if they share common inputs. When assembling slices, |
57 | Map gives priority to combine logic that is related. Doing so results in |
58 | the best timing performance. |
59 | |
60 | Unrelated logic shares no connectivity. Map will only begin packing |
61 | unrelated logic into a slice once 99% of the slices are occupied through |
62 | related logic packing. |
63 | |
64 | Note that once logic distribution reaches the 99% level through related |
65 | logic packing, this does not mean the device is completely utilized. |
66 | Unrelated logic packing will then begin, continuing until all usable LUTs |
67 | and FFs are occupied. Depending on your timing budget, increased levels of |
68 | unrelated logic packing may adversely affect the overall timing performance |
69 | of your design. |
70 | |
71 | Mapping completed. |
72 | See MAP report file "project.mrp" for details. |
73 |
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