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Source at commit 551a96ecc3a53a71a3127421055d5d559063874e created 13 years 4 months ago. By Erwin Lopez, Added .bit with hbridge pins and with testing pins | |
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1 | Release 12.2 Map M.63c (lin64) |
2 | Xilinx Mapping Report File for Design 'beta' |
3 | |
4 | Design Information |
5 | ------------------ |
6 | Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd |
7 | Target Device : xc3s500e |
8 | Target Package : vq100 |
9 | Target Speed : -4 |
10 | Mapper Version : spartan3e -- $Revision: 1.52 $ |
11 | Mapped Date : Sun Oct 31 12:20:35 2010 |
12 | |
13 | Design Summary |
14 | -------------- |
15 | Number of errors: 0 |
16 | Number of warnings: 0 |
17 | Logic Utilization: |
18 | Number of Slice Flip Flops: 131 out of 9,312 1% |
19 | Number of 4 input LUTs: 112 out of 9,312 1% |
20 | Logic Distribution: |
21 | Number of occupied Slices: 118 out of 4,656 2% |
22 | Number of Slices containing only related logic: 118 out of 118 100% |
23 | Number of Slices containing unrelated logic: 0 out of 118 0% |
24 | *See NOTES below for an explanation of the effects of unrelated logic. |
25 | Total Number of 4 input LUTs: 140 out of 9,312 1% |
26 | Number used as logic: 112 |
27 | Number used as a route-thru: 28 |
28 | |
29 | The Slice Logic Distribution report is not meaningful if the design is |
30 | over-mapped for a non-slice resource or if Placement fails. |
31 | |
32 | Number of bonded IOBs: 34 out of 66 51% |
33 | IOB Flip Flops: 27 |
34 | Number of RAMB16s: 4 out of 20 20% |
35 | Number of BUFGMUXs: 1 out of 24 4% |
36 | |
37 | Average Fanout of Non-Clock Nets: 2.51 |
38 | |
39 | Peak Memory Usage: 367 MB |
40 | Total REAL time to MAP completion: 4 secs |
41 | Total CPU time to MAP completion: 2 secs |
42 | |
43 | NOTES: |
44 | |
45 | Related logic is defined as being logic that shares connectivity - e.g. two |
46 | LUTs are "related" if they share common inputs. When assembling slices, |
47 | Map gives priority to combine logic that is related. Doing so results in |
48 | the best timing performance. |
49 | |
50 | Unrelated logic shares no connectivity. Map will only begin packing |
51 | unrelated logic into a slice once 99% of the slices are occupied through |
52 | related logic packing. |
53 | |
54 | Note that once logic distribution reaches the 99% level through related |
55 | logic packing, this does not mean the device is completely utilized. |
56 | Unrelated logic packing will then begin, continuing until all usable LUTs |
57 | and FFs are occupied. Depending on your timing budget, increased levels of |
58 | unrelated logic packing may adversely affect the overall timing performance |
59 | of your design. |
60 | |
61 | Table of Contents |
62 | ----------------- |
63 | Section 1 - Errors |
64 | Section 2 - Warnings |
65 | Section 3 - Informational |
66 | Section 4 - Removed Logic Summary |
67 | Section 5 - Removed Logic |
68 | Section 6 - IOB Properties |
69 | Section 7 - RPMs |
70 | Section 8 - Guide Report |
71 | Section 9 - Area Group and Partition Summary |
72 | Section 10 - Timing Report |
73 | Section 11 - Configuration String Information |
74 | Section 12 - Control Set Information |
75 | Section 13 - Utilization by Hierarchy |
76 | |
77 | Section 1 - Errors |
78 | ------------------ |
79 | |
80 | Section 2 - Warnings |
81 | -------------------- |
82 | |
83 | Section 3 - Informational |
84 | ------------------------- |
85 | INFO:MapLib:562 - No environment variables are currently set. |
86 | INFO:LIT:244 - All of the single ended outputs in this design are using slew |
87 | rate limited output drivers. The delay on speed critical single ended outputs |
88 | can be dramatically reduced by designating them as fast outputs. |
89 | |
90 | Section 4 - Removed Logic Summary |
91 | --------------------------------- |
92 | 2 block(s) optimized away |
93 | |
94 | Section 5 - Removed Logic |
95 | ------------------------- |
96 | |
97 | Optimized Block(s): |
98 | TYPE BLOCK |
99 | GND XST_GND |
100 | VCC XST_VCC |
101 | |
102 | To enable printing of redundant blocks removed and signals merged, set the |
103 | detailed map report option and rerun map. |
104 | |
105 | Section 6 - IOB Properties |
106 | -------------------------- |
107 | |
108 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
109 | | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | |
110 | | | | | | Term | Strength | Rate | | | Delay | |
111 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
112 | | addr<0> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
113 | | addr<1> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
114 | | addr<2> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
115 | | addr<3> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
116 | | addr<4> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
117 | | addr<5> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
118 | | addr<6> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
119 | | addr<7> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
120 | | addr<8> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
121 | | addr<9> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
122 | | addr<10> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
123 | | addr<11> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
124 | | addr<12> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
125 | | clk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
126 | | hbridge<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
127 | | hbridge<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
128 | | hbridge<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
129 | | hbridge<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
130 | | ncs | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
131 | | noe | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
132 | | nwe | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
133 | | quadA | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
134 | | quadB | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
135 | | quadC | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
136 | | quadD | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | |
137 | | reset | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
138 | | sram_data<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 | |
139 | | sram_data<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 | |
140 | | sram_data<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 | |
141 | | sram_data<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 | |
142 | | sram_data<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 | |
143 | | sram_data<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 | |
144 | | sram_data<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 | |
145 | | sram_data<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 | |
146 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
147 | |
148 | Section 7 - RPMs |
149 | ---------------- |
150 | |
151 | Section 8 - Guide Report |
152 | ------------------------ |
153 | Guide not run on this design. |
154 | |
155 | Section 9 - Area Group and Partition Summary |
156 | -------------------------------------------- |
157 | |
158 | Partition Implementation Status |
159 | ------------------------------- |
160 | |
161 | No Partitions were found in this design. |
162 | |
163 | ------------------------------- |
164 | |
165 | Area Group Information |
166 | ---------------------- |
167 | |
168 | No area groups were found in this design. |
169 | |
170 | ---------------------- |
171 | |
172 | Section 10 - Timing Report |
173 | -------------------------- |
174 | This design was not run using timing mode. |
175 | |
176 | Section 11 - Configuration String Details |
177 | ----------------------------------------- |
178 | Use the "-detail" map option to print out Configuration Strings |
179 | |
180 | Section 12 - Control Set Information |
181 | ------------------------------------ |
182 | No control set information for this architecture. |
183 | |
184 | Section 13 - Utilization by Hierarchy |
185 | ------------------------------------- |
186 | Use the "-detail" map option to print out the Utilization by Hierarchy section. |
187 |
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