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Source at commit 551a96ecc3a53a71a3127421055d5d559063874e created 13 years 4 months ago. By Erwin Lopez, Added .bit with hbridge pins and with testing pins | |
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1 | Release 12.2 par M.63c (lin64) |
2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
3 | |
4 | dellerwin:: Sun Oct 31 12:20:42 2010 |
5 | |
6 | par -w project.ncd project_r.ncd |
7 | |
8 | |
9 | Constraints file: project.pcf. |
10 | Loading device for application Rf_Device from file '3s500e.nph' in environment /home/erwin/Xilinxs/12.2/ISE_DS/ISE/. |
11 | "beta" is an NCD, version 3.2, device xc3s500e, package vq100, speed -4 |
12 | |
13 | Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) |
14 | Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts) |
15 | |
16 | INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par |
17 | -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all |
18 | internal clocks in this design. Because there are not defined timing requirements, a timing score will not be |
19 | reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. |
20 | Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". |
21 | |
22 | Device speed data version: "PRODUCTION 1.27 2010-06-22". |
23 | |
24 | |
25 | Design Summary Report: |
26 | |
27 | Number of External IOBs 34 out of 66 51% |
28 | |
29 | Number of External Input IOBs 22 |
30 | |
31 | Number of External Input IBUFs 22 |
32 | Number of LOCed External Input IBUFs 22 out of 22 100% |
33 | |
34 | |
35 | Number of External Output IOBs 4 |
36 | |
37 | Number of External Output IOBs 4 |
38 | Number of LOCed External Output IOBs 4 out of 4 100% |
39 | |
40 | |
41 | Number of External Bidir IOBs 8 |
42 | |
43 | Number of External Bidir IOBs 8 |
44 | Number of LOCed External Bidir IOBs 8 out of 8 100% |
45 | |
46 | |
47 | Number of BUFGMUXs 1 out of 24 4% |
48 | Number of RAMB16s 4 out of 20 20% |
49 | Number of Slices 118 out of 4656 2% |
50 | Number of SLICEMs 0 out of 2328 0% |
51 | |
52 | |
53 | |
54 | Overall effort level (-ol): Standard |
55 | Placer effort level (-pl): High |
56 | Placer cost table entry (-t): 1 |
57 | Router effort level (-rl): High |
58 | |
59 | Starting initial Timing Analysis. REAL time: 2 secs |
60 | Finished initial Timing Analysis. REAL time: 2 secs |
61 | |
62 | |
63 | Starting Placer |
64 | Total REAL time at the beginning of Placer: 2 secs |
65 | Total CPU time at the beginning of Placer: 1 secs |
66 | |
67 | Phase 1.1 Initial Placement Analysis |
68 | Phase 1.1 Initial Placement Analysis (Checksum:cb32ae9e) REAL time: 3 secs |
69 | |
70 | Phase 2.7 Design Feasibility Check |
71 | Phase 2.7 Design Feasibility Check (Checksum:cb32ae9e) REAL time: 3 secs |
72 | |
73 | Phase 3.31 Local Placement Optimization |
74 | Phase 3.31 Local Placement Optimization (Checksum:cb32ae9e) REAL time: 3 secs |
75 | |
76 | Phase 4.2 Initial Clock and IO Placement |
77 | |
78 | Phase 4.2 Initial Clock and IO Placement (Checksum:534cc618) REAL time: 4 secs |
79 | |
80 | Phase 5.30 Global Clock Region Assignment |
81 | Phase 5.30 Global Clock Region Assignment (Checksum:534cc618) REAL time: 4 secs |
82 | |
83 | Phase 6.36 Local Placement Optimization |
84 | Phase 6.36 Local Placement Optimization (Checksum:534cc618) REAL time: 4 secs |
85 | |
86 | Phase 7.8 Global Placement |
87 | .... |
88 | ... |
89 | ... |
90 | ... |
91 | .... |
92 | Phase 7.8 Global Placement (Checksum:b10264e) REAL time: 11 secs |
93 | |
94 | Phase 8.5 Local Placement Optimization |
95 | Phase 8.5 Local Placement Optimization (Checksum:b10264e) REAL time: 11 secs |
96 | |
97 | Phase 9.18 Placement Optimization |
98 | Phase 9.18 Placement Optimization (Checksum:a0b1bc3c) REAL time: 12 secs |
99 | |
100 | Phase 10.5 Local Placement Optimization |
101 | Phase 10.5 Local Placement Optimization (Checksum:a0b1bc3c) REAL time: 12 secs |
102 | |
103 | Total REAL time to Placer completion: 12 secs |
104 | Total CPU time to Placer completion: 10 secs |
105 | Writing design to file project_r.ncd |
106 | |
107 | |
108 | |
109 | Starting Router |
110 | |
111 | |
112 | Phase 1 : 776 unrouted; REAL time: 17 secs |
113 | |
114 | Phase 2 : 652 unrouted; REAL time: 17 secs |
115 | |
116 | Phase 3 : 110 unrouted; REAL time: 17 secs |
117 | |
118 | Phase 4 : 129 unrouted; (Par is working to improve performance) REAL time: 18 secs |
119 | |
120 | Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 18 secs |
121 | |
122 | Updating file: project_r.ncd with current fully routed design. |
123 | |
124 | Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs |
125 | |
126 | Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs |
127 | |
128 | Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs |
129 | |
130 | Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs |
131 | |
132 | Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs |
133 | |
134 | Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs |
135 | |
136 | Total REAL time to Router completion: 23 secs |
137 | Total CPU time to Router completion: 21 secs |
138 | |
139 | Partition Implementation Status |
140 | ------------------------------- |
141 | |
142 | No Partitions were found in this design. |
143 | |
144 | ------------------------------- |
145 | |
146 | Generating "PAR" statistics. |
147 | |
148 | ************************** |
149 | Generating Clock Report |
150 | ************************** |
151 | |
152 | +---------------------+--------------+------+------+------------+-------------+ |
153 | | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| |
154 | +---------------------+--------------+------+------+------------+-------------+ |
155 | | clk_BUFGP | BUFGMUX_X2Y1| No | 99 | 0.082 | 0.204 | |
156 | +---------------------+--------------+------+------+------------+-------------+ |
157 | |
158 | * Net Skew is the difference between the minimum and maximum routing |
159 | only delays for the net. Note this is different from Clock Skew which |
160 | is reported in TRCE timing report. Clock Skew is the difference between |
161 | the minimum and maximum path delays which includes logic delays. |
162 | |
163 | Timing Score: 0 (Setup: 0, Hold: 0) |
164 | |
165 | Asterisk (*) preceding a constraint indicates it was not met. |
166 | This may be due to a setup or hold violation. |
167 | |
168 | ---------------------------------------------------------------------------------------------------------- |
169 | Constraint | Check | Worst Case | Best Case | Timing | Timing |
170 | | | Slack | Achievable | Errors | Score |
171 | ---------------------------------------------------------------------------------------------------------- |
172 | Autotimespec constraint for clock net clk | SETUP | N/A| 9.173ns| N/A| 0 |
173 | _BUFGP | HOLD | 0.968ns| | 0| 0 |
174 | ---------------------------------------------------------------------------------------------------------- |
175 | |
176 | |
177 | All constraints were met. |
178 | INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the |
179 | constraint is not analyzed due to the following: No paths covered by this |
180 | constraint; Other constraints intersect with this constraint; or This |
181 | constraint was disabled by a Path Tracing Control. Please run the Timespec |
182 | Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. |
183 | |
184 | |
185 | Generating Pad Report. |
186 | |
187 | All signals are completely routed. |
188 | |
189 | Total REAL time to PAR completion: 24 secs |
190 | Total CPU time to PAR completion: 21 secs |
191 | |
192 | Peak Memory Usage: 366 MB |
193 | |
194 | Placement: Completed - No errors found. |
195 | Routing: Completed - No errors found. |
196 | |
197 | Number of error messages: 0 |
198 | Number of warning messages: 0 |
199 | Number of info messages: 1 |
200 | |
201 | Writing design to file project_r.ncd |
202 | |
203 | |
204 | |
205 | PAR done! |
206 |
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