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| 1 | `timescale 1ns / 1ps |
| 2 | |
| 3 | module PWM(clk, enable, PWM_in, PWM_out); |
| 4 | input clk, enable; |
| 5 | input [7:0] PWM_in; |
| 6 | output PWM_out; |
| 7 | |
| 8 | reg [7:0] PWM_in_reg=0; //Registro temporal para reiniciar el acumulador |
| 9 | reg [7:0] PWM_accum=0; //Acumulador |
| 10 | reg [8:0] ClkCount=0; //Para dividir la frecuencia en 2^VAL |
| 11 | |
| 12 | //Divisor de frecuencia |
| 13 | always @(posedge clk) if(enable) ClkCount <= ClkCount + 1; |
| 14 | |
| 15 | //Contador para el PWM |
| 16 | always @(posedge clk) |
| 17 | begin |
| 18 | PWM_in_reg<=PWM_in; |
| 19 | if(PWM_in_reg==PWM_in) PWM_accum<=PWM_accum+1; else PWM_accum<=0; |
| 20 | end |
| 21 | |
| 22 | //Salida para el PWM |
| 23 | |
| 24 | assign PWM_out=(PWM_accum<PWM_in); |
| 25 | |
| 26 | endmodule |
| 27 |
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