Root/Examples/Beta1/logic/PuenteH.v

1`timescale 1ns / 1ps
2
3module PuenteH(clk, reset, enable, we, addr, IN, pwm_out, ram_read);
4
5input clk;
6input enable; //enable
7input we; //enable de escritura
8input reset; //reset
9input [10:0]addr; //Direcciones ram
10input [7:0] IN; //Data
11output [3:0] pwm_out; //Pines de salida al PWM
12output [7:0] ram_read;//Lectura desde el HBRIDGE
13reg [7:0] PWM_1=0; //PWM motor derecho
14reg [7:0] PWM_2=0; //PWM motor izquierdo
15reg [7:0] PWM_3=0; //PWM motor derecho
16reg [7:0] PWM_4=0; //PWM motor izquierdo
17reg we1=0; //Write enable
18
19    // REGISTER BANK: Write control
20    always @(negedge clk)
21    begin
22        if(reset)
23            {PWM_1, PWM_2, PWM_3, PWM_4,we1} <= 0;
24        else if(we & enable) begin
25            case (addr)
26                    0: begin PWM_1 <= IN; end
27                    1: begin PWM_2 <= IN; end
28                    2: begin PWM_3 <= IN; end
29                    3: begin PWM_4 <= IN; end
30              default: begin we1 <= 1; end
31            endcase
32        end
33        else begin
34            we1 <= 0; end
35    end
36
37    RAMB16_S9 ba0( .CLK(~clk),
38            .EN(enable),
39            .DOP(),
40            .SSR(1'b0),
41            .ADDR(addr[10:0]),
42            .WE(we1),
43            .DI(IN),
44            .DIP(1'b0),
45            .DO(ram_read));
46
47
48/* // Dual-port RAM instatiation
49    RAMB16_S9_S9 ba0(
50            .DOA(out), // Port A 8-bit Data Output
51            .DOB(PWM_ram_reg), // Port B 8-bit Data Output
52            .DOPA(), // Port A 1-bit Parity Output
53            .DOPB(), // Port B 1-bit Parity Output
54            .ADDRA(addr[10:0]), // Port A 11-bit Address Input
55            .ADDRB(1'b0), // Port B 11-bit Address Input
56            .CLKA(~clk), // Port A Clock
57            .CLKB(~clk), // Port B Clock
58            .DIA(IN), // Port A 8-bit Data Input
59            .DIB(), // Port B 8-bit Data Input
60            .DIPA(1'b0), // Port A 1-bit parity Input
61            .DIPB(1'b0), // Port-B 1-bit parity Input
62            .ENA(1'b1), // Port A RAM Enable Input
63            .ENB(1'b1), // Port B RAM Enable Input
64            .SSRA(1'b0), // Port A Synchronous Set/Reset Input
65            .SSRB(1'b0), // Port B Synchronous Set/Reset Input
66            .WEA(we1), // Port A Write Enable Input
67            .WEB(1'b0) ); // Port B Write Enable Input
68*/
69                                                                  
70PWM OUT1A (
71    .clk(clk),
72    .enable(1'b1),
73    .PWM_in(PWM_1),
74    .PWM_out(pwm_out[0])
75    );
76
77PWM OUT1B (
78    .clk(clk),
79    .enable(1'b1),
80    .PWM_in(PWM_2),
81    .PWM_out(pwm_out[1])
82    );
83
84PWM OUT2A (
85    .clk(clk),
86    .enable(1'b1),
87    .PWM_in(PWM_3),
88    .PWM_out(pwm_out[2])
89    );
90
91PWM OUT2B (
92    .clk(clk),
93    .enable(1'b1),
94    .PWM_in(PWM_4),
95    .PWM_out(pwm_out[3])
96    );
97
98endmodule
99

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