Root/Examples/Beta1/logic/bb.v

1`timescale 1ns / 1ps
2
3module pwm_FINAL(clk, reset, enable, we, PWM_in, PWM_out,buffer_addr,out);
4input clk; //Clock
5input enable; //Seal enable
6input we; //Seal enable de escritura
7input reset; //Seal reset
8input [7:0] PWM_in; //Dutycycle
9input [10:0]buffer_addr; //Direcciones ram
10output PWM_out; //Salida PWM
11output [10:0]out;
12
13reg [7:0] PWM_accum=0; //Acumulador PWM
14reg [7:0] PWM_in_reg=0; //Registro para saber cambios en registro de RAM
15//reg [7:0] PWM_in_reg2=0; //Registro para saber cambios en registro de RAM
16reg we1=0; //registro write enable?
17wire [7:0] PWM_ram_reg; //Registro que se lee desde la ram
18
19/*always @(negedge clk)//sync de addres. Por ahora lleva todo a la primera direccion
20begin
21    if(enable&we)
22     begin
23     PWM_in_reg<=PWM_in;
24     PWM_in_reg2<=PWM_in_reg;
25     end
26end
27*/
28    // REGISTER BANK: Write control
29    always @(negedge clk)
30    begin
31        /*if(reset)
32            {PWM_in_reg,we1} <= 0;
33        else */if(we & enable) begin
34            /*case (buffer_addr)
35                    0: begin PWM_in_reg<=PWM_in; end
36                    1: begin PWM_in_reg<=PWM_in; end
37                    2: begin PWM_in_reg<=PWM_in; end
38              default: begin we1 <= 1; end
39            endcase */
40                we1<=1;
41        end
42        else begin
43            we1 <= 0; end
44    end
45     
46/*always @(posedge clk)//Manejo de escritura RAM??
47begin
48// if(reset) {PWM_accum, PWM_in_reg} <= 0;
49// else if(enable)
50// begin
51// PWM_ram_reg<=PWM_in;
52// PWM_in_reg<=PWM_in;
53// end
54       if(enable)
55begin
56         case (state)
57                    0: begin
58                          PWM_in_reg<=PWM_in;
59                          state <= 1; end
60                    1: begin state <= 1; end
61              default: begin state <= 0; end
62                endcase
63end
64end
65
66*/
67always @(posedge clk)//Manejo de escritura RAM??
68begin
69    PWM_in_reg<=PWM_ram_reg;
70    if(PWM_in_reg==PWM_ram_reg) PWM_accum<=PWM_accum+1; else PWM_accum<=0;
71  //PWM_accum<=PWM_accum+1;
72end
73/*RAMB16_S9 ba0( .CLK(~clk),
74            .EN(enable),
75            .DOP(),
76            .SSR(1'b0),
77            .ADDR(buffer_addr[10:0]),
78            .WE(we1),
79            .DI(PWM_in),
80            .DIP(1'b0),
81            .DO(out));
82*/
83    // Dual-port RAM instatiation
84    RAMB16_S9_S9 ba0(
85            .DOA(out), // Port A 8-bit Data Output
86            .DOB(PWM_ram_reg), // Port B 8-bit Data Output
87            .DOPA(), // Port A 1-bit Parity Output
88            .DOPB(), // Port B 1-bit Parity Output
89            .ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
90            .ADDRB(1'b0), // Port B 11-bit Address Input
91            .CLKA(~clk), // Port A Clock
92            .CLKB(~clk), // Port B Clock
93            .DIA(PWM_in), // Port A 8-bit Data Input
94            .DIB(), // Port B 8-bit Data Input
95            .DIPA(1'b0), // Port A 1-bit parity Input
96            .DIPB(1'b0), // Port-B 1-bit parity Input
97            .ENA(1'b1), // Port A RAM Enable Input
98            .ENB(1'b1), // Port B RAM Enable Input
99            .SSRA(1'b0), // Port A Synchronous Set/Reset Input
100            .SSRB(1'b0), // Port B Synchronous Set/Reset Input
101            .WEA(we1), // Port A Write Enable Input
102            .WEB(1'b0) ); // Port B Write Enable Input
103//Salida para el PWM
104
105assign PWM_out=(PWM_accum<PWM_ram_reg);
106
107
108endmodule

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