Root/Examples/Beta1/logic/beta.v

1`timescale 1ns / 1ps
2/*module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
3                ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART, led2);
4*/
5module beta(clk, sram_data, quadA, quadB, quadC, quadD, addr, nwe, ncs, noe, reset, hbridge);
6    
7    parameter B = (7);
8
9// input clk, addr, nwe, ncs, noe, reset, ADC_EOC;
10    inout [B:0] sram_data;
11// output led, led2, ADC_CS, ADC_CSTART, ADC_SCLK;//agregado led2, quitados ODn
12// inout ADC_SDIN, ADC_SDOUT;
13input clk, addr, nwe, ncs, noe, reset;
14output [3:0] hbridge;
15input quadA,quadB, quadC, quadD;
16
17    // External conection
18    //wire led, led2;
19
20    // synchronize signals
21    reg sncs, snwe;
22    reg [12:0] buffer_addr;
23    reg [B:0] buffer_data;
24
25    // bram interfaz signals
26    reg we;
27    reg w_st=0;
28    reg [B:0] wrBus;
29    wire [B:0] rdBus;
30    
31    // interfaz fpga signals
32    wire [12:0] addr;
33    
34    // interefaz signals assignments
35    wire T = ~noe | ncs;
36    assign sram_data = T?8'bZ:rdBus;
37
38    // synchronize assignment
39    always @(negedge clk)
40    begin
41        sncs <= ncs;
42        snwe <= nwe;
43        buffer_data <= sram_data;
44        buffer_addr <= addr;
45    end
46
47    // write access cpu to bram
48    always @(posedge clk)
49    if(~reset) {w_st, we, wrBus} <= 0;
50      else begin
51        wrBus <= buffer_data;
52        case (w_st)
53          0: begin
54              we <= 0;
55              if(sncs | snwe) w_st <= 1;
56          end
57          1: begin
58            if(~(sncs | snwe)) begin
59              we <= 1;
60              w_st <= 0;
61            end
62            else we <= 0;
63          end
64        endcase
65      end
66
67    // Peripherals control
68    wire [3:0] csN;
69    wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3;
70      
71    assign csN = buffer_addr[12]? (buffer_addr[11]? 4'b1000:
72                                                    4'b0100)
73                                : (buffer_addr[11]? 4'b0010:
74                                                    4'b0001);
75
76    assign rdBus = buffer_addr[12]? (buffer_addr[11]? rdBus3:
77                                                      rdBus2)
78                                  : (buffer_addr[11]? rdBus1:
79                                                      rdBus0);
80
81
82
83     
84//assign led2=1;
85// assign led=1;
86
87    // Peripheral instantiation
88   /* ADC_peripheral P1(
89            .clk(clk),
90            .reset(~reset),
91            .cs(csN[0]),
92            .ADC_EOC(ADC_EOC),
93            .ADC_CS(ADC_CS),
94            .ADC_CSTART(ADC_CSTART),
95            .ADC_SCLK(ADC_SCLK),
96            .ADC_SDIN(ADC_SDIN),
97            .ADC_SDOUT(ADC_SDOUT),
98            .addr(buffer_addr[10:0]),
99            .rdBus(rdBus0),
100            .wrBus(wrBus),
101            .we(we));
102*/
103
104enco enco1(
105    .clk(clk),
106    .enable(csN[0]),
107    .quadA(quadA),
108    .quadB(quadB),
109    .out(rdBus0),
110    .buffer_addr(buffer_addr[10:0])
111    );
112
113enco enco2(
114    .clk(clk),
115    .enable(csN[1]),
116    .quadA(quadC),
117    .quadB(quadD),
118    .out(rdBus1),
119    .buffer_addr(buffer_addr[10:0])
120    );
121        
122PuenteH puente (
123    .clk(clk),
124    .reset(~reset),
125    .enable(csN[2]),
126    .we(we),
127    .addr(buffer_addr[10:0]),
128    .IN(wrBus),
129     .pwm_out(hbridge),
130    .ram_read(rdBus2)
131    );
132            
133    RAMB16_S9 ba0( .CLK(~clk),
134            .EN(csN[3]),
135            .DOP(),
136            .SSR(1'b0),
137            .ADDR(buffer_addr[10:0]),
138            .WE(we),
139            .DI(wrBus),
140            .DIP(1'b0),
141            .DO(rdBus3));
142              
143endmodule
144
145

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