Root/Examples/Beta1/logic/build/project_r.par

1Release 12.2 par M.63c (lin64)
2Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
3
4dellerwin:: Sun Oct 31 20:56:36 2010
5
6par -w project.ncd project_r.ncd
7
8
9Constraints file: project.pcf.
10Loading device for application Rf_Device from file '3s500e.nph' in environment /home/erwin/Xilinxs/12.2/ISE_DS/ISE/.
11   "beta" is an NCD, version 3.2, device xc3s500e, package vq100, speed -4
12
13Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
14Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
15
16INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
17   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
18   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
19   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
20   Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
21
22Device speed data version: "PRODUCTION 1.27 2010-06-22".
23
24
25Design Summary Report:
26
27 Number of External IOBs 34 out of 66 51%
28
29   Number of External Input IOBs 22
30
31      Number of External Input IBUFs 22
32        Number of LOCed External Input IBUFs 22 out of 22 100%
33
34
35   Number of External Output IOBs 4
36
37      Number of External Output IOBs 4
38        Number of LOCed External Output IOBs 4 out of 4 100%
39
40
41   Number of External Bidir IOBs 8
42
43      Number of External Bidir IOBs 8
44        Number of LOCed External Bidir IOBs 8 out of 8 100%
45
46
47   Number of BUFGMUXs 1 out of 24 4%
48   Number of RAMB16s 4 out of 20 20%
49   Number of Slices 118 out of 4656 2%
50      Number of SLICEMs 0 out of 2328 0%
51
52
53
54Overall effort level (-ol): Standard
55Placer effort level (-pl): High
56Placer cost table entry (-t): 1
57Router effort level (-rl): High
58
59Starting initial Timing Analysis. REAL time: 2 secs
60Finished initial Timing Analysis. REAL time: 2 secs
61
62
63Starting Placer
64Total REAL time at the beginning of Placer: 2 secs
65Total CPU time at the beginning of Placer: 1 secs
66
67Phase 1.1 Initial Placement Analysis
68Phase 1.1 Initial Placement Analysis (Checksum:7a263013) REAL time: 4 secs
69
70Phase 2.7 Design Feasibility Check
71Phase 2.7 Design Feasibility Check (Checksum:7a263013) REAL time: 4 secs
72
73Phase 3.31 Local Placement Optimization
74Phase 3.31 Local Placement Optimization (Checksum:7a263013) REAL time: 4 secs
75
76Phase 4.2 Initial Clock and IO Placement
77
78Phase 4.2 Initial Clock and IO Placement (Checksum:240478d) REAL time: 4 secs
79
80Phase 5.30 Global Clock Region Assignment
81Phase 5.30 Global Clock Region Assignment (Checksum:240478d) REAL time: 4 secs
82
83Phase 6.36 Local Placement Optimization
84Phase 6.36 Local Placement Optimization (Checksum:240478d) REAL time: 4 secs
85
86Phase 7.8 Global Placement
87....
88...
89.....
90Phase 7.8 Global Placement (Checksum:15c67c8c) REAL time: 11 secs
91
92Phase 8.5 Local Placement Optimization
93Phase 8.5 Local Placement Optimization (Checksum:15c67c8c) REAL time: 11 secs
94
95Phase 9.18 Placement Optimization
96Phase 9.18 Placement Optimization (Checksum:8caa3353) REAL time: 11 secs
97
98Phase 10.5 Local Placement Optimization
99Phase 10.5 Local Placement Optimization (Checksum:8caa3353) REAL time: 11 secs
100
101Total REAL time to Placer completion: 11 secs
102Total CPU time to Placer completion: 10 secs
103Writing design to file project_r.ncd
104
105
106
107Starting Router
108
109
110Phase 1 : 776 unrouted; REAL time: 17 secs
111
112Phase 2 : 652 unrouted; REAL time: 17 secs
113
114Phase 3 : 136 unrouted; REAL time: 17 secs
115
116Phase 4 : 180 unrouted; (Par is working to improve performance) REAL time: 18 secs
117
118Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 18 secs
119
120Updating file: project_r.ncd with current fully routed design.
121
122Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
123
124Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
125
126Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
127
128Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
129
130Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
131
132Total REAL time to Router completion: 21 secs
133Total CPU time to Router completion: 19 secs
134
135Partition Implementation Status
136-------------------------------
137
138  No Partitions were found in this design.
139
140-------------------------------
141
142Generating "PAR" statistics.
143
144**************************
145Generating Clock Report
146**************************
147
148+---------------------+--------------+------+------+------------+-------------+
149| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
150+---------------------+--------------+------+------+------------+-------------+
151| clk_BUFGP | BUFGMUX_X2Y1| No | 99 | 0.086 | 0.204 |
152+---------------------+--------------+------+------+------------+-------------+
153
154* Net Skew is the difference between the minimum and maximum routing
155only delays for the net. Note this is different from Clock Skew which
156is reported in TRCE timing report. Clock Skew is the difference between
157the minimum and maximum path delays which includes logic delays.
158
159Timing Score: 0 (Setup: 0, Hold: 0)
160
161Asterisk (*) preceding a constraint indicates it was not met.
162   This may be due to a setup or hold violation.
163
164----------------------------------------------------------------------------------------------------------
165  Constraint | Check | Worst Case | Best Case | Timing | Timing
166                                            | | Slack | Achievable | Errors | Score
167----------------------------------------------------------------------------------------------------------
168  Autotimespec constraint for clock net clk | SETUP | N/A| 9.105ns| N/A| 0
169  _BUFGP | HOLD | 0.968ns| | 0| 0
170----------------------------------------------------------------------------------------------------------
171
172
173All constraints were met.
174INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
175   constraint is not analyzed due to the following: No paths covered by this
176   constraint; Other constraints intersect with this constraint; or This
177   constraint was disabled by a Path Tracing Control. Please run the Timespec
178   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
179
180
181Generating Pad Report.
182
183All signals are completely routed.
184
185Total REAL time to PAR completion: 22 secs
186Total CPU time to PAR completion: 19 secs
187
188Peak Memory Usage: 357 MB
189
190Placement: Completed - No errors found.
191Routing: Completed - No errors found.
192
193Number of error messages: 0
194Number of warning messages: 0
195Number of info messages: 1
196
197Writing design to file project_r.ncd
198
199
200
201PAR done!
202

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