Root/Examples/Beta1/logic/build/project_r.twr

1--------------------------------------------------------------------------------
2Release 12.2 Trace (lin64)
3Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
4
5/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 25
6project_r.ncd project.pcf
7
8Design file: project_r.ncd
9Physical constraint file: project.pcf
10Device,package,speed: xc3s500e,vq100,-4 (PRODUCTION 1.27 2010-06-22)
11Report level: verbose report, limited to 25 items per constraint
12
13Environment Variable Effect
14-------------------- ------
15NONE No environment variables were set
16--------------------------------------------------------------------------------
17
18INFO:Timing:2698 - No timing constraints found, doing default enumeration.
19INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
20   option. All paths that are not constrained will be reported in the
21   unconstrained paths section(s) of the report.
22INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
23   a 50 Ohm transmission line loading model. For the details of this model,
24   and for more information on accounting for different loading conditions,
25   please see the device datasheet.
26INFO:Timing:3390 - This architecture does not support a default System Jitter
27   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
28   Uncertainty calculation.
29INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
30   'Phase Error' calculations, these terms will be zero in the Clock
31   Uncertainty calculation. Please make appropriate modification to
32   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
33   Error.
34
35
36
37Data Sheet report:
38-----------------
39All values displayed in nanoseconds (ns)
40
41Setup/Hold to clock clk
42------------+------------+------------+------------------+--------+
43            |Max Setup to|Max Hold to | | Clock |
44Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
45------------+------------+------------+------------------+--------+
46addr<0> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
47addr<1> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
48addr<2> | 4.652(F)| -0.775(F)|clk_BUFGP | 0.000|
49addr<3> | 4.652(F)| -0.775(F)|clk_BUFGP | 0.000|
50addr<4> | 4.648(F)| -0.771(F)|clk_BUFGP | 0.000|
51addr<5> | 4.648(F)| -0.771(F)|clk_BUFGP | 0.000|
52addr<6> | 4.650(F)| -0.772(F)|clk_BUFGP | 0.000|
53addr<7> | 4.693(F)| -0.823(F)|clk_BUFGP | 0.000|
54addr<8> | 4.693(F)| -0.823(F)|clk_BUFGP | 0.000|
55addr<9> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
56addr<10> | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
57addr<11> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
58addr<12> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
59ncs | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
60nwe | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
61quadA | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
62quadB | 4.665(R)| -0.790(R)|clk_BUFGP | 0.000|
63quadC | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
64quadD | 4.663(R)| -0.788(R)|clk_BUFGP | 0.000|
65reset | 3.336(R)| -0.369(R)|clk_BUFGP | 0.000|
66            | 4.315(F)| -0.589(F)|clk_BUFGP | 0.000|
67sram_data<0>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
68sram_data<1>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
69sram_data<2>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
70sram_data<3>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
71sram_data<4>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
72sram_data<5>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
73sram_data<6>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
74sram_data<7>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
75------------+------------+------------+------------------+--------+
76
77Clock clk to Pad
78------------+------------+------------------+--------+
79            | clk (edge) | | Clock |
80Destination | to PAD |Internal Clock(s) | Phase |
81------------+------------+------------------+--------+
82hbridge<0> | 12.564(R)|clk_BUFGP | 0.000|
83            | 12.481(F)|clk_BUFGP | 0.000|
84hbridge<1> | 12.901(R)|clk_BUFGP | 0.000|
85            | 12.921(F)|clk_BUFGP | 0.000|
86hbridge<2> | 12.713(R)|clk_BUFGP | 0.000|
87            | 12.377(F)|clk_BUFGP | 0.000|
88hbridge<3> | 13.541(R)|clk_BUFGP | 0.000|
89            | 13.383(F)|clk_BUFGP | 0.000|
90sram_data<0>| 13.296(F)|clk_BUFGP | 0.000|
91sram_data<1>| 13.038(F)|clk_BUFGP | 0.000|
92sram_data<2>| 12.986(F)|clk_BUFGP | 0.000|
93sram_data<3>| 13.246(F)|clk_BUFGP | 0.000|
94sram_data<4>| 13.147(F)|clk_BUFGP | 0.000|
95sram_data<5>| 12.926(F)|clk_BUFGP | 0.000|
96sram_data<6>| 13.450(F)|clk_BUFGP | 0.000|
97sram_data<7>| 13.381(F)|clk_BUFGP | 0.000|
98------------+------------+------------------+--------+
99
100Clock to Setup on destination clock clk
101---------------+---------+---------+---------+---------+
102               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
103Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
104---------------+---------+---------+---------+---------+
105clk | 6.132| 4.553| 3.790| 9.078|
106---------------+---------+---------+---------+---------+
107
108Pad to Pad
109---------------+---------------+---------+
110Source Pad |Destination Pad| Delay |
111---------------+---------------+---------+
112ncs |sram_data<0> | 10.289|
113ncs |sram_data<1> | 10.543|
114ncs |sram_data<2> | 10.539|
115ncs |sram_data<3> | 10.091|
116ncs |sram_data<4> | 9.970|
117ncs |sram_data<5> | 10.339|
118ncs |sram_data<6> | 9.761|
119ncs |sram_data<7> | 10.018|
120noe |sram_data<0> | 8.488|
121noe |sram_data<1> | 8.742|
122noe |sram_data<2> | 8.738|
123noe |sram_data<3> | 8.290|
124noe |sram_data<4> | 8.169|
125noe |sram_data<5> | 8.538|
126noe |sram_data<6> | 7.960|
127noe |sram_data<7> | 8.217|
128---------------+---------------+---------+
129
130
131Analysis completed Sun Oct 31 20:57:02 2010
132--------------------------------------------------------------------------------
133
134Trace Settings:
135-------------------------
136Trace Settings
137
138Peak Memory Usage: 239 MB
139
140
141
142

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