Root/Examples/Beta1/logic/build/xst/work/hdllib.ref

1MO PWM NULL ../PWM.v vlg50/_p_w_m.bin 1288576575
2MO beta NULL ../beta.v vlg5C/beta.bin 1288576575
3MO PuenteH NULL ../PuenteH.v vlg69/_puente_h.bin 1288576575
4MO enco NULL ../enco.v vlg6D/enco.bin 1288576575
5

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