Root/Examples/Beta1/logic/enco.v

1`timescale 1ns / 1ps
2
3module enco(clk, enable,quadA, quadB, out,buffer_addr);
4input clk, quadA, quadB;
5input enable;
6input [10:0]buffer_addr;
7output [7:0] out;
8
9wire [7:0] vel_dir;
10//Registros para implementar retardos, con la idea de syncronizar las seales
11reg [2:0] quadA_delayed, quadB_delayed=0;
12always @(posedge clk) quadA_delayed <= {quadA_delayed[1:0], quadA};
13always @(posedge clk) quadB_delayed <= {quadB_delayed[1:0], quadB};
14
15//Valores internos para habilitar el conteo, y determinar la direccin del mismo
16wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2];
17wire count_direction = quadA_delayed[1] ^ quadB_delayed[2];
18
19//Registro para almacenar el contador
20reg [7:0] count=0; //Pendiente cambiar este, no sabemos que dato saldr al final
21always @(posedge clk)
22begin
23  if(count_enable)
24  begin
25    if(count_direction) count<=count+1; else count<=count-1;
26  end
27end
28
29//Falta definir como vamos a comunicar esta info, es ms facil como posicin
30
31/*reg [1:0] pos_reg0=0; //Registro temporal 1
32reg [1:0] pos_reg1=0; //Registro temporal
33reg dir=0; //Direccin, 1=adelante? 0=atras?
34always @(posedge clk)
35begin
36pos_reg0<={quadB, quadA};
37pos_reg1<=pos_reg0;
38    
39    if(pos_reg1==pos_reg0) dir<=dir;
40    else if(pos_reg0==1)
41  begin
42    if(pos_reg1<pos_reg0) dir<=0; else dir<=1;
43  end
44  else if(pos_reg1==1)
45  begin
46    if(pos_reg1<pos_reg0) dir<=0; else dir<=1;
47  end
48  else
49  begin
50    if(pos_reg1<pos_reg0) dir<=1; else dir<=0;
51  end
52  
53  
54end*/
55//Fue cambiado!
56assign vel_dir={count[7:0]};
57
58    // Dual-port RAM instatiation
59    RAMB16_S9_S9 ba0(
60            .DOA(out), // Port A 8-bit Data Output
61            .DOB(), // Port B 8-bit Data Output
62            .DOPA(), // Port A 1-bit Parity Output
63            .DOPB(), // Port B 1-bit Parity Output
64            .ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
65            .ADDRB(1'b0), // Port B 11-bit Address Input
66            .CLKA(~clk), // Port A Clock
67            .CLKB(~clk), // Port B Clock
68            .DIA(), // Port A 8-bit Data Input
69            .DIB(vel_dir), // Port B 8-bit Data Input
70            .DIPA(1'b0), // Port A 1-bit parity Input
71            .DIPB(1'b0), // Port-B 1-bit parity Input
72            .ENA(1'b1), // Port A RAM Enable Input
73            .ENB(1'b1), // Port B RAM Enable Input
74            .SSRA(1'b0), // Port A Synchronous Set/Reset Input
75            .SSRB(1'b0), // Port B Synchronous Set/Reset Input
76            .WEA(1'b0), // Port A Write Enable Input
77            .WEB(enable) ); // Port B Write Enable Input
78                
79endmodule
80

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