Date:2011-12-16 09:09:43 (8 years 10 months ago)
Author:Werner Almesberger
Commit:054df9f90e3498d29b3d2a893d569187cfa9f978
Message:m1/case/: added rear panel with JTAG hole

Files: m1/case/Makefile (1 diff)
m1/case/README (1 diff)
m1/case/case.fpd (4 diffs)
m1/case/doit (4 diffs)

Change Details

m1/case/Makefile
11SPOOL=/home/moko/svn.openmoko.org/developers/werner/cncmap/spool/spool
2CNGT=/home/qi/cae-tools/cngt/cngt
23
3BOARD=X0=5.0mm Y0=0.0mm Z0=-56.0mm BOARD_Z=4mm
4Z0=-55.0
5BOARD=X0=5.0mm Y0=0.0mm Z0=$(Z0)mm BOARD_Z=4.5mm
6TASK=Y=1
47
5.PHONY: all mill clean
8.PHONY: all front rear cng clean
69
7all: mill.rml
10all: front.rml rear.rml
811
9case.gp: case.fpd
10        fped -g $<
12front.gp: case.fpd
13        fped -g -1 M1-front $< $@
1114
12mill.rml: case.gp
13        ./doit $(BOARD) CLEARANCE=5mm || { rm -f $@; exit 1; }
15rear.gp: case.fpd
16        fped -g -1 M1-rear $< $@
1417
15mill: mill.rml
16        PORT=/dev/ttyUSB0 $(SPOOL) mill.rml
18%.rml: %.gp
19        ./doit `basename $< .gp` $(BOARD) $(TASK) CLEARANCE=5mm || \
20            { rm -f $@; exit 1; }
21
22front: front.rml
23        PORT=/dev/ttyUSB0 $(SPOOL) $<
24
25rear: rear.rml
26        PORT=/dev/ttyUSB0 $(SPOOL) $<
27
28cng: front.gp
29        $(CNGT) $(Z0) 20 front.gp
1730
1831clean:
19        rm -f case.gp mill.gp mill.rml
32        rm -f front.gp _front.gp front.rml
33        rm -f rear.gp _rear.gp rear.rml
m1/case/README
1Reengineered M1 case parts
2==========================
3
4case.fpd contains an fped-based design of the front and rear panel.
5The geometry is based on
6http://projects.qi-hardware.com/index.php/p/m1/source/tree/master/cad/protocase_v7_laser.dxf
7by Joachim Steiger.
8
9This design is fully parametrized and contains the following changes:
10
11- the holes for the USB sockets are raised by 1.4 mm, for the M1pre-rc4
12  prototype (parameter Iusby):
13  http://en.qi-hardware.com/wiki/File:M1pre-rc4-u-A022.JPG
14
15- additional hole in the rear panel for a mini-USB cable going to
16  the JTAG board (parameters Idbgx and Idbgy, with frame "debug")
17
18Known issues:
19
20- button holes are a bit too tight
21
22- DC connector hole is too tight on all sides
m1/case/case.fpd
5858    line . __19 w
5959}
6060
61frame usb {
62    set Wusb = 8.5mm
61frame debug {
62    table
63        { Wdbg, Hdbg }
64        { 14.5mm, 9.5mm }
6365
64    set Husb = 15.5mm
66    __0: vec @(Wdbg, Hdbg)
67    rect @ . w
68}
69
70frame dc {
71    table
72        { Wdc, Hdc }
73        { 9.4mm, 11.4mm }
74
75    __0: vec @(-Wdc, Hdc)
76    rect @ . w
77}
78
79frame ether {
80    table
81        { Weth, Heth }
82        { 16.5mm, 14mm }
83
84    __0: vec @(Weth, Heth)
85    rect @ . w
86}
87
88frame rgb {
89    set Rrgb = 6.3mm
90
91    __0: vec @(0mm, Rrgb)
92    circ @ . w
93}
94
95frame rear {
96    table
97        { Irgbx, Irgby, Drgb }
98        { 25.5mm, 14.5mm, 15mm }
99
100    table
101        { Iethx, Iethy }
102        { 67mm, 7mm }
103
104    table
105        { Idcx, Idcy }
106        { 14.8mm, 6.6mm }
107
108    table
109        { Idbgx, Idbgy }
110        { 88.1mm, 14.5mm }
111
112    loop if = 1, rear
113
114    __0: vec @(Irgbx, Irgby)
115    frame rgb .
116    __1: vec .(Drgb, 0mm)
117    frame rgb .
118    __2: vec .(Drgb, 0mm)
119    frame rgb .
120    __3: vec @(Iethx, Iethy)
121    frame ether .
122    __4: vec @(Ws, 0mm)
123    __5: vec .(-Idcx, Idcy)
124    frame dc .
125    __6: vec @(Idbgx, Idbgy)
126    frame debug .
127    frame short @
128}
129
130frame usb {
131    table
132        { Wusb, Husb }
133        { 8.5mm, 15.5mm }
65134
66135    __0: vec @(-Wusb, Husb)
67136    rect . @ w
...... 
81150
82151    table
83152        { Iusbx, Iusby, Dusb }
84        { 18.5mm, 6.5mm+1.3mm, 12.5mm }
153        { 18.5mm, 6.5mm+1.4mm, 12.5mm }
154
155    loop if = 1, front
85156
86157    __0: vec @(Ibutx, Ibuty)
87158    frame but .
...... 
97168    frame short @
98169}
99170
100package "M1"
171package "M1-$part"
101172unit mm
102173
103174table
...... 
110181    { H, Ws }
111182    { 36.5mm, 2*(Iox+Lox+Iix)+Lix }
112183
184table
185    { part, front, rear }
186    { "front", 1, 0 }
187    { "rear", 0, 1 }
188
113189frame front @
190frame rear @
m1/case/doit
1414# CLEARANCE tool clearance above PCB surface, default: 2mm
1515#
1616
17NAME=$1
18shift
19
1720while [ "$1" ]; do
1821    eval "$1"
1922    shift
...... 
3437
3538    cat <<EOF >_job
3639mm
37gnuplot $MILL case.gp
40gnuplot $MILL $NAME.gp
3841
3942align 1 $X0 $Y0 # align relative to board corner
4043translate 4mm 4mm # move to PCB zone assigned to project
...... 
4245z 0 $Z0 # board surface (tool fully retracted)
4346z -$BOARD_Z # board thickness
4447
45write merged.gp
4648offset
47write mill.gp
49write _$NAME.gp
4850EOF
4951
5052    cameo _job || exit
...... 
5658    yi=`expr $yi + 1`
5759done
5860
59gp2rml $CLEARANCE 10 10 mill.gp >mill.rml || exit
61gp2rml $CLEARANCE 10 10 _$NAME.gp >$NAME.rml || exit

Archive Download the corresponding diff file

Branches:
master



interactive