Werner's Miscellanea
Sign in or create your account | Project List | Help
Werner's Miscellanea Git Source Tree
Root/
Source at commit 054df9f90e3498d29b3d2a893d569187cfa9f978 created 12 years 3 months ago. By Werner Almesberger, m1/case/: added rear panel with JTAG hole | |
---|---|
1 | #!/bin/sh |
2 | PATH=$PATH:/home/qi/cae-tools/cameo |
3 | PATH=$PATH:/home/qi/cae-tools/gp2rml |
4 | |
5 | # |
6 | # Parameters: |
7 | # |
8 | # X0, Y0 lower left corner of raw board, default: 0mm 0mm |
9 | # Z0 position at which tool tip touches the piece's surface |
10 | # X, Y position in array, default: 0 0 |
11 | # XN, YN number of boards in X/Y direction, default: 1 1 |
12 | # MILL diameter of mill, default: 35mil |
13 | # BOARD_Z board tickness, default: 0.8 mm |
14 | # CLEARANCE tool clearance above PCB surface, default: 2mm |
15 | # |
16 | |
17 | NAME=$1 |
18 | shift |
19 | |
20 | while [ "$1" ]; do |
21 | eval "$1" |
22 | shift |
23 | done |
24 | |
25 | : ${X0:=0} ${Y0:=0} ${Z0:=0} |
26 | : ${X:=0} ${Y:=0} |
27 | : ${XN:=1} ${YN:=1} |
28 | : ${MILL:=35mil} |
29 | : ${BOARD_Z:=0.8mm} |
30 | : ${CLEARANCE:=2mm} |
31 | |
32 | write=write |
33 | yi=0 |
34 | while [ $yi -lt $YN ]; do |
35 | xi=0 |
36 | while [ $xi -lt $XN ]; do |
37 | |
38 | cat <<EOF >_job |
39 | mm |
40 | gnuplot $MILL $NAME.gp |
41 | |
42 | align 1 $X0 $Y0 # align relative to board corner |
43 | translate 4mm 4mm # move to PCB zone assigned to project |
44 | array +3mm +3mm `expr $X + $xi` `expr $Y + $yi` |
45 | z 0 $Z0 # board surface (tool fully retracted) |
46 | z -$BOARD_Z # board thickness |
47 | |
48 | offset |
49 | write _$NAME.gp |
50 | EOF |
51 | |
52 | cameo _job || exit |
53 | rm -f _job |
54 | |
55 | write=append |
56 | xi=`expr $xi + 1` |
57 | done |
58 | yi=`expr $yi + 1` |
59 | done |
60 | |
61 | gp2rml $CLEARANCE 10 10 _$NAME.gp >$NAME.rml || exit |
62 |
Branches:
master