Werner's Miscellanea
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Source at commit 1d4b89ec4f453cbdfdff8667b16b634fe0be251f created 12 years 6 months ago. By Werner Almesberger, labsw/mech/font.fpd: increased banana jack hole from 6 mm to 8 mm | |
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1 | --- Thu 2011-09-01 ------------------------------------------------------------ |
2 | |
3 | PCB milling #1: |
4 | - setup: |
5 | - board is pertinax |
6 | - locally sourced "W.T." (Taiwan) mounting tape |
7 | - measurements: |
8 | - board: 101.6 mm x 44.6 mm (nom. 102.0 mm x 50.0 mm) |
9 | - defects found: |
10 | - drill broke on first hole, due to insufficient clearance found in |
11 | run #2. Second drill just cleared the board by sheer luck. |
12 | - drill/mill depth too shallow |
13 | - column cavities too wide |
14 | - changes for next run: |
15 | - narrow column cavities from 8.4 mm to 8.0 mm (bad idea, see below) |
16 | |
17 | PCB milling #2; |
18 | - changes made: |
19 | - board is FR4 |
20 | - corrected depth |
21 | - defects found: |
22 | - clearance insufficient (top copper damaged; endmill broke) |
23 | - changes for next run: |
24 | - increase clearance by 1 mm |
25 | - future: include board thickness in gp2rml clearance calculation |
26 | (gp2rml calculates "clearance" from the highest point in the plot, |
27 | which for PCBs also happens to be the lowest point, and thus |
28 | includes the board itself and the vertical overshoot. 2 mm are |
29 | sufficient for 0.8 mm boards, but 1.6 mm boards need at least |
30 | 0.8 mm more.) |
31 | |
32 | PCB milling #3: |
33 | - changes made: |
34 | - corrected clearance |
35 | - Tesa 5767 mounting tape |
36 | - measurements: |
37 | - column cavity: ~7.6 mm x 10.3 mm (nom. 8.0 x 10.4 mm) |
38 | - board: 102.2 mm x 50.2 mm (nom. 102.0 mm x 50.0 mm) |
39 | - "narrow tongue": 9.1 mm (nom. 9.0 mm) |
40 | - "wide tongue": 14.1 mm (nom. 14.0 mm) |
41 | - defects found: |
42 | - column cavities too narrow (also in design; need 8.4 mm) |
43 | - 100 mil header holes a little bit too small |
44 | - 200 mil header holes much too small |
45 | - rear edge touches wall |
46 | - front edge very close to buttons (not sure how close) |
47 | - changes for next run: |
48 | - widen column cavities by 0.2 mm on each side |
49 | - compensate tool for 0.1 mm of board deflection on each side |
50 | |
51 | --- Fri 2011-09-02 ------------------------------------------------------------ |
52 | |
53 | Layout printed on #3: |
54 | - infrastructure: |
55 | - tried new approach of transferring both sides: instead of stapling |
56 | the two sheets, put adhesive tape around the edges. The result is |
57 | acceptable, but not as good as the work-intensive one side at a time |
58 | approach used for ben-wpan. |
59 | - battery pack for laminator control broke down mechanically. Replaced |
60 | with adapter for obscure 500 mil pack I had laying around. |
61 | - problems found: |
62 | - "make it look like an accident" isn't such a good idea for the trace |
63 | connecting the relays to 5V. I was tempted to scratch off the toner, |
64 | thinking the pin had bled into the trace. |
65 | - annulus around DIP pins seems too small for 35 mil holes. The holes |
66 | are nominally only 0.5 mm, but that in turn may make them too small. |
67 | - changes for next run: |
68 | - make 5V relay traces go clearly for the centers of the respective pins |
69 | - determine correct hole size for DIP |
70 | |
71 | --- Sat 2011-09-03 ------------------------------------------------------------ |
72 | |
73 | Soldered #3: |
74 | - problems found: |
75 | - DIP copper rings were too small for easy soldering, as expected |
76 | - cosmetic: screw-down headers (K1, K2) are very loose and end up |
77 | visibly angled |
78 | - cosmetic: vias between OUT opto-couplers are a bit close to the |
79 | sockets, making them almost disappear under them. Would be nicer if |
80 | they had more clearance. |
81 | - MCU and DIP sockets should have orientation markings on the copper |
82 | layer. In other news, Chip Quick is quite suitable for removing a |
83 | misplaced 32-LQFP. |
84 | - the footprints of the 1 W resistors (R7-R10) are way too short. |
85 | Placed 0805 instead. |
86 | |
87 | (next run) |
88 | - changes made |
89 | - made 5V relay traces go clearly for the centers of the respective pins |
90 | - changed DIP hole size from 0.5 mm to 0.8 mm, hole-to-copper ratio from |
91 | 2.5 to 2 |
92 | |
93 | Pending: |
94 | - widen column cavities by 0.2 mm on each side |
95 | - consider pulling in front edge a little in buttons area |
96 | - uncopper mounting holes (using "loop" as "if" in fped) |
97 | - change mill nominal diameter from 35 mil to 26-27 mil |
98 | - move vias between OUT opto-couplers 0.2 mm to the center |
99 | - add orientation markings on copper layer for MCU and DIP sockets |
100 | - verify 2512 footprint of 1 W resistors |
101 | - add ground zones |
102 |
Branches:
master