Root/labsw/LOG

Source at commit 761eae16bdfe2f97e34a927fd8fd9d14a9a18cc2 created 8 years 9 days ago.
By Werner Almesberger, labsw/: added hardware revision indication
1--- Thu 2011-09-01 ------------------------------------------------------------
2
3PCB milling #1:
4- setup:
5  - board is pertinax
6  - locally sourced "W.T." (Taiwan) mounting tape
7- measurements:
8  - board: 101.6 mm x 44.6 mm (nom. 102.0 mm x 50.0 mm)
9- defects found:
10  - drill broke on first hole, due to insufficient clearance found in
11    run #2. Second drill just cleared the board by sheer luck.
12  - drill/mill depth too shallow
13  - column cavities too wide
14- changes for next run:
15  - narrow column cavities from 8.4 mm to 8.0 mm (bad idea, see below)
16
17PCB milling #2;
18- changes made:
19  - board is FR4
20  - corrected depth
21- defects found:
22  - clearance insufficient (top copper damaged; endmill broke)
23- changes for next run:
24  - increase clearance by 1 mm
25  - future: include board thickness in gp2rml clearance calculation
26    (gp2rml calculates "clearance" from the highest point in the plot,
27   which for PCBs also happens to be the lowest point, and thus
28   includes the board itself and the vertical overshoot. 2 mm are
29   sufficient for 0.8 mm boards, but 1.6 mm boards need at least
30   0.8 mm more.)
31   
32PCB milling #3:
33- changes made:
34  - corrected clearance
35  - Tesa 5767 mounting tape (no longer available)
36- measurements:
37  - column cavity: ~7.6 mm x 10.3 mm (nom. 8.0 x 10.4 mm)
38  - board: 102.2 mm x 50.2 mm (nom. 102.0 mm x 50.0 mm)
39  - "narrow tongue": 9.1 mm (nom. 9.0 mm)
40  - "wide tongue": 14.1 mm (nom. 14.0 mm)
41- defects found:
42  - column cavities too narrow (also in design; need 8.4 mm)
43  - 100 mil header holes a little bit too small
44  - 200 mil header holes much too small
45  - rear edge touches wall
46  - front edge very close to buttons (not sure how close)
47- changes for next run:
48  - widen column cavities by 0.2 mm on each side
49  - compensate tool for 0.1 mm of board deflection on each side
50
51--- Fri 2011-09-02 ------------------------------------------------------------
52
53Layout printed on #3:
54- infrastructure:
55  - tried new approach of transferring both sides: instead of stapling
56    the two sheets, put adhesive tape around the edges. The result is
57    acceptable, but not as good as the work-intensive one side at a time
58    approach used for ben-wpan.
59  - battery pack for laminator control broke down mechanically. Replaced
60    with adapter for obscure 500 mil pack I had laying around.
61- problems found:
62  - "make it look like an accident" isn't such a good idea for the trace
63    connecting the relays to 5V. I was tempted to scratch off the toner,
64    thinking the pin had bled into the trace.
65  - annulus around DIP pins seems too small for 35 mil holes. The holes
66    are nominally only 0.5 mm, but that in turn may make them too small.
67- changes for next run:
68  - make 5V relay traces go clearly for the centers of the respective pins
69  - determine correct hole size for DIP
70
71--- Sat 2011-09-03 ------------------------------------------------------------
72
73Soldered #3:
74- problems found:
75  - DIP copper rings were too small for easy soldering, as expected
76  - cosmetic: screw-down headers (K1, K2) are very loose and end up
77    visibly angled
78  - cosmetic: vias between OUT opto-couplers are a bit close to the
79    sockets, making them almost disappear under them. Would be nicer if
80    they had more clearance.
81  - MCU and DIP sockets should have orientation markings on the copper
82    layer. In other news, Chip Quick is quite suitable for removing a
83    misplaced 32-LQFP.
84  - the footprints of the 1 W resistors (R7-R10) are way too short.
85    Placed 0805 instead.
86
87--- Sun 2011-09-04 ------------------------------------------------------------
88
89Milled face plate #0:
90- setup:
91  - board is pertinax
92  - locally sourced "W.T." (Taiwan) mounting tape
93- measurements:
94  - board: 104.0-104.1 mm x 35.1-35.6 mm (nom. 104.0 mm x 35.0 mm)
95  - button hole: 12.6-12.8 mm x 11.3-11.6 mm (nom. 12.6 x 11.3 mm)
96- defects found:
97  - engraving depth (0.2 mm) is a bit shallow, probably due to board
98    curvature
99  - got the banana jack diameter wrong: should be 8 mm, not 6 mm
100  - button holes show significant deviation from tool path on lower
101    edge
102- changes for next run:
103  - increase engraving depth to 0.5 mm (board is 1.6 mm)
104  - correct banana jack hole diameter
105
106Milled face plate #1:
107- changes made:
108  - increased engraving depth to 0.5 mm
109  - increased banana jack hole diameter to 8.0 mm
110- defects found:
111  - job didn't complete because board became unstuck while milling
112  - the 8.0 mm hole is still a bit too tight if jack sleeve is at
113    upper end of tolerance range
114  - noticed that the button holes are milled last, after cutting the
115    board outline. This explains the poor accuracy.
116
117--- Mon 2011-09-05 ------------------------------------------------------------
118
119Milled face plate #2:
120- changes made:
121  - board is unclad FR4
122  - added a bit more adhesive tape
123  - increased banana jack hole diameter from 8.0 mm to 8.1 mm, to
124    accommodate also jacks that are at the upper end of the tolerance
125    range
126  - corrected order of tool paths issues by cameo
127- measurements:
128  - board: 104.1-104.2 mm x 35.1 mm (nom. 104.0 mm x 35.0 mm)
129  - button hole: 12.5-12.6 mm x 11.3-11.4 mm (nom. 12.6 x 11.3 mm)
130- defects found:
131  - tight horizontal fit in the case
132  - LED holder have considerable play and retainer rings are loose to
133    the point of being useless
134  - adhesive tape now sticks almost too well :-) (it was hard to pry
135    the board loose after milling)
136
137Milled face plate #3:
138- changes made:
139  - reduced board width from 104.0 mm to 103.6 mm
140  - reduced LED hole from 6.9 mm to 6.2 mm
141- problems encountered:
142  - raw board wasn't quite large enough for the entire face plate, but
143    it seems I missed it by only < 0.1 mm.
144  - depth was too shallow, at the cost of the logo
145- measurements:
146  - board: 103.8 mm x 35.1 mm (nom. 103.6 mm x 35.0 mm)
147- defects found:
148  - LED holder works better but is still a bit wobbly
149  - (EE issue) there's a bit of current from 5 V through the opt-coupler
150    LEDs to the pull-ups. Work-around: add 10 kOhm in parallel to each
151    LED.
152
153--- Wed 2011-09-07 ------------------------------------------------------------
154
155Rework:
156- problem: labsw occasionally (around 1% of all cycles in an automated
157  test loop) gets some configuration bits wrong. The pattern observed
158  so far is that, in an attempt to turn on CH1, then CH2, CH1 comes on
159  normally while CH2 either doesn't come on at all or the relay switches
160  but the LED doesn't.
161- analysis:
162  This may be a problem with the power supply or with USB. Consider
163  some or all of the following improvements:
164
165  - follow SiLab's recommendations for regulator bypassing more closely
166  - enable the VDD monitor to catch brown-outs
167  - add ground areas to shield CPU and USB
168  - add redundancy to EP0 protocol
169  - add bead to relay power, to prevent upsetting the 5 V rail
170- rework:
171  Implemented power supply bypassing according to SiLabs' recommendations:
172  - added 4.7 uF in parallel to C1
173  - added 100 nF in parallel to C2
174- results:
175  A test run initially showed about 10% abnormal cycles. Detailed
176  observation, starting with first anomaly:
177
178  - turn-on cycle: CH2 LED green, M1 not powered (CH2 fully off ?)
179  - 21 normal cycles
180  - turn-on cycle: all LEDs green, no power (LEDs didn't go dark as they
181    would in DFU wait, so the MCU didn't reset)
182  - 8 normal cycles
183  - turn-on cycle: MAIN and CH2 LED green, M1 not powered
184  - 31 normal cycles
185  - turn-on cycle: all LEDs green, no power (not a reset)
186  - 12 normal cycles
187  - turn-on cycle: all LEDs green, no power (not a reset)
188  - 3 normal cycles
189  - turn-on cycle: all LEDs green, no power (not a reset)
190  - 3 normal cycles
191  - turn-on cycle: all LEDs green, no power (not a reset)
192  - 3 normal cycles
193  - turn-on cycle: all LEDs green, no power (not a reset)
194  - 68 normal cycles
195  - turn-on cycle: all LEDs green, no power (not a reset)
196  - 5+ normal cycles
197
198Further analysis: the absence of more abnormal states, such as LEDs
199contradicting relays or LEDs just going dark suggests that the problem
200is may not be USB data corruption. At least some of the symptoms would
201be compatible with EMI from switching the relay creating false signals
202on the buttons.
203
204The "all LEDs green" condition would be a false press of MAIN. The
205CH2 green condition would be harder to explain. Maybe the MAIN LED
206was also green and I didn't notice. In this case, it would have been
207a combination of the MAIN and CH1 buttons (MAIN to exit remote mode,
208turn off all the channels, and enable the channel buttons. Then CH1 to
209turn on CH1 again.)
210
211To do: debounce buttons (in software) before accepting a state change.
212
213---------------------
214
215(next PCB run)
216- changes made:
217  - made 5V relay traces go clearly for the centers of the respective pins
218  - changed DIP hole size from 0.5 mm to 0.8 mm, hole-to-copper ratio from
219    2.5 to 2
220  - bypass VBUS and VDD with 4.7 uF and 100 nF each
221  - added external pull-ups to IN_* and to buttons (so that we can turn
222    off the internal pull-ups and thus avoid sneak current through the
223    opto-coupler LEDs from VBUS via the pull-ups into VDD)
224  - added low-pass filters to button inputs, to suppress interferences,
225    e.g., from load being switched (with help from Joerg Reisenweber)
226  - added hardware revision ID pins
227
228Pending:
229- widen column cavities by 0.2 mm on each side
230- consider pulling in front edge a little in buttons area
231- uncopper mounting holes (using "loop" as "if" in fped)
232- change mill nominal diameter from 35 mil to 26-27 mil
233- move vias between OUT opto-couplers 0.2 mm to the center
234- add orientation markings on copper layer for MCU and DIP sockets
235- verify 2512 footprint of 1 W resistors
236- add ground zones
237- firmware: disable internal pull-ups
238

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