Root/m1/patches/rtems/milkymist-new-uart.patch

Source at commit f6fd776f528905e346c7f1caec97945535c7ca43 created 8 years 4 months ago.
By Werner Almesberger, m1/patches/rtems/: Milkymist-specific patches are in upstream (update by Xiangfu)
1Index: rtems/c/src/lib/libbsp/lm32/milkymist/include/system_conf.h
2===================================================================
3--- rtems.orig/c/src/lib/libbsp/lm32/milkymist/include/system_conf.h 2011-08-01 10:48:11.000000000 -0300
4+++ rtems/c/src/lib/libbsp/lm32/milkymist/include/system_conf.h 2011-11-20 16:02:10.000000000 -0300
5@@ -26,6 +26,16 @@
6 /* UART */
7 #define MM_UART_RXTX (0xe0000000)
8 #define MM_UART_DIV (0xe0000004)
9+#define MM_UART_STAT (0xe0000008)
10+#define MM_UART_CTRL (0xe000000c)
11+
12+#define UART_STAT_THRE (0x1)
13+#define UART_STAT_RX_EVT (0x2)
14+#define UART_STAT_TX_EVT (0x4)
15+
16+#define UART_CTRL_RX_INT (0x1)
17+#define UART_CTRL_TX_INT (0x2)
18+#define UART_CTRL_THRU (0x4)
19 
20 /* Timers */
21 #define MM_TIMER1_COMPARE (0xe0001024)
22@@ -225,8 +235,17 @@
23 
24 /* MIDI */
25 #define MM_MIDI_RXTX (0xe000b000)
26-#define MM_MIDI_DIVISOR (0xe000b004)
27-#define MM_MIDI_THRU (0xe000b008)
28+#define MM_MIDI_DIV (0xe000b004)
29+#define MM_MIDI_STAT (0xe000b008)
30+#define MM_MIDI_CTRL (0xe000b00c)
31+
32+#define MIDI_STAT_THRE (0x1)
33+#define MIDI_STAT_RX_EVT (0x2)
34+#define MIDI_STAT_TX_EVT (0x4)
35+
36+#define MIDI_CTRL_RX_INT (0x1)
37+#define MIDI_CTRL_TX_INT (0x2)
38+#define MIDI_CTRL_THRU (0x4)
39 
40 /* IR */
41 #define MM_IR_RX (0xe000e000)
42@@ -248,24 +267,22 @@
43 #define BT656_FILTER_INFRAME (0x4)
44 
45 /* Interrupts */
46-#define MM_IRQ_UARTRX (0)
47-#define MM_IRQ_UARTTX (1)
48-#define MM_IRQ_GPIO (2)
49-#define MM_IRQ_TIMER0 (3)
50-#define MM_IRQ_TIMER1 (4)
51-#define MM_IRQ_AC97CRREQUEST (5)
52-#define MM_IRQ_AC97CRREPLY (6)
53-#define MM_IRQ_AC97DMAR (7)
54-#define MM_IRQ_AC97DMAW (8)
55-#define MM_IRQ_PFPU (9)
56-#define MM_IRQ_TMU (10)
57-#define MM_IRQ_ETHRX (11)
58-#define MM_IRQ_ETHTX (12)
59-#define MM_IRQ_VIDEOIN (13)
60-#define MM_IRQ_MIDIRX (14)
61-#define MM_IRQ_MIDITX (15)
62-#define MM_IRQ_IR (16)
63-#define MM_IRQ_USB (17)
64+#define MM_IRQ_UART (0)
65+#define MM_IRQ_GPIO (1)
66+#define MM_IRQ_TIMER0 (2)
67+#define MM_IRQ_TIMER1 (3)
68+#define MM_IRQ_AC97CRREQUEST (4)
69+#define MM_IRQ_AC97CRREPLY (5)
70+#define MM_IRQ_AC97DMAR (6)
71+#define MM_IRQ_AC97DMAW (7)
72+#define MM_IRQ_PFPU (8)
73+#define MM_IRQ_TMU (9)
74+#define MM_IRQ_ETHRX (10)
75+#define MM_IRQ_ETHTX (11)
76+#define MM_IRQ_VIDEOIN (12)
77+#define MM_IRQ_MIDI (13)
78+#define MM_IRQ_IR (14)
79+#define MM_IRQ_USB (15)
80 
81 /* Flash layout */
82 #define FLASH_BASE (0x80000000)
83Index: rtems/c/src/lib/libbsp/lm32/shared/milkymist_console/console.c
84===================================================================
85--- rtems.orig/c/src/lib/libbsp/lm32/shared/milkymist_console/console.c 2011-08-01 10:48:39.000000000 -0300
86+++ rtems/c/src/lib/libbsp/lm32/shared/milkymist_console/console.c 2011-11-20 16:02:10.000000000 -0300
87@@ -119,25 +119,24 @@
88   rtems_interrupt_level level;
89 
90   rtems_interrupt_disable(level);
91- BSP_uart_txbusy = true;
92   MM_WRITE(MM_UART_RXTX, *buf);
93   rtems_interrupt_enable(level);
94   return 0;
95 }
96 
97-static rtems_isr mmconsole_txdone(rtems_vector_number n)
98-{
99- BSP_uart_txbusy = false;
100- lm32_interrupt_ack(1 << MM_IRQ_UARTTX);
101- rtems_termios_dequeue_characters(tty, 1);
102-}
103-
104-static rtems_isr mmconsole_rxdone(rtems_vector_number n)
105+static rtems_isr mmconsole_interrupt(rtems_vector_number n)
106 {
107   char c;
108- c = MM_READ(MM_UART_RXTX);
109- lm32_interrupt_ack(1 << MM_IRQ_UARTRX);
110- rtems_termios_enqueue_raw_characters(tty, &c, 1);
111+ while (MM_READ(MM_UART_STAT) & UART_STAT_RX_EVT) {
112+ c = MM_READ(MM_UART_RXTX);
113+ MM_WRITE(MM_UART_STAT, UART_STAT_RX_EVT);
114+ rtems_termios_enqueue_raw_characters(tty, &c, 1);
115+ }
116+ if (MM_READ(MM_UART_STAT) & UART_STAT_TX_EVT) {
117+ MM_WRITE(MM_UART_STAT, UART_STAT_TX_EVT);
118+ rtems_termios_dequeue_characters(tty, 1);
119+ }
120+ lm32_interrupt_ack(1 << MM_IRQ_UART);
121 }
122 
123 static const rtems_termios_callbacks mmconsole_callbacks = {
124@@ -166,10 +165,9 @@
125   if (status != RTEMS_SUCCESSFUL)
126     rtems_fatal_error_occurred(status);
127 
128- rtems_interrupt_catch(mmconsole_txdone, MM_IRQ_UARTTX, &dummy);
129- rtems_interrupt_catch(mmconsole_rxdone, MM_IRQ_UARTRX, &dummy);
130- bsp_interrupt_vector_enable(MM_IRQ_UARTTX);
131- bsp_interrupt_vector_enable(MM_IRQ_UARTRX);
132+ rtems_interrupt_catch(mmconsole_interrupt, MM_IRQ_UART, &dummy);
133+ bsp_interrupt_vector_enable(MM_IRQ_UART);
134+ MM_WRITE(MM_UART_CTRL, UART_CTRL_RX_INT|UART_CTRL_TX_INT);
135 
136   return RTEMS_SUCCESSFUL;
137 }
138Index: rtems/c/src/lib/libbsp/lm32/shared/milkymist_console/uart.c
139===================================================================
140--- rtems.orig/c/src/lib/libbsp/lm32/shared/milkymist_console/uart.c 2011-08-01 10:48:39.000000000 -0300
141+++ rtems/c/src/lib/libbsp/lm32/shared/milkymist_console/uart.c 2011-11-20 16:02:10.000000000 -0300
142@@ -17,8 +17,6 @@
143 #include "../include/system_conf.h"
144 #include "uart.h"
145 
146-bool BSP_uart_txbusy;
147-
148 void BSP_uart_init(int baud)
149 {
150   MM_WRITE(MM_UART_DIV, CPU_FREQUENCY/baud/16);
151@@ -26,40 +24,24 @@
152 
153 void BSP_uart_polled_write(char ch)
154 {
155- int ip;
156   rtems_interrupt_level level;
157 
158   rtems_interrupt_disable(level);
159- if (BSP_uart_txbusy) {
160- /* wait for the end of the transmission by the IRQ-based driver */
161- do {
162- lm32_read_interrupts(ip);
163- } while (!(ip & (1 << MM_IRQ_UARTTX)));
164- lm32_interrupt_ack(1 << MM_IRQ_UARTTX);
165- }
166+ while(!(MM_READ(MM_UART_STAT) & UART_STAT_THRE));
167   MM_WRITE(MM_UART_RXTX, ch);
168- do {
169- lm32_read_interrupts(ip);
170- } while (!(ip & (1 << MM_IRQ_UARTTX)));
171- /* if TX was busy, do not ack the IRQ
172- * so that the IRQ-based driver ISR is run */
173- if (!BSP_uart_txbusy)
174- lm32_interrupt_ack(1 << MM_IRQ_UARTTX);
175+ while(!(MM_READ(MM_UART_STAT) & UART_STAT_THRE));
176   rtems_interrupt_enable(level);
177 }
178 
179 int BSP_uart_polled_read(void)
180 {
181- int ip;
182   char r;
183   rtems_interrupt_level level;
184 
185   rtems_interrupt_disable(level);
186- do {
187- lm32_read_interrupts(ip);
188- } while (!(ip & (1 << MM_IRQ_UARTRX)));
189- lm32_interrupt_ack(1 << MM_IRQ_UARTRX);
190+ while(!(MM_READ(MM_UART_STAT) & UART_STAT_RX_EVT));
191   r = MM_READ(MM_UART_RXTX);
192+ MM_WRITE(MM_UART_STAT, UART_STAT_RX_EVT);
193   rtems_interrupt_enable(level);
194 
195   return r;
196Index: rtems/c/src/lib/libbsp/lm32/shared/milkymist_console/uart.h
197===================================================================
198--- rtems.orig/c/src/lib/libbsp/lm32/shared/milkymist_console/uart.h 2011-08-01 10:48:39.000000000 -0300
199+++ rtems/c/src/lib/libbsp/lm32/shared/milkymist_console/uart.h 2011-11-20 16:02:10.000000000 -0300
200@@ -1,21 +1,16 @@
201 /*
202- * This file contains definitions for LatticeMico32 UART
203+ * This file contains definitions for the Milkymist UART
204  *
205  * The license and distribution terms for this file may be
206  * found in the file LICENSE in this distribution or at
207  * http://www.rtems.com/license/LICENSE.
208  *
209  * $Id: uart.h,v 1.2 2011/08/01 13:48:39 joel Exp $
210- *
211- * COPYRIGHT (c) Yann Sionneau <yann.sionneau@telecom-sudparis.eu> (GSoC 2010)
212- * Telecom SudParis
213  */
214 
215 #ifndef _BSPUART_H
216 #define _BSPUART_H
217 
218-extern bool BSP_uart_txbusy;
219-
220 void BSP_uart_init(int baud);
221 void BSP_uart_polled_write(char ch);
222 int BSP_uart_polled_read(void);
223Index: rtems/c/src/lib/libbsp/lm32/shared/milkymist_midi/midi.c
224===================================================================
225--- rtems.orig/c/src/lib/libbsp/lm32/shared/milkymist_midi/midi.c 2011-08-01 10:48:40.000000000 -0300
226+++ rtems/c/src/lib/libbsp/lm32/shared/milkymist_midi/midi.c 2011-11-20 16:02:10.000000000 -0300
227@@ -31,9 +31,12 @@
228 {
229   unsigned char msg;
230 
231- lm32_interrupt_ack(1 << MM_IRQ_MIDIRX);
232- msg = MM_READ(MM_MIDI_RXTX);
233- rtems_message_queue_send(midi_q, &msg, 1);
234+ while (MM_READ(MM_MIDI_STAT) & MIDI_STAT_RX_EVT) {
235+ msg = MM_READ(MM_MIDI_RXTX);
236+ MM_WRITE(MM_MIDI_STAT, MIDI_STAT_RX_EVT);
237+ rtems_message_queue_send(midi_q, &msg, 1);
238+ }
239+ lm32_interrupt_ack(1 << MM_IRQ_MIDI);
240 }
241 
242 rtems_device_driver midi_initialize(
243@@ -57,11 +60,10 @@
244   );
245   RTEMS_CHECK_SC(sc, "create MIDI queue");
246 
247- rtems_interrupt_catch(interrupt_handler, MM_IRQ_MIDIRX, &dummy);
248- bsp_interrupt_vector_enable(MM_IRQ_MIDIRX);
249-
250+ rtems_interrupt_catch(interrupt_handler, MM_IRQ_MIDI, &dummy);
251+ bsp_interrupt_vector_enable(MM_IRQ_MIDI);
252   /* Only MIDI THRU mode is supported atm */
253- MM_WRITE(MM_MIDI_THRU, 1);
254+ MM_WRITE(MM_MIDI_CTRL, MIDI_CTRL_RX_INT|MIDI_CTRL_THRU);
255 
256   return RTEMS_SUCCESSFUL;
257 }
258

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