Date:2009-08-21 08:04:09 (10 years 9 months ago)
Author:Wolfgang Spraul
Commit:a1c4ecab6bc814e37376d771b363aa4b109a9c57
Message:Created xbboot.

Files: xbboot/.gitignore (1 diff)
xbboot/COPYING (1 diff)
xbboot/ChangeLog (1 diff)
xbboot/Makefile.am (1 diff)
xbboot/README (1 diff)
xbboot/autogen.sh (1 diff)
xbboot/configure.ac (1 diff)
xbboot/host-app/.gitignore (1 diff)
xbboot/host-app/Makefile.am (1 diff)
xbboot/host-app/host_main.c (1 diff)
xbboot/scripts/boot-echo.sh (1 diff)
xbboot/target-common/common-types.h (1 diff)
xbboot/target-common/jz4740.h (1 diff)
xbboot/target-common/serial.c (1 diff)
xbboot/target-common/serial.h (1 diff)
xbboot/target-echokernel/.gitignore (1 diff)
xbboot/target-echokernel/Makefile (1 diff)
xbboot/target-echokernel/echo-kernel.c (1 diff)
xbboot/target-echokernel/head.S (1 diff)
xbboot/target-echokernel/target.ld (1 diff)
xbboot/target-stage1/.gitignore (1 diff)
xbboot/target-stage1/Makefile (1 diff)
xbboot/target-stage1/head.S (1 diff)
xbboot/target-stage1/stage1.c (1 diff)
xbboot/target-stage1/target.ld (1 diff)

Change Details

xbboot/.gitignore
1m4
2autom4te.cache
3config.h
4config.h.in
5config.log
6config.status
7Makefile
8Makefile.in
9configure
10stamp-h1
11aclocal.m4
xbboot/COPYING
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557combined work, and to convey the resulting work. The terms of this
558License will continue to apply to the part which is the covered work,
559but the special requirements of the GNU Affero General Public License,
560section 13, concerning interaction through a network will apply to the
561combination as such.
562
563  14. Revised Versions of this License.
564
565  The Free Software Foundation may publish revised and/or new versions of
566the GNU General Public License from time to time. Such new versions will
567be similar in spirit to the present version, but may differ in detail to
568address new problems or concerns.
569
570  Each version is given a distinguishing version number. If the
571Program specifies that a certain numbered version of the GNU General
572Public License "or any later version" applies to it, you have the
573option of following the terms and conditions either of that numbered
574version or of any later version published by the Free Software
575Foundation. If the Program does not specify a version number of the
576GNU General Public License, you may choose any version ever published
577by the Free Software Foundation.
578
579  If the Program specifies that a proxy can decide which future
580versions of the GNU General Public License can be used, that proxy's
581public statement of acceptance of a version permanently authorizes you
582to choose that version for the Program.
583
584  Later license versions may give you additional or different
585permissions. However, no additional obligations are imposed on any
586author or copyright holder as a result of your choosing to follow a
587later version.
588
589  15. Disclaimer of Warranty.
590
591  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
592APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
593HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
594OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
595THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
596PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
597IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
598ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
599
600  16. Limitation of Liability.
601
602  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
603WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
604THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
605GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
606USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
607DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
608PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
609EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
610SUCH DAMAGES.
611
612  17. Interpretation of Sections 15 and 16.
613
614  If the disclaimer of warranty and limitation of liability provided
615above cannot be given local legal effect according to their terms,
616reviewing courts shall apply local law that most closely approximates
617an absolute waiver of all civil liability in connection with the
618Program, unless a warranty or assumption of liability accompanies a
619copy of the Program in return for a fee.
620
621                     END OF TERMS AND CONDITIONS
622
623            How to Apply These Terms to Your New Programs
624
625  If you develop a new program, and you want it to be of the greatest
626possible use to the public, the best way to achieve this is to make it
627free software which everyone can redistribute and change under these terms.
628
629  To do so, attach the following notices to the program. It is safest
630to attach them to the start of each source file to most effectively
631state the exclusion of warranty; and each file should have at least
632the "copyright" line and a pointer to where the full notice is found.
633
634    <one line to give the program's name and a brief idea of what it does.>
635    Copyright (C) <year> <name of author>
636
637    This program is free software: you can redistribute it and/or modify
638    it under the terms of the GNU General Public License as published by
639    the Free Software Foundation, either version 3 of the License, or
640    (at your option) any later version.
641
642    This program is distributed in the hope that it will be useful,
643    but WITHOUT ANY WARRANTY; without even the implied warranty of
644    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
645    GNU General Public License for more details.
646
647    You should have received a copy of the GNU General Public License
648    along with this program. If not, see <http://www.gnu.org/licenses/>.
649
650Also add information on how to contact you by electronic and paper mail.
651
652  If the program does terminal interaction, make it output a short
653notice like this when it starts in an interactive mode:
654
655    <program> Copyright (C) <year> <name of author>
656    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
657    This is free software, and you are welcome to redistribute it
658    under certain conditions; type `show c' for details.
659
660The hypothetical commands `show w' and `show c' should show the appropriate
661parts of the General Public License. Of course, your program's commands
662might be different; for a GUI interface, you would use an "about box".
663
664  You should also get your employer (if you work as a programmer) or school,
665if any, to sign a "copyright disclaimer" for the program, if necessary.
666For more information on this, and how to apply and follow the GNU GPL, see
667<http://www.gnu.org/licenses/>.
668
669  The GNU General Public License does not permit incorporating your program
670into proprietary programs. If your program is a subroutine library, you
671may consider it more useful to permit linking proprietary applications with
672the library. If this is what you want to do, use the GNU Lesser General
673Public License instead of this License. But first, please read
674<http://www.gnu.org/philosophy/why-not-lgpl.html>.
xbboot/ChangeLog
1
2 * xbboot ChangeLog
3
4 15Aug2009 [ws] Started.
xbboot/Makefile.am
1SUBDIRS = host-app
2EXTRA_DIST = autogen.sh
xbboot/README
1*
2* xbboot
3*
4* Use the Ingenic XBurst USB boot protocol to boot, load binaries
5* into memory and execute them.
6*
7
8Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
9
10This program is free software; you can redistribute it and/or
11modify it under the terms of the GNU General Public License
12as published by the Free Software Foundation; either version
133 of the License, or (at your option) any later version.
14
15Build Requirements: libusb-dev, libconfuse-dev
16
17Build and Installation:
18  ./autogen.sh
19  ./configure
20  make
21  make install
22    *) make install will install the xbboot binary to /usr/bin/xbboot
23       and the bootloader running on the device into /usr/share/xburst-tools
24
25Examples:
26  <TBD>
xbboot/autogen.sh
1#!/bin/sh
2export AUTOMAKE="automake --foreign --add-missing --copy"
3autoreconf
xbboot/configure.ac
1#
2# autoconf configuration for xbboot
3#
4
5AC_PREREQ(2.63)
6AC_INIT([xbboot], [0.1])
7AC_CONFIG_AUX_DIR(m4)
8AM_INIT_AUTOMAKE(AC_PACKAGE_NAME, AC_PACKAGE_VERSION)
9AM_CONFIG_HEADER([config.h])
10
11AM_MAINTAINER_MODE
12
13# Checks for programs.
14AC_PROG_CC
15AC_PROG_CXX
16
17# Checks for libraries.
18AC_CHECK_LIB([c], [main])
19AC_CHECK_LIB([confuse], [main], [], [
20echo "Error! You need to have libconfuse-dev.\n"
21echo "Maybe run 'sudo apt-get install libconfuse-dev' under debian"
22exit -1 ])
23AC_CHECK_LIB([gcc], [main])
24AC_CHECK_LIB([m], [main])
25AC_CHECK_LIB([usb], [main], [], [
26echo "Error! You need to have libusb-dev.\n"
27echo "Maybe run 'sudo apt-get install libusb-dev' under debian"
28exit -1 ])
29
30LIBS="$LIBS $USB_LIBS"
31CFLAGS="$CFLAGS $USB_CFLAGS"
32
33# Checks for header files.
34AC_HEADER_STDC
35AC_CHECK_HEADERS([fcntl.h stdint.h stdlib.h string.h unistd.h])
36
37# Checks for typedefs, structures, and compiler characteristics.
38AC_C_INLINE
39AC_TYPE_SIZE_T
40AC_TYPE_UINT8_T
41
42# Checks for library functions.
43AC_FUNC_MALLOC
44AC_FUNC_MEMCMP
45AC_CHECK_FUNCS([memset strerror])
46
47AC_CONFIG_FILES(Makefile host-app/Makefile)
48AC_OUTPUT
xbboot/host-app/.gitignore
1.deps
2host_main.o
3Makefile
4Makefile.in
5xbboot_version.h
6xbboot
xbboot/host-app/Makefile.am
1AM_CFLAGS = -pedantic -Wall -W -O1 -g3 -std=gnu99 -lusb -lconfuse
2
3xbboot_version.h:
4    echo -e '#ifndef XBBOOT_VERSION' \
5    '\n#define XBBOOT_VERSION "20090815-1"' \
6    '\n#endif' > xbboot_version.h
7BUILT_SOURCES = xbboot_version.h
8
9bin_PROGRAMS = xbboot
10xbboot_SOURCES = host_main.c
11
12prefix = /usr
13datadir = /usr/share/xburst-tools
14data_DATA = ../target-stage1/stage1.bin
15
16EXTRA_DIST = $(datadir)
17
18../target-stage1/stage.bin:
19    $(MAKE) -C ../target-stage1
xbboot/host-app/host_main.c
1//
2// Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
3//
4// This program is free software; you can redistribute it and/or
5// modify it under the terms of the GNU General Public License
6// as published by the Free Software Foundation; either version
7// 3 of the License, or (at your option) any later version.
8//
9
10#include <stdio.h>
11#include <string.h>
12#include <usb.h>
13#include "xbboot_version.h"
14
15#define HIWORD(dw) (((dw) >> 16) & 0xFFFF)
16#define LOWORD(dw) ((dw) & 0xFFFF)
17
18#define INGENIC_VENDOR_ID 0x601A
19#define INGENIC_XBURST_USBBOOT 0x4740
20
21// REQ_ values are negative so they can be mixed together with the VR_ types in a signed integer.
22#define REQ_BULK_READ -1
23#define REQ_BULK_WRITE -2
24
25#define VR_GET_CPU_INFO 0x00
26#define VR_SET_DATA_ADDRESS 0x01
27#define VR_SET_DATA_LENGTH 0x02
28#define VR_FLUSH_CACHES 0x03
29#define VR_PROGRAM_START1 0x04
30#define VR_PROGRAM_START2 0x05
31#define VR_NOR_OPS 0x06
32#define VR_NAND_OPS 0x07
33#define VR_SDRAM_OPS 0x08
34#define VR_CONFIGRATION 0x09
35#define VR_GET_NUM 0x0a
36
37#define USB_TIMEOUT 3000
38#define VR_GET_CPU_INFO_LEN 8
39#define INGENIC_IN_ENDPOINT 0x81
40#define INGENIC_OUT_ENDPOINT 0x01
41
42int main(int argc, char** argv)
43{
44    struct usb_device* xburst_dev = 0;
45    uint8_t xburst_interface = 0;
46    struct usb_dev_handle* xburst_h = 0;
47    int request_type, usb_status;
48
49    if (argc < 2
50        || !strcmp(argv[1], "-h")
51        || !strcmp(argv[1], "--help")) {
52        printf("\n"
53               "xbboot version %s - Ingenic XBurst USB Boot Vendor Requests\n"
54               "(c) 2009 Wolfgang Spraul\n"
55               "Report bugs to <wolfgang@qi-hardware.com>.\n"
56               "\n"
57               "xbboot [vendor_request] ... (must run as root)\n"
58               " -h --help print this help message\n"
59               " -v --version print the version number\n"
60               "\n"
61               " bulk_read <len> read len bulk bytes from USB, write to stdout\n"
62               " bulk_write <path> write file at <path> to USB\n"
63               " [get_info | VR_GET_CPU_INFO] read 8-byte CPU info and write to stdout\n"
64               " [set_addr | VR_SET_DATA_ADDRESS] <addr> send memory address\n"
65               " [set_len | VR_SET_DATA_LENGTH] <len> send data length\n"
66               " [flush_cache | VR_FLUSH_CACHES] flush I-Cache and D-Cache\n"
67               " [start1 | VR_PROGRAM_START1] <addr> transfer data from D-Cache to I-Cache and branch to I-Cache\n"
68               " [start2 | VR_PROGRAM_START2] <addr> branch to <addr> directly\n"
69               "\n"
70               "- all numbers can be prefixed 0x for hex otherwise decimal\n"
71               "\n", XBBOOT_VERSION);
72// stage1: 0x80002000
73// stage2: 0x81C00000
74// u-boot: 0x80600000
75// uImage: 0x80010000
76        return EXIT_SUCCESS;
77    }
78    if (!strcmp(argv[1], "-v") || !strcmp(argv[1], "--version")) {
79        printf("xbboot version %s\n", XBBOOT_VERSION);
80        return EXIT_SUCCESS;
81    }
82    if (!strcmp(argv[1], "bulk_read"))
83        request_type = REQ_BULK_READ;
84    else if (!strcmp(argv[1], "bulk_write"))
85        request_type = REQ_BULK_WRITE;
86    else if (!strcmp(argv[1], "VR_GET_CPU_INFO") || !strcmp(argv[1], "get_info"))
87        request_type = VR_GET_CPU_INFO;
88    else if (!strcmp(argv[1], "VR_SET_DATA_ADDRESS") || !strcmp(argv[1], "set_addr"))
89        request_type = VR_SET_DATA_ADDRESS;
90    else if (!strcmp(argv[1], "VR_SET_DATA_LENGTH") || !strcmp(argv[1], "set_len"))
91        request_type = VR_SET_DATA_LENGTH;
92    else if (!strcmp(argv[1], "VR_FLUSH_CACHES") || !strcmp(argv[1], "flush_cache"))
93        request_type = VR_FLUSH_CACHES;
94    else if (!strcmp(argv[1], "VR_PROGRAM_START1") || !strcmp(argv[1], "start1"))
95        request_type = VR_PROGRAM_START1;
96    else if (!strcmp(argv[1], "VR_PROGRAM_START2") || !strcmp(argv[1], "start2"))
97        request_type = VR_PROGRAM_START2;
98    else {
99        fprintf(stderr, "Error - unknown vendor request %s - run with --help to see all requests\n", argv[1]);
100        return EXIT_FAILURE;
101    }
102    if ((getuid()) || (getgid())) {
103        fprintf(stderr, "Error - you must be root to run '%s'\n", argv[0]);
104        return EXIT_FAILURE;
105    }
106
107    usb_init();
108    usb_find_busses();
109    usb_find_devices();
110
111    // look for Ingenic XBurst USB boot device & interface
112    {
113        {
114            struct usb_bus* usb_bus;
115            struct usb_device* usb_dev;
116
117            for (usb_bus = usb_get_busses(); usb_bus != 0; usb_bus = usb_bus->next) {
118                for (usb_dev = usb_bus->devices; usb_dev != 0; usb_dev = usb_dev->next) {
119                    if (usb_dev->descriptor.idVendor == INGENIC_VENDOR_ID
120                        && usb_dev->descriptor.idProduct == INGENIC_XBURST_USBBOOT) {
121                        if (xburst_dev) {
122                            fprintf(stderr, "Error - more than one XBurst boot device found.\n");
123                            goto xout;
124                        }
125                        xburst_dev = usb_dev;
126                        // keep searching to make sure there is only 1 XBurst device
127                    }
128                }
129            }
130            if (!xburst_dev) {
131                fprintf(stderr, "Error - no XBurst boot device found.\n");
132                goto xout;
133            }
134        }
135        {
136            struct usb_config_descriptor* usb_config_desc;
137            struct usb_interface_descriptor* usb_if_desc;
138            struct usb_interface* usb_if;
139            int cfg_index, if_index, alt_index;
140
141            for (cfg_index = 0; cfg_index < xburst_dev->descriptor.bNumConfigurations; cfg_index++) {
142                usb_config_desc = &xburst_dev->config[cfg_index];
143                if (!usb_config_desc) {
144                    fprintf(stderr, "Error - usb_config_desc NULL\n");
145                    goto xout;
146                }
147                for (if_index = 0; if_index < usb_config_desc->bNumInterfaces; if_index++) {
148                    usb_if = &usb_config_desc->interface[if_index];
149                    if (!usb_if) {
150                        fprintf(stderr, "Error - usb_if NULL\n");
151                        goto xout;
152                    }
153                    for (alt_index = 0; alt_index < usb_if->num_altsetting; alt_index++) {
154                        usb_if_desc = &usb_if->altsetting[alt_index];
155                        if (!usb_if_desc) {
156                            fprintf(stderr, "Error - usb_if_desc NULL\n");
157                            goto xout;
158                        }
159                        if (usb_if_desc->bInterfaceClass == 0xFF
160                            && usb_if_desc->bInterfaceSubClass == 0) {
161                            xburst_interface = usb_if_desc->bInterfaceNumber;
162                            goto interface_found;
163                        }
164                    }
165                }
166            }
167        interface_found: ;
168        }
169    }
170    xburst_h = usb_open(xburst_dev);
171    if (!xburst_h) {
172        fprintf(stderr, "Error - can't open XBurst device: %s\n", usb_strerror());
173        goto xout;
174    }
175    if (usb_claim_interface(xburst_h, xburst_interface) < 0) {
176        fprintf(stderr, "Error - can't claim XBurst interface: %s\n", usb_strerror());
177        goto xout_xburst_h;
178    }
179    switch (request_type) {
180        case VR_GET_CPU_INFO: {
181            char cpu_info_buf[VR_GET_CPU_INFO_LEN+1] = {0};
182            usb_status = usb_control_msg(xburst_h,
183                /* requesttype */ USB_ENDPOINT_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
184                /* request */ VR_GET_CPU_INFO,
185                /* value */ 0,
186                /* index */ 0,
187                /* bytes */ cpu_info_buf,
188                /* size */ VR_GET_CPU_INFO_LEN,
189                /* timeout */ USB_TIMEOUT);
190            if (usb_status != VR_GET_CPU_INFO_LEN) {
191                fprintf(stderr, "Error - %s() returned %i\n", argv[1], usb_status);
192                goto xout_xburst_interface;
193            }
194            printf("VR_GET_CPU_INFO %s\n", cpu_info_buf);
195            break;
196        }
197        case VR_SET_DATA_ADDRESS:
198        case VR_SET_DATA_LENGTH:
199        case VR_PROGRAM_START1:
200        case VR_PROGRAM_START2: {
201            uint32_t u32_param;
202            if (argc != 3) {
203                fprintf(stderr, "Error - number of %s parameters %i\n", argv[1], argc);
204                goto xout_xburst_interface;
205            }
206            u32_param = strtoul(argv[2], 0 /* endptr */, 16 /* base */);
207
208            usb_status = usb_control_msg(xburst_h,
209                /* requesttype */ USB_ENDPOINT_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
210                /* request */ request_type,
211                /* value */ HIWORD(u32_param),
212                /* index */ LOWORD(u32_param),
213                /* bytes */ 0,
214                /* size */ 0,
215                /* timeout */ USB_TIMEOUT);
216            if (usb_status) {
217                fprintf(stderr, "Error - %s() returned %i\n", argv[1], usb_status);
218                goto xout_xburst_interface;
219            }
220            printf("%s %lxh\n", argv[1], (unsigned long) u32_param);
221            break;
222        }
223        case VR_FLUSH_CACHES: {
224            usb_status = usb_control_msg(xburst_h,
225                /* requesttype */ USB_ENDPOINT_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
226                /* request */ VR_FLUSH_CACHES,
227                /* value */ 0,
228                /* index */ 0,
229                /* bytes */ 0,
230                /* size */ 0,
231                /* timeout */ USB_TIMEOUT);
232            if (usb_status) {
233                fprintf(stderr, "Error - %s() returned %i\n", argv[1], usb_status);
234                goto xout_xburst_interface;
235            }
236            printf("VR_FLUSH_CACHES\n");
237            break;
238        }
239        case REQ_BULK_READ: {
240            int read_len;
241            char* read_buf;
242
243            if (argc != 3) {
244                fprintf(stderr, "Error - number of %s parameters %i\n", argv[1], argc);
245                goto xout_xburst_interface;
246            }
247            read_len = strtol(argv[2], 0 /* endptr */, 16 /* base */);
248            read_buf = (char*) malloc(read_len);
249            if (!read_buf) {
250                fprintf(stderr, "Error - cannot allocate %i bytes read buffer.\n", read_len);
251                goto xout_xburst_interface;
252            }
253            usb_status = usb_bulk_read(xburst_h,
254                /* endpoint */ INGENIC_IN_ENDPOINT,
255                /* bytes */ read_buf,
256                /* size */ read_len,
257                /* timeout */ USB_TIMEOUT);
258            if (usb_status > 0)
259                fwrite(read_buf, 1 /* size */, usb_status, stdout);
260            free(read_buf);
261            if (usb_status < read_len) {
262                fprintf(stderr, "Error reading %d bytes (result %i).\n", read_len, usb_status);
263                goto xout_xburst_interface;
264            }
265            break;
266        }
267        case REQ_BULK_WRITE: {
268            char* file_data;
269            int file_len;
270            FILE* file_h;
271            size_t num_read;
272
273            if (argc != 3) {
274                fprintf(stderr, "Error - number of parameters %i\n", argc);
275                goto xout_xburst_interface;
276            }
277            file_h = fopen(argv[2], "rb");
278            if (!file_h) {
279                fprintf(stderr, "Error opening %s.\n", argv[2]);
280                goto xout_xburst_interface;
281            }
282            if (fseek(file_h, 0, SEEK_END)) {
283                fprintf(stderr, "Error seeking to end of %s.\n", argv[2]);
284                fclose(file_h);
285                goto xout_xburst_interface;
286            }
287            file_len = ftell(file_h);
288            if (fseek(file_h, 0, SEEK_SET)) {
289                fprintf(stderr, "Error seeking to beginning of %s.\n", argv[2]);
290                fclose(file_h);
291                goto xout_xburst_interface;
292            }
293            file_data = (char*) malloc(file_len);
294            if (!file_data) {
295                fprintf(stderr, "Error allocating %d bytes data.\n", file_len);
296                fclose(file_h);
297                goto xout_xburst_interface;
298            }
299            num_read = fread(file_data, 1, file_len, file_h);
300            fclose(file_h);
301            if (num_read != (size_t) file_len) {
302                fprintf(stderr, "Error reading %d bytes (got %d).\n", file_len, num_read);
303                free(file_data);
304                goto xout_xburst_interface;
305            }
306            usb_status = usb_bulk_write(xburst_h,
307                /* endpoint */ INGENIC_OUT_ENDPOINT,
308                /* bytes */ file_data,
309                /* size */ file_len,
310                /* timeout */ USB_TIMEOUT);
311            free(file_data);
312            if (usb_status < file_len) {
313                fprintf(stderr, "Error writing %d bytes (result %i).\n", file_len, usb_status);
314                goto xout_xburst_interface;
315            }
316            printf("bulk_write successfully wrote %i bytes.\n", usb_status);
317            break;
318        }
319    }
320    usb_release_interface(xburst_h, xburst_interface);
321    usb_close(xburst_h);
322    return EXIT_SUCCESS;
323
324xout_xburst_interface:
325    usb_release_interface(xburst_h, xburst_interface);
326xout_xburst_h:
327    usb_close(xburst_h);
328xout:
329    return EXIT_FAILURE;
330}
xbboot/scripts/boot-echo.sh
1#!/bin/bash
2../host-app/xbboot set_addr 80002000
3../host-app/xbboot bulk_write ../target-stage1/stage1.bin
4../host-app/xbboot start1 80002000
5../host-app/xbboot set_addr 81c00000
6../host-app/xbboot bulk_write ../target-echokernel/echo-kernel.bin
7../host-app/xbboot flush_cache
8../host-app/xbboot start2 81c00000
xbboot/target-common/common-types.h
1/*
2 * Authors: Xiangfu Liu <xiangfu@qi-hardware.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 3 of the License, or (at your option) any later version.
8 */
9
10#ifndef __COMMON_TYPES_H__
11#define __COMMON_TYPES_H__
12
13typedef unsigned int size_t;
14typedef unsigned char u8;
15typedef unsigned short u16;
16typedef unsigned int u32;
17
18#endif // __COMMON_TYPES_H__
xbboot/target-common/jz4740.h
1/*
2 * Include file for Ingenic Semiconductor's JZ4740 CPU.
3 *
4 * Copyright 2009 (C) Qi Hardware Inc.,
5 * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 3 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
19 * Boston, MA 02110-1301, USA
20 */
21#ifndef __JZ4740_H__
22#define __JZ4740_H__
23
24#include "common-types.h"
25
26#ifndef __ASSEMBLY__
27#define UCOS_CSP 0
28
29#if UCOS_CSP
30#define __KERNEL__
31#include <bsp.h>
32#include <types.h>
33
34#include <sysdefs.h>
35#include <cacheops.h>
36#define KSEG0 KSEG0BASE
37#else
38/* #include <asm/cacheops.h> */
39#endif
40
41#define cache_unroll(base,op) \
42    __asm__ __volatile__(" \
43        .set noreorder; \
44        .set mips3; \
45        cache %1, (%0); \
46        .set mips0; \
47        .set reorder" \
48        : \
49        : "r" (base), \
50          "i" (op));
51#if 0
52static inline void jz_flush_dcache(void)
53{
54    unsigned long start;
55    unsigned long end;
56
57    start = KSEG0;
58    end = start + CFG_DCACHE_SIZE;
59    while (start < end) {
60        cache_unroll(start,Index_Writeback_Inv_D);
61        start += CFG_CACHELINE_SIZE;
62    }
63}
64
65static inline void jz_flush_icache(void)
66{
67    unsigned long start;
68    unsigned long end;
69
70    start = KSEG0;
71    end = start + CFG_ICACHE_SIZE;
72    while(start < end) {
73        cache_unroll(start,Index_Invalidate_I);
74        start += CFG_CACHELINE_SIZE;
75    }
76}
77
78#endif
79/* cpu pipeline flush */
80static inline void jz_sync(void)
81{
82    __asm__ volatile ("sync");
83}
84
85static inline void jz_writeb(u32 address, u8 value)
86{
87    *((volatile u8 *)address) = value;
88}
89
90static inline void jz_writew(u32 address, u16 value)
91{
92    *((volatile u16 *)address) = value;
93}
94
95static inline void jz_writel(u32 address, u32 value)
96{
97    *((volatile u32 *)address) = value;
98}
99
100static inline u8 jz_readb(u32 address)
101{
102    return *((volatile u8 *)address);
103}
104
105static inline u16 jz_readw(u32 address)
106{
107    return *((volatile u16 *)address);
108}
109
110static inline u32 jz_readl(u32 address)
111{
112    return *((volatile u32 *)address);
113}
114
115#define REG8(addr) *((volatile u8 *)(addr))
116#define REG16(addr) *((volatile u16 *)(addr))
117#define REG32(addr) *((volatile u32 *)(addr))
118
119#else
120
121#define REG8(addr) (addr)
122#define REG16(addr) (addr)
123#define REG32(addr) (addr)
124
125#endif /* !ASSEMBLY */
126
127/* Boot ROM Specification */
128
129/* NOR Boot config */
130#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
131#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
132#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
133
134/* NAND Boot config */
135#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
136#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
137#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
138#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
139
140
141/* Register Definitions */
142#define CPM_BASE 0xB0000000
143#define INTC_BASE 0xB0001000
144#define TCU_BASE 0xB0002000
145#define WDT_BASE 0xB0002000
146#define RTC_BASE 0xB0003000
147#define GPIO_BASE 0xB0010000
148#define AIC_BASE 0xB0020000
149#define ICDC_BASE 0xB0020000
150#define MSC_BASE 0xB0021000
151#define UART0_BASE 0xB0030000
152#define I2C_BASE 0xB0042000
153#define SSI_BASE 0xB0043000
154#define SADC_BASE 0xB0070000
155#define EMC_BASE 0xB3010000
156#define DMAC_BASE 0xB3020000
157#define UHC_BASE 0xB3030000
158#define UDC_BASE 0xB3040000
159#define LCD_BASE 0xB3050000
160#define SLCD_BASE 0xB3050000
161#define CIM_BASE 0xB3060000
162#define ETH_BASE 0xB3100000
163
164
165/*************************************************************************
166 * INTC (Interrupt Controller)
167 *************************************************************************/
168#define INTC_ISR (INTC_BASE + 0x00)
169#define INTC_IMR (INTC_BASE + 0x04)
170#define INTC_IMSR (INTC_BASE + 0x08)
171#define INTC_IMCR (INTC_BASE + 0x0c)
172#define INTC_IPR (INTC_BASE + 0x10)
173
174#define REG_INTC_ISR REG32(INTC_ISR)
175#define REG_INTC_IMR REG32(INTC_IMR)
176#define REG_INTC_IMSR REG32(INTC_IMSR)
177#define REG_INTC_IMCR REG32(INTC_IMCR)
178#define REG_INTC_IPR REG32(INTC_IPR)
179
180/* 1st-level interrupts */
181#define IRQ_I2C 1
182#define IRQ_UHC 3
183#define IRQ_UART0 9
184#define IRQ_SADC 12
185#define IRQ_MSC 14
186#define IRQ_RTC 15
187#define IRQ_SSI 16
188#define IRQ_CIM 17
189#define IRQ_AIC 18
190#define IRQ_ETH 19
191#define IRQ_DMAC 20
192#define IRQ_TCU2 21
193#define IRQ_TCU1 22
194#define IRQ_TCU0 23
195#define IRQ_UDC 24
196#define IRQ_GPIO3 25
197#define IRQ_GPIO2 26
198#define IRQ_GPIO1 27
199#define IRQ_GPIO0 28
200#define IRQ_IPU 29
201#define IRQ_LCD 30
202
203/* 2nd-level interrupts */
204#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
205#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
206
207
208/*************************************************************************
209 * RTC
210 *************************************************************************/
211#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
212#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
213#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
214#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
215
216#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
217#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
218#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
219#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
220#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
221#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
222
223#define REG_RTC_RCR REG32(RTC_RCR)
224#define REG_RTC_RSR REG32(RTC_RSR)
225#define REG_RTC_RSAR REG32(RTC_RSAR)
226#define REG_RTC_RGR REG32(RTC_RGR)
227#define REG_RTC_HCR REG32(RTC_HCR)
228#define REG_RTC_HWFCR REG32(RTC_HWFCR)
229#define REG_RTC_HRCR REG32(RTC_HRCR)
230#define REG_RTC_HWCR REG32(RTC_HWCR)
231#define REG_RTC_HWRSR REG32(RTC_HWRSR)
232#define REG_RTC_HSPR REG32(RTC_HSPR)
233
234/* RTC Control Register */
235#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
236#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
237#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
238#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
239#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
240#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
241#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
242
243/* RTC Regulator Register */
244#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
245#define RTC_RGR_ADJC_BIT 16
246#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
247#define RTC_RGR_NC1HZ_BIT 0
248#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
249
250/* Hibernate Control Register */
251#define RTC_HCR_PD (1 << 0) /* Power Down */
252
253/* Hibernate Wakeup Filter Counter Register */
254#define RTC_HWFCR_BIT 5
255#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
256
257/* Hibernate Reset Counter Register */
258#define RTC_HRCR_BIT 5
259#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
260
261/* Hibernate Wakeup Control Register */
262#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
263
264/* Hibernate Wakeup Status Register */
265#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
266#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
267#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
268#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
269
270
271/*************************************************************************
272 * CPM (Clock reset and Power control Management)
273 *************************************************************************/
274#define CPM_CPCCR (CPM_BASE+0x00)
275#define CPM_CPPCR (CPM_BASE+0x10)
276#define CPM_I2SCDR (CPM_BASE+0x60)
277#define CPM_LPCDR (CPM_BASE+0x64)
278#define CPM_MSCCDR (CPM_BASE+0x68)
279#define CPM_UHCCDR (CPM_BASE+0x6C)
280
281#define CPM_LCR (CPM_BASE+0x04)
282#define CPM_CLKGR (CPM_BASE+0x20)
283#define CPM_SCR (CPM_BASE+0x24)
284
285#define CPM_HCR (CPM_BASE+0x30)
286#define CPM_HWFCR (CPM_BASE+0x34)
287#define CPM_HRCR (CPM_BASE+0x38)
288#define CPM_HWCR (CPM_BASE+0x3c)
289#define CPM_HWSR (CPM_BASE+0x40)
290#define CPM_HSPR (CPM_BASE+0x44)
291
292#define CPM_RSR (CPM_BASE+0x08)
293
294
295#define REG_CPM_CPCCR REG32(CPM_CPCCR)
296#define REG_CPM_CPPCR REG32(CPM_CPPCR)
297#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
298#define REG_CPM_LPCDR REG32(CPM_LPCDR)
299#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
300#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
301
302#define REG_CPM_LCR REG32(CPM_LCR)
303#define REG_CPM_CLKGR REG32(CPM_CLKGR)
304#define REG_CPM_SCR REG32(CPM_SCR)
305#define REG_CPM_HCR REG32(CPM_HCR)
306#define REG_CPM_HWFCR REG32(CPM_HWFCR)
307#define REG_CPM_HRCR REG32(CPM_HRCR)
308#define REG_CPM_HWCR REG32(CPM_HWCR)
309#define REG_CPM_HWSR REG32(CPM_HWSR)
310#define REG_CPM_HSPR REG32(CPM_HSPR)
311
312#define REG_CPM_RSR REG32(CPM_RSR)
313
314
315/* Clock Control Register */
316#define CPM_CPCCR_I2CS (1 << 31)
317#define CPM_CPCCR_CLKOEN (1 << 30)
318#define CPM_CPCCR_UCS (1 << 29)
319#define CPM_CPCCR_UDIV_BIT 23
320#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
321#define CPM_CPCCR_CE (1 << 22)
322#define CPM_CPCCR_PCS (1 << 21)
323#define CPM_CPCCR_LDIV_BIT 16
324#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
325#define CPM_CPCCR_MDIV_BIT 12
326#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
327#define CPM_CPCCR_PDIV_BIT 8
328#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
329#define CPM_CPCCR_HDIV_BIT 4
330#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
331#define CPM_CPCCR_CDIV_BIT 0
332#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
333
334/* I2S Clock Divider Register */
335#define CPM_I2SCDR_I2SDIV_BIT 0
336#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
337
338/* LCD Pixel Clock Divider Register */
339#define CPM_LPCDR_PIXDIV_BIT 0
340#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
341
342/* MSC Clock Divider Register */
343#define CPM_MSCCDR_MSCDIV_BIT 0
344#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
345
346/* PLL Control Register */
347#define CPM_CPPCR_PLLM_BIT 23
348#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
349#define CPM_CPPCR_PLLN_BIT 18
350#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
351#define CPM_CPPCR_PLLOD_BIT 16
352#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
353#define CPM_CPPCR_PLLS (1 << 10)
354#define CPM_CPPCR_PLLBP (1 << 9)
355#define CPM_CPPCR_PLLEN (1 << 8)
356#define CPM_CPPCR_PLLST_BIT 0
357#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
358
359/* Low Power Control Register */
360#define CPM_LCR_DOZE_DUTY_BIT 3
361#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
362#define CPM_LCR_DOZE_ON (1 << 2)
363#define CPM_LCR_LPM_BIT 0
364#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
365  #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
366  #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
367
368/* Clock Gate Register */
369#define CPM_CLKGR_UART1 (1 << 15)
370#define CPM_CLKGR_UHC (1 << 14)
371#define CPM_CLKGR_IPU (1 << 13)
372#define CPM_CLKGR_DMAC (1 << 12)
373#define CPM_CLKGR_UDC (1 << 11)
374#define CPM_CLKGR_LCD (1 << 10)
375#define CPM_CLKGR_CIM (1 << 9)
376#define CPM_CLKGR_SADC (1 << 8)
377#define CPM_CLKGR_MSC (1 << 7)
378#define CPM_CLKGR_AIC1 (1 << 6)
379#define CPM_CLKGR_AIC2 (1 << 5)
380#define CPM_CLKGR_SSI (1 << 4)
381#define CPM_CLKGR_I2C (1 << 3)
382#define CPM_CLKGR_RTC (1 << 2)
383#define CPM_CLKGR_TCU (1 << 1)
384#define CPM_CLKGR_UART0 (1 << 0)
385
386/* Sleep Control Register */
387#define CPM_SCR_O1ST_BIT 8
388#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
389#define CPM_SCR_USBPHY_ENABLE (1 << 6)
390#define CPM_SCR_OSC_ENABLE (1 << 4)
391
392/* Hibernate Control Register */
393#define CPM_HCR_PD (1 << 0)
394
395/* Wakeup Filter Counter Register in Hibernate Mode */
396#define CPM_HWFCR_TIME_BIT 0
397#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
398
399/* Reset Counter Register in Hibernate Mode */
400#define CPM_HRCR_TIME_BIT 0
401#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
402
403/* Wakeup Control Register in Hibernate Mode */
404#define CPM_HWCR_WLE_LOW (0 << 2)
405#define CPM_HWCR_WLE_HIGH (1 << 2)
406#define CPM_HWCR_PIN_WAKEUP (1 << 1)
407#define CPM_HWCR_RTC_WAKEUP (1 << 0)
408
409/* Wakeup Status Register in Hibernate Mode */
410#define CPM_HWSR_WSR_PIN (1 << 1)
411#define CPM_HWSR_WSR_RTC (1 << 0)
412
413/* Reset Status Register */
414#define CPM_RSR_HR (1 << 2)
415#define CPM_RSR_WR (1 << 1)
416#define CPM_RSR_PR (1 << 0)
417
418
419/*************************************************************************
420 * TCU (Timer Counter Unit)
421 *************************************************************************/
422#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
423#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
424#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
425#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
426#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
427#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
428#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
429#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
430#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
431#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
432#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
433#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
434#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
435#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
436#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
437#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
438#define TCU_TDFR1 (TCU_BASE + 0x50)
439#define TCU_TDHR1 (TCU_BASE + 0x54)
440#define TCU_TCNT1 (TCU_BASE + 0x58)
441#define TCU_TCSR1 (TCU_BASE + 0x5C)
442#define TCU_TDFR2 (TCU_BASE + 0x60)
443#define TCU_TDHR2 (TCU_BASE + 0x64)
444#define TCU_TCNT2 (TCU_BASE + 0x68)
445#define TCU_TCSR2 (TCU_BASE + 0x6C)
446#define TCU_TDFR3 (TCU_BASE + 0x70)
447#define TCU_TDHR3 (TCU_BASE + 0x74)
448#define TCU_TCNT3 (TCU_BASE + 0x78)
449#define TCU_TCSR3 (TCU_BASE + 0x7C)
450#define TCU_TDFR4 (TCU_BASE + 0x80)
451#define TCU_TDHR4 (TCU_BASE + 0x84)
452#define TCU_TCNT4 (TCU_BASE + 0x88)
453#define TCU_TCSR4 (TCU_BASE + 0x8C)
454#define TCU_TDFR5 (TCU_BASE + 0x90)
455#define TCU_TDHR5 (TCU_BASE + 0x94)
456#define TCU_TCNT5 (TCU_BASE + 0x98)
457#define TCU_TCSR5 (TCU_BASE + 0x9C)
458
459#define REG_TCU_TSR REG32(TCU_TSR)
460#define REG_TCU_TSSR REG32(TCU_TSSR)
461#define REG_TCU_TSCR REG32(TCU_TSCR)
462#define REG_TCU_TER REG8(TCU_TER)
463#define REG_TCU_TESR REG8(TCU_TESR)
464#define REG_TCU_TECR REG8(TCU_TECR)
465#define REG_TCU_TFR REG32(TCU_TFR)
466#define REG_TCU_TFSR REG32(TCU_TFSR)
467#define REG_TCU_TFCR REG32(TCU_TFCR)
468#define REG_TCU_TMR REG32(TCU_TMR)
469#define REG_TCU_TMSR REG32(TCU_TMSR)
470#define REG_TCU_TMCR REG32(TCU_TMCR)
471#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
472#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
473#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
474#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
475#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
476#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
477#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
478#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
479#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
480#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
481#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
482#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
483#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
484#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
485#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
486#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
487#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
488#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
489#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
490#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
491
492/* n = 0,1,2,3,4,5 */
493#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
494#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
495#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
496#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
497
498#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
499#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
500#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
501#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
502
503/* Register definitions */
504#define TCU_TCSR_PWM_SD (1 << 9)
505#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
506#define TCU_TCSR_PWM_EN (1 << 7)
507#define TCU_TCSR_PRESCALE_BIT 3
508#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
509  #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
510  #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
511  #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
512  #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
513  #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
514  #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
515#define TCU_TCSR_EXT_EN (1 << 2)
516#define TCU_TCSR_RTC_EN (1 << 1)
517#define TCU_TCSR_PCK_EN (1 << 0)
518
519#define TCU_TER_TCEN5 (1 << 5)
520#define TCU_TER_TCEN4 (1 << 4)
521#define TCU_TER_TCEN3 (1 << 3)
522#define TCU_TER_TCEN2 (1 << 2)
523#define TCU_TER_TCEN1 (1 << 1)
524#define TCU_TER_TCEN0 (1 << 0)
525
526#define TCU_TESR_TCST5 (1 << 5)
527#define TCU_TESR_TCST4 (1 << 4)
528#define TCU_TESR_TCST3 (1 << 3)
529#define TCU_TESR_TCST2 (1 << 2)
530#define TCU_TESR_TCST1 (1 << 1)
531#define TCU_TESR_TCST0 (1 << 0)
532
533#define TCU_TECR_TCCL5 (1 << 5)
534#define TCU_TECR_TCCL4 (1 << 4)
535#define TCU_TECR_TCCL3 (1 << 3)
536#define TCU_TECR_TCCL2 (1 << 2)
537#define TCU_TECR_TCCL1 (1 << 1)
538#define TCU_TECR_TCCL0 (1 << 0)
539
540#define TCU_TFR_HFLAG5 (1 << 21)
541#define TCU_TFR_HFLAG4 (1 << 20)
542#define TCU_TFR_HFLAG3 (1 << 19)
543#define TCU_TFR_HFLAG2 (1 << 18)
544#define TCU_TFR_HFLAG1 (1 << 17)
545#define TCU_TFR_HFLAG0 (1 << 16)
546#define TCU_TFR_FFLAG5 (1 << 5)
547#define TCU_TFR_FFLAG4 (1 << 4)
548#define TCU_TFR_FFLAG3 (1 << 3)
549#define TCU_TFR_FFLAG2 (1 << 2)
550#define TCU_TFR_FFLAG1 (1 << 1)
551#define TCU_TFR_FFLAG0 (1 << 0)
552
553#define TCU_TFSR_HFLAG5 (1 << 21)
554#define TCU_TFSR_HFLAG4 (1 << 20)
555#define TCU_TFSR_HFLAG3 (1 << 19)
556#define TCU_TFSR_HFLAG2 (1 << 18)
557#define TCU_TFSR_HFLAG1 (1 << 17)
558#define TCU_TFSR_HFLAG0 (1 << 16)
559#define TCU_TFSR_FFLAG5 (1 << 5)
560#define TCU_TFSR_FFLAG4 (1 << 4)
561#define TCU_TFSR_FFLAG3 (1 << 3)
562#define TCU_TFSR_FFLAG2 (1 << 2)
563#define TCU_TFSR_FFLAG1 (1 << 1)
564#define TCU_TFSR_FFLAG0 (1 << 0)
565
566#define TCU_TFCR_HFLAG5 (1 << 21)
567#define TCU_TFCR_HFLAG4 (1 << 20)
568#define TCU_TFCR_HFLAG3 (1 << 19)
569#define TCU_TFCR_HFLAG2 (1 << 18)
570#define TCU_TFCR_HFLAG1 (1 << 17)
571#define TCU_TFCR_HFLAG0 (1 << 16)
572#define TCU_TFCR_FFLAG5 (1 << 5)
573#define TCU_TFCR_FFLAG4 (1 << 4)
574#define TCU_TFCR_FFLAG3 (1 << 3)
575#define TCU_TFCR_FFLAG2 (1 << 2)
576#define TCU_TFCR_FFLAG1 (1 << 1)
577#define TCU_TFCR_FFLAG0 (1 << 0)
578
579#define TCU_TMR_HMASK5 (1 << 21)
580#define TCU_TMR_HMASK4 (1 << 20)
581#define TCU_TMR_HMASK3 (1 << 19)
582#define TCU_TMR_HMASK2 (1 << 18)
583#define TCU_TMR_HMASK1 (1 << 17)
584#define TCU_TMR_HMASK0 (1 << 16)
585#define TCU_TMR_FMASK5 (1 << 5)
586#define TCU_TMR_FMASK4 (1 << 4)
587#define TCU_TMR_FMASK3 (1 << 3)
588#define TCU_TMR_FMASK2 (1 << 2)
589#define TCU_TMR_FMASK1 (1 << 1)
590#define TCU_TMR_FMASK0 (1 << 0)
591
592#define TCU_TMSR_HMST5 (1 << 21)
593#define TCU_TMSR_HMST4 (1 << 20)
594#define TCU_TMSR_HMST3 (1 << 19)
595#define TCU_TMSR_HMST2 (1 << 18)
596#define TCU_TMSR_HMST1 (1 << 17)
597#define TCU_TMSR_HMST0 (1 << 16)
598#define TCU_TMSR_FMST5 (1 << 5)
599#define TCU_TMSR_FMST4 (1 << 4)
600#define TCU_TMSR_FMST3 (1 << 3)
601#define TCU_TMSR_FMST2 (1 << 2)
602#define TCU_TMSR_FMST1 (1 << 1)
603#define TCU_TMSR_FMST0 (1 << 0)
604
605#define TCU_TMCR_HMCL5 (1 << 21)
606#define TCU_TMCR_HMCL4 (1 << 20)
607#define TCU_TMCR_HMCL3 (1 << 19)
608#define TCU_TMCR_HMCL2 (1 << 18)
609#define TCU_TMCR_HMCL1 (1 << 17)
610#define TCU_TMCR_HMCL0 (1 << 16)
611#define TCU_TMCR_FMCL5 (1 << 5)
612#define TCU_TMCR_FMCL4 (1 << 4)
613#define TCU_TMCR_FMCL3 (1 << 3)
614#define TCU_TMCR_FMCL2 (1 << 2)
615#define TCU_TMCR_FMCL1 (1 << 1)
616#define TCU_TMCR_FMCL0 (1 << 0)
617
618#define TCU_TSR_WDTS (1 << 16)
619#define TCU_TSR_STOP5 (1 << 5)
620#define TCU_TSR_STOP4 (1 << 4)
621#define TCU_TSR_STOP3 (1 << 3)
622#define TCU_TSR_STOP2 (1 << 2)
623#define TCU_TSR_STOP1 (1 << 1)
624#define TCU_TSR_STOP0 (1 << 0)
625
626#define TCU_TSSR_WDTSS (1 << 16)
627#define TCU_TSSR_STPS5 (1 << 5)
628#define TCU_TSSR_STPS4 (1 << 4)
629#define TCU_TSSR_STPS3 (1 << 3)
630#define TCU_TSSR_STPS2 (1 << 2)
631#define TCU_TSSR_STPS1 (1 << 1)
632#define TCU_TSSR_STPS0 (1 << 0)
633
634#define TCU_TSSR_WDTSC (1 << 16)
635#define TCU_TSSR_STPC5 (1 << 5)
636#define TCU_TSSR_STPC4 (1 << 4)
637#define TCU_TSSR_STPC3 (1 << 3)
638#define TCU_TSSR_STPC2 (1 << 2)
639#define TCU_TSSR_STPC1 (1 << 1)
640#define TCU_TSSR_STPC0 (1 << 0)
641
642
643/*************************************************************************
644 * WDT (WatchDog Timer)
645 *************************************************************************/
646#define WDT_TDR (WDT_BASE + 0x00)
647#define WDT_TCER (WDT_BASE + 0x04)
648#define WDT_TCNT (WDT_BASE + 0x08)
649#define WDT_TCSR (WDT_BASE + 0x0C)
650
651#define REG_WDT_TDR REG16(WDT_TDR)
652#define REG_WDT_TCER REG8(WDT_TCER)
653#define REG_WDT_TCNT REG16(WDT_TCNT)
654#define REG_WDT_TCSR REG16(WDT_TCSR)
655
656/* Register definition */
657#define WDT_TCSR_PRESCALE_BIT 3
658#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
659  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
660  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
661  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
662  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
663  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
664  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
665#define WDT_TCSR_EXT_EN (1 << 2)
666#define WDT_TCSR_RTC_EN (1 << 1)
667#define WDT_TCSR_PCK_EN (1 << 0)
668
669#define WDT_TCER_TCEN (1 << 0)
670
671
672/*************************************************************************
673 * DMAC (DMA Controller)
674 *************************************************************************/
675
676#define MAX_DMA_NUM 6 /* max 6 channels */
677
678#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
679#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
680#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
681#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
682#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
683#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
684#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
685#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
686#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
687#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
688#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
689
690/* channel 0 */
691#define DMAC_DSAR0 DMAC_DSAR(0)
692#define DMAC_DTAR0 DMAC_DTAR(0)
693#define DMAC_DTCR0 DMAC_DTCR(0)
694#define DMAC_DRSR0 DMAC_DRSR(0)
695#define DMAC_DCCSR0 DMAC_DCCSR(0)
696#define DMAC_DCMD0 DMAC_DCMD(0)
697#define DMAC_DDA0 DMAC_DDA(0)
698
699/* channel 1 */
700#define DMAC_DSAR1 DMAC_DSAR(1)
701#define DMAC_DTAR1 DMAC_DTAR(1)
702#define DMAC_DTCR1 DMAC_DTCR(1)
703#define DMAC_DRSR1 DMAC_DRSR(1)
704#define DMAC_DCCSR1 DMAC_DCCSR(1)
705#define DMAC_DCMD1 DMAC_DCMD(1)
706#define DMAC_DDA1 DMAC_DDA(1)
707
708/* channel 2 */
709#define DMAC_DSAR2 DMAC_DSAR(2)
710#define DMAC_DTAR2 DMAC_DTAR(2)
711#define DMAC_DTCR2 DMAC_DTCR(2)
712#define DMAC_DRSR2 DMAC_DRSR(2)
713#define DMAC_DCCSR2 DMAC_DCCSR(2)
714#define DMAC_DCMD2 DMAC_DCMD(2)
715#define DMAC_DDA2 DMAC_DDA(2)
716
717/* channel 3 */
718#define DMAC_DSAR3 DMAC_DSAR(3)
719#define DMAC_DTAR3 DMAC_DTAR(3)
720#define DMAC_DTCR3 DMAC_DTCR(3)
721#define DMAC_DRSR3 DMAC_DRSR(3)
722#define DMAC_DCCSR3 DMAC_DCCSR(3)
723#define DMAC_DCMD3 DMAC_DCMD(3)
724#define DMAC_DDA3 DMAC_DDA(3)
725
726/* channel 4 */
727#define DMAC_DSAR4 DMAC_DSAR(4)
728#define DMAC_DTAR4 DMAC_DTAR(4)
729#define DMAC_DTCR4 DMAC_DTCR(4)
730#define DMAC_DRSR4 DMAC_DRSR(4)
731#define DMAC_DCCSR4 DMAC_DCCSR(4)
732#define DMAC_DCMD4 DMAC_DCMD(4)
733#define DMAC_DDA4 DMAC_DDA(4)
734
735/* channel 5 */
736#define DMAC_DSAR5 DMAC_DSAR(5)
737#define DMAC_DTAR5 DMAC_DTAR(5)
738#define DMAC_DTCR5 DMAC_DTCR(5)
739#define DMAC_DRSR5 DMAC_DRSR(5)
740#define DMAC_DCCSR5 DMAC_DCCSR(5)
741#define DMAC_DCMD5 DMAC_DCMD(5)
742#define DMAC_DDA5 DMAC_DDA(5)
743
744#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
745#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
746#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
747#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
748#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
749#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
750#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
751#define REG_DMAC_DMACR REG32(DMAC_DMACR)
752#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
753#define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
754#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
755
756/* DMA request source register */
757#define DMAC_DRSR_RS_BIT 0
758#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
759  #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
760  #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
761  #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
762  #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
763  #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
764  #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
765  #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
766  #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
767  #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
768  #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
769  #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
770  #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
771
772/* DMA channel control/status register */
773#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
774#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
775#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
776#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
777#define DMAC_DCCSR_AR (1 << 4) /* address error */
778#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
779#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
780#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
781#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
782
783/* DMA channel command register */
784#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
785#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
786#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
787#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
788  #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
789  #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
790  #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
791  #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
792  #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
793  #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
794  #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
795  #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
796  #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
797  #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
798  #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
799  #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
800  #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
801  #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
802  #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
803  #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
804#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
805#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
806  #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
807  #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
808  #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
809#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
810#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
811  #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
812  #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
813  #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
814#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
815#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
816  #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
817  #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
818  #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
819  #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
820  #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
821#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
822#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
823#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
824#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
825#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
826#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
827
828/* DMA descriptor address register */
829#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
830#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
831#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
832#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
833
834/* DMA control register */
835#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
836#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
837  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
838  #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
839  #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
840  #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
841#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
842#define DMAC_DMACR_AR (1 << 2) /* address error flag */
843#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
844
845/* DMA doorbell register */
846#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
847#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
848#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
849#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
850#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
851#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
852
853/* DMA doorbell set register */
854#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
855#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
856#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
857#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
858#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
859#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
860
861/* DMA interrupt pending register */
862#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
863#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
864#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
865#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
866#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
867#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
868
869
870/*************************************************************************
871 * GPIO (General-Purpose I/O Ports)
872 *************************************************************************/
873#define MAX_GPIO_NUM 128
874
875/*n = 0,1,2,3 */
876#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
877#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
878#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
879#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
880#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
881#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
882#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
883#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
884#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
885#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
886#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
887#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
888#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
889#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
890#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
891#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
892#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
893#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
894#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
895#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
896#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
897#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
898#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
899#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
900
901#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
902#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
903#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
904#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
905#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
906#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
907#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
908#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
909#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
910#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
911#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
912#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
913#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
914#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
915#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
916#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
917#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
918#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
919#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
920#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
921#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
922#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
923#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
924#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
925
926
927/*************************************************************************
928 * UART
929 *************************************************************************/
930
931#define IRDA_BASE UART0_BASE
932/*#define UART_BASE UART0_BASE */
933#define UART_OFF 0x1000
934
935/* Register Offset */
936#define OFF_RDR (0x00) /* R 8b H'xx */
937#define OFF_TDR (0x00) /* W 8b H'xx */
938#define OFF_DLLR (0x00) /* RW 8b H'00 */
939#define OFF_DLHR (0x04) /* RW 8b H'00 */
940#define OFF_IER (0x04) /* RW 8b H'00 */
941#define OFF_ISR (0x08) /* R 8b H'01 */
942#define OFF_FCR (0x08) /* W 8b H'00 */
943#define OFF_LCR (0x0C) /* RW 8b H'00 */
944#define OFF_MCR (0x10) /* RW 8b H'00 */
945#define OFF_LSR (0x14) /* R 8b H'00 */
946#define OFF_MSR (0x18) /* R 8b H'00 */
947#define OFF_SPR (0x1C) /* RW 8b H'00 */
948#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
949#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
950#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
951
952/* Register Address */
953#define UART0_RDR (UART0_BASE + OFF_RDR)
954#define UART0_TDR (UART0_BASE + OFF_TDR)
955#define UART0_DLLR (UART0_BASE + OFF_DLLR)
956#define UART0_DLHR (UART0_BASE + OFF_DLHR)
957#define UART0_IER (UART0_BASE + OFF_IER)
958#define UART0_ISR (UART0_BASE + OFF_ISR)
959#define UART0_FCR (UART0_BASE + OFF_FCR)
960#define UART0_LCR (UART0_BASE + OFF_LCR)
961#define UART0_MCR (UART0_BASE + OFF_MCR)
962#define UART0_LSR (UART0_BASE + OFF_LSR)
963#define UART0_MSR (UART0_BASE + OFF_MSR)
964#define UART0_SPR (UART0_BASE + OFF_SPR)
965#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
966#define UART0_UMR (UART0_BASE + OFF_UMR)
967#define UART0_UACR (UART0_BASE + OFF_UACR)
968
969/*
970 * Define macros for UART_IER
971 * UART Interrupt Enable Register
972 */
973#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
974#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
975#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
976#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
977#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
978
979/*
980 * Define macros for UART_ISR
981 * UART Interrupt Status Register
982 */
983#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
984#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
985#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
986#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
987#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
988#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
989#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
990#define UART_ISR_FFMS_NO_FIFO (0 << 6)
991#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
992
993/*
994 * Define macros for UART_FCR
995 * UART FIFO Control Register
996 */
997#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
998#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
999#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
1000#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
1001#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
1002#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
1003#define UART_FCR_RTRG_1 (0 << 6)
1004#define UART_FCR_RTRG_4 (1 << 6)
1005#define UART_FCR_RTRG_8 (2 << 6)
1006#define UART_FCR_RTRG_15 (3 << 6)
1007
1008/*
1009 * Define macros for UART_LCR
1010 * UART Line Control Register
1011 */
1012#define UART_LCR_WLEN (3 << 0) /* word length */
1013#define UART_LCR_WLEN_5 (0 << 0)
1014#define UART_LCR_WLEN_6 (1 << 0)
1015#define UART_LCR_WLEN_7 (2 << 0)
1016#define UART_LCR_WLEN_8 (3 << 0)
1017#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1018                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1019#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1020                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1021#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1022                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1023
1024#define UART_LCR_PE (1 << 3) /* 0: parity disable */
1025#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
1026#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
1027#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
1028#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
1029
1030/*
1031 * Define macros for UART_LSR
1032 * UART Line Status Register
1033 */
1034#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
1035#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
1036#define UART_LSR_PER (1 << 2) /* 0: no parity error */
1037#define UART_LSR_FER (1 << 3) /* 0; no framing error */
1038#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
1039#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
1040#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
1041#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
1042
1043/*
1044 * Define macros for UART_MCR
1045 * UART Modem Control Register
1046 */
1047#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
1048#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
1049#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
1050#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
1051#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
1052#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
1053
1054/*
1055 * Define macros for UART_MSR
1056 * UART Modem Status Register
1057 */
1058#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
1059#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
1060#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
1061#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
1062#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
1063#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
1064#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
1065#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
1066
1067/*
1068 * Define macros for SIRCR
1069 * Slow IrDA Control Register
1070 */
1071#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
1072#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
1073#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1074                       1: 0 pulse width is 1.6us for 115.2Kbps */
1075#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1076#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1077
1078
1079/*************************************************************************
1080 * AIC (AC97/I2S Controller)
1081 *************************************************************************/
1082#define AIC_FR (AIC_BASE + 0x000)
1083#define AIC_CR (AIC_BASE + 0x004)
1084#define AIC_ACCR1 (AIC_BASE + 0x008)
1085#define AIC_ACCR2 (AIC_BASE + 0x00C)
1086#define AIC_I2SCR (AIC_BASE + 0x010)
1087#define AIC_SR (AIC_BASE + 0x014)
1088#define AIC_ACSR (AIC_BASE + 0x018)
1089#define AIC_I2SSR (AIC_BASE + 0x01C)
1090#define AIC_ACCAR (AIC_BASE + 0x020)
1091#define AIC_ACCDR (AIC_BASE + 0x024)
1092#define AIC_ACSAR (AIC_BASE + 0x028)
1093#define AIC_ACSDR (AIC_BASE + 0x02C)
1094#define AIC_I2SDIV (AIC_BASE + 0x030)
1095#define AIC_DR (AIC_BASE + 0x034)
1096
1097#define REG_AIC_FR REG32(AIC_FR)
1098#define REG_AIC_CR REG32(AIC_CR)
1099#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1100#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1101#define REG_AIC_I2SCR REG32(AIC_I2SCR)
1102#define REG_AIC_SR REG32(AIC_SR)
1103#define REG_AIC_ACSR REG32(AIC_ACSR)
1104#define REG_AIC_I2SSR REG32(AIC_I2SSR)
1105#define REG_AIC_ACCAR REG32(AIC_ACCAR)
1106#define REG_AIC_ACCDR REG32(AIC_ACCDR)
1107#define REG_AIC_ACSAR REG32(AIC_ACSAR)
1108#define REG_AIC_ACSDR REG32(AIC_ACSDR)
1109#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1110#define REG_AIC_DR REG32(AIC_DR)
1111
1112/* AIC Controller Configuration Register (AIC_FR) */
1113
1114#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1115#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1116#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1117#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1118#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1119#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1120#define AIC_FR_RST (1 << 3) /* AIC registers reset */
1121#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1122#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1123#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1124
1125/* AIC Controller Common Control Register (AIC_CR) */
1126
1127#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1128#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1129  #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1130  #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1131  #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1132  #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1133  #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1134#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1135#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1136  #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1137  #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1138  #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1139  #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1140  #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1141#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1142#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1143#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1144#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1145#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1146#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1147#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1148#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1149#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1150#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1151#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1152#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1153#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1154
1155/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1156
1157#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1158#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1159  #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1160  #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1161  #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1162  #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1163  #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1164  #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1165  #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1166  #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1167  #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1168  #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1169#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1170#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1171  #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1172  #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1173  #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1174  #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1175  #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1176  #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1177  #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1178  #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1179  #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1180  #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1181
1182/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1183
1184#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1185#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1186#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1187#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1188#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1189  #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1190  #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1191  #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1192  #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1193#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1194#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1195  #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1196  #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1197  #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1198  #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1199#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1200#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1201#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1202#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1203
1204/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1205
1206#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1207#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1208#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1209  #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1210  #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1211  #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1212  #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1213  #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1214#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1215
1216/* AIC Controller FIFO Status Register (AIC_SR) */
1217
1218#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1219#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1220#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1221#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1222#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1223#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1224#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1225#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1226
1227/* AIC Controller AC-link Status Register (AIC_ACSR) */
1228
1229#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1230#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1231#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1232#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1233#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1234#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1235
1236/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1237
1238#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1239
1240/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1241
1242#define AIC_ACCAR_CAR_BIT 0
1243#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1244
1245/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1246
1247#define AIC_ACCDR_CDR_BIT 0
1248#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1249
1250/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1251
1252#define AIC_ACSAR_SAR_BIT 0
1253#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1254
1255/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1256
1257#define AIC_ACSDR_SDR_BIT 0
1258#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1259
1260/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1261
1262#define AIC_I2SDIV_DIV_BIT 0
1263#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1264  #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1265  #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1266  #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1267  #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1268  #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1269  #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1270
1271
1272/*************************************************************************
1273 * ICDC (Internal CODEC)
1274 *************************************************************************/
1275#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1276#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1277#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1278#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1279#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1280#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1281#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1282
1283#define REG_ICDC_CR REG32(ICDC_CR)
1284#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1285#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1286#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1287#define REG_ICDC_APSR REG32(ICDC_APSR)
1288#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1289#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1290
1291/* ICDC Control Register */
1292#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1293#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1294#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1295#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1296  #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1297  #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1298  #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1299  #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1300  #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1301  #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1302  #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1303  #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1304  #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1305#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1306#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1307  #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1308  #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1309  #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1310  #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1311#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1312#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1313  #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1314  #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1315  #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1316  #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1317#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1318#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1319#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1320#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1321#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1322#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1323#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1324#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1325#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1326#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1327#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1328#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1329
1330/* Anti-Pop WAIT Stage Timing Control Register */
1331#define ICDC_APWAIT_WAITSN_BIT 0
1332#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1333
1334/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1335#define ICDC_APPRE_PRESN_BIT 0
1336#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1337
1338/* Anti-Pop HPEN Stage Timing Control Register */
1339#define ICDC_APHPEN_HPENSN_BIT 0
1340#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1341
1342/* Anti-Pop Status Register */
1343#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1344#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1345#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1346#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1347  #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1348#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1349  #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1350  #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1351  #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1352  #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1353#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1354#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1355
1356
1357/*************************************************************************
1358 * I2C
1359 *************************************************************************/
1360#define I2C_DR (I2C_BASE + 0x000)
1361#define I2C_CR (I2C_BASE + 0x004)
1362#define I2C_SR (I2C_BASE + 0x008)
1363#define I2C_GR (I2C_BASE + 0x00C)
1364
1365#define REG_I2C_DR REG8(I2C_DR)
1366#define REG_I2C_CR REG8(I2C_CR)
1367#define REG_I2C_SR REG8(I2C_SR)
1368#define REG_I2C_GR REG16(I2C_GR)
1369
1370/* I2C Control Register (I2C_CR) */
1371
1372#define I2C_CR_IEN (1 << 4)
1373#define I2C_CR_STA (1 << 3)
1374#define I2C_CR_STO (1 << 2)
1375#define I2C_CR_AC (1 << 1)
1376#define I2C_CR_I2CE (1 << 0)
1377
1378/* I2C Status Register (I2C_SR) */
1379
1380#define I2C_SR_STX (1 << 4)
1381#define I2C_SR_BUSY (1 << 3)
1382#define I2C_SR_TEND (1 << 2)
1383#define I2C_SR_DRF (1 << 1)
1384#define I2C_SR_ACKF (1 << 0)
1385
1386
1387/*************************************************************************
1388 * SSI
1389 *************************************************************************/
1390#define SSI_DR (SSI_BASE + 0x000)
1391#define SSI_CR0 (SSI_BASE + 0x004)
1392#define SSI_CR1 (SSI_BASE + 0x008)
1393#define SSI_SR (SSI_BASE + 0x00C)
1394#define SSI_ITR (SSI_BASE + 0x010)
1395#define SSI_ICR (SSI_BASE + 0x014)
1396#define SSI_GR (SSI_BASE + 0x018)
1397
1398#define REG_SSI_DR REG32(SSI_DR)
1399#define REG_SSI_CR0 REG16(SSI_CR0)
1400#define REG_SSI_CR1 REG32(SSI_CR1)
1401#define REG_SSI_SR REG32(SSI_SR)
1402#define REG_SSI_ITR REG16(SSI_ITR)
1403#define REG_SSI_ICR REG8(SSI_ICR)
1404#define REG_SSI_GR REG16(SSI_GR)
1405
1406/* SSI Data Register (SSI_DR) */
1407
1408#define SSI_DR_GPC_BIT 0
1409#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1410
1411/* SSI Control Register 0 (SSI_CR0) */
1412
1413#define SSI_CR0_SSIE (1 << 15)
1414#define SSI_CR0_TIE (1 << 14)
1415#define SSI_CR0_RIE (1 << 13)
1416#define SSI_CR0_TEIE (1 << 12)
1417#define SSI_CR0_REIE (1 << 11)
1418#define SSI_CR0_LOOP (1 << 10)
1419#define SSI_CR0_RFINE (1 << 9)
1420#define SSI_CR0_RFINC (1 << 8)
1421#define SSI_CR0_FSEL (1 << 6)
1422#define SSI_CR0_TFLUSH (1 << 2)
1423#define SSI_CR0_RFLUSH (1 << 1)
1424#define SSI_CR0_DISREV (1 << 0)
1425
1426/* SSI Control Register 1 (SSI_CR1) */
1427
1428#define SSI_CR1_FRMHL_BIT 30
1429#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1430  #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1431  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1432  #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1433  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1434#define SSI_CR1_TFVCK_BIT 28
1435#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1436  #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1437  #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1438  #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1439  #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1440#define SSI_CR1_TCKFI_BIT 26
1441#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1442  #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1443  #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1444  #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1445  #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1446#define SSI_CR1_LFST (1 << 25)
1447#define SSI_CR1_ITFRM (1 << 24)
1448#define SSI_CR1_UNFIN (1 << 23)
1449#define SSI_CR1_MULTS (1 << 22)
1450#define SSI_CR1_FMAT_BIT 20
1451#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1452  #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1453  #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1454  #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1455  #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1456#define SSI_CR1_TTRG_BIT 16
1457#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
1458  #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
1459  #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
1460  #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
1461  #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
1462  #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
1463  #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
1464  #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
1465  #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
1466  #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
1467  #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
1468  #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
1469  #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
1470  #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
1471  #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
1472  #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
1473  #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
1474#define SSI_CR1_MCOM_BIT 12
1475#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1476  #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1477  #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1478  #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1479  #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1480  #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1481  #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1482  #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1483  #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1484  #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1485  #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1486  #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1487  #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1488  #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1489  #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1490  #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1491  #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1492#define SSI_CR1_RTRG_BIT 8
1493#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
1494  #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
1495  #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
1496  #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
1497  #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
1498  #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
1499  #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
1500  #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
1501  #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
1502  #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
1503  #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
1504  #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
1505  #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
1506  #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
1507  #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
1508  #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
1509  #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
1510#define SSI_CR1_FLEN_BIT 4
1511#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1512  #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1513  #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1514  #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1515  #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1516  #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1517  #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1518  #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1519  #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1520  #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1521  #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1522  #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1523  #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1524  #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1525  #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1526  #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1527  #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1528#define SSI_CR1_PHA (1 << 1)
1529#define SSI_CR1_POL (1 << 0)
1530
1531/* SSI Status Register (SSI_SR) */
1532
1533#define SSI_SR_TFIFONUM_BIT 16
1534#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1535#define SSI_SR_RFIFONUM_BIT 8
1536#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1537#define SSI_SR_END (1 << 7)
1538#define SSI_SR_BUSY (1 << 6)
1539#define SSI_SR_TFF (1 << 5)
1540#define SSI_SR_RFE (1 << 4)
1541#define SSI_SR_TFHE (1 << 3)
1542#define SSI_SR_RFHF (1 << 2)
1543#define SSI_SR_UNDR (1 << 1)
1544#define SSI_SR_OVER (1 << 0)
1545
1546/* SSI Interval Time Control Register (SSI_ITR) */
1547
1548#define SSI_ITR_CNTCLK (1 << 15)
1549#define SSI_ITR_IVLTM_BIT 0
1550#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1551
1552
1553/*************************************************************************
1554 * MSC
1555 *************************************************************************/
1556#define MSC_STRPCL (MSC_BASE + 0x000)
1557#define MSC_STAT (MSC_BASE + 0x004)
1558#define MSC_CLKRT (MSC_BASE + 0x008)
1559#define MSC_CMDAT (MSC_BASE + 0x00C)
1560#define MSC_RESTO (MSC_BASE + 0x010)
1561#define MSC_RDTO (MSC_BASE + 0x014)
1562#define MSC_BLKLEN (MSC_BASE + 0x018)
1563#define MSC_NOB (MSC_BASE + 0x01C)
1564#define MSC_SNOB (MSC_BASE + 0x020)
1565#define MSC_IMASK (MSC_BASE + 0x024)
1566#define MSC_IREG (MSC_BASE + 0x028)
1567#define MSC_CMD (MSC_BASE + 0x02C)
1568#define MSC_ARG (MSC_BASE + 0x030)
1569#define MSC_RES (MSC_BASE + 0x034)
1570#define MSC_RXFIFO (MSC_BASE + 0x038)
1571#define MSC_TXFIFO (MSC_BASE + 0x03C)
1572
1573#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1574#define REG_MSC_STAT REG32(MSC_STAT)
1575#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1576#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1577#define REG_MSC_RESTO REG16(MSC_RESTO)
1578#define REG_MSC_RDTO REG16(MSC_RDTO)
1579#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1580#define REG_MSC_NOB REG16(MSC_NOB)
1581#define REG_MSC_SNOB REG16(MSC_SNOB)
1582#define REG_MSC_IMASK REG16(MSC_IMASK)
1583#define REG_MSC_IREG REG16(MSC_IREG)
1584#define REG_MSC_CMD REG8(MSC_CMD)
1585#define REG_MSC_ARG REG32(MSC_ARG)
1586#define REG_MSC_RES REG16(MSC_RES)
1587#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1588#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1589
1590/* MSC Clock and Control Register (MSC_STRPCL) */
1591
1592#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1593#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1594#define MSC_STRPCL_START_READWAIT (1 << 5)
1595#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1596#define MSC_STRPCL_RESET (1 << 3)
1597#define MSC_STRPCL_START_OP (1 << 2)
1598#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1599#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1600  #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1601  #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1602
1603/* MSC Status Register (MSC_STAT) */
1604
1605#define MSC_STAT_IS_RESETTING (1 << 15)
1606#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1607#define MSC_STAT_PRG_DONE (1 << 13)
1608#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1609#define MSC_STAT_END_CMD_RES (1 << 11)
1610#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1611#define MSC_STAT_IS_READWAIT (1 << 9)
1612#define MSC_STAT_CLK_EN (1 << 8)
1613#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1614#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1615#define MSC_STAT_CRC_RES_ERR (1 << 5)
1616#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1617#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1618#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1619  #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1620  #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1621  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1622#define MSC_STAT_TIME_OUT_RES (1 << 1)
1623#define MSC_STAT_TIME_OUT_READ (1 << 0)
1624
1625/* MSC Bus Clock Control Register (MSC_CLKRT) */
1626
1627#define MSC_CLKRT_CLK_RATE_BIT 0
1628#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1629  #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1630  #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1631  #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1632  #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1633  #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1634  #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1635  #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1636  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1637
1638/* MSC Command Sequence Control Register (MSC_CMDAT) */
1639
1640#define MSC_CMDAT_IO_ABORT (1 << 11)
1641#define MSC_CMDAT_BUS_WIDTH_BIT 9
1642#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1643  #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1644  #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1645  #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1646  #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1647#define MSC_CMDAT_DMA_EN (1 << 8)
1648#define MSC_CMDAT_INIT (1 << 7)
1649#define MSC_CMDAT_BUSY (1 << 6)
1650#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1651#define MSC_CMDAT_WRITE (1 << 4)
1652#define MSC_CMDAT_READ (0 << 4)
1653#define MSC_CMDAT_DATA_EN (1 << 3)
1654#define MSC_CMDAT_RESPONSE_BIT 0
1655#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1656  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1657  #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1658  #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1659  #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1660  #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1661  #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1662  #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1663
1664#define CMDAT_DMA_EN (1 << 8)
1665#define CMDAT_INIT (1 << 7)
1666#define CMDAT_BUSY (1 << 6)
1667#define CMDAT_STREAM (1 << 5)
1668#define CMDAT_WRITE (1 << 4)
1669#define CMDAT_DATA_EN (1 << 3)
1670
1671/* MSC Interrupts Mask Register (MSC_IMASK) */
1672
1673#define MSC_IMASK_SDIO (1 << 7)
1674#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1675#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1676#define MSC_IMASK_END_CMD_RES (1 << 2)
1677#define MSC_IMASK_PRG_DONE (1 << 1)
1678#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1679
1680
1681/* MSC Interrupts Status Register (MSC_IREG) */
1682
1683#define MSC_IREG_SDIO (1 << 7)
1684#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1685#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1686#define MSC_IREG_END_CMD_RES (1 << 2)
1687#define MSC_IREG_PRG_DONE (1 << 1)
1688#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1689
1690
1691/*************************************************************************
1692 * EMC (External Memory Controller)
1693 *************************************************************************/
1694#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
1695
1696#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1697#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1698#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1699#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1700#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1701#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1702#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1703#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1704#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1705#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1706
1707#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1708#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
1709#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
1710#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
1711#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
1712#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
1713#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
1714#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
1715#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
1716#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
1717#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
1718#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
1719
1720#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1721#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1722#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1723#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1724#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1725#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
1726
1727#define REG_EMC_BCR REG32(EMC_BCR)
1728
1729#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1730#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1731#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1732#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1733#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1734#define REG_EMC_SACR0 REG32(EMC_SACR0)
1735#define REG_EMC_SACR1 REG32(EMC_SACR1)
1736#define REG_EMC_SACR2 REG32(EMC_SACR2)
1737#define REG_EMC_SACR3 REG32(EMC_SACR3)
1738#define REG_EMC_SACR4 REG32(EMC_SACR4)
1739
1740#define REG_EMC_NFCSR REG32(EMC_NFCSR)
1741#define REG_EMC_NFECR REG32(EMC_NFECR)
1742#define REG_EMC_NFECC REG32(EMC_NFECC)
1743#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
1744#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
1745#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
1746#define REG_EMC_NFINTS REG32(EMC_NFINTS)
1747#define REG_EMC_NFINTE REG32(EMC_NFINTE)
1748#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
1749#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
1750#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
1751#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
1752
1753#define REG_EMC_DMCR REG32(EMC_DMCR)
1754#define REG_EMC_RTCSR REG16(EMC_RTCSR)
1755#define REG_EMC_RTCNT REG16(EMC_RTCNT)
1756#define REG_EMC_RTCOR REG16(EMC_RTCOR)
1757#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1758
1759/* Static Memory Control Register */
1760#define EMC_SMCR_STRV_BIT 24
1761#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1762#define EMC_SMCR_TAW_BIT 20
1763#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1764#define EMC_SMCR_TBP_BIT 16
1765#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1766#define EMC_SMCR_TAH_BIT 12
1767#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1768#define EMC_SMCR_TAS_BIT 8
1769#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1770#define EMC_SMCR_BW_BIT 6
1771#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1772  #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1773  #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1774  #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1775#define EMC_SMCR_BCM (1 << 3)
1776#define EMC_SMCR_BL_BIT 1
1777#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1778  #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1779  #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1780  #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1781  #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1782#define EMC_SMCR_SMT (1 << 0)
1783
1784/* Static Memory Bank Addr Config Reg */
1785#define EMC_SACR_BASE_BIT 8
1786#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1787#define EMC_SACR_MASK_BIT 0
1788#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1789
1790/* NAND Flash Control/Status Register */
1791#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1792#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1793#define EMC_NFCSR_NFCE3 (1 << 5)
1794#define EMC_NFCSR_NFE3 (1 << 4)
1795#define EMC_NFCSR_NFCE2 (1 << 3)
1796#define EMC_NFCSR_NFE2 (1 << 2)
1797#define EMC_NFCSR_NFCE1 (1 << 1)
1798#define EMC_NFCSR_NFE1 (1 << 0)
1799
1800/* NAND Flash ECC Control Register */
1801#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
1802#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
1803#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
1804#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
1805#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
1806#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
1807#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
1808
1809/* NAND Flash ECC Data Register */
1810#define EMC_NFECC_ECC2_BIT 16
1811#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1812#define EMC_NFECC_ECC1_BIT 8
1813#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1814#define EMC_NFECC_ECC0_BIT 0
1815#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1816
1817/* NAND Flash Interrupt Status Register */
1818#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
1819#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
1820#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
1821#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
1822#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
1823#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
1824#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
1825
1826/* NAND Flash Interrupt Enable Register */
1827#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
1828#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
1829#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
1830#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
1831#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
1832
1833/* NAND Flash RS Error Report Register */
1834#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
1835#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
1836#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
1837#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
1838
1839
1840/* DRAM Control Register */
1841#define EMC_DMCR_BW_BIT 31
1842#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1843#define EMC_DMCR_CA_BIT 26
1844#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1845  #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1846  #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1847  #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1848  #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1849  #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1850#define EMC_DMCR_RMODE (1 << 25)
1851#define EMC_DMCR_RFSH (1 << 24)
1852#define EMC_DMCR_MRSET (1 << 23)
1853#define EMC_DMCR_RA_BIT 20
1854#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1855  #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1856  #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1857  #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1858#define EMC_DMCR_BA_BIT 19
1859#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1860#define EMC_DMCR_PDM (1 << 18)
1861#define EMC_DMCR_EPIN (1 << 17)
1862#define EMC_DMCR_TRAS_BIT 13
1863#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1864#define EMC_DMCR_RCD_BIT 11
1865#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1866#define EMC_DMCR_TPC_BIT 8
1867#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1868#define EMC_DMCR_TRWL_BIT 5
1869#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1870#define EMC_DMCR_TRC_BIT 2
1871#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1872#define EMC_DMCR_TCL_BIT 0
1873#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1874
1875/* Refresh Time Control/Status Register */
1876#define EMC_RTCSR_CMF (1 << 7)
1877#define EMC_RTCSR_CKS_BIT 0
1878#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1879  #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1880  #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1881  #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1882  #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1883  #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1884  #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1885  #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1886  #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1887
1888/* SDRAM Bank Address Configuration Register */
1889#define EMC_DMAR_BASE_BIT 8
1890#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1891#define EMC_DMAR_MASK_BIT 0
1892#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1893
1894/* Mode Register of SDRAM bank 0 */
1895#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1896#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1897#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1898  #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1899#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1900#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1901  #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1902  #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1903  #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1904#define EMC_SDMR_BT_BIT 3 /* Burst Type */
1905#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1906  #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1907  #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1908#define EMC_SDMR_BL_BIT 0 /* Burst Length */
1909#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1910  #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1911  #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1912  #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1913  #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1914
1915#define EMC_SDMR_CAS2_16BIT \
1916  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1917#define EMC_SDMR_CAS2_32BIT \
1918  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1919#define EMC_SDMR_CAS3_16BIT \
1920  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1921#define EMC_SDMR_CAS3_32BIT \
1922  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1923
1924
1925/*************************************************************************
1926 * CIM
1927 *************************************************************************/
1928#define CIM_CFG (CIM_BASE + 0x0000)
1929#define CIM_CTRL (CIM_BASE + 0x0004)
1930#define CIM_STATE (CIM_BASE + 0x0008)
1931#define CIM_IID (CIM_BASE + 0x000C)
1932#define CIM_RXFIFO (CIM_BASE + 0x0010)
1933#define CIM_DA (CIM_BASE + 0x0020)
1934#define CIM_FA (CIM_BASE + 0x0024)
1935#define CIM_FID (CIM_BASE + 0x0028)
1936#define CIM_CMD (CIM_BASE + 0x002C)
1937
1938#define REG_CIM_CFG REG32(CIM_CFG)
1939#define REG_CIM_CTRL REG32(CIM_CTRL)
1940#define REG_CIM_STATE REG32(CIM_STATE)
1941#define REG_CIM_IID REG32(CIM_IID)
1942#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1943#define REG_CIM_DA REG32(CIM_DA)
1944#define REG_CIM_FA REG32(CIM_FA)
1945#define REG_CIM_FID REG32(CIM_FID)
1946#define REG_CIM_CMD REG32(CIM_CMD)
1947
1948/* CIM Configuration Register (CIM_CFG) */
1949
1950#define CIM_CFG_INV_DAT (1 << 15)
1951#define CIM_CFG_VSP (1 << 14)
1952#define CIM_CFG_HSP (1 << 13)
1953#define CIM_CFG_PCP (1 << 12)
1954#define CIM_CFG_DUMMY_ZERO (1 << 9)
1955#define CIM_CFG_EXT_VSYNC (1 << 8)
1956#define CIM_CFG_PACK_BIT 4
1957#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1958  #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1959  #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1960  #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1961  #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1962  #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1963  #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1964  #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1965  #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1966#define CIM_CFG_DSM_BIT 0
1967#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1968  #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1969  #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1970  #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1971  #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1972
1973/* CIM Control Register (CIM_CTRL) */
1974
1975#define CIM_CTRL_MCLKDIV_BIT 24
1976#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1977#define CIM_CTRL_FRC_BIT 16
1978#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1979  #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1980  #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1981  #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1982  #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1983  #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1984  #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1985  #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1986  #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1987  #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1988  #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1989  #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1990  #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1991  #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1992  #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1993  #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1994  #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1995#define CIM_CTRL_VDDM (1 << 13)
1996#define CIM_CTRL_DMA_SOFM (1 << 12)
1997#define CIM_CTRL_DMA_EOFM (1 << 11)
1998#define CIM_CTRL_DMA_STOPM (1 << 10)
1999#define CIM_CTRL_RXF_TRIGM (1 << 9)
2000#define CIM_CTRL_RXF_OFM (1 << 8)
2001#define CIM_CTRL_RXF_TRIG_BIT 4
2002#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
2003  #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
2004  #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
2005  #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
2006  #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
2007  #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
2008  #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
2009  #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
2010  #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
2011#define CIM_CTRL_DMA_EN (1 << 2)
2012#define CIM_CTRL_RXF_RST (1 << 1)
2013#define CIM_CTRL_ENA (1 << 0)
2014
2015/* CIM State Register (CIM_STATE) */
2016
2017#define CIM_STATE_DMA_SOF (1 << 6)
2018#define CIM_STATE_DMA_EOF (1 << 5)
2019#define CIM_STATE_DMA_STOP (1 << 4)
2020#define CIM_STATE_RXF_OF (1 << 3)
2021#define CIM_STATE_RXF_TRIG (1 << 2)
2022#define CIM_STATE_RXF_EMPTY (1 << 1)
2023#define CIM_STATE_VDD (1 << 0)
2024
2025/* CIM DMA Command Register (CIM_CMD) */
2026
2027#define CIM_CMD_SOFINT (1 << 31)
2028#define CIM_CMD_EOFINT (1 << 30)
2029#define CIM_CMD_STOP (1 << 28)
2030#define CIM_CMD_LEN_BIT 0
2031#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
2032
2033
2034/*************************************************************************
2035 * SADC (Smart A/D Controller)
2036 *************************************************************************/
2037
2038#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
2039#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
2040#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
2041#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
2042#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
2043#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
2044#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
2045#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
2046#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
2047
2048#define REG_SADC_ENA REG8(SADC_ENA)
2049#define REG_SADC_CFG REG32(SADC_CFG)
2050#define REG_SADC_CTRL REG8(SADC_CTRL)
2051#define REG_SADC_STATE REG8(SADC_STATE)
2052#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
2053#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
2054#define REG_SADC_TSDAT REG32(SADC_TSDAT)
2055#define REG_SADC_BATDAT REG16(SADC_BATDAT)
2056#define REG_SADC_SADDAT REG16(SADC_SADDAT)
2057
2058/* ADC Enable Register */
2059#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
2060#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
2061#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
2062#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
2063
2064/* ADC Configure Register */
2065#define SADC_CFG_CLKOUT_NUM_BIT 16
2066#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
2067#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
2068#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
2069#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
2070  #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
2071  #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
2072  #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
2073#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
2074#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
2075  #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
2076  #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
2077  #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
2078  #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
2079  #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
2080  #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
2081  #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
2082  #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
2083#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
2084#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
2085#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
2086#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
2087#define SADC_CFG_CMD_BIT 0 /* ADC Command */
2088#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
2089  #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
2090  #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
2091  #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
2092  #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
2093  #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
2094  #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
2095  #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
2096  #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
2097  #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
2098  #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
2099  #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
2100  #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
2101  #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
2102
2103/* ADC Control Register */
2104#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
2105#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
2106#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
2107#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
2108#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
2109
2110/* ADC Status Register */
2111#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
2112#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
2113#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
2114#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
2115#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
2116#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
2117#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
2118#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
2119
2120/* ADC Touch Screen Data Register */
2121#define SADC_TSDAT_DATA0_BIT 0
2122#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
2123#define SADC_TSDAT_TYPE0 (1 << 15)
2124#define SADC_TSDAT_DATA1_BIT 16
2125#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
2126#define SADC_TSDAT_TYPE1 (1 << 31)
2127
2128
2129/*************************************************************************
2130 * SLCD (Smart LCD Controller)
2131 *************************************************************************/
2132
2133#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2134#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2135#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2136#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2137#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
2138
2139#define REG_SLCD_CFG REG32(SLCD_CFG)
2140#define REG_SLCD_CTRL REG8(SLCD_CTRL)
2141#define REG_SLCD_STATE REG8(SLCD_STATE)
2142#define REG_SLCD_DATA REG32(SLCD_DATA)
2143#define REG_SLCD_FIFO REG32(SLCD_FIFO)
2144
2145/* SLCD Configure Register */
2146#define SLCD_CFG_BURST_BIT 14
2147#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2148  #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2149  #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2150#define SLCD_CFG_DWIDTH_BIT 10
2151#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2152  #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2153  #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2154  #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2155  #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2156  #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
2157#define SLCD_CFG_CWIDTH_16BIT (0 << 8)
2158#define SLCD_CFG_CWIDTH_8BIT (1 << 8)
2159#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2160#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2161#define SLCD_CFG_RS_CMD_LOW (0 << 3)
2162#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2163#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2164#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2165#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2166#define SLCD_CFG_TYPE_SERIAL (1 << 0)
2167
2168/* SLCD Control Register */
2169#define SLCD_CTRL_DMA_EN (1 << 0)
2170
2171/* SLCD Status Register */
2172#define SLCD_STATE_BUSY (1 << 0)
2173
2174/* SLCD Data Register */
2175#define SLCD_DATA_RS_DATA (0 << 31)
2176#define SLCD_DATA_RS_COMMAND (1 << 31)
2177
2178/* SLCD FIFO Register */
2179#define SLCD_FIFO_RS_DATA (0 << 31)
2180#define SLCD_FIFO_RS_COMMAND (1 << 31)
2181
2182
2183/*************************************************************************
2184 * LCD (LCD Controller)
2185 *************************************************************************/
2186#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2187#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2188#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2189#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2190#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2191#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2192#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2193#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2194#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2195#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2196#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2197#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2198#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2199#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2200#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2201#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2202#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2203#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2204#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2205#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2206#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2207
2208#define REG_LCD_CFG REG32(LCD_CFG)
2209#define REG_LCD_VSYNC REG32(LCD_VSYNC)
2210#define REG_LCD_HSYNC REG32(LCD_HSYNC)
2211#define REG_LCD_VAT REG32(LCD_VAT)
2212#define REG_LCD_DAH REG32(LCD_DAH)
2213#define REG_LCD_DAV REG32(LCD_DAV)
2214#define REG_LCD_PS REG32(LCD_PS)
2215#define REG_LCD_CLS REG32(LCD_CLS)
2216#define REG_LCD_SPL REG32(LCD_SPL)
2217#define REG_LCD_REV REG32(LCD_REV)
2218#define REG_LCD_CTRL REG32(LCD_CTRL)
2219#define REG_LCD_STATE REG32(LCD_STATE)
2220#define REG_LCD_IID REG32(LCD_IID)
2221#define REG_LCD_DA0 REG32(LCD_DA0)
2222#define REG_LCD_SA0 REG32(LCD_SA0)
2223#define REG_LCD_FID0 REG32(LCD_FID0)
2224#define REG_LCD_CMD0 REG32(LCD_CMD0)
2225#define REG_LCD_DA1 REG32(LCD_DA1)
2226#define REG_LCD_SA1 REG32(LCD_SA1)
2227#define REG_LCD_FID1 REG32(LCD_FID1)
2228#define REG_LCD_CMD1 REG32(LCD_CMD1)
2229
2230/* LCD Configure Register */
2231#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2232#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2233  #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2234  #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2235#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2236#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2237#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2238#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2239#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2240#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2241#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2242#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2243#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2244#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2245#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2246#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2247#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2248#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2249#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2250#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2251#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2252#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2253#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2254  #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2255  #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2256  #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2257#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2258#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2259  #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2260  #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2261  #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2262  #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2263  #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2264  #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT)
2265  #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2266  #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2267  #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2268  #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2269  #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2270  #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT)
2271  /* JZ47XX defines */
2272  #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2273  #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2274  #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2275
2276
2277
2278/* Vertical Synchronize Register */
2279#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2280#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2281#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2282#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2283
2284/* Horizontal Synchronize Register */
2285#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2286#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2287#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2288#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2289
2290/* Virtual Area Setting Register */
2291#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2292#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2293#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2294#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2295
2296/* Display Area Horizontal Start/End Point Register */
2297#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2298#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2299#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2300#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2301
2302/* Display Area Vertical Start/End Point Register */
2303#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2304#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2305#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2306#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2307
2308/* PS Signal Setting */
2309#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2310#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2311#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2312#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2313
2314/* CLS Signal Setting */
2315#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2316#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2317#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2318#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2319
2320/* SPL Signal Setting */
2321#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2322#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2323#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2324#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2325
2326/* REV Signal Setting */
2327#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2328#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2329
2330/* LCD Control Register */
2331#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2332#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2333  #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2334  #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2335  #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2336#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
2337#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
2338#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2339#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2340#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2341  #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2342  #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2343  #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2344#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2345#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2346#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2347#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2348#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2349#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2350#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2351#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2352#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2353#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2354#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2355#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2356#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2357#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2358#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2359  #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2360  #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2361  #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2362  #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2363  #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2364  #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2365
2366/* LCD Status Register */
2367#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2368#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2369#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2370#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2371#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2372#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2373#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2374
2375/* DMA Command Register */
2376#define LCD_CMD_SOFINT (1 << 31)
2377#define LCD_CMD_EOFINT (1 << 30)
2378#define LCD_CMD_PAL (1 << 28)
2379#define LCD_CMD_LEN_BIT 0
2380#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
2381
2382
2383/*************************************************************************
2384 * USB Device
2385 *************************************************************************/
2386#define USB_BASE UDC_BASE
2387
2388#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2389#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2390#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2391#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2392#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2393#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2394#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2395#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2396#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2397#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2398#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2399
2400#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2401#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2402#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2403#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2404#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2405#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2406#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2407#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2408
2409#define USB_FIFO_EP0 (USB_BASE + 0x20)
2410#define USB_FIFO_EP1 (USB_BASE + 0x24)
2411#define USB_FIFO_EP2 (USB_BASE + 0x28)
2412
2413#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2414#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2415
2416#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
2417#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
2418#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
2419#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
2420#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
2421#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
2422#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
2423
2424
2425/* Power register bit masks */
2426#define USB_POWER_SUSPENDM 0x01
2427#define USB_POWER_RESUME 0x04
2428#define USB_POWER_HSMODE 0x10
2429#define USB_POWER_HSENAB 0x20
2430#define USB_POWER_SOFTCONN 0x40
2431
2432/* Interrupt register bit masks */
2433#define USB_INTR_SUSPEND 0x01
2434#define USB_INTR_RESUME 0x02
2435#define USB_INTR_RESET 0x04
2436
2437#define USB_INTR_EP0 0x0001
2438#define USB_INTR_INEP1 0x0002
2439#define USB_INTR_INEP2 0x0004
2440#define USB_INTR_OUTEP1 0x0002
2441
2442/* CSR0 bit masks */
2443#define USB_CSR0_OUTPKTRDY 0x01
2444#define USB_CSR0_INPKTRDY 0x02
2445#define USB_CSR0_SENTSTALL 0x04
2446#define USB_CSR0_DATAEND 0x08
2447#define USB_CSR0_SETUPEND 0x10
2448#define USB_CSR0_SENDSTALL 0x20
2449#define USB_CSR0_SVDOUTPKTRDY 0x40
2450#define USB_CSR0_SVDSETUPEND 0x80
2451
2452/* Endpoint CSR register bits */
2453#define USB_INCSRH_AUTOSET 0x80
2454#define USB_INCSRH_ISO 0x40
2455#define USB_INCSRH_MODE 0x20
2456#define USB_INCSRH_DMAREQENAB 0x10
2457#define USB_INCSRH_DMAREQMODE 0x04
2458#define USB_INCSR_CDT 0x40
2459#define USB_INCSR_SENTSTALL 0x20
2460#define USB_INCSR_SENDSTALL 0x10
2461#define USB_INCSR_FF 0x08
2462#define USB_INCSR_UNDERRUN 0x04
2463#define USB_INCSR_FFNOTEMPT 0x02
2464#define USB_INCSR_INPKTRDY 0x01
2465#define USB_OUTCSRH_AUTOCLR 0x80
2466#define USB_OUTCSRH_ISO 0x40
2467#define USB_OUTCSRH_DMAREQENAB 0x20
2468#define USB_OUTCSRH_DNYT 0x10
2469#define USB_OUTCSRH_DMAREQMODE 0x08
2470#define USB_OUTCSR_CDT 0x80
2471#define USB_OUTCSR_SENTSTALL 0x40
2472#define USB_OUTCSR_SENDSTALL 0x20
2473#define USB_OUTCSR_FF 0x10
2474#define USB_OUTCSR_DATAERR 0x08
2475#define USB_OUTCSR_OVERRUN 0x04
2476#define USB_OUTCSR_FFFULL 0x02
2477#define USB_OUTCSR_OUTPKTRDY 0x01
2478
2479/* Testmode register bits */
2480#define USB_TEST_SE0NAK 0x01
2481#define USB_TEST_J 0x02
2482#define USB_TEST_K 0x04
2483#define USB_TEST_PACKET 0x08
2484
2485/* DMA control bits */
2486#define USB_CNTL_ENA 0x01
2487#define USB_CNTL_DIR_IN 0x02
2488#define USB_CNTL_MODE_1 0x04
2489#define USB_CNTL_INTR_EN 0x08
2490#define USB_CNTL_EP(n) ((n) << 4)
2491#define USB_CNTL_BURST_0 (0 << 9)
2492#define USB_CNTL_BURST_4 (1 << 9)
2493#define USB_CNTL_BURST_8 (2 << 9)
2494#define USB_CNTL_BURST_16 (3 << 9)
2495
2496
2497/* Module Operation Definitions */
2498#ifndef __ASSEMBLY__
2499
2500/***************************************************************************
2501 * GPIO
2502 ***************************************************************************/
2503
2504//------------------------------------------------------
2505// GPIO Pins Description
2506//
2507// PORT 0:
2508//
2509// PIN/BIT N FUNC0 FUNC1
2510// 0 D0 -
2511// 1 D1 -
2512// 2 D2 -
2513// 3 D3 -
2514// 4 D4 -
2515// 5 D5 -
2516// 6 D6 -
2517// 7 D7 -
2518// 8 D8 -
2519// 9 D9 -
2520// 10 D10 -
2521// 11 D11 -
2522// 12 D12 -
2523// 13 D13 -
2524// 14 D14 -
2525// 15 D15 -
2526// 16 D16 -
2527// 17 D17 -
2528// 18 D18 -
2529// 19 D19 -
2530// 20 D20 -
2531// 21 D21 -
2532// 22 D22 -
2533// 23 D23 -
2534// 24 D24 -
2535// 25 D25 -
2536// 26 D26 -
2537// 27 D27 -
2538// 28 D28 -
2539// 29 D29 -
2540// 30 D30 -
2541// 31 D31 -
2542//
2543//------------------------------------------------------
2544// PORT 1:
2545//
2546// PIN/BIT N FUNC0 FUNC1
2547// 0 A0 -
2548// 1 A1 -
2549// 2 A2 -
2550// 3 A3 -
2551// 4 A4 -
2552// 5 A5 -
2553// 6 A6 -
2554// 7 A7 -
2555// 8 A8 -
2556// 9 A9 -
2557// 10 A10 -
2558// 11 A11 -
2559// 12 A12 -
2560// 13 A13 -
2561// 14 A14 -
2562// 15 A15/CL -
2563// 16 A16/AL -
2564// 17 LCD_CLS A21
2565// 18 LCD_SPL A22
2566// 19 DCS# -
2567// 20 RAS# -
2568// 21 CAS# -
2569// 22 RDWE#/BUFD# -
2570// 23 CKE -
2571// 24 CKO -
2572// 25 CS1# -
2573// 26 CS2# -
2574// 27 CS3# -
2575// 28 CS4# -
2576// 29 RD# -
2577// 30 WR# -
2578// 31 WE0# -
2579//
2580// Note: PIN15&16 are CL&AL when connecting to NAND flash.
2581//------------------------------------------------------
2582// PORT 2:
2583//
2584// PIN/BIT N FUNC0 FUNC1
2585// 0 LCD_D0 -
2586// 1 LCD_D1 -
2587// 2 LCD_D2 -
2588// 3 LCD_D3 -
2589// 4 LCD_D4 -
2590// 5 LCD_D5 -
2591// 6 LCD_D6 -
2592// 7 LCD_D7 -
2593// 8 LCD_D8 -
2594// 9 LCD_D9 -
2595// 10 LCD_D10 -
2596// 11 LCD_D11 -
2597// 12 LCD_D12 -
2598// 13 LCD_D13 -
2599// 14 LCD_D14 -
2600// 15 LCD_D15 -
2601// 16 LCD_D16 -
2602// 17 LCD_D17 -
2603// 18 LCD_PCLK -
2604// 19 LCD_HSYNC -
2605// 20 LCD_VSYNC -
2606// 21 LCD_DE -
2607// 22 LCD_PS A19
2608// 23 LCD_REV A20
2609// 24 WE1# -
2610// 25 WE2# -
2611// 26 WE3# -
2612// 27 WAIT# -
2613// 28 FRE# -
2614// 29 FWE# -
2615// 30(NOTE:FRB#) - -
2616// 31 - -
2617//
2618// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash.
2619//------------------------------------------------------
2620// PORT 3:
2621//
2622// PIN/BIT N FUNC0 FUNC1
2623// 0 CIM_D0 -
2624// 1 CIM_D1 -
2625// 2 CIM_D2 -
2626// 3 CIM_D3 -
2627// 4 CIM_D4 -
2628// 5 CIM_D5 -
2629// 6 CIM_D6 -
2630// 7 CIM_D7 -
2631// 8 MSC_CMD -
2632// 9 MSC_CLK -
2633// 10 MSC_D0 -
2634// 11 MSC_D1 -
2635// 12 MSC_D2 -
2636// 13 MSC_D3 -
2637// 14 CIM_MCLK -
2638// 15 CIM_PCLK -
2639// 16 CIM_VSYNC -
2640// 17 CIM_HSYNC -
2641// 18 SSI_CLK SCLK_RSTN
2642// 19 SSI_CE0# BIT_CLK(AIC)
2643// 20 SSI_DT SDATA_OUT(AIC)
2644// 21 SSI_DR SDATA_IN(AIC)
2645// 22 SSI_CE1#&GPC SYNC(AIC)
2646// 23 PWM0 I2C_SDA
2647// 24 PWM1 I2C_SCK
2648// 25 PWM2 UART0_TxD
2649// 26 PWM3 UART0_RxD
2650// 27 PWM4 A17
2651// 28 PWM5 A18
2652// 29 - -
2653// 30 PWM6 UART0_CTS/UART1_RxD
2654// 31 PWM7 UART0_RTS/UART1_TxD
2655//
2656//////////////////////////////////////////////////////////
2657
2658/*
2659 * p is the port number (0,1,2,3)
2660 * o is the pin offset (0-31) inside the port
2661 * n is the absolute number of a pin (0-127), regardless of the port
2662 */
2663
2664//-------------------------------------------
2665// Function Pins Mode
2666
2667#define __gpio_as_func0(n) \
2668do { \
2669    unsigned int p, o; \
2670    p = (n) / 32; \
2671    o = (n) % 32; \
2672    REG_GPIO_PXFUNS(p) = (1 << o); \
2673    REG_GPIO_PXSELC(p) = (1 << o); \
2674} while (0)
2675
2676#define __gpio_as_func1(n) \
2677do { \
2678    unsigned int p, o; \
2679    p = (n) / 32; \
2680    o = (n) % 32; \
2681    REG_GPIO_PXFUNS(p) = (1 << o); \
2682    REG_GPIO_PXSELS(p) = (1 << o); \
2683} while (0)
2684
2685/*
2686 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2687 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2688 */
2689#define __gpio_as_sdram_32bit() \
2690do { \
2691    REG_GPIO_PXFUNS(0) = 0xffffffff; \
2692    REG_GPIO_PXSELC(0) = 0xffffffff; \
2693    REG_GPIO_PXPES(0) = 0xffffffff; \
2694    REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2695    REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2696    REG_GPIO_PXPES(1) = 0x81f9ffff; \
2697    REG_GPIO_PXFUNS(2) = 0x07000000; \
2698    REG_GPIO_PXSELC(2) = 0x07000000; \
2699    REG_GPIO_PXPES(2) = 0x07000000; \
2700} while (0)
2701
2702/*
2703 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2704 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2705 */
2706#define __gpio_as_sdram_16bit() \
2707do { \
2708    REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
2709    REG_GPIO_PXSELC(0) = 0x5442bfaa; \
2710    REG_GPIO_PXPES(0) = 0x5442bfaa; \
2711    REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2712    REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2713    REG_GPIO_PXPES(1) = 0x81f9ffff; \
2714    REG_GPIO_PXFUNS(2) = 0x01000000; \
2715    REG_GPIO_PXSELC(2) = 0x01000000; \
2716    REG_GPIO_PXPES(2) = 0x01000000; \
2717} while (0)
2718
2719/*
2720 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
2721 */
2722#define __gpio_as_nand() \
2723do { \
2724    REG_GPIO_PXFUNS(1) = 0x02018000; \
2725    REG_GPIO_PXSELC(1) = 0x02018000; \
2726    REG_GPIO_PXPES(1) = 0x02018000; \
2727    REG_GPIO_PXFUNS(2) = 0x30000000; \
2728    REG_GPIO_PXSELC(2) = 0x30000000; \
2729    REG_GPIO_PXPES(2) = 0x30000000; \
2730    REG_GPIO_PXFUNC(2) = 0x40000000; \
2731    REG_GPIO_PXSELC(2) = 0x40000000; \
2732    REG_GPIO_PXDIRC(2) = 0x40000000; \
2733    REG_GPIO_PXPES(2) = 0x40000000; \
2734    REG_GPIO_PXFUNS(1) = 0x00400000; \
2735    REG_GPIO_PXSELC(1) = 0x00400000; \
2736} while (0)
2737
2738/*
2739 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
2740 */
2741#define __gpio_as_nor_8bit() \
2742do { \
2743    REG_GPIO_PXFUNS(0) = 0x000000ff; \
2744    REG_GPIO_PXSELC(0) = 0x000000ff; \
2745    REG_GPIO_PXPES(0) = 0x000000ff; \
2746    REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2747    REG_GPIO_PXSELC(1) = 0x7041ffff; \
2748    REG_GPIO_PXPES(1) = 0x7041ffff; \
2749    REG_GPIO_PXFUNS(1) = 0x00060000; \
2750    REG_GPIO_PXSELS(1) = 0x00060000; \
2751    REG_GPIO_PXPES(1) = 0x00060000; \
2752    REG_GPIO_PXFUNS(2) = 0x08000000; \
2753    REG_GPIO_PXSELC(2) = 0x08000000; \
2754    REG_GPIO_PXPES(2) = 0x08000000; \
2755    REG_GPIO_PXFUNS(2) = 0x00c00000; \
2756    REG_GPIO_PXSELS(2) = 0x00c00000; \
2757    REG_GPIO_PXPES(2) = 0x00c00000; \
2758    REG_GPIO_PXFUNS(3) = 0x18000000; \
2759    REG_GPIO_PXSELS(3) = 0x18000000; \
2760    REG_GPIO_PXPES(3) = 0x18000000; \
2761} while (0)
2762
2763/*
2764 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
2765 */
2766#define __gpio_as_nor_16bit() \
2767do { \
2768    REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2769    REG_GPIO_PXSELC(0) = 0x0000ffff; \
2770    REG_GPIO_PXPES(0) = 0x0000ffff; \
2771    REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2772    REG_GPIO_PXSELC(1) = 0x7041ffff; \
2773    REG_GPIO_PXPES(1) = 0x7041ffff; \
2774    REG_GPIO_PXFUNS(1) = 0x00060000; \
2775    REG_GPIO_PXSELS(1) = 0x00060000; \
2776    REG_GPIO_PXPES(1) = 0x00060000; \
2777    REG_GPIO_PXFUNS(2) = 0x08000000; \
2778    REG_GPIO_PXSELC(2) = 0x08000000; \
2779    REG_GPIO_PXPES(2) = 0x08000000; \
2780    REG_GPIO_PXFUNS(2) = 0x00c00000; \
2781    REG_GPIO_PXSELS(2) = 0x00c00000; \
2782    REG_GPIO_PXPES(2) = 0x00c00000; \
2783    REG_GPIO_PXFUNS(3) = 0x18000000; \
2784    REG_GPIO_PXSELS(3) = 0x18000000; \
2785    REG_GPIO_PXPES(3) = 0x18000000; \
2786} while (0)
2787
2788/*
2789 * UART0_TxD, UART_RxD0
2790 */
2791#define __gpio_as_uart0() \
2792do { \
2793    REG_GPIO_PXFUNS(3) = 0x06000000; \
2794    REG_GPIO_PXSELS(3) = 0x06000000; \
2795    REG_GPIO_PXPES(3) = 0x06000000; \
2796} while (0)
2797
2798/*
2799 * UART0_CTS, UART0_RTS
2800 */
2801#define __gpio_as_ctsrts() \
2802do { \
2803    REG_GPIO_PXFUNS(3) = 0xc0000000; \
2804    REG_GPIO_PXSELS(3) = 0xc0000000; \
2805    REG_GPIO_PXTRGC(3) = 0xc0000000; \
2806    REG_GPIO_PXPES(3) = 0xc0000000; \
2807} while (0)
2808
2809/*
2810 * UART1_TxD, UART1_RxD1
2811 */
2812#define __gpio_as_uart1() \
2813do { \
2814    REG_GPIO_PXFUNS(3) = 0xc0000000; \
2815    REG_GPIO_PXSELC(3) = 0xc0000000; \
2816    REG_GPIO_PXTRGS(3) = 0xc0000000; \
2817    REG_GPIO_PXPES(3) = 0xc0000000; \
2818} while (0)
2819
2820/*
2821 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2822 */
2823#define __gpio_as_lcd_16bit() \
2824do { \
2825    REG_GPIO_PXFUNS(2) = 0x003cffff; \
2826    REG_GPIO_PXSELC(2) = 0x003cffff; \
2827    REG_GPIO_PXPES(2) = 0x003cffff; \
2828} while (0)
2829
2830/*
2831 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2832 */
2833#define __gpio_as_lcd_18bit() \
2834do { \
2835    REG_GPIO_PXFUNS(2) = 0x003fffff; \
2836    REG_GPIO_PXSELC(2) = 0x003fffff; \
2837    REG_GPIO_PXPES(2) = 0x003fffff; \
2838} while (0)
2839
2840/*
2841 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
2842 */
2843#define __gpio_as_cim() \
2844do { \
2845    REG_GPIO_PXFUNS(3) = 0x0003c0ff; \
2846    REG_GPIO_PXSELC(3) = 0x0003c0ff; \
2847    REG_GPIO_PXPES(3) = 0x0003c0ff; \
2848} while (0)
2849
2850/*
2851 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
2852 */
2853#define __gpio_as_aic() \
2854do { \
2855    REG_GPIO_PXFUNS(3) = 0x007c0000; \
2856    REG_GPIO_PXSELS(3) = 0x007c0000; \
2857    REG_GPIO_PXPES(3) = 0x007c0000; \
2858} while (0)
2859
2860/*
2861 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
2862 */
2863#define __gpio_as_msc() \
2864do { \
2865    REG_GPIO_PXFUNS(3) = 0x00003f00; \
2866    REG_GPIO_PXSELC(3) = 0x00003f00; \
2867    REG_GPIO_PXPES(3) = 0x00003f00; \
2868} while (0)
2869
2870/*
2871 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
2872 */
2873#define __gpio_as_ssi() \
2874do { \
2875    REG_GPIO_PXFUNS(3) = 0x003c0000; \
2876    REG_GPIO_PXSELC(3) = 0x003c0000; \
2877    REG_GPIO_PXPES(3) = 0x003c0000; \
2878} while (0)
2879
2880/*
2881 * I2C_SCK, I2C_SDA
2882 */
2883#define __gpio_as_i2c() \
2884do { \
2885    REG_GPIO_PXFUNS(3) = 0x01800000; \
2886    REG_GPIO_PXSELS(3) = 0x01800000; \
2887    REG_GPIO_PXPES(3) = 0x01800000; \
2888} while (0)
2889
2890/*
2891 * PWM0
2892 */
2893#define __gpio_as_pwm0() \
2894do { \
2895    REG_GPIO_PXFUNS(3) = 0x00800000; \
2896    REG_GPIO_PXSELC(3) = 0x00800000; \
2897    REG_GPIO_PXPES(3) = 0x00800000; \
2898} while (0)
2899
2900/*
2901 * PWM1
2902 */
2903#define __gpio_as_pwm1() \
2904do { \
2905    REG_GPIO_PXFUNS(3) = 0x01000000; \
2906    REG_GPIO_PXSELC(3) = 0x01000000; \
2907    REG_GPIO_PXPES(3) = 0x01000000; \
2908} while (0)
2909
2910/*
2911 * PWM2
2912 */
2913#define __gpio_as_pwm2() \
2914do { \
2915    REG_GPIO_PXFUNS(3) = 0x02000000; \
2916    REG_GPIO_PXSELC(3) = 0x02000000; \
2917    REG_GPIO_PXPES(3) = 0x02000000; \
2918} while (0)
2919
2920/*
2921 * PWM3
2922 */
2923#define __gpio_as_pwm3() \
2924do { \
2925    REG_GPIO_PXFUNS(3) = 0x04000000; \
2926    REG_GPIO_PXSELC(3) = 0x04000000; \
2927    REG_GPIO_PXPES(3) = 0x04000000; \
2928} while (0)
2929
2930/*
2931 * PWM4
2932 */
2933#define __gpio_as_pwm4() \
2934do { \
2935    REG_GPIO_PXFUNS(3) = 0x08000000; \
2936    REG_GPIO_PXSELC(3) = 0x08000000; \
2937    REG_GPIO_PXPES(3) = 0x08000000; \
2938} while (0)
2939
2940/*
2941 * PWM5
2942 */
2943#define __gpio_as_pwm5() \
2944do { \
2945    REG_GPIO_PXFUNS(3) = 0x10000000; \
2946    REG_GPIO_PXSELC(3) = 0x10000000; \
2947    REG_GPIO_PXPES(3) = 0x10000000; \
2948} while (0)
2949
2950/*
2951 * PWM6
2952 */
2953#define __gpio_as_pwm6() \
2954do { \
2955    REG_GPIO_PXFUNS(3) = 0x40000000; \
2956    REG_GPIO_PXSELC(3) = 0x40000000; \
2957    REG_GPIO_PXPES(3) = 0x40000000; \
2958} while (0)
2959
2960/*
2961 * PWM7
2962 */
2963#define __gpio_as_pwm7() \
2964do { \
2965    REG_GPIO_PXFUNS(3) = 0x80000000; \
2966    REG_GPIO_PXSELC(3) = 0x80000000; \
2967    REG_GPIO_PXPES(3) = 0x80000000; \
2968} while (0)
2969
2970/*
2971 * n = 0 ~ 7
2972 */
2973#define __gpio_as_pwm(n) __gpio_as_pwm##n()
2974
2975//-------------------------------------------
2976// GPIO or Interrupt Mode
2977
2978#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
2979
2980#define __gpio_port_as_output(p, o) \
2981do { \
2982    REG_GPIO_PXFUNC(p) = (1 << (o)); \
2983    REG_GPIO_PXSELC(p) = (1 << (o)); \
2984    REG_GPIO_PXDIRS(p) = (1 << (o)); \
2985} while (0)
2986
2987#define __gpio_port_as_input(p, o) \
2988do { \
2989    REG_GPIO_PXFUNC(p) = (1 << (o)); \
2990    REG_GPIO_PXSELC(p) = (1 << (o)); \
2991    REG_GPIO_PXDIRC(p) = (1 << (o)); \
2992} while (0)
2993
2994#define __gpio_as_output(n) \
2995do { \
2996    unsigned int p, o; \
2997    p = (n) / 32; \
2998    o = (n) % 32; \
2999    __gpio_port_as_output(p, o); \
3000} while (0)
3001
3002#define __gpio_as_input(n) \
3003do { \
3004    unsigned int p, o; \
3005    p = (n) / 32; \
3006    o = (n) % 32; \
3007    __gpio_port_as_input(p, o); \
3008} while (0)
3009
3010#define __gpio_set_pin(n) \
3011do { \
3012    unsigned int p, o; \
3013    p = (n) / 32; \
3014    o = (n) % 32; \
3015    REG_GPIO_PXDATS(p) = (1 << o); \
3016} while (0)
3017
3018#define __gpio_clear_pin(n) \
3019do { \
3020    unsigned int p, o; \
3021    p = (n) / 32; \
3022    o = (n) % 32; \
3023    REG_GPIO_PXDATC(p) = (1 << o); \
3024} while (0)
3025
3026#define __gpio_get_pin(n) \
3027({ \
3028    unsigned int p, o, v; \
3029    p = (n) / 32; \
3030    o = (n) % 32; \
3031    if (__gpio_get_port(p) & (1 << o)) \
3032        v = 1; \
3033    else \
3034        v = 0; \
3035    v; \
3036})
3037
3038#define __gpio_as_irq_high_level(n) \
3039do { \
3040    unsigned int p, o; \
3041    p = (n) / 32; \
3042    o = (n) % 32; \
3043    REG_GPIO_PXIMS(p) = (1 << o); \
3044    REG_GPIO_PXTRGC(p) = (1 << o); \
3045    REG_GPIO_PXFUNC(p) = (1 << o); \
3046    REG_GPIO_PXSELS(p) = (1 << o); \
3047    REG_GPIO_PXDIRS(p) = (1 << o); \
3048    REG_GPIO_PXFLGC(p) = (1 << o); \
3049    REG_GPIO_PXIMC(p) = (1 << o); \
3050} while (0)
3051
3052#define __gpio_as_irq_low_level(n) \
3053do { \
3054    unsigned int p, o; \
3055    p = (n) / 32; \
3056    o = (n) % 32; \
3057    REG_GPIO_PXIMS(p) = (1 << o); \
3058    REG_GPIO_PXTRGC(p) = (1 << o); \
3059    REG_GPIO_PXFUNC(p) = (1 << o); \
3060    REG_GPIO_PXSELS(p) = (1 << o); \
3061    REG_GPIO_PXDIRC(p) = (1 << o); \
3062    REG_GPIO_PXFLGC(p) = (1 << o); \
3063    REG_GPIO_PXIMC(p) = (1 << o); \
3064} while (0)
3065
3066#define __gpio_as_irq_rise_edge(n) \
3067do { \
3068    unsigned int p, o; \
3069    p = (n) / 32; \
3070    o = (n) % 32; \
3071    REG_GPIO_PXIMS(p) = (1 << o); \
3072    REG_GPIO_PXTRGS(p) = (1 << o); \
3073    REG_GPIO_PXFUNC(p) = (1 << o); \
3074    REG_GPIO_PXSELS(p) = (1 << o); \
3075    REG_GPIO_PXDIRS(p) = (1 << o); \
3076    REG_GPIO_PXFLGC(p) = (1 << o); \
3077    REG_GPIO_PXIMC(p) = (1 << o); \
3078} while (0)
3079
3080#define __gpio_as_irq_fall_edge(n) \
3081do { \
3082    unsigned int p, o; \
3083    p = (n) / 32; \
3084    o = (n) % 32; \
3085    REG_GPIO_PXIMS(p) = (1 << o); \
3086    REG_GPIO_PXTRGS(p) = (1 << o); \
3087    REG_GPIO_PXFUNC(p) = (1 << o); \
3088    REG_GPIO_PXSELS(p) = (1 << o); \
3089    REG_GPIO_PXDIRC(p) = (1 << o); \
3090    REG_GPIO_PXFLGC(p) = (1 << o); \
3091    REG_GPIO_PXIMC(p) = (1 << o); \
3092} while (0)
3093
3094#define __gpio_mask_irq(n) \
3095do { \
3096    unsigned int p, o; \
3097    p = (n) / 32; \
3098    o = (n) % 32; \
3099    REG_GPIO_PXIMS(p) = (1 << o); \
3100} while (0)
3101
3102#define __gpio_unmask_irq(n) \
3103do { \
3104    unsigned int p, o; \
3105    p = (n) / 32; \
3106    o = (n) % 32; \
3107    REG_GPIO_PXIMC(p) = (1 << o); \
3108} while (0)
3109
3110#define __gpio_ack_irq(n) \
3111do { \
3112    unsigned int p, o; \
3113    p = (n) / 32; \
3114    o = (n) % 32; \
3115    REG_GPIO_PXFLGC(p) = (1 << o); \
3116} while (0)
3117
3118#define __gpio_get_irq() \
3119({ \
3120    unsigned int p, i, tmp, v = 0; \
3121    for (p = 3; p >= 0; p--) { \
3122        tmp = REG_GPIO_PXFLG(p); \
3123        for (i = 0; i < 32; i++) \
3124            if (tmp & (1 << i)) \
3125                v = (32*p + i); \
3126    } \
3127    v; \
3128})
3129
3130#define __gpio_group_irq(n) \
3131({ \
3132    register int tmp, i; \
3133    tmp = REG_GPIO_PXFLG((n)); \
3134    for (i=31;i>=0;i--) \
3135        if (tmp & (1 << i)) \
3136            break; \
3137    i; \
3138})
3139
3140#define __gpio_enable_pull(n) \
3141do { \
3142    unsigned int p, o; \
3143    p = (n) / 32; \
3144    o = (n) % 32; \
3145    REG_GPIO_PXPEC(p) = (1 << o); \
3146} while (0)
3147
3148#define __gpio_disable_pull(n) \
3149do { \
3150    unsigned int p, o; \
3151    p = (n) / 32; \
3152    o = (n) % 32; \
3153    REG_GPIO_PXPES(p) = (1 << o); \
3154} while (0)
3155
3156
3157/***************************************************************************
3158 * CPM
3159 ***************************************************************************/
3160#define __cpm_get_pllm() \
3161    ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
3162#define __cpm_get_plln() \
3163    ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
3164#define __cpm_get_pllod() \
3165    ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
3166
3167#define __cpm_get_cdiv() \
3168    ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
3169#define __cpm_get_hdiv() \
3170    ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
3171#define __cpm_get_pdiv() \
3172    ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
3173#define __cpm_get_mdiv() \
3174    ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
3175#define __cpm_get_ldiv() \
3176    ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
3177#define __cpm_get_udiv() \
3178    ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
3179#define __cpm_get_i2sdiv() \
3180    ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
3181#define __cpm_get_pixdiv() \
3182    ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
3183#define __cpm_get_mscdiv() \
3184    ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
3185
3186#define __cpm_set_cdiv(v) \
3187    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
3188#define __cpm_set_hdiv(v) \
3189    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
3190#define __cpm_set_pdiv(v) \
3191    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
3192#define __cpm_set_mdiv(v) \
3193    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
3194#define __cpm_set_ldiv(v) \
3195    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
3196#define __cpm_set_udiv(v) \
3197    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
3198#define __cpm_set_i2sdiv(v) \
3199    (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
3200#define __cpm_set_pixdiv(v) \
3201    (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
3202#define __cpm_set_mscdiv(v) \
3203    (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
3204
3205#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
3206#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
3207#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
3208#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
3209#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
3210#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
3211#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
3212#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
3213
3214#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
3215#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
3216#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
3217
3218#define __cpm_get_cclk_doze_duty() \
3219    ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
3220#define __cpm_set_cclk_doze_duty(v) \
3221    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
3222
3223#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
3224#define __cpm_idle_mode() \
3225    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
3226#define __cpm_sleep_mode() \
3227    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
3228
3229#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
3230#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
3231#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
3232#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
3233#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
3234#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
3235#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
3236#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
3237#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
3238#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
3239#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
3240#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
3241#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
3242#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
3243#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
3244#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
3245#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
3246
3247#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
3248#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
3249#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
3250#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
3251#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
3252#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
3253#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
3254#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
3255#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
3256#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
3257#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
3258#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
3259#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
3260#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
3261#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
3262#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
3263#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
3264
3265#define __cpm_get_o1st() \
3266    ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
3267#define __cpm_set_o1st(v) \
3268    (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
3269#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
3270#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
3271
3272
3273#ifdef CFG_EXTAL
3274#define JZ_EXTAL CFG_EXTAL
3275#else
3276#define JZ_EXTAL 3686400
3277#endif
3278#define JZ_EXTAL2 32768 /* RTC clock */
3279
3280/* PLL output frequency */
3281static __inline__ unsigned int __cpm_get_pllout(void)
3282{
3283    unsigned long m, n, no, pllout;
3284    unsigned long cppcr = REG_CPM_CPPCR;
3285    unsigned long od[4] = {1, 2, 2, 4};
3286    if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
3287        m = __cpm_get_pllm() + 2;
3288        n = __cpm_get_plln() + 2;
3289        no = od[__cpm_get_pllod()];
3290        pllout = ((JZ_EXTAL) / (n * no)) * m;
3291    } else
3292        pllout = JZ_EXTAL;
3293    return pllout;
3294}
3295
3296/* PLL output frequency for MSC/I2S/LCD/USB */
3297static __inline__ unsigned int __cpm_get_pllout2(void)
3298{
3299    if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
3300        return __cpm_get_pllout();
3301    else
3302        return __cpm_get_pllout()/2;
3303}
3304
3305/* CPU core clock */
3306static __inline__ unsigned int __cpm_get_cclk(void)
3307{
3308    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3309
3310    return __cpm_get_pllout() / div[__cpm_get_cdiv()];
3311}
3312
3313/* AHB system bus clock */
3314static __inline__ unsigned int __cpm_get_hclk(void)
3315{
3316    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3317
3318    return __cpm_get_pllout() / div[__cpm_get_hdiv()];
3319}
3320
3321/* Memory bus clock */
3322static __inline__ unsigned int __cpm_get_mclk(void)
3323{
3324    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3325
3326    return __cpm_get_pllout() / div[__cpm_get_mdiv()];
3327}
3328
3329/* APB peripheral bus clock */
3330static __inline__ unsigned int __cpm_get_pclk(void)
3331{
3332    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3333
3334    return __cpm_get_pllout() / div[__cpm_get_pdiv()];
3335}
3336
3337/* LCDC module clock */
3338static __inline__ unsigned int __cpm_get_lcdclk(void)
3339{
3340    return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
3341}
3342
3343/* LCD pixel clock */
3344static __inline__ unsigned int __cpm_get_pixclk(void)
3345{
3346    return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
3347}
3348
3349/* I2S clock */
3350static __inline__ unsigned int __cpm_get_i2sclk(void)
3351{
3352    if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
3353        return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
3354    }
3355    else {
3356        return JZ_EXTAL;
3357    }
3358}
3359
3360/* USB clock */
3361static __inline__ unsigned int __cpm_get_usbclk(void)
3362{
3363    if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
3364        return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
3365    }
3366    else {
3367        return JZ_EXTAL;
3368    }
3369}
3370
3371/* MSC clock */
3372static __inline__ unsigned int __cpm_get_mscclk(void)
3373{
3374    return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
3375}
3376
3377/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
3378static __inline__ unsigned int __cpm_get_extalclk(void)
3379{
3380    return JZ_EXTAL;
3381}
3382
3383/* RTC clock for CPM,INTC,RTC,TCU,WDT */
3384static __inline__ unsigned int __cpm_get_rtcclk(void)
3385{
3386    return JZ_EXTAL2;
3387}
3388
3389/*
3390 * Output 24MHz for SD and 16MHz for MMC.
3391 */
3392static inline void __cpm_select_msc_clk(int sd)
3393{
3394    unsigned int pllout2 = __cpm_get_pllout2();
3395    unsigned int div = 0;
3396
3397    if (sd) {
3398        div = pllout2 / 24000000;
3399    }
3400    else {
3401        div = pllout2 / 16000000;
3402    }
3403
3404    REG_CPM_MSCCDR = div - 1;
3405}
3406
3407/***************************************************************************
3408 * TCU
3409 ***************************************************************************/
3410// where 'n' is the TCU channel
3411#define __tcu_select_extalclk(n) \
3412    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
3413#define __tcu_select_rtcclk(n) \
3414    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
3415#define __tcu_select_pclk(n) \
3416    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
3417
3418#define __tcu_select_clk_div1(n) \
3419    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
3420#define __tcu_select_clk_div4(n) \
3421    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
3422#define __tcu_select_clk_div16(n) \
3423    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
3424#define __tcu_select_clk_div64(n) \
3425    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
3426#define __tcu_select_clk_div256(n) \
3427    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
3428#define __tcu_select_clk_div1024(n) \
3429    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
3430
3431#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
3432#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
3433
3434#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
3435#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
3436
3437#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
3438#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
3439
3440#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
3441#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
3442
3443#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
3444#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
3445#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
3446#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
3447#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
3448#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
3449#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
3450#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
3451#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
3452#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
3453
3454#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
3455#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
3456
3457#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
3458#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
3459
3460#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
3461#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
3462
3463#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
3464#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
3465#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
3466#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
3467
3468
3469/***************************************************************************
3470 * WDT
3471 ***************************************************************************/
3472#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
3473#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
3474#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
3475#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
3476
3477#define __wdt_select_extalclk() \
3478    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
3479#define __wdt_select_rtcclk() \
3480    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
3481#define __wdt_select_pclk() \
3482    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
3483
3484#define __wdt_select_clk_div1() \
3485    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
3486#define __wdt_select_clk_div4() \
3487    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
3488#define __wdt_select_clk_div16() \
3489    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
3490#define __wdt_select_clk_div64() \
3491    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
3492#define __wdt_select_clk_div256() \
3493    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
3494#define __wdt_select_clk_div1024() \
3495    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
3496
3497
3498/***************************************************************************
3499 * UART
3500 ***************************************************************************/
3501
3502#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
3503#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
3504
3505#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
3506#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
3507
3508#define __uart_enable_receive_irq() \
3509  ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
3510#define __uart_disable_receive_irq() \
3511  ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
3512
3513#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
3514#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
3515
3516#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
3517
3518#define __uart_set_baud(devclk, baud) \
3519  do { \
3520    REG8(UART0_LCR) |= UARTLCR_DLAB; \
3521    REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
3522    REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
3523    REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
3524  } while (0)
3525
3526#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
3527#define __uart_clear_errors() \
3528  ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
3529
3530#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
3531#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
3532#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
3533#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3534#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3535#define __uart_receive_char() REG8(UART0_RDR)
3536#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
3537#define __uart_enable_irda() \
3538  /* Tx high pulse as 0, Rx low pulse as 0 */ \
3539  ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
3540
3541
3542/***************************************************************************
3543 * DMAC
3544 ***************************************************************************/
3545
3546/* n is the DMA channel (0 - 5) */
3547
3548#define __dmac_enable_module() \
3549  ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
3550#define __dmac_disable_module() \
3551  ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
3552
3553/* p=0,1,2,3 */
3554#define __dmac_set_priority(p) \
3555do { \
3556    REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
3557    REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
3558} while (0)
3559
3560#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
3561#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
3562
3563#define __dmac_enable_descriptor(n) \
3564  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
3565#define __dmac_disable_descriptor(n) \
3566  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
3567
3568#define __dmac_enable_channel(n) \
3569  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
3570#define __dmac_disable_channel(n) \
3571  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
3572#define __dmac_channel_enabled(n) \
3573  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
3574
3575#define __dmac_channel_enable_irq(n) \
3576  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
3577#define __dmac_channel_disable_irq(n) \
3578  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
3579
3580#define __dmac_channel_transmit_halt_detected(n) \
3581  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
3582#define __dmac_channel_transmit_end_detected(n) \
3583  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
3584#define __dmac_channel_address_error_detected(n) \
3585  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
3586#define __dmac_channel_count_terminated_detected(n) \
3587  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
3588#define __dmac_channel_descriptor_invalid_detected(n) \
3589  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
3590
3591#define __dmac_channel_clear_transmit_halt(n) \
3592  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
3593#define __dmac_channel_clear_transmit_end(n) \
3594  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
3595#define __dmac_channel_clear_address_error(n) \
3596  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
3597#define __dmac_channel_clear_count_terminated(n) \
3598  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
3599#define __dmac_channel_clear_descriptor_invalid(n) \
3600  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
3601
3602#define __dmac_channel_set_single_mode(n) \
3603  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
3604#define __dmac_channel_set_block_mode(n) \
3605  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
3606
3607#define __dmac_channel_set_transfer_unit_32bit(n) \
3608do { \
3609    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3610    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
3611} while (0)
3612
3613#define __dmac_channel_set_transfer_unit_16bit(n) \
3614do { \
3615    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3616    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
3617} while (0)
3618
3619#define __dmac_channel_set_transfer_unit_8bit(n) \
3620do { \
3621    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3622    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
3623} while (0)
3624
3625#define __dmac_channel_set_transfer_unit_16byte(n) \
3626do { \
3627    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3628    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
3629} while (0)
3630
3631#define __dmac_channel_set_transfer_unit_32byte(n) \
3632do { \
3633    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3634    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
3635} while (0)
3636
3637/* w=8,16,32 */
3638#define __dmac_channel_set_dest_port_width(n,w) \
3639do { \
3640    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
3641    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
3642} while (0)
3643
3644/* w=8,16,32 */
3645#define __dmac_channel_set_src_port_width(n,w) \
3646do { \
3647    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
3648    REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
3649} while (0)
3650
3651/* v=0-15 */
3652#define __dmac_channel_set_rdil(n,v) \
3653do { \
3654    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
3655    REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
3656} while (0)
3657
3658#define __dmac_channel_dest_addr_fixed(n) \
3659  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
3660#define __dmac_channel_dest_addr_increment(n) \
3661  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
3662
3663#define __dmac_channel_src_addr_fixed(n) \
3664  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
3665#define __dmac_channel_src_addr_increment(n) \
3666  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
3667
3668#define __dmac_channel_set_doorbell(n) \
3669  ( REG_DMAC_DMADBSR = (1 << (n)) )
3670
3671#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) )
3672#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
3673
3674static __inline__ int __dmac_get_irq(void)
3675{
3676    int i;
3677    for (i = 0; i < MAX_DMA_NUM; i++)
3678        if (__dmac_channel_irq_detected(i))
3679            return i;
3680    return -1;
3681}
3682
3683
3684/***************************************************************************
3685 * AIC (AC'97 & I2S Controller)
3686 ***************************************************************************/
3687
3688#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
3689#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
3690
3691#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
3692#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
3693
3694#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
3695#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
3696#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
3697
3698#define __aic_reset() \
3699do { \
3700        REG_AIC_FR |= AIC_FR_RST; \
3701} while(0)
3702
3703
3704#define __aic_set_transmit_trigger(n) \
3705do { \
3706    REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
3707    REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
3708} while(0)
3709
3710#define __aic_set_receive_trigger(n) \
3711do { \
3712    REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
3713    REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
3714} while(0)
3715
3716#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
3717#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
3718#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
3719#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
3720#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
3721#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
3722
3723#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
3724#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
3725
3726#define __aic_enable_transmit_intr() \
3727  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
3728#define __aic_disable_transmit_intr() \
3729  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
3730#define __aic_enable_receive_intr() \
3731  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
3732#define __aic_disable_receive_intr() \
3733  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
3734
3735#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
3736#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
3737#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
3738#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
3739
3740#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
3741#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
3742#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
3743#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
3744#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
3745#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
3746
3747#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
3748#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
3749#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
3750#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
3751#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
3752#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
3753
3754#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
3755#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
3756#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
3757#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
3758#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
3759#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
3760
3761#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
3762#define __ac97_set_xs_mono() \
3763do { \
3764    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3765    REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
3766} while(0)
3767#define __ac97_set_xs_stereo() \
3768do { \
3769    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3770    REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
3771} while(0)
3772
3773/* In fact, only stereo is support now. */
3774#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
3775#define __ac97_set_rs_mono() \
3776do { \
3777    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3778    REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
3779} while(0)
3780#define __ac97_set_rs_stereo() \
3781do { \
3782    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3783    REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
3784} while(0)
3785
3786#define __ac97_warm_reset_codec() \
3787 do { \
3788    REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
3789    REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
3790    udelay(2); \
3791    REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
3792    REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
3793 } while (0)
3794
3795#define __ac97_cold_reset_codec() \
3796 do { \
3797    REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
3798    udelay(2); \
3799    REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
3800 } while (0)
3801
3802/* n=8,16,18,20 */
3803#define __ac97_set_iass(n) \
3804 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
3805#define __ac97_set_oass(n) \
3806 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
3807
3808#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
3809#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
3810
3811/* n=8,16,18,20,24 */
3812/*#define __i2s_set_sample_size(n) \
3813 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
3814
3815#define __i2s_set_oss_sample_size(n) \
3816 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
3817#define __i2s_set_iss_sample_size(n) \
3818 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
3819
3820#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
3821#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
3822
3823#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
3824#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
3825#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
3826#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
3827
3828#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
3829
3830#define __aic_get_transmit_resident() \
3831  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
3832#define __aic_get_receive_count() \
3833  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
3834
3835#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
3836#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
3837#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
3838#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
3839#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
3840#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
3841#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
3842
3843#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
3844
3845#define CODEC_READ_CMD (1 << 19)
3846#define CODEC_WRITE_CMD (0 << 19)
3847#define CODEC_REG_INDEX_BIT 12
3848#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
3849#define CODEC_REG_DATA_BIT 4
3850#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
3851
3852#define __ac97_out_rcmd_addr(reg) \
3853do { \
3854    REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3855} while (0)
3856
3857#define __ac97_out_wcmd_addr(reg) \
3858do { \
3859    REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3860} while (0)
3861
3862#define __ac97_out_data(value) \
3863do { \
3864    REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
3865} while (0)
3866
3867#define __ac97_in_data() \
3868 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
3869
3870#define __ac97_in_status_addr() \
3871 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
3872
3873#define __i2s_set_sample_rate(i2sclk, sync) \
3874  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
3875
3876#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
3877#define __aic_read_rfifo() ( REG_AIC_DR )
3878
3879#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
3880#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
3881
3882//
3883// Define next ops for AC97 compatible
3884//
3885
3886#define AC97_ACSR AIC_ACSR
3887
3888#define __ac97_enable() __aic_enable(); __aic_select_ac97()
3889#define __ac97_disable() __aic_disable()
3890#define __ac97_reset() __aic_reset()
3891
3892#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
3893#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
3894
3895#define __ac97_enable_record() __aic_enable_record()
3896#define __ac97_disable_record() __aic_disable_record()
3897#define __ac97_enable_replay() __aic_enable_replay()
3898#define __ac97_disable_replay() __aic_disable_replay()
3899#define __ac97_enable_loopback() __aic_enable_loopback()
3900#define __ac97_disable_loopback() __aic_disable_loopback()
3901
3902#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
3903#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
3904#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
3905#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
3906
3907#define __ac97_transmit_request() __aic_transmit_request()
3908#define __ac97_receive_request() __aic_receive_request()
3909#define __ac97_transmit_underrun() __aic_transmit_underrun()
3910#define __ac97_receive_overrun() __aic_receive_overrun()
3911
3912#define __ac97_clear_errors() __aic_clear_errors()
3913
3914#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
3915#define __ac97_get_receive_count() __aic_get_receive_count()
3916
3917#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
3918#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
3919#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
3920#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
3921
3922#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
3923#define __ac97_read_rfifo() __aic_read_rfifo()
3924
3925//
3926// Define next ops for I2S compatible
3927//
3928
3929#define I2S_ACSR AIC_I2SSR
3930
3931#define __i2s_enable() __aic_enable(); __aic_select_i2s()
3932#define __i2s_disable() __aic_disable()
3933#define __i2s_reset() __aic_reset()
3934
3935#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
3936#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
3937
3938#define __i2s_enable_record() __aic_enable_record()
3939#define __i2s_disable_record() __aic_disable_record()
3940#define __i2s_enable_replay() __aic_enable_replay()
3941#define __i2s_disable_replay() __aic_disable_replay()
3942#define __i2s_enable_loopback() __aic_enable_loopback()
3943#define __i2s_disable_loopback() __aic_disable_loopback()
3944
3945#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
3946#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
3947#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
3948#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
3949
3950#define __i2s_transmit_request() __aic_transmit_request()
3951#define __i2s_receive_request() __aic_receive_request()
3952#define __i2s_transmit_underrun() __aic_transmit_underrun()
3953#define __i2s_receive_overrun() __aic_receive_overrun()
3954
3955#define __i2s_clear_errors() __aic_clear_errors()
3956
3957#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
3958#define __i2s_get_receive_count() __aic_get_receive_count()
3959
3960#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
3961#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
3962#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
3963#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
3964
3965#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
3966#define __i2s_read_rfifo() __aic_read_rfifo()
3967
3968#define __i2s_reset_codec() \
3969 do { \
3970 } while (0)
3971
3972
3973/***************************************************************************
3974 * ICDC
3975 ***************************************************************************/
3976#define __i2s_internal_codec() __aic_internal_codec()
3977#define __i2s_external_codec() __aic_external_codec()
3978
3979/***************************************************************************
3980 * INTC
3981 ***************************************************************************/
3982#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
3983#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
3984#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
3985
3986
3987/***************************************************************************
3988 * I2C
3989 ***************************************************************************/
3990
3991#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
3992#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
3993
3994#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
3995#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
3996#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
3997#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
3998
3999#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
4000#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
4001#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
4002
4003#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
4004#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
4005#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
4006
4007#define __i2c_set_clk(dev_clk, i2c_clk) \
4008  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
4009
4010#define __i2c_read() ( REG_I2C_DR )
4011#define __i2c_write(val) ( REG_I2C_DR = (val) )
4012
4013
4014/***************************************************************************
4015 * MSC
4016 ***************************************************************************/
4017
4018#define __msc_start_op() \
4019  ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
4020
4021#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
4022#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
4023#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
4024#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
4025#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
4026#define __msc_get_nob() ( REG_MSC_NOB )
4027#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
4028#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
4029#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
4030#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
4031
4032#define __msc_set_cmdat_bus_width1() \
4033do { \
4034    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4035    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
4036} while(0)
4037
4038#define __msc_set_cmdat_bus_width4() \
4039do { \
4040    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4041    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
4042} while(0)
4043
4044#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
4045#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
4046#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
4047#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
4048#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
4049#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
4050#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
4051#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
4052
4053/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
4054#define __msc_set_cmdat_res_format(r) \
4055do { \
4056    REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
4057    REG_MSC_CMDAT |= (r); \
4058} while(0)
4059
4060#define __msc_clear_cmdat() \
4061  REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
4062  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
4063  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
4064
4065#define __msc_get_imask() ( REG_MSC_IMASK )
4066#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
4067#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
4068#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
4069#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
4070#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
4071#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
4072#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
4073#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
4074#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
4075#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
4076#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
4077#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
4078
4079/* n=0,1,2,3,4,5,6,7 */
4080#define __msc_set_clkrt(n) \
4081do { \
4082    REG_MSC_CLKRT = n; \
4083} while(0)
4084
4085#define __msc_get_ireg() ( REG_MSC_IREG )
4086#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
4087#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
4088#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
4089#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
4090#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
4091#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
4092#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
4093#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
4094
4095#define __msc_get_stat() ( REG_MSC_STAT )
4096#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
4097#define __msc_stat_crc_err() \
4098  ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
4099#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
4100#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
4101#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
4102#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
4103#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
4104
4105#define __msc_rd_resfifo() ( REG_MSC_RES )
4106#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
4107#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
4108
4109#define __msc_reset() \
4110do { \
4111    REG_MSC_STRPCL = MSC_STRPCL_RESET; \
4112     while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
4113} while (0)
4114
4115#define __msc_start_clk() \
4116do { \
4117    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
4118} while (0)
4119
4120#define __msc_stop_clk() \
4121do { \
4122    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
4123} while (0)
4124
4125#define MMC_CLK 19169200
4126#define SD_CLK 24576000
4127
4128/* msc_clk should little than pclk and little than clk retrieve from card */
4129#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
4130do { \
4131    unsigned int rate, pclk, i; \
4132    pclk = dev_clk; \
4133    rate = type?SD_CLK:MMC_CLK; \
4134      if (msc_clk && msc_clk < pclk) \
4135            pclk = msc_clk; \
4136    i = 0; \
4137      while (pclk < rate) \
4138        { \
4139              i ++; \
4140              rate >>= 1; \
4141        } \
4142      lv = i; \
4143} while(0)
4144
4145/* divide rate to little than or equal to 400kHz */
4146#define __msc_calc_slow_clk_divisor(type, lv) \
4147do { \
4148    unsigned int rate, i; \
4149    rate = (type?SD_CLK:MMC_CLK)/1000/400; \
4150    i = 0; \
4151    while (rate > 0) \
4152        { \
4153              rate >>= 1; \
4154              i ++; \
4155        } \
4156      lv = i; \
4157} while(0)
4158
4159
4160/***************************************************************************
4161 * SSI
4162 ***************************************************************************/
4163
4164#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
4165#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
4166#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
4167
4168#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
4169
4170#define __ssi_select_ce2() \
4171do { \
4172    REG_SSI_CR0 |= SSI_CR0_FSEL; \
4173    REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
4174} while (0)
4175
4176#define __ssi_select_gpc() \
4177do { \
4178    REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
4179    REG_SSI_CR1 |= SSI_CR1_MULTS; \
4180} while (0)
4181
4182#define __ssi_enable_tx_intr() \
4183  ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
4184
4185#define __ssi_disable_tx_intr() \
4186  ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
4187
4188#define __ssi_enable_rx_intr() \
4189  ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
4190
4191#define __ssi_disable_rx_intr() \
4192  ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
4193
4194#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP )
4195#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
4196
4197#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
4198#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV )
4199
4200#define __ssi_finish_receive() \
4201  ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
4202
4203#define __ssi_disable_recvfinish() \
4204  ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
4205
4206#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
4207#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
4208
4209#define __ssi_flush_fifo() \
4210  ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
4211
4212#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
4213
4214#define __ssi_spi_format() \
4215do { \
4216    REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
4217    REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \
4218    REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4219    REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
4220} while (0)
4221
4222/* TI's SSP format, must clear SSI_CR1.UNFIN */
4223#define __ssi_ssp_format() \
4224do { \
4225    REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
4226    REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \
4227} while (0)
4228
4229/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
4230#define __ssi_microwire_format() \
4231do { \
4232    REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
4233    REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \
4234    REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4235    REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
4236    REG_SSI_CR0 &= ~SSI_CR0_RFINE; \
4237} while (0)
4238
4239/* CE# level (FRMHL), CE# in interval time (ITFRM),
4240   clock phase and polarity (PHA POL),
4241   interval time (SSIITR), interval characters/frame (SSIICR) */
4242
4243 /* frmhl,endian,mcom,flen,pha,pol MASK */
4244#define SSICR1_MISC_MASK \
4245    ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
4246    | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \
4247
4248#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \
4249do { \
4250    REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \
4251    REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \
4252         (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
4253             ((pha) << 1) | (pol); \
4254} while(0)
4255
4256/* Transfer with MSB or LSB first */
4257#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
4258#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
4259
4260#define __ssi_set_frame_length(n) \
4261    REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4)
4262
4263/* n = 1 - 16 */
4264#define __ssi_set_microwire_command_length(n) \
4265    ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
4266
4267/* Set the clock phase for SPI */
4268#define __ssi_set_spi_clock_phase(n) \
4269    ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) )
4270
4271/* Set the clock polarity for SPI */
4272#define __ssi_set_spi_clock_polarity(n) \
4273    ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
4274
4275/* n = ix8 */
4276#define __ssi_set_tx_trigger(n) \
4277do { \
4278    REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \
4279    REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \
4280} while (0)
4281
4282/* n = ix8 */
4283#define __ssi_set_rx_trigger(n) \
4284do { \
4285    REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \
4286    REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \
4287} while (0)
4288
4289#define __ssi_get_txfifo_count() \
4290    ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
4291
4292#define __ssi_get_rxfifo_count() \
4293    ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
4294
4295#define __ssi_clear_errors() \
4296    ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
4297
4298#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END )
4299#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY )
4300
4301#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF )
4302#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE )
4303#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF )
4304
4305#define __ssi_set_clk(dev_clk, ssi_clk) \
4306  ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
4307
4308#define __ssi_receive_data() REG_SSI_DR
4309#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) )
4310
4311
4312/***************************************************************************
4313 * CIM
4314 ***************************************************************************/
4315
4316#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
4317#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
4318
4319#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
4320#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
4321
4322#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
4323#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
4324
4325#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
4326#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
4327
4328#define __cim_sample_data_at_pclk_falling_edge() \
4329  ( REG_CIM_CFG |= CIM_CFG_PCP )
4330#define __cim_sample_data_at_pclk_rising_edge() \
4331  ( REG_CIM_CFG &= ~CIM_CFG_PCP )
4332
4333#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
4334#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
4335
4336#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
4337#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
4338
4339/* n=0-7 */
4340#define __cim_set_data_packing_mode(n) \
4341do { \
4342    REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
4343    REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
4344} while (0)
4345
4346#define __cim_enable_ccir656_progressive_mode() \
4347do { \
4348    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4349    REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
4350} while (0)
4351
4352#define __cim_enable_ccir656_interlace_mode() \
4353do { \
4354    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4355    REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
4356} while (0)
4357
4358#define __cim_enable_gated_clock_mode() \
4359do { \
4360    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4361    REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
4362} while (0)
4363
4364#define __cim_enable_nongated_clock_mode() \
4365do { \
4366    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4367    REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
4368} while (0)
4369
4370/* sclk:system bus clock
4371 * mclk: CIM master clock
4372 */
4373#define __cim_set_master_clk(sclk, mclk) \
4374do { \
4375    REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
4376    REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
4377} while (0)
4378
4379#define __cim_enable_sof_intr() \
4380  ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
4381#define __cim_disable_sof_intr() \
4382  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
4383
4384#define __cim_enable_eof_intr() \
4385  ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
4386#define __cim_disable_eof_intr() \
4387  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
4388
4389#define __cim_enable_stop_intr() \
4390  ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
4391#define __cim_disable_stop_intr() \
4392  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
4393
4394#define __cim_enable_trig_intr() \
4395  ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
4396#define __cim_disable_trig_intr() \
4397  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
4398
4399#define __cim_enable_rxfifo_overflow_intr() \
4400  ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
4401#define __cim_disable_rxfifo_overflow_intr() \
4402  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
4403
4404/* n=1-16 */
4405#define __cim_set_frame_rate(n) \
4406do { \
4407    REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
4408    REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
4409} while (0)
4410
4411#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
4412#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
4413
4414#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
4415#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
4416
4417/* n=4,8,12,16,20,24,28,32 */
4418#define __cim_set_rxfifo_trigger(n) \
4419do { \
4420    REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
4421    REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
4422} while (0)
4423
4424#define __cim_clear_state() ( REG_CIM_STATE = 0 )
4425
4426#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
4427#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
4428#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
4429#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
4430#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
4431#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
4432#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
4433#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
4434
4435#define __cim_get_iid() ( REG_CIM_IID )
4436#define __cim_get_image_data() ( REG_CIM_RXFIFO )
4437#define __cim_get_dam_cmd() ( REG_CIM_CMD )
4438
4439#define __cim_set_da(a) ( REG_CIM_DA = (a) )
4440
4441/***************************************************************************
4442 * LCD
4443 ***************************************************************************/
4444#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
4445#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
4446
4447#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
4448#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
4449
4450#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
4451#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
4452
4453/* n=1,2,4,8,16 */
4454#define __lcd_set_bpp(n) \
4455  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
4456
4457/* n=4,8,16 */
4458#define __lcd_set_burst_length(n) \
4459do { \
4460    REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
4461    REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
4462} while (0)
4463
4464#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
4465#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
4466
4467#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
4468#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
4469
4470/* n=2,4,16 */
4471#define __lcd_set_stn_frc(n) \
4472do { \
4473    REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
4474    REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
4475} while (0)
4476
4477
4478#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
4479#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
4480
4481#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
4482#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
4483
4484#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
4485#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
4486
4487#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
4488#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
4489
4490#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
4491#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
4492
4493#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
4494#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
4495
4496#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
4497#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
4498
4499#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
4500#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
4501
4502#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
4503#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
4504
4505
4506/* LCD status register indication */
4507
4508#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
4509#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
4510#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
4511#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
4512#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
4513#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
4514#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
4515
4516#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
4517#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
4518#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
4519
4520#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
4521#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
4522
4523/* n=1,2,4,8 for single mono-STN
4524 * n=4,8 for dual mono-STN
4525 */
4526#define __lcd_set_panel_datawidth(n) \
4527do { \
4528    REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
4529    REG_LCD_CFG |= LCD_CFG_PDW_n##; \
4530} while (0)
4531
4532/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
4533#define __lcd_set_panel_mode(m) \
4534do { \
4535    REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
4536    REG_LCD_CFG |= (m); \
4537} while(0)
4538
4539/* n = 0-255 */
4540#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
4541#define __lcd_set_ac_bias(n) \
4542do { \
4543    REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
4544    REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
4545} while(0)
4546
4547#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
4548#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
4549
4550#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
4551#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
4552
4553#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
4554#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
4555
4556#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
4557#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
4558
4559#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
4560#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
4561
4562#define __lcd_vsync_get_vps() \
4563  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
4564
4565#define __lcd_vsync_get_vpe() \
4566  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
4567#define __lcd_vsync_set_vpe(n) \
4568do { \
4569    REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
4570    REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
4571} while (0)
4572
4573#define __lcd_hsync_get_hps() \
4574  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
4575#define __lcd_hsync_set_hps(n) \
4576do { \
4577    REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
4578    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
4579} while (0)
4580
4581#define __lcd_hsync_get_hpe() \
4582  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
4583#define __lcd_hsync_set_hpe(n) \
4584do { \
4585    REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
4586    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
4587} while (0)
4588
4589#define __lcd_vat_get_ht() \
4590  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
4591#define __lcd_vat_set_ht(n) \
4592do { \
4593    REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
4594    REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
4595} while (0)
4596
4597#define __lcd_vat_get_vt() \
4598  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
4599#define __lcd_vat_set_vt(n) \
4600do { \
4601    REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
4602    REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
4603} while (0)
4604
4605#define __lcd_dah_get_hds() \
4606  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
4607#define __lcd_dah_set_hds(n) \
4608do { \
4609    REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
4610    REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
4611} while (0)
4612
4613#define __lcd_dah_get_hde() \
4614  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
4615#define __lcd_dah_set_hde(n) \
4616do { \
4617    REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
4618    REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
4619} while (0)
4620
4621#define __lcd_dav_get_vds() \
4622  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
4623#define __lcd_dav_set_vds(n) \
4624do { \
4625    REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
4626    REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
4627} while (0)
4628
4629#define __lcd_dav_get_vde() \
4630  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
4631#define __lcd_dav_set_vde(n) \
4632do { \
4633    REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
4634    REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
4635} while (0)
4636
4637#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
4638#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
4639#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
4640#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
4641
4642#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
4643#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
4644#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
4645#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
4646
4647#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
4648#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
4649
4650#define __lcd_cmd0_get_len() \
4651  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4652#define __lcd_cmd1_get_len() \
4653  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4654
4655/***************************************************************************
4656 * RTC ops
4657 ***************************************************************************/
4658
4659#define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY )
4660#define __rtc_enabled() \
4661do{ \
4662      while(!__rtc_write_ready()); \
4663      REG_RTC_RCR |= RTC_RCR_RTCE ; \
4664}while(0) \
4665
4666#define __rtc_disabled() \
4667do{ \
4668      while(!__rtc_write_ready()); \
4669      REG_RTC_RCR &= ~RTC_RCR_RTCE; \
4670}while(0)
4671#define __rtc_enable_alarm() \
4672do{ \
4673      while(!__rtc_write_ready()); \
4674      REG_RTC_RCR |= RTC_RCR_AE; \
4675}while(0)
4676
4677#define __rtc_disable_alarm() \
4678do{ \
4679      while(!__rtc_write_ready()); \
4680      REG_RTC_RCR &= ~RTC_RCR_AE; \
4681}while(0)
4682
4683#define __rtc_enable_alarm_irq() \
4684do{ \
4685      while(!__rtc_write_ready()); \
4686      REG_RTC_RCR |= RTC_RCR_AIE; \
4687}while(0)
4688
4689#define __rtc_disable_alarm_irq() \
4690do{ \
4691      while(!__rtc_write_ready()); \
4692      REG_RTC_RCR &= ~RTC_RCR_AIE; \
4693}while(0)
4694#define __rtc_enable_Hz_irq() \
4695do{ \
4696      while(!__rtc_write_ready()); \
4697      REG_RTC_RCR |= RTC_RCR_HZIE; \
4698}while(0)
4699
4700#define __rtc_disable_Hz_irq() \
4701do{ \
4702      while(!__rtc_write_ready()); \
4703      REG_RTC_RCR &= ~RTC_RCR_HZIE; \
4704}while(0)
4705#define __rtc_get_1Hz_flag() \
4706do{ \
4707      while(!__rtc_write_ready()); \
4708      ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
4709}while(0)
4710#define __rtc_clear_1Hz_flag() \
4711do{ \
4712      while(!__rtc_write_ready()); \
4713      REG_RTC_RCR &= ~RTC_RCR_HZ; \
4714}while(0)
4715#define __rtc_get_alarm_flag() \
4716do{ \
4717       while(!__rtc_write_ready()); \
4718      ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \
4719while(0)
4720#define __rtc_clear_alarm_flag() \
4721do{ \
4722      while(!__rtc_write_ready()); \
4723      REG_RTC_RCR &= ~RTC_RCR_AF; \
4724}while(0)
4725#define __rtc_get_second() \
4726do{ \
4727       while(!__rtc_write_ready());\
4728       REG_RTC_RSR; \
4729}while(0)
4730
4731#define __rtc_set_second(v) \
4732do{ \
4733      while(!__rtc_write_ready()); \
4734      REG_RTC_RSR = v; \
4735}while(0)
4736
4737#define __rtc_get_alarm_second() \
4738do{ \
4739      while(!__rtc_write_ready()); \
4740      REG_RTC_RSAR; \
4741}while(0)
4742
4743
4744#define __rtc_set_alarm_second(v) \
4745do{ \
4746      while(!__rtc_write_ready()); \
4747      REG_RTC_RSAR = v; \
4748}while(0)
4749
4750#define __rtc_RGR_is_locked() \
4751do{ \
4752      while(!__rtc_write_ready()); \
4753      REG_RTC_RGR >> RTC_RGR_LOCK; \
4754}while(0)
4755#define __rtc_lock_RGR() \
4756do{ \
4757      while(!__rtc_write_ready()); \
4758      REG_RTC_RGR |= RTC_RGR_LOCK; \
4759}while(0)
4760
4761#define __rtc_unlock_RGR() \
4762do{ \
4763      while(!__rtc_write_ready()); \
4764      REG_RTC_RGR &= ~RTC_RGR_LOCK; \
4765}while(0)
4766
4767#define __rtc_get_adjc_val() \
4768do{ \
4769      while(!__rtc_write_ready()); \
4770      ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
4771}while(0)
4772#define __rtc_set_adjc_val(v) \
4773do{ \
4774      while(!__rtc_write_ready()); \
4775      ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \
4776}while(0)
4777
4778#define __rtc_get_nc1Hz_val() \
4779      while(!__rtc_write_ready()); \
4780      ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
4781
4782#define __rtc_set_nc1Hz_val(v) \
4783do{ \
4784      while(!__rtc_write_ready()); \
4785      ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \
4786}while(0)
4787#define __rtc_power_down() \
4788do{ \
4789      while(!__rtc_write_ready()); \
4790      REG_RTC_HCR |= RTC_HCR_PD; \
4791}while(0)
4792
4793#define __rtc_get_hwfcr_val() \
4794do{ \
4795      while(!__rtc_write_ready()); \
4796      REG_RTC_HWFCR & RTC_HWFCR_MASK; \
4797}while(0)
4798#define __rtc_set_hwfcr_val(v) \
4799do{ \
4800      while(!__rtc_write_ready()); \
4801      REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \
4802}while(0)
4803
4804#define __rtc_get_hrcr_val() \
4805do{ \
4806      while(!__rtc_write_ready()); \
4807      ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
4808}while(0)
4809#define __rtc_set_hrcr_val(v) \
4810do{ \
4811      while(!__rtc_write_ready()); \
4812      ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \
4813}while(0)
4814
4815#define __rtc_enable_alarm_wakeup() \
4816do{ \
4817      while(!__rtc_write_ready()); \
4818      ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \
4819}while(0)
4820
4821#define __rtc_disable_alarm_wakeup() \
4822do{ \
4823      while(!__rtc_write_ready()); \
4824      ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \
4825}while(0)
4826
4827#define __rtc_status_hib_reset_occur() \
4828do{ \
4829      while(!__rtc_write_ready()); \
4830    ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \
4831}while(0)
4832#define __rtc_status_ppr_reset_occur() \
4833do{ \
4834      while(!__rtc_write_ready()); \
4835   ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \
4836}while(0)
4837#define __rtc_status_wakeup_pin_waken_up() \
4838do{ \
4839      while(!__rtc_write_ready()); \
4840   ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
4841}while(0)
4842#define __rtc_status_alarm_waken_up() \
4843do{ \
4844      while(!__rtc_write_ready()); \
4845  ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
4846}while(0)
4847#define __rtc_clear_hib_stat_all() \
4848do{ \
4849      while(!__rtc_write_ready()); \
4850      ( REG_RTC_HWRSR = 0 ); \
4851}while(0)
4852
4853#define __rtc_get_scratch_pattern() \
4854      while(!__rtc_write_ready()); \
4855          (REG_RTC_HSPR)
4856#define __rtc_set_scratch_pattern(n) \
4857do{ \
4858      while(!__rtc_write_ready()); \
4859      (REG_RTC_HSPR = n ); \
4860}while(0)
4861
4862#endif /* !__ASSEMBLY__ */
4863
4864#endif /* __JZ4740_H__ */
xbboot/target-common/serial.c
1//
2// Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
3//
4// This program is free software; you can redistribute it and/or
5// modify it under the terms of the GNU General Public License
6// as published by the Free Software Foundation; either version
7// 3 of the License, or (at your option) any later version.
8//
9
10#include "serial.h"
11#include "jz4740.h"
12
13u32 UART_BASE;
14
15void serial_putc(char c)
16{
17    volatile u8* uart_lsr = (volatile u8*)(UART_BASE + OFF_LSR);
18    volatile u8* uart_tdr = (volatile u8*)(UART_BASE + OFF_TDR);
19
20    if (c == '\n') serial_putc ('\r');
21
22    /* Wait for fifo to shift out some bytes */
23    while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
24
25    *uart_tdr = (u8) c;
26}
27
28void serial_puts(const char *s)
29{
30    while (*s) serial_putc(*s++);
31}
32
33void serial_put_hex(unsigned int v)
34{
35    unsigned char c[12];
36    char i;
37    for(i = 0; i < 8;i++)
38    {
39        c[i] = (v >> ((7 - i) * 4)) & 0xf;
40        if(c[i] < 10)
41            c[i] += 0x30;
42        else
43            c[i] += (0x41 - 10);
44    }
45    c[8] = '\n';
46    c[9] = 0;
47    serial_puts(c);
48}
49
50int serial_getc()
51{
52    volatile u8* uart_rdr = (volatile u8*)(UART_BASE + OFF_RDR);
53    while (!serial_tstc());
54    return *uart_rdr;
55}
56
57int serial_tstc()
58{
59    volatile u8* uart_lsr = (volatile u8*)(UART_BASE + OFF_LSR);
60    if (*uart_lsr & UART_LSR_DR) {
61        /* Data in rfifo */
62        return 1;
63    }
64    return 0;
65}
xbboot/target-common/serial.h
1//
2// Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
3//
4// This program is free software; you can redistribute it and/or
5// modify it under the terms of the GNU General Public License
6// as published by the Free Software Foundation; either version
7// 3 of the License, or (at your option) any later version.
8//
9
10#include "common-types.h"
11
12extern u32 UART_BASE;
13
14void serial_putc(char c);
15void serial_puts(const char *s);
16void serial_put_hex(unsigned int v);
17int serial_getc();
18int serial_tstc();
xbboot/target-echokernel/.gitignore
1echo-kernel.bin
2echo-kernel.dump
3echo-kernel.lst
4echo-kernel.o
5echo-kernel.sym
6echo-kernel.map
7echo-kernel.elf
8head.lst
9head.o
10serial.lst
11serial.o
xbboot/target-echokernel/Makefile
1#
2# Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
3#
4# This program is free software; you can redistribute it and/or
5# modify it under the terms of the GNU General Public License
6# as published by the Free Software Foundation; either version
7# 3 of the License, or (at your option) any later version.
8#
9
10ifeq ($(CROSS_COMPILE),)
11$(error CROSS_COMPILE variable not set, should point to .../mipsel-openwrt-linux-)
12endif
13
14CC = $(CROSS_COMPILE)gcc
15AR = $(CROSS_COMPILE)ar rcsv
16LD = $(CROSS_COMPILE)ld
17OBJCOPY = $(CROSS_COMPILE)objcopy
18NM = $(CROSS_COMPILE)nm
19OBJDUMP = $(CROSS_COMPILE)objdump
20
21DEBUG_CFLAGS = -g -Wa,-a=$(basename $@).lst
22# Wolfgang saw data corruptions in stage2 when dealing with ECC data on random writes
23# to NAND. Disabling the unit-at-a-time optimization reproducibly fixed the bug.
24# The compiler may be optimizing in a way that conflicts with how the hardware ECC
25# registers work. Since other register accesses might be affected too it seems the best
26# is to disable this optimization right now.
27CFLAGS = -mips32 -O2 -fno-exceptions -fno-unit-at-a-time -fno-zero-initialized-in-bss \
28    -ffunction-sections -fomit-frame-pointer -msoft-float -G 0 $(DEBUG_CFLAGS)
29LDFLAGS = -nostdlib -T target.ld $(CFLAGS)
30LIBS = -lstdc++ -lc -lm -lgcc
31VPATH = ../target-common
32
33OBJS = echo-kernel.o serial.o
34
35all: echo-kernel.elf
36    $(OBJCOPY) -O binary echo-kernel.elf echo-kernel.bin
37    $(OBJDUMP) -D echo-kernel.elf > echo-kernel.dump
38    $(NM) echo-kernel.elf | sort > echo-kernel.sym
39    $(OBJDUMP) -h echo-kernel.elf > echo-kernel.map
40
41echo-kernel.elf: head.o $(OBJS)
42    $(CC) $(LDFLAGS) $^ -o $@
43
44.c.o:
45    $(CC) $(CFLAGS) -o $@ -c $<
46.cpp.o:
47    $(CC) $(CFLAGS) -fno-rtti -fvtable-gc -o $@ -c $<
48.S.o:
49    $(CC) $(CFLAGS) -o $@ -c $<
50
51clean:
52    rm -f $(addprefix echo-kernel., bin dump elf map sym)
53    rm -f head.o head.lst $(OBJS) $(OBJS:.o=.lst)
xbboot/target-echokernel/echo-kernel.c
1//
2// Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
3//
4// This program is free software; you can redistribute it and/or
5// modify it under the terms of the GNU General Public License
6// as published by the Free Software Foundation; either version
7// 3 of the License, or (at your option) any later version.
8//
9
10#include <inttypes.h>
11#include "../target-common/jz4740.h"
12#include "../target-common/serial.h"
13
14void c_main();
15
16void pre_main(void)
17{
18    volatile unsigned int start_addr, got_start, got_end, addr, offset;
19
20    /* get absolute start address */
21    __asm__ __volatile__(
22        "move %0, $20\n\t"
23        : "=r"(start_addr)
24        :
25        );
26
27    /* get related GOT address */
28    __asm__ __volatile__(
29        "la $4, _GLOBAL_OFFSET_TABLE_\n\t"
30        "move %0, $4\n\t"
31        "la $5, _got_end\n\t"
32        "move %1, $5\n\t"
33        : "=r"(got_start),"=r"(got_end)
34        :
35        );
36
37    /* calculate offset and correct GOT*/
38    offset = start_addr - 0x80000000;
39     got_start += offset;
40    got_end += offset;
41
42    for ( addr = got_start + 8; addr < got_end; addr += 4 )
43        *((volatile unsigned int *)(addr)) += offset; // add offset to correct all GOT
44
45// fw_args = (struct fw_args *)(start_addr + 0x8); //get the fw args from memory
46    UART_BASE = 0xB0030000;
47    serial_puts("Start address is:");
48    serial_put_hex(start_addr);
49    serial_puts("Address offset is:");
50    serial_put_hex(start_addr - 0x80000000);
51    serial_puts("GOT corrected to:");
52    serial_put_hex(got_start);
53    c_main();
54}
55
56void c_main()
57{
58    // start infinite 'echo' kernel
59    while (1) {
60        if (serial_tstc()) {
61            int c = serial_getc();
62            serial_putc(c);
63            if (c == '\r')
64                serial_putc('\n');
65        }
66    }
67}
xbboot/target-echokernel/head.S
1//
2// Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
3//
4// This program is free software; you can redistribute it and/or
5// modify it under the terms of the GNU General Public License
6// as published by the Free Software Foundation; either version
7// 3 of the License, or (at your option) any later version.
8//
9
10    .text
11    .extern pre_main
12
13    .globl _start
14    .set noreorder
15_start:
16    b real_start
17    nop
18    .word 0x0 // its address == start address + 8
19    .word 0x0
20    .word 0x0
21    .word 0x0
22    .word 0x0
23    .word 0x0
24    .word 0x0
25    .word 0x0
26
27real_start:
28    /* setup stack, jump to C code */
29    add $29, $20, 0x3ffff0 // sp locate at start address offset 0x2ffff0
30    add $25, $20, 0x40 // t9 = pre_main()
31    j $25
32    nop
33
34    .set reorder
xbboot/target-echokernel/target.ld
1OUTPUT_ARCH(mips)
2ENTRY(_start)
3MEMORY
4{
5    ram : ORIGIN = 0x80000000 , LENGTH = 3M
6}
7
8SECTIONS
9{
10    . = ALIGN(4);
11    .text : { *(.text*) } > ram
12
13    . = ALIGN(4);
14    .rodata : { *(.rodata*) } > ram
15
16    . = ALIGN(4);
17    .sdata : { *(.sdata*) } > ram
18
19    . = ALIGN(4);
20    .data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram
21
22    _gp = ALIGN(16);
23
24    .got : { *(.got*) } > ram
25    _got_end = ABSOLUTE(.);
26
27    . = ALIGN(4);
28    .sbss : { *(.sbss*) } > ram
29    .bss : { *(.bss*) } > ram
30    . = ALIGN (4);
31}
xbboot/target-stage1/.gitignore
1System.map
2head.o
3stage1.o
4stage1.bin
5stage1.dump
6stage1.elf
7stage1.map
8serial.o
xbboot/target-stage1/Makefile
1#
2# Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
3#
4# This program is free software; you can redistribute it and/or
5# modify it under the terms of the GNU General Public License
6# as published by the Free Software Foundation; either version
7# 3 of the License, or (at your option) any later version.
8#
9
10ifeq ($(CROSS_COMPILE),)
11$(error CROSS_COMPILE variable not set, should point to .../mipsel-openwrt-linux-)
12endif
13
14CFLAGS = -O2 -fno-unit-at-a-time -fno-zero-initialized-in-bss -mips32 -fno-pic \
15      -mno-abicalls -I$(INFLASH_SRC_PATH) -I$(XBURST_INCLUDE_PATH)
16LDFLAGS = -nostdlib -EL -T target.ld
17VPATH = ../target-common
18
19OBJS = head.o stage1.o serial.o
20
21all: stage1.bin
22
23stage1.bin: stage1.elf
24    $(CROSS_COMPILE)objcopy -O binary $< $@
25    $(CROSS_COMPILE)objdump -D $< > stage1.dump
26    $(CROSS_COMPILE)objdump -h $< > stage1.map
27    $(CROSS_COMPILE)nm -n $< > System.map
28
29stage1.elf: $(OBJS)
30    $(CROSS_COMPILE)ld $(LDFLAGS) $(OBJS) -o $@
31.c.o:
32    $(CROSS_COMPILE)gcc $(CFLAGS) -c $< -o $@
33.S.o:
34    $(CROSS_COMPILE)gcc $(CFLAGS) -c $< -o $@
35clean:
36    rm -f stage1.bin stage1.elf stage1.dump stage1.map
37    rm -f $(OBJS)
38    rm -f System.map
xbboot/target-stage1/head.S
1//
2// Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
3//
4// This program is free software; you can redistribute it and/or
5// modify it under the terms of the GNU General Public License
6// as published by the Free Software Foundation; either version
7// 3 of the License, or (at your option) any later version.
8//
9
10    .text
11    .extern c_main
12    .globl _start
13    .set noreorder
14
15_start:
16    b real_start
17    nop
18    // 8 words for firmware parameters (0x80002008)
19    .word 0x0
20    .word 0x0
21    .word 0x0
22    .word 0x0
23    .word 0x0
24    .word 0x0
25    .word 0x0
26    .word 0x0
27
28real_start:
29    la $29, 0x80004000 // setup stack (sp)
30    j c_main
31    nop
32
33    .set reorder
xbboot/target-stage1/stage1.c
1//
2// Authors: Wolfgang Spraul <wolfgang@qi-hardware.com>
3//
4// This program is free software; you can redistribute it and/or
5// modify it under the terms of the GNU General Public License
6// as published by the Free Software Foundation; either version
7// 3 of the License, or (at your option) any later version.
8//
9
10#include <inttypes.h>
11#include "../target-common/jz4740.h"
12#include "../target-common/serial.h"
13
14#define STAGE1_ARGS_ADDR 0x80002008
15
16struct stage1_args {
17    // PLL
18    unsigned char ext_clk; // external crystal in MHz
19    unsigned char cpu_speed; // PLL output frequency=cpu_speed * ext_clk Mhz
20    unsigned char phm_div; // frequency divider ratio of PLL=CCLK:PCLK=HCLK=MCLK
21
22    // UART
23    unsigned char uart_num; // which UART to use (default: 0)
24    unsigned int uart_baud; // default: 57600
25
26    // SDRAM
27    unsigned char bus_width_16; // bus width of SDRAM is 16-bit (default is 32-bit)
28    unsigned char bank_addr_2bit; // 2-bit bank address width (=4 banks each chip select), default is 1-bit bank address=2 banks
29    unsigned char row_addr; // row address width in bits (11-13)
30    unsigned char col_addr; // column address width in bits (8-12)
31} __attribute__((packed));
32
33void load_args();
34void gpio_init();
35void pll_init();
36void serial_init();
37void sdram_init();
38
39void c_main(void)
40{
41    load_args();
42    gpio_init();
43    pll_init();
44    serial_init();
45    serial_puts("XBurst boot stage1...\n");
46    sdram_init();
47    serial_puts("stage 1 finished: GPIO, clocks, SDRAM, UART setup - now jump back to BOOT ROM...\n");
48}
49
50// tbd: do they have to be copied into globals? or just reference STAGE1_ARGS_ADDR?
51volatile u32 ARG_EXTAL;
52volatile u32 ARG_CPU_SPEED;
53volatile u8 ARG_PHM_DIV;
54volatile u32 ARG_UART_BASE;
55volatile u32 ARG_UART_BAUD;
56volatile u8 ARG_BUS_WIDTH_16;
57volatile u8 ARG_BANK_ADDR_2BIT;
58volatile u8 ARG_ROW_ADDR;
59volatile u8 ARG_COL_ADDR;
60
61void load_args()
62{
63    struct stage1_args* args = (struct stage1_args*) STAGE1_ARGS_ADDR;
64// NanoNote defaults
65args->ext_clk = 12;
66args->cpu_speed = 21;
67args->phm_div = 3;
68args->uart_num = 0;
69args->uart_baud = 57600;
70args->bus_width_16 = 1;
71args->bank_addr_2bit = 1;
72args->row_addr = 13;
73args->col_addr = 9;
74// END NanoNote defaults
75    ARG_EXTAL = args->ext_clk * 1000000;
76    ARG_CPU_SPEED = args->cpu_speed * ARG_EXTAL;
77    ARG_PHM_DIV = args->phm_div;
78    ARG_UART_BASE = UART0_BASE + args->uart_num * UART_OFF;
79    UART_BASE = ARG_UART_BASE; // for ../target-common/serial.c
80    ARG_UART_BAUD = args->uart_baud;
81    ARG_BUS_WIDTH_16 = args->bus_width_16;
82    ARG_BANK_ADDR_2BIT = args->bank_addr_2bit;
83    ARG_ROW_ADDR = args->row_addr;
84    ARG_COL_ADDR = args->col_addr;
85}
86
87void gpio_init()
88{
89    __gpio_as_nand();
90    __gpio_as_sdram_32bit();
91