Date:2010-06-18 08:33:47 (4 years 3 months ago)
Author:Xiangfu Liu
Commit:bcc23ae567cc592207ff9449a6885a1c58971e27
Message:add jz4760 support to xburst_stage1

Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
Files: usbboot/xburst_include/target/configs.h (3 diffs)
usbboot/xburst_include/target/jz4750.h (1 diff)
usbboot/xburst_include/target/jz4760.h (1 diff)
usbboot/xburst_stage1/Makefile (1 diff)
usbboot/xburst_stage1/board-jz4760.c (1 diff)
usbboot/xburst_stage1/board-jz4760.h (1 diff)
usbboot/xburst_stage1/board_4750.c (1 diff)
usbboot/xburst_stage1/common.c (1 diff)
usbboot/xburst_stage1/debug.c (2 diffs)
usbboot/xburst_stage1/main.c (4 diffs)

Change Details

usbboot/xburst_include/target/configs.h
2525/* Once your system configration change, just modify the file */
2626
2727#include "target/xburst_types.h"
28
2829#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
2930#define SDRAM_CASL 3 /* CAS latency: 2 or 3 */
3031/* SDRAM Timings, unit: ns */
...... 
3435#define SDRAM_TRWL 7 /* Write Latency Time */
3536#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
3637
37
3838extern volatile u32 CPU_ID;
3939extern volatile u8 SDRAM_BW16;
4040extern volatile u8 SDRAM_BANK4;
...... 
4848extern volatile u32 UART_BASE;
4949extern volatile u8 CONFIG_MOBILE_SDRAM;
5050extern volatile u8 IS_SHARE;
51
52extern void gpio_init_4740(void);
53extern void sdram_init_4740(void);
54extern void pll_init_4740(void);
55
56extern void gpio_init_4760(void);
57extern void sdram_init_4760(void);
58extern void pll_init_4760(void);
59
6051#endif
usbboot/xburst_include/target/jz4750.h
1/*
2 * Include file for Ingenic Semiconductor's JZ4750 CPU.
3 *
4 * Copyright 2009 (C) Qi Hardware Inc.,
5 * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 3 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
19 * Boston, MA 02110-1301, USA
20 */
21
22#ifndef __JZ4750_H__
23#define __JZ4750_H__
24
25#include "xburst_types.h"
26
27#ifndef __ASSEMBLY__
28#define UCOS_CSP 0
29
30#if 0
31#if UCOS_CSP
32#define __KERNEL__
33#include <bsp.h>
34#include <types.h>
35
36#include <sysdefs.h>
37#include <cacheops.h>
38#define KSEG0 KSEG0BASE
39#else
40#include <asm/addrspace.h>
41#include <asm/cacheops.h>
42#endif
43#endif
44#define cache_unroll(base,op) \
45    __asm__ __volatile__(" \
46        .set noreorder; \
47        .set mips3; \
48        cache %1, (%0); \
49        .set mips0; \
50        .set reorder" \
51        : \
52        : "r" (base), \
53          "i" (op));
54#if 0
55static inline void jz_flush_dcache(void)
56{
57    unsigned long start;
58    unsigned long end;
59
60    start = KSEG0;
61    end = start + CFG_DCACHE_SIZE;
62    while (start < end) {
63        cache_unroll(start,Index_Writeback_Inv_D);
64        start += CFG_CACHELINE_SIZE;
65    }
66}
67
68static inline void jz_flush_icache(void)
69{
70    unsigned long start;
71    unsigned long end;
72
73    start = KSEG0;
74    end = start + CFG_ICACHE_SIZE;
75    while(start < end) {
76        cache_unroll(start,Index_Invalidate_I);
77        start += CFG_CACHELINE_SIZE;
78    }
79}
80
81#endif
82/* cpu pipeline flush */
83static inline void jz_sync(void)
84{
85    __asm__ volatile ("sync");
86}
87
88static inline void jz_writeb(u32 address, u8 value)
89{
90    *((volatile u8 *)address) = value;
91}
92
93static inline void jz_writew(u32 address, u16 value)
94{
95    *((volatile u16 *)address) = value;
96}
97
98static inline void jz_writel(u32 address, u32 value)
99{
100    *((volatile u32 *)address) = value;
101}
102
103static inline u8 jz_readb(u32 address)
104{
105    return *((volatile u8 *)address);
106}
107
108static inline u16 jz_readw(u32 address)
109{
110    return *((volatile u16 *)address);
111}
112
113static inline u32 jz_readl(u32 address)
114{
115    return *((volatile u32 *)address);
116}
117
118#define REG8(addr) *((volatile u8 *)(addr))
119#define REG16(addr) *((volatile u16 *)(addr))
120#define REG32(addr) *((volatile u32 *)(addr))
121
122#else
123
124#define REG8(addr) (addr)
125#define REG16(addr) (addr)
126#define REG32(addr) (addr)
127
128#endif /* !ASSEMBLY */
129
130//----------------------------------------------------------------------
131// Boot ROM Specification
132//
133
134/* NOR Boot config */
135#define JZ4750_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
136#define JZ4750_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
137#define JZ4750_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
138
139/* NAND Boot config */
140#define JZ4750_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
141#define JZ4750_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
142#define JZ4750_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
143#define JZ4750_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
144
145
146//----------------------------------------------------------------------
147// Register Definitions
148//
149#define CPM_BASE 0xB0000000
150#define INTC_BASE 0xB0001000
151#define TCU_BASE 0xB0002000
152#define WDT_BASE 0xB0002000
153#define RTC_BASE 0xB0003000
154#define GPIO_BASE 0xB0010000
155#define AIC_BASE 0xB0020000
156#define ICDC_BASE 0xB0020000
157#define MSC_BASE 0xB0021000
158#define UART0_BASE 0xB0030000
159#define UART1_BASE 0xB0031000
160#define UART2_BASE 0xB0032000
161#define UART3_BASE 0xB0033000
162#define I2C_BASE 0xB0042000
163#define SSI_BASE 0xB0043000
164#define SADC_BASE 0xB0070000
165#define EMC_BASE 0xB3010000
166#define DMAC_BASE 0xB3020000
167#define UHC_BASE 0xB3030000
168#define UDC_BASE 0xB3040000
169#define LCD_BASE 0xB3050000
170#define SLCD_BASE 0xB3050000
171#define CIM_BASE 0xB3060000
172#define BCH_BASE 0xB30D0000
173#define ETH_BASE 0xB3100000
174
175
176/*************************************************************************
177 * INTC (Interrupt Controller)
178 *************************************************************************/
179#define INTC_ISR (INTC_BASE + 0x00)
180#define INTC_IMR (INTC_BASE + 0x04)
181#define INTC_IMSR (INTC_BASE + 0x08)
182#define INTC_IMCR (INTC_BASE + 0x0c)
183#define INTC_IPR (INTC_BASE + 0x10)
184
185#define REG_INTC_ISR REG32(INTC_ISR)
186#define REG_INTC_IMR REG32(INTC_IMR)
187#define REG_INTC_IMSR REG32(INTC_IMSR)
188#define REG_INTC_IMCR REG32(INTC_IMCR)
189#define REG_INTC_IPR REG32(INTC_IPR)
190
191// 1st-level interrupts
192#define IRQ_OWI 0
193#define IRQ_I2C 1
194#define IRQ_TSSI 2
195#define IRQ_UART3 3
196#define IRQ_UART2 4
197#define IRQ_UART1 5
198#define IRQ_UART0 6
199#define IRQ_PCM 7
200#define IRQ_AIC 8
201#define IRQ_RTC 9
202#define IRQ_SADC 10
203#define IRQ_SSI1 11
204#define IRQ_SSI0 12
205#define IRQ_MSC1 13
206#define IRQ_MSC0 14
207#define IRQ_ETH 15
208#define IRQ_BCH 16
209#define IRQ_UHC 17
210#define IRQ_CIM 18
211#define IRQ_UDC 19
212#define IRQ_DMAC 20
213#define IRQ_TCU2 21
214#define IRQ_TCU1 22
215#define IRQ_TCU0 23
216#define IRQ_GPIO5 24
217#define IRQ_GPIO4 25
218#define IRQ_GPIO3 26
219#define IRQ_GPIO2 27
220#define IRQ_GPIO1 28
221#define IRQ_GPIO0 29
222#define IRQ_IPU 30
223#define IRQ_LCD 31
224
225// 2nd-level interrupts
226#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
227#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
228
229
230/*************************************************************************
231 * RTC
232 *************************************************************************/
233#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
234#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
235#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
236#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
237
238#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
239#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
240#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
241#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
242#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
243#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
244
245#define REG_RTC_RCR REG32(RTC_RCR)
246#define REG_RTC_RSR REG32(RTC_RSR)
247#define REG_RTC_RSAR REG32(RTC_RSAR)
248#define REG_RTC_RGR REG32(RTC_RGR)
249#define REG_RTC_HCR REG32(RTC_HCR)
250#define REG_RTC_HWFCR REG32(RTC_HWFCR)
251#define REG_RTC_HRCR REG32(RTC_HRCR)
252#define REG_RTC_HWCR REG32(RTC_HWCR)
253#define REG_RTC_HWRSR REG32(RTC_HWRSR)
254#define REG_RTC_HSPR REG32(RTC_HSPR)
255
256/* RTC Control Register */
257#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
258#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
259#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
260#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
261#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
262#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
263#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
264
265/* RTC Regulator Register */
266#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
267#define RTC_RGR_ADJC_BIT 16
268#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
269#define RTC_RGR_NC1HZ_BIT 0
270#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
271
272/* Hibernate Control Register */
273#define RTC_HCR_PD (1 << 0) /* Power Down */
274
275/* Hibernate Wakeup Filter Counter Register */
276#define RTC_HWFCR_BIT 5
277#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
278
279/* Hibernate Reset Counter Register */
280#define RTC_HRCR_BIT 5
281#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
282
283/* Hibernate Wakeup Control Register */
284#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
285
286/* Hibernate Wakeup Status Register */
287#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
288#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
289#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
290#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
291
292
293/*************************************************************************
294 * CPM (Clock reset and Power control Management)
295 *************************************************************************/
296#define CPM_CPCCR (CPM_BASE+0x00)
297#define CPM_CPPCR (CPM_BASE+0x10)
298#define CPM_CPPSR (CPM_BASE+0x14) /* PLL Switch and Status Register */
299#define CPM_I2SCDR (CPM_BASE+0x60)
300#define CPM_LPCDR (CPM_BASE+0x64)
301#define CPM_MSCCDR(n) (CPM_BASE+0x10*(n)+0x68) /* MSC0(n=0) or MSC1(n=1) device clock divider Register */
302#define CPM_UHCCDR (CPM_BASE+0x6C)
303#define CPM_SSICDR (CPM_BASE+0x74)
304#define CPM_PCMCDR (CPM_BASE+0x7C) /* PCM device clock divider Register */
305
306#define CPM_LCR (CPM_BASE+0x04)
307#define CPM_CLKGR (CPM_BASE+0x20)
308#define CPM_OPCR (CPM_BASE+0x24) /* Oscillator and Power Control Register */
309
310#define CPM_RSR (CPM_BASE+0x08)
311
312#define REG_CPM_CPCCR REG32(CPM_CPCCR)
313#define REG_CPM_CPPCR REG32(CPM_CPPCR)
314#define REG_CPM_CPPSR REG32(CPM_CPPSR)
315#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
316#define REG_CPM_LPCDR REG32(CPM_LPCDR)
317#define REG_CPM_MSCCDR(n) REG32(CPM_MSCCDR(n))
318#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
319#define REG_CPM_SSICDR REG32(CPM_SSICDR)
320#define REG_CPM_PCMCDR REG32(CPM_PCMCDR)
321
322#define REG_CPM_LCR REG32(CPM_LCR)
323#define REG_CPM_CLKGR REG32(CPM_CLKGR)
324#define REG_CPM_OPCR REG32(CPM_OPCR)
325
326#define REG_CPM_RSR REG32(CPM_RSR)
327
328/* Clock Control Register */
329#define CPM_CPCCR_I2CS (1 << 31)
330#define CPM_CPCCR_ECS (1 << 30) /* Select the between EXCLK and EXCLK/2 output */
331#define CPM_CPCCR_UCS (1 << 29)
332#define CPM_CPCCR_UDIV_BIT 23
333#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
334#define CPM_CPCCR_CE (1 << 22)
335#define CPM_CPCCR_PCS (1 << 21)
336#define CPM_CPCCR_LDIV_BIT 16
337#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
338#define CPM_CPCCR_MDIV_BIT 12
339#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
340#define CPM_CPCCR_PDIV_BIT 8
341#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
342#define CPM_CPCCR_HDIV_BIT 4
343#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
344#define CPM_CPCCR_CDIV_BIT 0
345#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
346
347/* PLL Switch and Status Register */
348#define CPM_CPPSR_PLLOFF 31
349#define CPM_CPPSR_PLLBP 30
350#define CPM_CPPSR_PLLON 29
351#define CPM_CPPSR_PS 28 /* Indicate whether the PLL parameters' change has finished */
352#define CPM_CPPSR_FS 27 /* Indicate whether the main clock's change has finished */
353#define CPM_CPPSR_CS 26 /* Indicate whether the clock switch has finished */
354#define CPM_CPPSR_PM 1 /* Clock switch mode */
355#define CPM_CPPSR_FM 0 /* Clock frequency change mode */
356
357/* I2S Clock Divider Register */
358#define CPM_I2SCDR_I2SDIV_BIT 0
359#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
360
361/* LCD Pixel Clock Divider Register */
362#define CPM_LPCDR_LSCS 31 /* TV encoder Source Pixel Clock Selection */
363#define CPM_LPCDR_LPCS 30 /* LCD Panel pix clock Selection */
364#define CPM_LPCDR_LTCS 29 /* LCD TV Encoder or Panel pix clock Selection */
365#define CPM_LPCDR_PIXDIV_BIT 0
366#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
367
368/* MSC Clock Divider Register */
369#define CPM_MSCCDR_MSCDIV_BIT 0
370#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
371
372/* UHC Clock Divider Register */
373#define CPM_UHCCDR_UHCDIV_BIT 0
374#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
375
376/* SSI Clock Divider Register */
377#define CPM_SSICDR_SSIDIV_BIT 0
378#define CPM_SSICDR_SSIDIV_MASK (0xf << CPM_SSICDR_SSIDIV_BIT)
379
380/* PCM device clock divider Register */
381#define CPM_PCMCDR_PCMS 31 /* PCM source clock Selection */
382#define CPM_PCMCDR_PCMCD_BIT 0
383#define CPM_PCMCDR_PCMCD_MASK (0x1ff << CPM_PCMCDR_PCMCD_BIT)
384
385/* PLL Control Register */
386#define CPM_CPPCR_PLLM_BIT 23
387#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
388#define CPM_CPPCR_PLLN_BIT 18
389#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
390#define CPM_CPPCR_PLLOD_BIT 16
391#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
392#define CPM_CPPCR_PLLS (1 << 10) /* obsolete, replaced by CPM_CPPSR_PLLON */
393#define CPM_CPPCR_PLLBP (1 << 9)
394#define CPM_CPPCR_PLLEN (1 << 8)
395#define CPM_CPPCR_PLLST_BIT 0
396#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
397
398/* Low Power Control Register */
399#define CPM_LCR_DOZE_DUTY_BIT 3
400#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
401#define CPM_LCR_DOZE_ON (1 << 2)
402#define CPM_LCR_LPM_BIT 0
403#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
404  #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
405  #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
406
407/* Clock Gate Register */
408#define CPM_CLKGR_CIMRAM (1 << 28)
409#define CPM_CLKGR_IDCT (1 << 27)
410#define CPM_CLKGR_DB (1 << 26)
411#define CPM_CLKGR_ME (1 << 25)
412#define CPM_CLKGR_MC (1 << 24)
413#define CPM_CLKGR_TVE (1 << 23)
414#define CPM_CLKGR_TSSI (1 << 22)
415#define CPM_CLKGR_OWI (1 << 21)
416#define CPM_CLKGR_PCM (1 << 20)
417#define CPM_CLKGR_MSC1 (1 << 19)
418#define CPM_CLKGR_SSI0 (1 << 18)
419#define CPM_CLKGR_UART3 (1 << 17)
420#define CPM_CLKGR_UART2 (1 << 16)
421#define CPM_CLKGR_UART1 (1 << 15)
422#define CPM_CLKGR_UHC (1 << 14)
423#define CPM_CLKGR_IPU (1 << 13)
424#define CPM_CLKGR_DMAC (1 << 12)
425#define CPM_CLKGR_UDC (1 << 11)
426#define CPM_CLKGR_LCD (1 << 10)
427#define CPM_CLKGR_CIM (1 << 9)
428#define CPM_CLKGR_SADC (1 << 8)
429#define CPM_CLKGR_MSC0 (1 << 7)
430#define CPM_CLKGR_AIC1 (1 << 6)
431#define CPM_CLKGR_AIC2 (1 << 5)
432#define CPM_CLKGR_SSI1 (1 << 4)
433#define CPM_CLKGR_I2C (1 << 3)
434#define CPM_CLKGR_RTC (1 << 2)
435#define CPM_CLKGR_TCU (1 << 1)
436#define CPM_CLKGR_UART0 (1 << 0)
437
438/* Oscillator and Power Control Register */
439#define CPM_OPCR_O1ST_BIT 8
440#define CPM_OPCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
441#define CPM_OPCR_UHCPHY_DISABLE (1 << 7)
442#define CPM_OPCR_UDCPHY_ENABLE (1 << 6)
443#define CPM_OPCR_OSC_ENABLE (1 << 4)
444#define CPM_OPCR_ERCS (1 << 2) /* EXCLK/512 clock and RTCLK clock selection */
445#define CPM_OPCR_MOSE (1 << 1) /* Main Oscillator Enable */
446#define CPM_OPCR_MCS (1 << 0) /* Main clock source select register */
447
448/* Reset Status Register */
449#define CPM_RSR_HR (1 << 2)
450#define CPM_RSR_WR (1 << 1)
451#define CPM_RSR_PR (1 << 0)
452
453
454/*************************************************************************
455 * TCU (Timer Counter Unit)
456 *************************************************************************/
457#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
458#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
459#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
460#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
461#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
462#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
463#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
464#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
465#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
466#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
467#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
468#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
469#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
470#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
471#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
472#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
473#define TCU_TDFR1 (TCU_BASE + 0x50)
474#define TCU_TDHR1 (TCU_BASE + 0x54)
475#define TCU_TCNT1 (TCU_BASE + 0x58)
476#define TCU_TCSR1 (TCU_BASE + 0x5C)
477#define TCU_TDFR2 (TCU_BASE + 0x60)
478#define TCU_TDHR2 (TCU_BASE + 0x64)
479#define TCU_TCNT2 (TCU_BASE + 0x68)
480#define TCU_TCSR2 (TCU_BASE + 0x6C)
481#define TCU_TDFR3 (TCU_BASE + 0x70)
482#define TCU_TDHR3 (TCU_BASE + 0x74)
483#define TCU_TCNT3 (TCU_BASE + 0x78)
484#define TCU_TCSR3 (TCU_BASE + 0x7C)
485#define TCU_TDFR4 (TCU_BASE + 0x80)
486#define TCU_TDHR4 (TCU_BASE + 0x84)
487#define TCU_TCNT4 (TCU_BASE + 0x88)
488#define TCU_TCSR4 (TCU_BASE + 0x8C)
489#define TCU_TDFR5 (TCU_BASE + 0x90)
490#define TCU_TDHR5 (TCU_BASE + 0x94)
491#define TCU_TCNT5 (TCU_BASE + 0x98)
492#define TCU_TCSR5 (TCU_BASE + 0x9C)
493
494#define REG_TCU_TSR REG32(TCU_TSR)
495#define REG_TCU_TSSR REG32(TCU_TSSR)
496#define REG_TCU_TSCR REG32(TCU_TSCR)
497#define REG_TCU_TER REG8(TCU_TER)
498#define REG_TCU_TESR REG8(TCU_TESR)
499#define REG_TCU_TECR REG8(TCU_TECR)
500#define REG_TCU_TFR REG32(TCU_TFR)
501#define REG_TCU_TFSR REG32(TCU_TFSR)
502#define REG_TCU_TFCR REG32(TCU_TFCR)
503#define REG_TCU_TMR REG32(TCU_TMR)
504#define REG_TCU_TMSR REG32(TCU_TMSR)
505#define REG_TCU_TMCR REG32(TCU_TMCR)
506#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
507#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
508#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
509#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
510#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
511#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
512#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
513#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
514#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
515#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
516#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
517#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
518#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
519#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
520#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
521#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
522#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
523#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
524#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
525#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
526
527// n = 0,1,2,3,4,5
528#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
529#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
530#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
531#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
532
533#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
534#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
535#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
536#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
537
538// Register definitions
539#define TCU_TCSR_PWM_SD (1 << 9)
540#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
541#define TCU_TCSR_PWM_EN (1 << 7)
542#define TCU_TCSR_PRESCALE_BIT 3
543#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
544  #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
545  #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
546  #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
547  #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
548  #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
549  #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
550#define TCU_TCSR_EXT_EN (1 << 2)
551#define TCU_TCSR_RTC_EN (1 << 1)
552#define TCU_TCSR_PCK_EN (1 << 0)
553
554#define TCU_TER_TCEN5 (1 << 5)
555#define TCU_TER_TCEN4 (1 << 4)
556#define TCU_TER_TCEN3 (1 << 3)
557#define TCU_TER_TCEN2 (1 << 2)
558#define TCU_TER_TCEN1 (1 << 1)
559#define TCU_TER_TCEN0 (1 << 0)
560
561#define TCU_TESR_TCST5 (1 << 5)
562#define TCU_TESR_TCST4 (1 << 4)
563#define TCU_TESR_TCST3 (1 << 3)
564#define TCU_TESR_TCST2 (1 << 2)
565#define TCU_TESR_TCST1 (1 << 1)
566#define TCU_TESR_TCST0 (1 << 0)
567
568#define TCU_TECR_TCCL5 (1 << 5)
569#define TCU_TECR_TCCL4 (1 << 4)
570#define TCU_TECR_TCCL3 (1 << 3)
571#define TCU_TECR_TCCL2 (1 << 2)
572#define TCU_TECR_TCCL1 (1 << 1)
573#define TCU_TECR_TCCL0 (1 << 0)
574
575#define TCU_TFR_HFLAG5 (1 << 21)
576#define TCU_TFR_HFLAG4 (1 << 20)
577#define TCU_TFR_HFLAG3 (1 << 19)
578#define TCU_TFR_HFLAG2 (1 << 18)
579#define TCU_TFR_HFLAG1 (1 << 17)
580#define TCU_TFR_HFLAG0 (1 << 16)
581#define TCU_TFR_FFLAG5 (1 << 5)
582#define TCU_TFR_FFLAG4 (1 << 4)
583#define TCU_TFR_FFLAG3 (1 << 3)
584#define TCU_TFR_FFLAG2 (1 << 2)
585#define TCU_TFR_FFLAG1 (1 << 1)
586#define TCU_TFR_FFLAG0 (1 << 0)
587
588#define TCU_TFSR_HFLAG5 (1 << 21)
589#define TCU_TFSR_HFLAG4 (1 << 20)
590#define TCU_TFSR_HFLAG3 (1 << 19)
591#define TCU_TFSR_HFLAG2 (1 << 18)
592#define TCU_TFSR_HFLAG1 (1 << 17)
593#define TCU_TFSR_HFLAG0 (1 << 16)
594#define TCU_TFSR_FFLAG5 (1 << 5)
595#define TCU_TFSR_FFLAG4 (1 << 4)
596#define TCU_TFSR_FFLAG3 (1 << 3)
597#define TCU_TFSR_FFLAG2 (1 << 2)
598#define TCU_TFSR_FFLAG1 (1 << 1)
599#define TCU_TFSR_FFLAG0 (1 << 0)
600
601#define TCU_TFCR_HFLAG5 (1 << 21)
602#define TCU_TFCR_HFLAG4 (1 << 20)
603#define TCU_TFCR_HFLAG3 (1 << 19)
604#define TCU_TFCR_HFLAG2 (1 << 18)
605#define TCU_TFCR_HFLAG1 (1 << 17)
606#define TCU_TFCR_HFLAG0 (1 << 16)
607#define TCU_TFCR_FFLAG5 (1 << 5)
608#define TCU_TFCR_FFLAG4 (1 << 4)
609#define TCU_TFCR_FFLAG3 (1 << 3)
610#define TCU_TFCR_FFLAG2 (1 << 2)
611#define TCU_TFCR_FFLAG1 (1 << 1)
612#define TCU_TFCR_FFLAG0 (1 << 0)
613
614#define TCU_TMR_HMASK5 (1 << 21)
615#define TCU_TMR_HMASK4 (1 << 20)
616#define TCU_TMR_HMASK3 (1 << 19)
617#define TCU_TMR_HMASK2 (1 << 18)
618#define TCU_TMR_HMASK1 (1 << 17)
619#define TCU_TMR_HMASK0 (1 << 16)
620#define TCU_TMR_FMASK5 (1 << 5)
621#define TCU_TMR_FMASK4 (1 << 4)
622#define TCU_TMR_FMASK3 (1 << 3)
623#define TCU_TMR_FMASK2 (1 << 2)
624#define TCU_TMR_FMASK1 (1 << 1)
625#define TCU_TMR_FMASK0 (1 << 0)
626
627#define TCU_TMSR_HMST5 (1 << 21)
628#define TCU_TMSR_HMST4 (1 << 20)
629#define TCU_TMSR_HMST3 (1 << 19)
630#define TCU_TMSR_HMST2 (1 << 18)
631#define TCU_TMSR_HMST1 (1 << 17)
632#define TCU_TMSR_HMST0 (1 << 16)
633#define TCU_TMSR_FMST5 (1 << 5)
634#define TCU_TMSR_FMST4 (1 << 4)
635#define TCU_TMSR_FMST3 (1 << 3)
636#define TCU_TMSR_FMST2 (1 << 2)
637#define TCU_TMSR_FMST1 (1 << 1)
638#define TCU_TMSR_FMST0 (1 << 0)
639
640#define TCU_TMCR_HMCL5 (1 << 21)
641#define TCU_TMCR_HMCL4 (1 << 20)
642#define TCU_TMCR_HMCL3 (1 << 19)
643#define TCU_TMCR_HMCL2 (1 << 18)
644#define TCU_TMCR_HMCL1 (1 << 17)
645#define TCU_TMCR_HMCL0 (1 << 16)
646#define TCU_TMCR_FMCL5 (1 << 5)
647#define TCU_TMCR_FMCL4 (1 << 4)
648#define TCU_TMCR_FMCL3 (1 << 3)
649#define TCU_TMCR_FMCL2 (1 << 2)
650#define TCU_TMCR_FMCL1 (1 << 1)
651#define TCU_TMCR_FMCL0 (1 << 0)
652
653#define TCU_TSR_WDTS (1 << 16)
654#define TCU_TSR_STOP5 (1 << 5)
655#define TCU_TSR_STOP4 (1 << 4)
656#define TCU_TSR_STOP3 (1 << 3)
657#define TCU_TSR_STOP2 (1 << 2)
658#define TCU_TSR_STOP1 (1 << 1)
659#define TCU_TSR_STOP0 (1 << 0)
660
661#define TCU_TSSR_WDTSS (1 << 16)
662#define TCU_TSSR_STPS5 (1 << 5)
663#define TCU_TSSR_STPS4 (1 << 4)
664#define TCU_TSSR_STPS3 (1 << 3)
665#define TCU_TSSR_STPS2 (1 << 2)
666#define TCU_TSSR_STPS1 (1 << 1)
667#define TCU_TSSR_STPS0 (1 << 0)
668
669#define TCU_TSSR_WDTSC (1 << 16)
670#define TCU_TSSR_STPC5 (1 << 5)
671#define TCU_TSSR_STPC4 (1 << 4)
672#define TCU_TSSR_STPC3 (1 << 3)
673#define TCU_TSSR_STPC2 (1 << 2)
674#define TCU_TSSR_STPC1 (1 << 1)
675#define TCU_TSSR_STPC0 (1 << 0)
676
677
678/*************************************************************************
679 * WDT (WatchDog Timer)
680 *************************************************************************/
681#define WDT_TDR (WDT_BASE + 0x00)
682#define WDT_TCER (WDT_BASE + 0x04)
683#define WDT_TCNT (WDT_BASE + 0x08)
684#define WDT_TCSR (WDT_BASE + 0x0C)
685
686#define REG_WDT_TDR REG16(WDT_TDR)
687#define REG_WDT_TCER REG8(WDT_TCER)
688#define REG_WDT_TCNT REG16(WDT_TCNT)
689#define REG_WDT_TCSR REG16(WDT_TCSR)
690
691// Register definition
692#define WDT_TCSR_PRESCALE_BIT 3
693#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
694  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
695  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
696  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
697  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
698  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
699  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
700#define WDT_TCSR_EXT_EN (1 << 2)
701#define WDT_TCSR_RTC_EN (1 << 1)
702#define WDT_TCSR_PCK_EN (1 << 0)
703
704#define WDT_TCER_TCEN (1 << 0)
705
706
707/*************************************************************************
708 * DMAC (DMA Controller)
709 *************************************************************************/
710
711#define MAX_DMA_NUM 12 /* max 12 channels */
712#define HALF_DMA_NUM 6 /* the number of one dma controller's channels */
713
714/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
715
716#define DMAC_DSAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x00 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA source address */
717#define DMAC_DTAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x04 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA target address */
718#define DMAC_DTCR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x08 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA transfer count */
719#define DMAC_DRSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x0c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA request source */
720#define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */
721#define DMAC_DCMD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */
722#define DMAC_DDA(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */
723#define DMAC_DSD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0xc0 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */
724
725#define DMAC_DMACR(m) (DMAC_BASE + 0x0300 + 0x100 * m) /* DMA control register */
726#define DMAC_DMAIPR(m) (DMAC_BASE + 0x0304 + 0x100 * m) /* DMA interrupt pending */
727#define DMAC_DMADBR(m) (DMAC_BASE + 0x0308 + 0x100 * m) /* DMA doorbell */
728#define DMAC_DMADBSR(m) (DMAC_BASE + 0x030C + 0x100 * m) /* DMA doorbell set */
729
730#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
731#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
732#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
733#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
734#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
735#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
736#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
737#define REG_DMAC_DSD(n) REG32(DMAC_DSD(n))
738#define REG_DMAC_DMACR(m) REG32(DMAC_DMACR(m))
739#define REG_DMAC_DMAIPR(m) REG32(DMAC_DMAIPR(m))
740#define REG_DMAC_DMADBR(m) REG32(DMAC_DMADBR(m))
741#define REG_DMAC_DMADBSR(m) REG32(DMAC_DMADBSR(m))
742
743// DMA request source register
744#define DMAC_DRSR_RS_BIT 0
745#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
746  #define DMAC_DRSR_RS_EXT (0 << DMAC_DRSR_RS_BIT)
747  #define DMAC_DRSR_RS_NAND (1 << DMAC_DRSR_RS_BIT)
748  #define DMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT)
749  #define DMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT)
750  #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
751  #define DMAC_DRSR_RS_TSSIIN (9 << DMAC_DRSR_RS_BIT)
752  #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT)
753  #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT)
754  #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT)
755  #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT)
756  #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT)
757  #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT)
758  #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
759  #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
760  #define DMAC_DRSR_RS_SSI0OUT (22 << DMAC_DRSR_RS_BIT)
761  #define DMAC_DRSR_RS_SSI0IN (23 << DMAC_DRSR_RS_BIT)
762  #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
763  #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
764  #define DMAC_DRSR_RS_MSC0OUT (26 << DMAC_DRSR_RS_BIT)
765  #define DMAC_DRSR_RS_MSC0IN (27 << DMAC_DRSR_RS_BIT)
766  #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
767  #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
768  #define DMAC_DRSR_RS_MSC1OUT (30 << DMAC_DRSR_RS_BIT)
769  #define DMAC_DRSR_RS_MSC1IN (31 << DMAC_DRSR_RS_BIT)
770  #define DMAC_DRSR_RS_SSI1OUT (32 << DMAC_DRSR_RS_BIT)
771  #define DMAC_DRSR_RS_SSI1IN (33 << DMAC_DRSR_RS_BIT)
772  #define DMAC_DRSR_RS_PMOUT (34 << DMAC_DRSR_RS_BIT)
773  #define DMAC_DRSR_RS_PMIN (35 << DMAC_DRSR_RS_BIT)
774
775// DMA channel control/status register
776#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
777#define DMAC_DCCSR_DES8 (1 << 30) /* Descriptor 8 Word */
778#define DMAC_DCCSR_DES4 (0 << 30) /* Descriptor 4 Word */
779#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
780#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
781#define DMAC_DCCSR_BERR (1 << 7) /* BCH error within this transfer, Only for channel 0 */
782#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
783#define DMAC_DCCSR_AR (1 << 4) /* address error */
784#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
785#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
786#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
787#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
788
789// DMA channel command register
790#define DMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */
791#define DMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */
792#define DMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */
793#define DMAC_DCMD_EACKM_READ (0 << 30) /* External DACK Output Mode Select, output in read cycle */
794#define DMAC_DCMD_ERDM_BIT 28 /* External DREQ Detection Mode Select */
795#define DMAC_DCMD_ERDM_MASK (0x03 << DMAC_DCMD_ERDM_BIT)
796  #define DMAC_DCMD_ERDM_LOW (0 << DMAC_DCMD_ERDM_BIT)
797  #define DMAC_DCMD_ERDM_FALL (1 << DMAC_DCMD_ERDM_BIT)
798  #define DMAC_DCMD_ERDM_HIGH (2 << DMAC_DCMD_ERDM_BIT)
799  #define DMAC_DCMD_ERDM_RISE (3 << DMAC_DCMD_ERDM_BIT)
800#define DMAC_DCMD_BLAST (1 << 25) /* BCH last */
801#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
802#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
803#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
804#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
805  #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
806  #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
807  #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
808  #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
809  #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
810  #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
811  #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
812  #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
813  #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
814  #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
815  #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
816  #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
817  #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
818  #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
819  #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
820  #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
821#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
822#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
823  #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
824  #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
825  #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
826#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
827#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
828  #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
829  #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
830  #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
831#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
832#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
833  #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
834  #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
835  #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
836  #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
837  #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
838#define DMAC_DCMD_STDE (1 << 5) /* Stride Disable/Enable */
839#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
840#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
841#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
842#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
843#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
844
845// DMA descriptor address register
846#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
847#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
848#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
849#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
850
851// DMA stride address register
852#define DMAC_DSD_TSD_BIT 16 /* target stride address */
853#define DMAC_DSD_TSD_MASK (0xffff << DMAC_DSD_TSD_BIT)
854#define DMAC_DSD_SSD_BIT 0 /* source stride address */
855#define DMAC_DSD_SSD_MASK (0xffff << DMAC_DSD_SSD_BIT)
856
857// DMA control register
858#define DMAC_DMACR_FMSC (1 << 31) /* MSC Fast DMA mode */
859#define DMAC_DMACR_FSSI (1 << 30) /* SSI Fast DMA mode */
860#define DMAC_DMACR_FTSSI (1 << 29) /* TSSI Fast DMA mode */
861#define DMAC_DMACR_FUART (1 << 28) /* UART Fast DMA mode */
862#define DMAC_DMACR_FAIC (1 << 27) /* AIC Fast DMA mode */
863#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
864#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
865  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
866  #define DMAC_DMACR_PR_120345 (1 << DMAC_DMACR_PR_BIT)
867  #define DMAC_DMACR_PR_230145 (2 << DMAC_DMACR_PR_BIT)
868  #define DMAC_DMACR_PR_340125 (3 << DMAC_DMACR_PR_BIT)
869#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
870#define DMAC_DMACR_AR (1 << 2) /* address error flag */
871#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
872
873// DMA doorbell register
874#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
875#define DMAC_DMADBR_DB4 (1 << 4) /* doorbell for channel 4 */
876#define DMAC_DMADBR_DB3 (1 << 3) /* doorbell for channel 3 */
877#define DMAC_DMADBR_DB2 (1 << 2) /* doorbell for channel 2 */
878#define DMAC_DMADBR_DB1 (1 << 1) /* doorbell for channel 1 */
879#define DMAC_DMADBR_DB0 (1 << 0) /* doorbell for channel 0 */
880
881// DMA doorbell set register
882#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
883#define DMAC_DMADBSR_DBS4 (1 << 4) /* enable doorbell for channel 4 */
884#define DMAC_DMADBSR_DBS3 (1 << 3) /* enable doorbell for channel 3 */
885#define DMAC_DMADBSR_DBS2 (1 << 2) /* enable doorbell for channel 2 */
886#define DMAC_DMADBSR_DBS1 (1 << 1) /* enable doorbell for channel 1 */
887#define DMAC_DMADBSR_DBS0 (1 << 0) /* enable doorbell for channel 0 */
888
889// DMA interrupt pending register
890#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
891#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
892#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
893#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
894#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
895#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
896
897
898/*************************************************************************
899 * GPIO (General-Purpose I/O Ports)
900 *************************************************************************/
901#define MAX_GPIO_NUM 192
902
903//n = 0,1,2,3,4,5
904#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
905#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
906#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
907#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
908#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
909#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
910#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
911#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Disable Register */
912#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Disable Set Reg. */
913#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Disable Clear Reg. */
914#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
915#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
916#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
917#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
918#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
919#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
920#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
921#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
922#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
923#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
924#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
925#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Clear Register */
926#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
927#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
928
929#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
930#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
931#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
932#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
933#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
934#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
935#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
936#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
937#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
938#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
939#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO/INTR, 1:FUNC */
940#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
941#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
942#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
943#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
944#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
945#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
946#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
947#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
948#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:Level-trigger/Fun0, 1:Edge-trigger/Fun1 */
949#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
950#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
951#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
952#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
953
954
955/*************************************************************************
956 * UART
957 *************************************************************************/
958
959#define IRDA_BASE UART0_BASE
960//#define UART_BASE UART0_BASE
961#define UART_OFF 0x1000
962
963/* Register Offset */
964#define OFF_RDR (0x00) /* R 8b H'xx */
965#define OFF_TDR (0x00) /* W 8b H'xx */
966#define OFF_DLLR (0x00) /* RW 8b H'00 */
967#define OFF_DLHR (0x04) /* RW 8b H'00 */
968#define OFF_IER (0x04) /* RW 8b H'00 */
969#define OFF_ISR (0x08) /* R 8b H'01 */
970#define OFF_FCR (0x08) /* W 8b H'00 */
971#define OFF_LCR (0x0C) /* RW 8b H'00 */
972#define OFF_MCR (0x10) /* RW 8b H'00 */
973#define OFF_LSR (0x14) /* R 8b H'00 */
974#define OFF_MSR (0x18) /* R 8b H'00 */
975#define OFF_SPR (0x1C) /* RW 8b H'00 */
976#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
977#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
978#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
979
980/* Register Address */
981#define UART0_RDR (UART0_BASE + OFF_RDR)
982#define UART0_TDR (UART0_BASE + OFF_TDR)
983#define UART0_DLLR (UART0_BASE + OFF_DLLR)
984#define UART0_DLHR (UART0_BASE + OFF_DLHR)
985#define UART0_IER (UART0_BASE + OFF_IER)
986#define UART0_ISR (UART0_BASE + OFF_ISR)
987#define UART0_FCR (UART0_BASE + OFF_FCR)
988#define UART0_LCR (UART0_BASE + OFF_LCR)
989#define UART0_MCR (UART0_BASE + OFF_MCR)
990#define UART0_LSR (UART0_BASE + OFF_LSR)
991#define UART0_MSR (UART0_BASE + OFF_MSR)
992#define UART0_SPR (UART0_BASE + OFF_SPR)
993#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
994#define UART0_UMR (UART0_BASE + OFF_UMR)
995#define UART0_UACR (UART0_BASE + OFF_UACR)
996
997/*
998 * Define macros for UART_IER
999 * UART Interrupt Enable Register
1000 */
1001#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
1002#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
1003#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
1004#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
1005#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
1006
1007/*
1008 * Define macros for UART_ISR
1009 * UART Interrupt Status Register
1010 */
1011#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
1012#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
1013#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
1014#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
1015#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
1016#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
1017#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
1018#define UART_ISR_FFMS_NO_FIFO (0 << 6)
1019#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
1020
1021/*
1022 * Define macros for UART_FCR
1023 * UART FIFO Control Register
1024 */
1025#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
1026#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
1027#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
1028#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
1029#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
1030#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
1031#define UART_FCR_RTRG_1 (0 << 6)
1032#define UART_FCR_RTRG_4 (1 << 6)
1033#define UART_FCR_RTRG_8 (2 << 6)
1034#define UART_FCR_RTRG_15 (3 << 6)
1035
1036/*
1037 * Define macros for UART_LCR
1038 * UART Line Control Register
1039 */
1040#define UART_LCR_WLEN (3 << 0) /* word length */
1041#define UART_LCR_WLEN_5 (0 << 0)
1042#define UART_LCR_WLEN_6 (1 << 0)
1043#define UART_LCR_WLEN_7 (2 << 0)
1044#define UART_LCR_WLEN_8 (3 << 0)
1045#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1046                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1047#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1048                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1049#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1050                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1051
1052#define UART_LCR_PE (1 << 3) /* 0: parity disable */
1053#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
1054#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
1055#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
1056#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
1057
1058/*
1059 * Define macros for UART_LSR
1060 * UART Line Status Register
1061 */
1062#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
1063#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
1064#define UART_LSR_PER (1 << 2) /* 0: no parity error */
1065#define UART_LSR_FER (1 << 3) /* 0; no framing error */
1066#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
1067#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
1068#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
1069#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
1070
1071/*
1072 * Define macros for UART_MCR
1073 * UART Modem Control Register
1074 */
1075#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
1076#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
1077#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
1078#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
1079#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
1080#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
1081
1082/*
1083 * Define macros for UART_MSR
1084 * UART Modem Status Register
1085 */
1086#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
1087#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
1088#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
1089#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
1090#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
1091#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
1092#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
1093#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
1094
1095/*
1096 * Define macros for SIRCR
1097 * Slow IrDA Control Register
1098 */
1099#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
1100#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
1101#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1102                       1: 0 pulse width is 1.6us for 115.2Kbps */
1103#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1104#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1105
1106
1107/*************************************************************************
1108 * AIC (AC97/I2S Controller)
1109 *************************************************************************/
1110#define AIC_FR (AIC_BASE + 0x000)
1111#define AIC_CR (AIC_BASE + 0x004)
1112#define AIC_ACCR1 (AIC_BASE + 0x008)
1113#define AIC_ACCR2 (AIC_BASE + 0x00C)
1114#define AIC_I2SCR (AIC_BASE + 0x010)
1115#define AIC_SR (AIC_BASE + 0x014)
1116#define AIC_ACSR (AIC_BASE + 0x018)
1117#define AIC_I2SSR (AIC_BASE + 0x01C)
1118#define AIC_ACCAR (AIC_BASE + 0x020)
1119#define AIC_ACCDR (AIC_BASE + 0x024)
1120#define AIC_ACSAR (AIC_BASE + 0x028)
1121#define AIC_ACSDR (AIC_BASE + 0x02C)
1122#define AIC_I2SDIV (AIC_BASE + 0x030)
1123#define AIC_DR (AIC_BASE + 0x034)
1124
1125#define REG_AIC_FR REG32(AIC_FR)
1126#define REG_AIC_CR REG32(AIC_CR)
1127#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1128#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1129#define REG_AIC_I2SCR REG32(AIC_I2SCR)
1130#define REG_AIC_SR REG32(AIC_SR)
1131#define REG_AIC_ACSR REG32(AIC_ACSR)
1132#define REG_AIC_I2SSR REG32(AIC_I2SSR)
1133#define REG_AIC_ACCAR REG32(AIC_ACCAR)
1134#define REG_AIC_ACCDR REG32(AIC_ACCDR)
1135#define REG_AIC_ACSAR REG32(AIC_ACSAR)
1136#define REG_AIC_ACSDR REG32(AIC_ACSDR)
1137#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1138#define REG_AIC_DR REG32(AIC_DR)
1139
1140/* AIC Controller Configuration Register (AIC_FR) */
1141
1142#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1143#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1144#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1145#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1146#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1147#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1148#define AIC_FR_RST (1 << 3) /* AIC registers reset */
1149#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1150#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1151#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1152
1153/* AIC Controller Common Control Register (AIC_CR) */
1154
1155#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1156#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1157  #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1158  #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1159  #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1160  #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1161  #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1162#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1163#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1164  #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1165  #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1166  #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1167  #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1168  #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1169#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1170#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1171#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1172#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1173#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1174#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1175#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1176#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1177#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1178#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1179#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1180#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1181#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1182
1183/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1184
1185#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1186#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1187  #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1188  #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1189  #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1190  #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1191  #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1192  #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1193  #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1194  #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1195  #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1196  #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1197#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1198#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1199  #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1200  #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1201  #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1202  #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1203  #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1204  #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1205  #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1206  #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1207  #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1208  #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1209
1210/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1211
1212#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1213#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1214#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1215#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1216#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1217  #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1218  #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1219  #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1220  #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1221#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1222#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1223  #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1224  #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1225  #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1226  #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1227#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1228#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1229#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1230#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1231
1232/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1233
1234#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1235#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1236#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1237  #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1238  #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1239  #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1240  #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1241  #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1242#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1243
1244/* AIC Controller FIFO Status Register (AIC_SR) */
1245
1246#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1247#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1248#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1249#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1250#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1251#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1252#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1253#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1254
1255/* AIC Controller AC-link Status Register (AIC_ACSR) */
1256
1257#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1258#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1259#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1260#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1261#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1262#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1263
1264/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1265
1266#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1267
1268/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1269
1270#define AIC_ACCAR_CAR_BIT 0
1271#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1272
1273/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1274
1275#define AIC_ACCDR_CDR_BIT 0
1276#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1277
1278/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1279
1280#define AIC_ACSAR_SAR_BIT 0
1281#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1282
1283/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1284
1285#define AIC_ACSDR_SDR_BIT 0
1286#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1287
1288/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1289
1290#define AIC_I2SDIV_DIV_BIT 0
1291#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1292  #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1293  #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1294  #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1295  #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1296  #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1297  #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1298
1299
1300/*************************************************************************
1301 * ICDC (Internal CODEC)
1302 *************************************************************************/
1303#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1304#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1305#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1306#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1307#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1308#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1309#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1310
1311#define REG_ICDC_CR REG32(ICDC_CR)
1312#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1313#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1314#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1315#define REG_ICDC_APSR REG32(ICDC_APSR)
1316#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1317#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1318
1319/* ICDC Control Register */
1320#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1321#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1322#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1323#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1324  #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1325  #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1326  #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1327  #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1328  #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1329  #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1330  #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1331  #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1332  #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1333#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1334#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1335  #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1336  #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1337  #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1338  #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1339#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1340#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1341  #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1342  #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1343  #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1344  #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1345#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1346#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1347#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1348#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1349#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1350#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1351#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1352#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1353#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1354#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1355#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1356#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1357
1358/* Anti-Pop WAIT Stage Timing Control Register */
1359#define ICDC_APWAIT_WAITSN_BIT 0
1360#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1361
1362/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1363#define ICDC_APPRE_PRESN_BIT 0
1364#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1365
1366/* Anti-Pop HPEN Stage Timing Control Register */
1367#define ICDC_APHPEN_HPENSN_BIT 0
1368#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1369
1370/* Anti-Pop Status Register */
1371#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1372#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1373#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1374#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1375  #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1376#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1377  #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1378  #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1379  #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1380  #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1381#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1382#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1383
1384
1385/*************************************************************************
1386 * I2C
1387 *************************************************************************/
1388#define I2C_DR (I2C_BASE + 0x000)
1389#define I2C_CR (I2C_BASE + 0x004)
1390#define I2C_SR (I2C_BASE + 0x008)
1391#define I2C_GR (I2C_BASE + 0x00C)
1392
1393#define REG_I2C_DR REG8(I2C_DR)
1394#define REG_I2C_CR REG8(I2C_CR)
1395#define REG_I2C_SR REG8(I2C_SR)
1396#define REG_I2C_GR REG16(I2C_GR)
1397
1398/* I2C Control Register (I2C_CR) */
1399
1400#define I2C_CR_IEN (1 << 4)
1401#define I2C_CR_STA (1 << 3)
1402#define I2C_CR_STO (1 << 2)
1403#define I2C_CR_AC (1 << 1)
1404#define I2C_CR_I2CE (1 << 0)
1405
1406/* I2C Status Register (I2C_SR) */
1407
1408#define I2C_SR_STX (1 << 4)
1409#define I2C_SR_BUSY (1 << 3)
1410#define I2C_SR_TEND (1 << 2)
1411#define I2C_SR_DRF (1 << 1)
1412#define I2C_SR_ACKF (1 << 0)
1413
1414
1415/*************************************************************************
1416 * SSI (Synchronous Serial Interface)
1417 *************************************************************************/
1418/* n = 0, 1 (SSI0, SSI1) */
1419#define SSI_DR(n) (SSI_BASE + 0x000 + (n)*0x2000)
1420#define SSI_CR0(n) (SSI_BASE + 0x004 + (n)*0x2000)
1421#define SSI_CR1(n) (SSI_BASE + 0x008 + (n)*0x2000)
1422#define SSI_SR(n) (SSI_BASE + 0x00C + (n)*0x2000)
1423#define SSI_ITR(n) (SSI_BASE + 0x010 + (n)*0x2000)
1424#define SSI_ICR(n) (SSI_BASE + 0x014 + (n)*0x2000)
1425#define SSI_GR(n) (SSI_BASE + 0x018 + (n)*0x2000)
1426
1427#define REG_SSI_DR(n) REG32(SSI_DR(n))
1428#define REG_SSI_CR0(n) REG16(SSI_CR0(n))
1429#define REG_SSI_CR1(n) REG32(SSI_CR1(n))
1430#define REG_SSI_SR(n) REG32(SSI_SR(n))
1431#define REG_SSI_ITR(n) REG16(SSI_ITR(n))
1432#define REG_SSI_ICR(n) REG8(SSI_ICR(n))
1433#define REG_SSI_GR(n) REG16(SSI_GR(n))
1434
1435/* SSI Data Register (SSI_DR) */
1436
1437#define SSI_DR_GPC_BIT 0
1438#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1439
1440#define SSI_MAX_FIFO_ENTRIES 128 /* 128 txfifo and 128 rxfifo */
1441
1442/* SSI Control Register 0 (SSI_CR0) */
1443
1444#define SSI_CR0_SSIE (1 << 15)
1445#define SSI_CR0_TIE (1 << 14)
1446#define SSI_CR0_RIE (1 << 13)
1447#define SSI_CR0_TEIE (1 << 12)
1448#define SSI_CR0_REIE (1 << 11)
1449#define SSI_CR0_LOOP (1 << 10)
1450#define SSI_CR0_RFINE (1 << 9)
1451#define SSI_CR0_RFINC (1 << 8)
1452#define SSI_CR0_EACLRUN (1 << 7) /* hardware auto clear underrun when TxFifo no empty */
1453#define SSI_CR0_FSEL (1 << 6)
1454#define SSI_CR0_TFLUSH (1 << 2)
1455#define SSI_CR0_RFLUSH (1 << 1)
1456#define SSI_CR0_DISREV (1 << 0)
1457
1458/* SSI Control Register 1 (SSI_CR1) */
1459
1460#define SSI_CR1_FRMHL_BIT 30
1461#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1462  #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1463  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1464  #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1465  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1466#define SSI_CR1_TFVCK_BIT 28
1467#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1468  #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1469  #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1470  #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1471  #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1472#define SSI_CR1_TCKFI_BIT 26
1473#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1474  #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1475  #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1476  #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1477  #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1478#define SSI_CR1_LFST (1 << 25)
1479#define SSI_CR1_ITFRM (1 << 24)
1480#define SSI_CR1_UNFIN (1 << 23)
1481#define SSI_CR1_MULTS (1 << 22)
1482#define SSI_CR1_FMAT_BIT 20
1483#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1484  #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1485  #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1486  #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1487  #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1488#define SSI_CR1_TTRG_BIT 16 /* SSI1 TX trigger */
1489#define SSI_CR1_TTRG_MASK (0xf << SSI1_CR1_TTRG_BIT)
1490#define SSI_CR1_MCOM_BIT 12
1491#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1492  #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1493  #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1494  #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1495  #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1496  #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1497  #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1498  #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1499  #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1500  #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1501  #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1502  #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1503  #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1504  #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1505  #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1506  #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1507  #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1508#define SSI_CR1_RTRG_BIT 8 /* SSI RX trigger */
1509#define SSI_CR1_RTRG_MASK (0xf << SSI1_CR1_RTRG_BIT)
1510#define SSI_CR1_FLEN_BIT 4
1511#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1512  #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1513  #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1514  #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1515  #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1516  #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1517  #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1518  #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1519  #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1520  #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1521  #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1522  #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1523  #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1524  #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1525  #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1526  #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1527  #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1528#define SSI_CR1_PHA (1 << 1)
1529#define SSI_CR1_POL (1 << 0)
1530
1531/* SSI Status Register (SSI_SR) */
1532
1533#define SSI_SR_TFIFONUM_BIT 16
1534#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1535#define SSI_SR_RFIFONUM_BIT 8
1536#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1537#define SSI_SR_END (1 << 7)
1538#define SSI_SR_BUSY (1 << 6)
1539#define SSI_SR_TFF (1 << 5)
1540#define SSI_SR_RFE (1 << 4)
1541#define SSI_SR_TFHE (1 << 3)
1542#define SSI_SR_RFHF (1 << 2)
1543#define SSI_SR_UNDR (1 << 1)
1544#define SSI_SR_OVER (1 << 0)
1545
1546/* SSI Interval Time Control Register (SSI_ITR) */
1547
1548#define SSI_ITR_CNTCLK (1 << 15)
1549#define SSI_ITR_IVLTM_BIT 0
1550#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1551
1552
1553/*************************************************************************
1554 * MSC
1555 *************************************************************************/
1556#define MSC_STRPCL (MSC_BASE + 0x000)
1557#define MSC_STAT (MSC_BASE + 0x004)
1558#define MSC_CLKRT (MSC_BASE + 0x008)
1559#define MSC_CMDAT (MSC_BASE + 0x00C)
1560#define MSC_RESTO (MSC_BASE + 0x010)
1561#define MSC_RDTO (MSC_BASE + 0x014)
1562#define MSC_BLKLEN (MSC_BASE + 0x018)
1563#define MSC_NOB (MSC_BASE + 0x01C)
1564#define MSC_SNOB (MSC_BASE + 0x020)
1565#define MSC_IMASK (MSC_BASE + 0x024)
1566#define MSC_IREG (MSC_BASE + 0x028)
1567#define MSC_CMD (MSC_BASE + 0x02C)
1568#define MSC_ARG (MSC_BASE + 0x030)
1569#define MSC_RES (MSC_BASE + 0x034)
1570#define MSC_RXFIFO (MSC_BASE + 0x038)
1571#define MSC_TXFIFO (MSC_BASE + 0x03C)
1572
1573#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1574#define REG_MSC_STAT REG32(MSC_STAT)
1575#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1576#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1577#define REG_MSC_RESTO REG16(MSC_RESTO)
1578#define REG_MSC_RDTO REG16(MSC_RDTO)
1579#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1580#define REG_MSC_NOB REG16(MSC_NOB)
1581#define REG_MSC_SNOB REG16(MSC_SNOB)
1582#define REG_MSC_IMASK REG16(MSC_IMASK)
1583#define REG_MSC_IREG REG16(MSC_IREG)
1584#define REG_MSC_CMD REG8(MSC_CMD)
1585#define REG_MSC_ARG REG32(MSC_ARG)
1586#define REG_MSC_RES REG16(MSC_RES)
1587#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1588#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1589
1590/* MSC Clock and Control Register (MSC_STRPCL) */
1591
1592#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1593#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1594#define MSC_STRPCL_START_READWAIT (1 << 5)
1595#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1596#define MSC_STRPCL_RESET (1 << 3)
1597#define MSC_STRPCL_START_OP (1 << 2)
1598#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1599#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1600  #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1601  #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1602
1603/* MSC Status Register (MSC_STAT) */
1604
1605#define MSC_STAT_IS_RESETTING (1 << 15)
1606#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1607#define MSC_STAT_PRG_DONE (1 << 13)
1608#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1609#define MSC_STAT_END_CMD_RES (1 << 11)
1610#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1611#define MSC_STAT_IS_READWAIT (1 << 9)
1612#define MSC_STAT_CLK_EN (1 << 8)
1613#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1614#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1615#define MSC_STAT_CRC_RES_ERR (1 << 5)
1616#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1617#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1618#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1619  #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1620  #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1621  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1622#define MSC_STAT_TIME_OUT_RES (1 << 1)
1623#define MSC_STAT_TIME_OUT_READ (1 << 0)
1624
1625/* MSC Bus Clock Control Register (MSC_CLKRT) */
1626
1627#define MSC_CLKRT_CLK_RATE_BIT 0
1628#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1629  #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1630  #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1631  #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1632  #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1633  #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1634  #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1635  #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1636  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1637
1638/* MSC Command Sequence Control Register (MSC_CMDAT) */
1639
1640#define MSC_CMDAT_IO_ABORT (1 << 11)
1641#define MSC_CMDAT_BUS_WIDTH_BIT 9
1642#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1643  #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1644  #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1645  #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1646  #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1647#define MSC_CMDAT_DMA_EN (1 << 8)
1648#define MSC_CMDAT_INIT (1 << 7)
1649#define MSC_CMDAT_BUSY (1 << 6)
1650#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1651#define MSC_CMDAT_WRITE (1 << 4)
1652#define MSC_CMDAT_READ (0 << 4)
1653#define MSC_CMDAT_DATA_EN (1 << 3)
1654#define MSC_CMDAT_RESPONSE_BIT 0
1655#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1656  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1657  #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1658  #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1659  #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1660  #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1661  #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1662  #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1663
1664#define CMDAT_DMA_EN (1 << 8)
1665#define CMDAT_INIT (1 << 7)
1666#define CMDAT_BUSY (1 << 6)
1667#define CMDAT_STREAM (1 << 5)
1668#define CMDAT_WRITE (1 << 4)
1669#define CMDAT_DATA_EN (1 << 3)
1670
1671/* MSC Interrupts Mask Register (MSC_IMASK) */
1672
1673#define MSC_IMASK_SDIO (1 << 7)
1674#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1675#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1676#define MSC_IMASK_END_CMD_RES (1 << 2)
1677#define MSC_IMASK_PRG_DONE (1 << 1)
1678#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1679
1680
1681/* MSC Interrupts Status Register (MSC_IREG) */
1682
1683#define MSC_IREG_SDIO (1 << 7)
1684#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1685#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1686#define MSC_IREG_END_CMD_RES (1 << 2)
1687#define MSC_IREG_PRG_DONE (1 << 1)
1688#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1689
1690
1691/*************************************************************************
1692 * EMC (External Memory Controller)
1693 *************************************************************************/
1694#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
1695
1696#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1697#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1698#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1699#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1700#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1701#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1702#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1703#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1704#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1705#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1706
1707#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1708
1709#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1710#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1711#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1712#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1713#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1714#define EMC_DMAR1 (EMC_BASE + 0x94) /* SDRAM Bank 1 Addr Config Register */
1715#define EMC_SDMR0 (EMC_BASE + 0x8000) /* Mode Register of SDRAM bank 0 */
1716
1717#define REG_EMC_BCR REG32(EMC_BCR)
1718
1719#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1720#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1721#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1722#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1723#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1724#define REG_EMC_SACR0 REG32(EMC_SACR0)
1725#define REG_EMC_SACR1 REG32(EMC_SACR1)
1726#define REG_EMC_SACR2 REG32(EMC_SACR2)
1727#define REG_EMC_SACR3 REG32(EMC_SACR3)
1728#define REG_EMC_SACR4 REG32(EMC_SACR4)
1729
1730#define REG_EMC_NFCSR REG32(EMC_NFCSR)
1731
1732#define REG_EMC_DMCR REG32(EMC_DMCR)
1733#define REG_EMC_RTCSR REG16(EMC_RTCSR)
1734#define REG_EMC_RTCNT REG16(EMC_RTCNT)
1735#define REG_EMC_RTCOR REG16(EMC_RTCOR)
1736#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1737#define REG_EMC_DMAR1 REG32(EMC_DMAR1)
1738
1739/* Bus Control Register */
1740#define EMC_BCR_BT_SEL_BIT 30
1741#define EMC_BCR_BT_SEL_MASK (0x3 << EMC_BCR_BT_SEL_BIT)
1742#define EMC_BCR_PK_SEL (1 << 24)
1743#define EMC_BCR_BSR_MASK (1 << 2) /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */
1744  #define EMC_BCR_BSR_SHARE (0 << 2)
1745  #define EMC_BCR_BSR_UNSHARE (1 << 2)
1746#define EMC_BCR_BRE (1 << 1)
1747#define EMC_BCR_ENDIAN (1 << 0)
1748
1749/* Static Memory Control Register */
1750#define EMC_SMCR_STRV_BIT 24
1751#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1752#define EMC_SMCR_TAW_BIT 20
1753#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1754#define EMC_SMCR_TBP_BIT 16
1755#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1756#define EMC_SMCR_TAH_BIT 12
1757#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1758#define EMC_SMCR_TAS_BIT 8
1759#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1760#define EMC_SMCR_BW_BIT 6
1761#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1762  #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1763  #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1764  #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1765#define EMC_SMCR_BCM (1 << 3)
1766#define EMC_SMCR_BL_BIT 1
1767#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1768  #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1769  #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1770  #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1771  #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1772#define EMC_SMCR_SMT (1 << 0)
1773
1774/* Static Memory Bank Addr Config Reg */
1775#define EMC_SACR_BASE_BIT 8
1776#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1777#define EMC_SACR_MASK_BIT 0
1778#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1779
1780/* NAND Flash Control/Status Register */
1781#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1782#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1783#define EMC_NFCSR_NFCE3 (1 << 5)
1784#define EMC_NFCSR_NFE3 (1 << 4)
1785#define EMC_NFCSR_NFCE2 (1 << 3)
1786#define EMC_NFCSR_NFE2 (1 << 2)
1787#define EMC_NFCSR_NFCE1 (1 << 1)
1788#define EMC_NFCSR_NFE1 (1 << 0)
1789
1790/* DRAM Control Register */
1791#define EMC_DMCR_BW_BIT 31
1792#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1793#define EMC_DMCR_CA_BIT 26
1794#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1795  #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1796  #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1797  #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1798  #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1799  #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1800#define EMC_DMCR_RMODE (1 << 25)
1801#define EMC_DMCR_RFSH (1 << 24)
1802#define EMC_DMCR_MRSET (1 << 23)
1803#define EMC_DMCR_RA_BIT 20
1804#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1805  #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1806  #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1807  #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1808#define EMC_DMCR_BA_BIT 19
1809#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1810#define EMC_DMCR_PDM (1 << 18)
1811#define EMC_DMCR_EPIN (1 << 17)
1812#define EMC_DMCR_MBSEL_BIT 16
1813  #define EMC_DMCR_MBSEL_B0 (0 << 16)
1814  #define EMC_DMCR_MBSEL_B1 (1 << 16)
1815#define EMC_DMCR_TRAS_BIT 13
1816#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1817#define EMC_DMCR_RCD_BIT 11
1818#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1819#define EMC_DMCR_TPC_BIT 8
1820#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1821#define EMC_DMCR_TRWL_BIT 5
1822#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1823#define EMC_DMCR_TRC_BIT 2
1824#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1825#define EMC_DMCR_TCL_BIT 0
1826#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1827
1828/* Refresh Time Control/Status Register */
1829#define EMC_RTCSR_CMF (1 << 7)
1830#define EMC_RTCSR_CKS_BIT 0
1831#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1832  #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1833  #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1834  #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1835  #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1836  #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1837  #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1838  #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1839  #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1840
1841/* SDRAM Bank Address Configuration Register */
1842#define EMC_DMAR_BASE_BIT 8
1843#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1844#define EMC_DMAR_MASK_BIT 0
1845#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1846
1847/* Mode Register of SDRAM bank 0 */
1848#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1849#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1850#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1851  #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1852#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1853#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1854  #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1855  #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1856  #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1857#define EMC_SDMR_BT_BIT 3 /* Burst Type */
1858#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1859  #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1860  #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1861#define EMC_SDMR_BL_BIT 0 /* Burst Length */
1862#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1863  #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1864  #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1865  #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1866  #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1867
1868#define EMC_SDMR_CAS2_16BIT \
1869  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1870#define EMC_SDMR_CAS2_32BIT \
1871  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1872#define EMC_SDMR_CAS3_16BIT \
1873  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1874#define EMC_SDMR_CAS3_32BIT \
1875  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1876
1877/* Extended Mode Register of Mobile SDRAM*/
1878#define EMC_SDMR_SET_BA1 (1 << 14) /*BA1*/
1879#define EMC_SDMR_SET_BA0 (1 << 13) /*BA0*/
1880
1881#define EMC_SDMR_DS_BIT 5 /* Driver strength */
1882#define EMC_SDMR_DS_MASK (3 << EMC_SDMR_DS_BIT)
1883  #define EMC_SDMR_DS_FULL (0 << EMC_SDMR_DS_BIT) /*Full*/
1884  #define EMC_SDMR_DS_HALF (1 << EMC_SDMR_DS_BIT) /*1/2 Strength*/
1885  #define EMC_SDMR_DS_QUTR (2 << EMC_SDMR_DS_BIT) /*1/4 Strength*/
1886
1887#define EMC_SDMR_PRSR_BIT 0 /* Partial Array Self Refresh */
1888#define EMC_SDMR_PRSR_MASK (7 << EMC_SDMR_PRSR_BIT)
1889  #define EMC_SDMR_PRSR_ALL (0 << EMC_SDMR_PRSR_BIT) /*All Banks*/
1890  #define EMC_SDMR_PRSR_HALF_TL (1 << EMC_SDMR_PRSR_BIT) /*Half of Total Bank*/
1891  #define EMC_SDMR_PRSR_QUTR_TL (2 << EMC_SDMR_PRSR_BIT) /*Quarter of Total Bank*/
1892  #define EMC_SDMR_PRSR_HALF_B0 (5 << EMC_SDMR_PRSR_BIT) /*Half of Bank0*/
1893  #define EMC_SDMR_PRSR_QUTR_B0 (6 << EMC_SDMR_PRSR_BIT) /*Quarter of Bank0*/
1894
1895#define EMC_DMAR_BASE_BIT 8
1896#define EMC_DMAR_MASK_BIT 0
1897
1898#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1899#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1900
1901#define EMC_DMAR0_BASE (0x20 << EMC_DMAR_BASE_BIT)
1902#define EMC_DMAR1_BASE_64M (0x24 << EMC_DMAR_BASE_BIT) /*when bank0 is 64M*/
1903#define EMC_DMAR1_BASE_128M (0x28 << EMC_DMAR_BASE_BIT) /*when bank0 is 128M*/
1904
1905#define EMC_DMAR_MASK_64_64 (0xfc << EMC_DMAR_MASK_BIT) /*mask for two 64M SDRAM*/
1906#define EMC_DMAR_MASK_128_128 (0xf8 << EMC_DMAR_MASK_BIT) /*mask for two 128M SDRAM*/
1907
1908/*************************************************************************
1909 * CIM
1910 *************************************************************************/
1911#define CIM_CFG (CIM_BASE + 0x0000)
1912#define CIM_CTRL (CIM_BASE + 0x0004)
1913#define CIM_STATE (CIM_BASE + 0x0008)
1914#define CIM_IID (CIM_BASE + 0x000C)
1915#define CIM_RXFIFO (CIM_BASE + 0x0010)
1916#define CIM_DA (CIM_BASE + 0x0020)
1917#define CIM_FA (CIM_BASE + 0x0024)
1918#define CIM_FID (CIM_BASE + 0x0028)
1919#define CIM_CMD (CIM_BASE + 0x002C)
1920
1921#define REG_CIM_CFG REG32(CIM_CFG)
1922#define REG_CIM_CTRL REG32(CIM_CTRL)
1923#define REG_CIM_STATE REG32(CIM_STATE)
1924#define REG_CIM_IID REG32(CIM_IID)
1925#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1926#define REG_CIM_DA REG32(CIM_DA)
1927#define REG_CIM_FA REG32(CIM_FA)
1928#define REG_CIM_FID REG32(CIM_FID)
1929#define REG_CIM_CMD REG32(CIM_CMD)
1930
1931/* CIM Configuration Register (CIM_CFG) */
1932
1933#define CIM_CFG_INV_DAT (1 << 15)
1934#define CIM_CFG_VSP (1 << 14)
1935#define CIM_CFG_HSP (1 << 13)
1936#define CIM_CFG_PCP (1 << 12)
1937#define CIM_CFG_DUMMY_ZERO (1 << 9)
1938#define CIM_CFG_EXT_VSYNC (1 << 8)
1939#define CIM_CFG_PACK_BIT 4
1940#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1941  #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1942  #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1943  #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1944  #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1945  #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1946  #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1947  #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1948  #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1949#define CIM_CFG_DSM_BIT 0
1950#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1951  #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1952  #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1953  #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1954  #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1955
1956/* CIM Control Register (CIM_CTRL) */
1957
1958#define CIM_CTRL_MCLKDIV_BIT 24
1959#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1960#define CIM_CTRL_FRC_BIT 16
1961#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1962  #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1963  #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1964  #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1965  #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1966  #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1967  #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1968  #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1969  #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1970  #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1971  #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1972  #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1973  #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1974  #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1975  #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1976  #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1977  #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1978#define CIM_CTRL_VDDM (1 << 13)
1979#define CIM_CTRL_DMA_SOFM (1 << 12)
1980#define CIM_CTRL_DMA_EOFM (1 << 11)
1981#define CIM_CTRL_DMA_STOPM (1 << 10)
1982#define CIM_CTRL_RXF_TRIGM (1 << 9)
1983#define CIM_CTRL_RXF_OFM (1 << 8)
1984#define CIM_CTRL_RXF_TRIG_BIT 4
1985#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1986  #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1987  #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1988  #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1989  #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1990  #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1991  #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1992  #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1993  #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1994#define CIM_CTRL_DMA_EN (1 << 2)
1995#define CIM_CTRL_RXF_RST (1 << 1)
1996#define CIM_CTRL_ENA (1 << 0)
1997
1998/* CIM State Register (CIM_STATE) */
1999
2000#define CIM_STATE_DMA_SOF (1 << 6)
2001#define CIM_STATE_DMA_EOF (1 << 5)
2002#define CIM_STATE_DMA_STOP (1 << 4)
2003#define CIM_STATE_RXF_OF (1 << 3)
2004#define CIM_STATE_RXF_TRIG (1 << 2)
2005#define CIM_STATE_RXF_EMPTY (1 << 1)
2006#define CIM_STATE_VDD (1 << 0)
2007
2008/* CIM DMA Command Register (CIM_CMD) */
2009
2010#define CIM_CMD_SOFINT (1 << 31)
2011#define CIM_CMD_EOFINT (1 << 30)
2012#define CIM_CMD_STOP (1 << 28)
2013#define CIM_CMD_LEN_BIT 0
2014#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
2015
2016
2017/*************************************************************************
2018 * SADC (Smart A/D Controller)
2019 *************************************************************************/
2020
2021#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
2022#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
2023#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
2024#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
2025#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
2026#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
2027#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
2028#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
2029#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
2030
2031#define REG_SADC_ENA REG8(SADC_ENA)
2032#define REG_SADC_CFG REG32(SADC_CFG)
2033#define REG_SADC_CTRL REG8(SADC_CTRL)
2034#define REG_SADC_STATE REG8(SADC_STATE)
2035#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
2036#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
2037#define REG_SADC_TSDAT REG32(SADC_TSDAT)
2038#define REG_SADC_BATDAT REG16(SADC_BATDAT)
2039#define REG_SADC_SADDAT REG16(SADC_SADDAT)
2040
2041/* ADC Enable Register */
2042#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
2043#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
2044#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
2045#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
2046
2047/* ADC Configure Register */
2048#define SADC_CFG_CLKOUT_NUM_BIT 16
2049#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
2050#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
2051#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
2052#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
2053  #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
2054  #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
2055  #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
2056#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
2057#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
2058  #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
2059  #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
2060  #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
2061  #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
2062  #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
2063  #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
2064  #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
2065  #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
2066#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
2067#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
2068#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
2069#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
2070#define SADC_CFG_CMD_BIT 0 /* ADC Command */
2071#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
2072  #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
2073  #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
2074  #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
2075  #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
2076  #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
2077  #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
2078  #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
2079  #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
2080  #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
2081  #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
2082  #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
2083  #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
2084  #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
2085
2086/* ADC Control Register */
2087#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
2088#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
2089#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
2090#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
2091#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
2092
2093/* ADC Status Register */
2094#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
2095#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
2096#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
2097#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
2098#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
2099#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
2100#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
2101#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
2102
2103/* ADC Touch Screen Data Register */
2104#define SADC_TSDAT_DATA0_BIT 0
2105#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
2106#define SADC_TSDAT_TYPE0 (1 << 15)
2107#define SADC_TSDAT_DATA1_BIT 16
2108#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
2109#define SADC_TSDAT_TYPE1 (1 << 31)
2110
2111
2112/*************************************************************************
2113 * SLCD (Smart LCD Controller)
2114 *************************************************************************/
2115
2116#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2117#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2118#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2119#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2120
2121#define REG_SLCD_CFG REG32(SLCD_CFG)
2122#define REG_SLCD_CTRL REG8(SLCD_CTRL)
2123#define REG_SLCD_STATE REG8(SLCD_STATE)
2124#define REG_SLCD_DATA REG32(SLCD_DATA)
2125
2126/* SLCD Configure Register */
2127#define SLCD_CFG_BURST_BIT 14
2128#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2129  #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2130  #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2131#define SLCD_CFG_DWIDTH_BIT 10
2132#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2133  #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2134  #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2135  #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2136  #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2137  #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
2138#define SLCD_CFG_CWIDTH_16BIT (0 << 8)
2139#define SLCD_CFG_CWIDTH_8BIT (1 << 8)
2140#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2141#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2142#define SLCD_CFG_RS_CMD_LOW (0 << 3)
2143#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2144#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2145#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2146#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2147#define SLCD_CFG_TYPE_SERIAL (1 << 0)
2148
2149/* SLCD Control Register */
2150#define SLCD_CTRL_DMA_EN (1 << 0)
2151
2152/* SLCD Status Register */
2153#define SLCD_STATE_BUSY (1 << 0)
2154
2155/* SLCD Data Register */
2156#define SLCD_DATA_RS_DATA (0 << 31)
2157#define SLCD_DATA_RS_COMMAND (1 << 31)
2158
2159/*************************************************************************
2160 * LCD (LCD Controller)
2161 *************************************************************************/
2162#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2163#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2164#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2165
2166#define LCD_OSDC (LCD_BASE + 0x100) /* LCD OSD Configure Register */
2167#define LCD_OSDCTRL (LCD_BASE + 0x104) /* LCD OSD Control Register */
2168#define LCD_OSDS (LCD_BASE + 0x108) /* LCD OSD Status Register */
2169#define LCD_BGC (LCD_BASE + 0x10C) /* LCD Background Color Register */
2170#define LCD_KEY0 (LCD_BASE + 0x110) /* LCD Foreground Color Key Register 0 */
2171#define LCD_KEY1 (LCD_BASE + 0x114) /* LCD Foreground Color Key Register 1 */
2172#define LCD_ALPHA (LCD_BASE + 0x118) /* LCD ALPHA Register */
2173#define LCD_IPUR (LCD_BASE + 0x11C) /* LCD IPU Restart Register */
2174
2175#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2176#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2177#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2178
2179#define LCD_XYP0 (LCD_BASE + 0x120) /* Foreground 0 XY Position Register */
2180#define LCD_XYP1 (LCD_BASE + 0x124) /* Foreground 1 XY Position Register */
2181#define LCD_SIZE0 (LCD_BASE + 0x128) /* Foreground 0 Size Register */
2182#define LCD_SIZE1 (LCD_BASE + 0x12C) /* Foreground 1 Size Register */
2183#define LCD_RGBC (LCD_BASE + 0x90) /* RGB Controll Register */
2184
2185#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2186#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2187#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2188#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2189#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2190#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2191#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2192#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2193#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2194#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2195#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2196#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2197#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2198#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2199#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2200
2201#define LCD_OFFS0 (LCD_BASE + 0x60) /* DMA Offsize Register 0 */
2202#define LCD_PW0 (LCD_BASE + 0x64) /* DMA Page Width Register 0 */
2203#define LCD_CNUM0 (LCD_BASE + 0x68) /* DMA Command Counter Register 0 */
2204#define LCD_DESSIZE0 (LCD_BASE + 0x6C) /* Foreground Size in Descriptor 0 Register*/
2205#define LCD_OFFS1 (LCD_BASE + 0x70) /* DMA Offsize Register 1 */
2206#define LCD_PW1 (LCD_BASE + 0x74) /* DMA Page Width Register 1 */
2207#define LCD_CNUM1 (LCD_BASE + 0x78) /* DMA Command Counter Register 1 */
2208#define LCD_DESSIZE1 (LCD_BASE + 0x7C) /* Foreground Size in Descriptor 1 Register*/
2209
2210#define REG_LCD_CFG REG32(LCD_CFG)
2211#define REG_LCD_CTRL REG32(LCD_CTRL)
2212#define REG_LCD_STATE REG32(LCD_STATE)
2213
2214#define REG_LCD_OSDC REG16(LCD_OSDC)
2215#define REG_LCD_OSDCTRL REG16(LCD_OSDCTRL)
2216#define REG_LCD_OSDS REG16(LCD_OSDS)
2217#define REG_LCD_BGC REG32(LCD_BGC)
2218#define REG_LCD_KEY0 REG32(LCD_KEY0)
2219#define REG_LCD_KEY1 REG32(LCD_KEY1)
2220#define REG_LCD_ALPHA REG8(LCD_ALPHA)
2221#define REG_LCD_IPUR REG32(LCD_IPUR)
2222
2223#define REG_LCD_VAT REG32(LCD_VAT)
2224#define REG_LCD_DAH REG32(LCD_DAH)
2225#define REG_LCD_DAV REG32(LCD_DAV)
2226
2227#define REG_LCD_XYP0 REG32(LCD_XYP0)
2228#define REG_LCD_XYP1 REG32(LCD_XYP1)
2229#define REG_LCD_SIZE0 REG32(LCD_SIZE0)
2230#define REG_LCD_SIZE1 REG32(LCD_SIZE1)
2231#define REG_LCD_RGBC REG16(LCD_RGBC)
2232
2233#define REG_LCD_VSYNC REG32(LCD_VSYNC)
2234#define REG_LCD_HSYNC REG32(LCD_HSYNC)
2235#define REG_LCD_PS REG32(LCD_PS)
2236#define REG_LCD_CLS REG32(LCD_CLS)
2237#define REG_LCD_SPL REG32(LCD_SPL)
2238#define REG_LCD_REV REG32(LCD_REV)
2239#define REG_LCD_IID REG32(LCD_IID)
2240#define REG_LCD_DA0 REG32(LCD_DA0)
2241#define REG_LCD_SA0 REG32(LCD_SA0)
2242#define REG_LCD_FID0 REG32(LCD_FID0)
2243#define REG_LCD_CMD0 REG32(LCD_CMD0)
2244#define REG_LCD_DA1 REG32(LCD_DA1)
2245#define REG_LCD_SA1 REG32(LCD_SA1)
2246#define REG_LCD_FID1 REG32(LCD_FID1)
2247#define REG_LCD_CMD1 REG32(LCD_CMD1)
2248
2249#define REG_LCD_OFFS0 REG32(LCD_OFFS0)
2250#define REG_LCD_PW0 REG32(LCD_PW0)
2251#define REG_LCD_CNUM0 REG32(LCD_CNUM0)
2252#define REG_LCD_DESSIZE0 REG32(LCD_DESSIZE0)
2253#define REG_LCD_OFFS1 REG32(LCD_OFFS1)
2254#define REG_LCD_PW1 REG32(LCD_PW1)
2255#define REG_LCD_CNUM1 REG32(LCD_CNUM1)
2256#define REG_LCD_DESSIZE1 REG32(LCD_DESSIZE1)
2257
2258/* LCD Configure Register */
2259#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2260#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2261  #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2262  #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2263#define LCD_CFG_FUHOLD (1 << 29) /* hold pixel clock when outFIFO underrun */
2264#define LCD_CFG_NEWDES (1 << 28) /* use new descripter. old: 4words, new:8words */
2265#define LCD_CFG_PALBP (1 << 27) /* bypass data format and alpha blending */
2266#define LCD_CFG_TVEN (1 << 26) /* indicate the terminal is lcd or tv */
2267#define LCD_CFG_RECOVER (1 << 25) /* Auto recover when output fifo underrun */
2268#define LCD_CFG_DITHER (1 << 24) /* Dither function */
2269#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2270#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2271#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2272#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2273#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2274#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2275#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2276#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2277#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2278#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2279#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2280#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2281#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2282#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2283#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2284#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2285#define MODE_TFT_18BIT (1 << 7) /* 18bit TFT */
2286#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2287#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2288#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2289  #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2290  #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2291  #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2292#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2293#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2294  #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2295  #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2296  #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2297  #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2298  #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2299  #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT)
2300  #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2301  #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2302  #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2303  #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2304  #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2305  #define LCD_CFG_MODE_LCM (13 << LCD_CFG_MODE_BIT)
2306  /* JZ47XX defines */
2307  #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2308  #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2309  #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2310
2311/* LCD Control Register */
2312#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2313#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2314  #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2315  #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2316  #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2317  #define LCD_CTRL_BST_32 (3 << LCD_CTRL_BST_BIT) /* 32-word */
2318#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode(foreground 0 in OSD mode) */
2319#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode(foreground 0 in OSD mode) */
2320#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2321#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2322#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2323  #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2324  #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2325  #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2326#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2327#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2328#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2329#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2330#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2331#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2332#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2333#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2334#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2335#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2336#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2337#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2338#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2339#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2340#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2341  #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2342  #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2343  #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2344  #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2345  #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2346  #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2347
2348/* LCD Status Register */
2349#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2350#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2351#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2352#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2353#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2354#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2355#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2356
2357/* OSD Configure Register */
2358#define LCD_OSDC_SOFM1 (1 << 15) /* Start of frame interrupt mask for foreground 1 */
2359#define LCD_OSDC_EOFM1 (1 << 14) /* End of frame interrupt mask for foreground 1 */
2360#define LCD_OSDC_REM1 (1 << 13) /* Real end of frame mask for foreground 1 */
2361#define LCD_OSDC_SOFM0 (1 << 11) /* Start of frame interrupt mask for foreground 0 */
2362#define LCD_OSDC_EOFM0 (1 << 10) /* End of frame interrupt mask for foreground 0 */
2363#define LCD_OSDC_REM0 (1 << 9) /* Real end of frame mask for foreground 0 */
2364#define LCD_OSDC_REMB (1 << 7) /* Real end of frame mask for background */
2365#define LCD_OSDC_F1EN (1 << 4) /* enable foreground 1 */
2366#define LCD_OSDC_F0EN (1 << 3) /* enable foreground 0 */
2367#define LCD_OSDC_ALPHAEN (1 << 2) /* enable alpha blending */
2368#define LCD_OSDC_ALPHAMD (1 << 1) /* alpha blending mode */
2369#define LCD_OSDC_OSDEN (1 << 0) /* OSD mode enable */
2370
2371/* OSD Controll Register */
2372#define LCD_OSDCTRL_IPU (1 << 15) /* input data from IPU */
2373#define LCD_OSDCTRL_RGB565 (0 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
2374#define LCD_OSDCTRL_RGB555 (1 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
2375#define LCD_OSDCTRL_CHANGES (1 << 3) /* Change size flag */
2376#define LCD_OSDCTRL_OSDBPP_BIT 0 /* Bits Per Pixel of OSD Channel 1 */
2377#define LCD_OSDCTRL_OSDBPP_MASK (0x3<<LCD_OSDCTRL_OSDBPP_BIT) /* Bits Per Pixel of OSD Channel 1's MASK */
2378  #define LCD_OSDCTRL_OSDBPP_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
2379  #define LCD_OSDCTRL_OSDBPP_15_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
2380  #define LCD_OSDCTRL_OSDBPP_18_24 (5 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/
2381
2382/* OSD State Register */
2383#define LCD_OSDS_SOF1 (1 << 15) /* Start of frame flag for foreground 1 */
2384#define LCD_OSDS_EOF1 (1 << 14) /* End of frame flag for foreground 1 */
2385#define LCD_OSDS_SOF0 (1 << 11) /* Start of frame flag for foreground 0 */
2386#define LCD_OSDS_EOF0 (1 << 10) /* End of frame flag for foreground 0 */
2387#define LCD_OSDS_READY (1 << 0) /* Read for accept the change */
2388
2389/* Background Color Register */
2390#define LCD_BGC_RED_OFFSET (1 << 16) /* Red color offset */
2391#define LCD_BGC_RED_MASK (0xFF<<LCD_BGC_RED_OFFSET)
2392#define LCD_BGC_GREEN_OFFSET (1 << 8) /* Green color offset */
2393#define LCD_BGC_GREEN_MASK (0xFF<<LCD_BGC_GREEN_OFFSET)
2394#define LCD_BGC_BLUE_OFFSET (1 << 0) /* Blue color offset */
2395#define LCD_BGC_BLUE_MASK (0xFF<<LCD_BGC_BLUE_OFFSET)
2396
2397/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */
2398#define LCD_KEY_KEYEN (1 << 31) /* enable color key */
2399#define LCD_KEY_KEYMD (1 << 30) /* color key mode */
2400#define LCD_KEY_RED_OFFSET (1 << 16) /* Red color offset */
2401#define LCD_KEY_RED_MASK (0xFF<<LCD_KEY_RED_OFFSET)
2402#define LCD_KEY_GREEN_OFFSET (1 << 8) /* Green color offset */
2403#define LCD_KEY_GREEN_MASK (0xFF<<LCD_KEY_GREEN_OFFSET)
2404#define LCD_KEY_BLUE_OFFSET (1 << 0) /* Blue color offset */
2405#define LCD_KEY_BLUE_MASK (0xFF<<LCD_KEY_BLUE_OFFSET)
2406
2407/* IPU Restart Register */
2408#define LCD_IPUR_IPUREN (1 << 31) /* IPU restart function enable*/
2409
2410/* RGB Control Register */
2411#define LCD_RGBC_RGBDM (1 << 15) /* enable RGB Dummy data */
2412#define LCD_RGBC_DMM (1 << 14) /* RGB Dummy mode */
2413#define LCD_RGBC_YCC (1 << 8) /* RGB to YCC */
2414#define LCD_RGBC_ODDRGB_BIT 4 /* odd line serial RGB data arrangement */
2415#define LCD_RGBC_ODDRGB_MASK (0x7<<LCD_RGBC_ODDRGB_BIT)
2416  #define LCD_RGBC_ODD_RGB 0
2417  #define LCD_RGBC_ODD_RBG 1
2418  #define LCD_RGBC_ODD_GRB 2
2419  #define LCD_RGBC_ODD_GBR 3
2420  #define LCD_RGBC_ODD_BRG 4
2421  #define LCD_RGBC_ODD_BGR 5
2422#define LCD_RGBC_EVENRGB_BIT 0 /* even line serial RGB data arrangement */
2423#define LCD_RGBC_EVENRGB_MASK (0x7<<LCD_RGBC_EVENRGB_BIT)
2424  #define LCD_RGBC_EVEN_RGB 0
2425  #define LCD_RGBC_EVEN_RBG 1
2426  #define LCD_RGBC_EVEN_GRB 2
2427  #define LCD_RGBC_EVEN_GBR 3
2428  #define LCD_RGBC_EVEN_BRG 4
2429  #define LCD_RGBC_EVEN_BGR 5
2430
2431/* Vertical Synchronize Register */
2432#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2433#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2434#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2435#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2436
2437/* Horizontal Synchronize Register */
2438#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2439#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2440#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2441#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2442
2443/* Virtual Area Setting Register */
2444#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2445#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2446#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2447#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2448
2449/* Display Area Horizontal Start/End Point Register */
2450#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2451#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2452#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2453#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2454
2455/* Display Area Vertical Start/End Point Register */
2456#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2457#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2458#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2459#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2460
2461/* Foreground XY Position Register */
2462#define LCD_XYP_YPOS_BIT 16 /* Y position bit of foreground 0 or 1 */
2463#define LCD_XYP_YPOS_MASK (0xffff << LCD_XYP_YPOS_BIT)
2464#define LCD_XYP_XPOS_BIT 0 /* X position bit of foreground 0 or 1 */
2465#define LCD_XYP_XPOS_MASK (0xffff << LCD_XYP_XPOS_BIT)
2466
2467/* PS Signal Setting */
2468#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2469#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2470#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2471#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2472
2473/* CLS Signal Setting */
2474#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2475#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2476#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2477#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2478
2479/* SPL Signal Setting */
2480#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2481#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2482#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2483#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2484
2485/* REV Signal Setting */
2486#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2487#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2488
2489/* DMA Command Register */
2490#define LCD_CMD_SOFINT (1 << 31)
2491#define LCD_CMD_EOFINT (1 << 30)
2492#define LCD_CMD_CMD (1 << 29) /* indicate command in slcd mode */
2493#define LCD_CMD_PAL (1 << 28)
2494#define LCD_CMD_LEN_BIT 0
2495#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
2496
2497/* DMA Offsize Register 0,1 */
2498
2499/* DMA Page Width Register 0,1 */
2500
2501/* DMA Command Counter Register 0,1 */
2502
2503/* Foreground 0,1 Size Register */
2504#define LCD_DESSIZE_HEIGHT_BIT 16 /* height of foreground 1 */
2505#define LCD_DESSIZE_HEIGHT_MASK (0xffff << LCD_DESSIZE_HEIGHT_BIT)
2506#define LCD_DESSIZE_WIDTH_BIT 0 /* width of foreground 1 */
2507#define LCD_DESSIZE_WIDTH_MASK (0xffff << LCD_DESSIZE_WIDTH_BIT)
2508
2509/*************************************************************************
2510 * USB Device
2511 *************************************************************************/
2512#define USB_BASE UDC_BASE
2513
2514#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2515#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2516#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2517#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2518#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2519#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2520#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2521#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2522#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2523#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2524#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2525
2526#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2527#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2528#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2529#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2530#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2531#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2532#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2533#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2534
2535#define USB_FIFO_EP0 (USB_BASE + 0x20)
2536#define USB_FIFO_EP1 (USB_BASE + 0x24)
2537#define USB_FIFO_EP2 (USB_BASE + 0x28)
2538
2539#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2540#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2541
2542#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
2543#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
2544#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
2545#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
2546#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
2547#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
2548#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
2549
2550
2551/* Power register bit masks */
2552#define USB_POWER_SUSPENDM 0x01
2553#define USB_POWER_RESUME 0x04
2554#define USB_POWER_HSMODE 0x10
2555#define USB_POWER_HSENAB 0x20
2556#define USB_POWER_SOFTCONN 0x40
2557
2558/* Interrupt register bit masks */
2559#define USB_INTR_SUSPEND 0x01
2560#define USB_INTR_RESUME 0x02
2561#define USB_INTR_RESET 0x04
2562
2563#define USB_INTR_EP0 0x0001
2564#define USB_INTR_INEP1 0x0002
2565#define USB_INTR_INEP2 0x0004
2566#define USB_INTR_OUTEP1 0x0002
2567
2568/* CSR0 bit masks */
2569#define USB_CSR0_OUTPKTRDY 0x01
2570#define USB_CSR0_INPKTRDY 0x02
2571#define USB_CSR0_SENTSTALL 0x04
2572#define USB_CSR0_DATAEND 0x08
2573#define USB_CSR0_SETUPEND 0x10
2574#define USB_CSR0_SENDSTALL 0x20
2575#define USB_CSR0_SVDOUTPKTRDY 0x40
2576#define USB_CSR0_SVDSETUPEND 0x80
2577
2578/* Endpoint CSR register bits */
2579#define USB_INCSRH_AUTOSET 0x80
2580#define USB_INCSRH_ISO 0x40
2581#define USB_INCSRH_MODE 0x20
2582#define USB_INCSRH_DMAREQENAB 0x10
2583#define USB_INCSRH_DMAREQMODE 0x04
2584#define USB_INCSR_CDT 0x40
2585#define USB_INCSR_SENTSTALL 0x20
2586#define USB_INCSR_SENDSTALL 0x10
2587#define USB_INCSR_FF 0x08
2588#define USB_INCSR_UNDERRUN 0x04
2589#define USB_INCSR_FFNOTEMPT 0x02
2590#define USB_INCSR_INPKTRDY 0x01
2591#define USB_OUTCSRH_AUTOCLR 0x80
2592#define USB_OUTCSRH_ISO 0x40
2593#define USB_OUTCSRH_DMAREQENAB 0x20
2594#define USB_OUTCSRH_DNYT 0x10
2595#define USB_OUTCSRH_DMAREQMODE 0x08
2596#define USB_OUTCSR_CDT 0x80
2597#define USB_OUTCSR_SENTSTALL 0x40
2598#define USB_OUTCSR_SENDSTALL 0x20
2599#define USB_OUTCSR_FF 0x10
2600#define USB_OUTCSR_DATAERR 0x08
2601#define USB_OUTCSR_OVERRUN 0x04
2602#define USB_OUTCSR_FFFULL 0x02
2603#define USB_OUTCSR_OUTPKTRDY 0x01
2604
2605/* Testmode register bits */
2606#define USB_TEST_SE0NAK 0x01
2607#define USB_TEST_J 0x02
2608#define USB_TEST_K 0x04
2609#define USB_TEST_PACKET 0x08
2610
2611/* DMA control bits */
2612#define USB_CNTL_ENA 0x01
2613#define USB_CNTL_DIR_IN 0x02
2614#define USB_CNTL_MODE_1 0x04
2615#define USB_CNTL_INTR_EN 0x08
2616#define USB_CNTL_EP(n) ((n) << 4)
2617#define USB_CNTL_BURST_0 (0 << 9)
2618#define USB_CNTL_BURST_4 (1 << 9)
2619#define USB_CNTL_BURST_8 (2 << 9)
2620#define USB_CNTL_BURST_16 (3 << 9)
2621
2622/*************************************************************************
2623 * BCH
2624 *************************************************************************/
2625#define BCH_CR (BCH_BASE + 0x00) /* BCH Control register */
2626#define BCH_CRS (BCH_BASE + 0x04) /* BCH Control Set register */
2627#define BCH_CRC (BCH_BASE + 0x08) /* BCH Control Clear register */
2628#define BCH_CNT (BCH_BASE + 0x0C) /* BCH ENC/DEC Count register */
2629#define BCH_DR (BCH_BASE + 0x10) /* BCH data register */
2630#define BCH_PAR0 (BCH_BASE + 0x14) /* BCH Parity 0 register */
2631#define BCH_PAR1 (BCH_BASE + 0x18) /* BCH Parity 1 register */
2632#define BCH_PAR2 (BCH_BASE + 0x1C) /* BCH Parity 2 register */
2633#define BCH_PAR3 (BCH_BASE + 0x20) /* BCH Parity 3 register */
2634#define BCH_INTS (BCH_BASE + 0x24) /* BCH Interrupt Status register */
2635#define BCH_ERR0 (BCH_BASE + 0x28) /* BCH Error Report 0 register */
2636#define BCH_ERR1 (BCH_BASE + 0x2C) /* BCH Error Report 1 register */
2637#define BCH_ERR2 (BCH_BASE + 0x30) /* BCH Error Report 2 register */
2638#define BCH_ERR3 (BCH_BASE + 0x34) /* BCH Error Report 3 register */
2639#define BCH_INTE (BCH_BASE + 0x38) /* BCH Interrupt Enable register */
2640#define BCH_INTES (BCH_BASE + 0x3C) /* BCH Interrupt Set register */
2641#define BCH_INTEC (BCH_BASE + 0x40) /* BCH Interrupt Clear register */
2642
2643#define REG_BCH_CR REG32(BCH_CR)
2644#define REG_BCH_CRS REG32(BCH_CRS)
2645#define REG_BCH_CRC REG32(BCH_CRC)
2646#define REG_BCH_CNT REG32(BCH_CNT)
2647#define REG_BCH_DR REG8(BCH_DR)
2648#define REG_BCH_PAR0 REG32(BCH_PAR0)
2649#define REG_BCH_PAR1 REG32(BCH_PAR1)
2650#define REG_BCH_PAR2 REG32(BCH_PAR2)
2651#define REG_BCH_PAR3 REG32(BCH_PAR3)
2652#define REG_BCH_INTS REG32(BCH_INTS)
2653#define REG_BCH_ERR0 REG32(BCH_ERR0)
2654#define REG_BCH_ERR1 REG32(BCH_ERR1)
2655#define REG_BCH_ERR2 REG32(BCH_ERR2)
2656#define REG_BCH_ERR3 REG32(BCH_ERR3)
2657#define REG_BCH_INTE REG32(BCH_INTE)
2658#define REG_BCH_INTEC REG32(BCH_INTEC)
2659#define REG_BCH_INTES REG32(BCH_INTES)
2660
2661/* BCH Control Register*/
2662#define BCH_CR_DMAE (1 << 4) /* BCH DMA Enable */
2663#define BCH_CR_ENCE (1 << 3) /* BCH Encoding Select */
2664#define BCH_CR_DECE (0 << 3) /* BCH Decoding Select */
2665#define BCH_CR_BSEL8 (1 << 2) /* 8 Bit BCH Select */
2666#define BCH_CR_BSEL4 (0 << 2) /* 4 Bit BCH Select */
2667#define BCH_CR_BRST (1 << 1) /* BCH Reset */
2668#define BCH_CR_BCHE (1 << 0) /* BCH Enable */
2669
2670/* BCH Interrupt Status Register */
2671#define BCH_INTS_ERRC_BIT 28
2672#define BCH_INTS_ERRC_MASK (0xf << BCH_INTS_ERRC_BIT)
2673#define BCH_INTS_ALL0 (1 << 5)
2674#define BCH_INTS_ALLf (1 << 4)
2675#define BCH_INTS_DECF (1 << 3)
2676#define BCH_INTS_ENCF (1 << 2)
2677#define BCH_INTS_UNCOR (1 << 1)
2678#define BCH_INTS_ERR (1 << 0)
2679
2680/* BCH ENC/DEC Count Register */
2681#define BCH_CNT_DEC_BIT 16
2682#define BCH_CNT_DEC_MASK (0x3ff << BCH_CNT_DEC_BIT)
2683#define BCH_CNT_ENC_BIT 0
2684#define BCH_CNT_ENC_MASK (0x3ff << BCH_CNT_ENC_BIT)
2685
2686/* BCH Error Report Register */
2687#define BCH_ERR_INDEX_ODD_BIT 16
2688#define BCH_ERR_INDEX_ODD_MASK (0x1fff << BCH_ERR_INDEX_ODD_BIT)
2689#define BCH_ERR_INDEX_EVEN_BIT 0
2690#define BCH_ERR_INDEX_EVEN_MASK (0x1fff << BCH_ERR_INDEX_EVEN_BIT)
2691
2692
2693//----------------------------------------------------------------------
2694//
2695// Module Operation Definitions
2696//
2697//----------------------------------------------------------------------
2698#ifndef __ASSEMBLY__
2699
2700/***************************************************************************
2701 * GPIO
2702 ***************************************************************************/
2703
2704//------------------------------------------------------
2705// GPIO Pins Description
2706//
2707// PORT 0:
2708//
2709// PIN/BIT N FUNC0 FUNC1 NOTE
2710// 0 D0 -
2711// 1 D1 -
2712// 2 D2 -
2713// 3 D3 -
2714// 4 D4 -
2715// 5 D5 -
2716// 6 D6 -
2717// 7 D7 -
2718// 8 D8 -
2719// 9 D9 -
2720// 10 D10 -
2721// 11 D11 -
2722// 12 D12 -
2723// 13 D13 -
2724// 14 D14 -
2725// 15 D15 -
2726// 16 D16 -
2727// 17 D17 -
2728// 18 D18 -
2729// 19 D19 -
2730// 20 D20 -
2731// 21 D21 -
2732// 22 D22 -
2733// 23 D23 -
2734// 24 D24 -
2735// 25 D25 -
2736// 26 D26 -
2737// 27 D27 -
2738// 28 D28 -
2739// 29 D29 -
2740// 30 D30 -
2741// 31 D31 -
2742//
2743//------------------------------------------------------
2744// PORT 1:
2745//
2746// PIN/BIT N FUNC0 FUNC1 NOTE
2747// 0 A0 -
2748// 1 A1 -
2749// 2 A2 -
2750// 3 A3 -
2751// 4 A4 -
2752// 5 A5 -
2753// 6 A6 -
2754// 7 A7 -
2755// 8 A8 -
2756// 9 A9 -
2757// 10 A10 -
2758// 11 A11 -
2759// 12 A12 -
2760// 13 A13 -
2761// 14 A14 -
2762// 15 A15/CLE SA3
2763// 16 DCS0# -
2764// 17 RAS# -
2765// 18 CAS# -
2766// 19 RDWE#/BUFD# -
2767// 20 WE0# -
2768// 21 WE1# -
2769// 22 WE2# -
2770// 23 WE3# -
2771// 24 CKO - Note1
2772// 25 CKE -
2773// 26 SSI0_CLK -
2774// 27 SSI0_DT -
2775// 28 SSI0_DR -
2776// 29 SSI0_CE0# -
2777// 30 SSI0_CE1#_GPC -
2778// 31 SSI0_CE2# -
2779//
2780// Note1: BIT24: it is CKO when chip is reset
2781//
2782//------------------------------------------------------
2783// PORT 2:
2784//
2785// PIN/BIT N FUNC0 FUNC1 NOTE
2786// 0 SD0 A20
2787// 1 SD1 A21
2788// 2 SD2 A22
2789// 3 SD3 A23
2790// 4 SD4 A24
2791// 5 SD5 A25
2792// 6 SD6 -
2793// 7 SD7 -
2794// 8 SD8 TSDI0
2795// 9 SD9 TSDI1
2796// 10 SD10 TSDI2
2797// 11 SD11 TSDI3
2798// 12 SD12 TSDI4
2799// 13 SD13 TSDI5
2800// 14 SD14 TSDI6
2801// 15 SD15 TSDI7
2802// 16 A16/ALE SA4
2803// 17 SA0 A17
2804// 18 SA1 A18
2805// 19 SA2 A19
2806// 20 WAIT# - Note2
2807// 21 CS1# -
2808// 22 CS2# -
2809// 23 CS3# -
2810// 24 CS4# -
2811// 25 RD# -
2812// 26 WR# -
2813// 27 FRB# - Note3
2814// 28 FRE# -
2815// 29 FWE# -
2816// 30 BOOT_SEL0 - Note4
2817// 31 BOOT_SEL1 - Note5
2818//
2819// Note2: BIT20: it is WIAT# pin when chip is reset
2820//
2821// Note3: BIT27: when NAND is used, it should connect to NANF FRB#.
2822//
2823// Note4: BIT30: it is BOOT_SEL0 when chip is reset, it can used as output GPIO.
2824//
2825// Note5: BIT31: it is BOOT_SEL1 when chip is reset, it can used as general GPIO.
2826//
2827//------------------------------------------------------
2828// PORT 3:
2829//
2830// PIN/BIT N FUNC0 FUNC1 NOTE
2831// 0 LCD_D0 -
2832// 1 LCD_D1 -
2833// 2 LCD_D2 -
2834// 3 LCD_D3 -
2835// 4 LCD_D4 -
2836// 5 LCD_D5 -
2837// 6 LCD_D6 -
2838// 7 LCD_D7 -
2839// 8 LCD_D8 -
2840// 9 LCD_D9 -
2841// 10 LCD_D10 -
2842// 11 LCD_D11 -
2843// 12 LCD_D12 -
2844// 13 LCD_D13 -
2845// 14 LCD_D14 -
2846// 15 LCD_D15 -
2847// 16 LCD_D16 -
2848// 17 LCD_D17 -
2849// 18 LCD_PCLK -
2850// 19 LCD_HSYNC -
2851// 20 LCD_VSYNC -
2852// 21 LCD_DE -
2853// 22 LCD_CLS -
2854// 23 LCD_SPL -
2855// 24 LCD_PS -
2856// 25 LCD_REV -
2857// 26 SSI1_CLK -
2858// 27 SSI1_DT -
2859// 28 SSI1_DR -
2860// 29 SSI1_CE0# -
2861// 30 SSI1_CE1# -
2862// 31 - -
2863//
2864//------------------------------------------------------
2865// PORT 4:
2866//
2867// PIN/BIT N FUNC0 FUNC1 NOTE
2868// 0 CIM_D0 -
2869// 1 CIM_D1 -
2870// 2 CIM_D2 -
2871// 3 CIM_D3 -
2872// 4 CIM_D4 -
2873// 5 CIM_D5 -
2874// 6 CIM_D6 -
2875// 7 CIM_D7 -
2876// 8 CIM_MCLK -
2877// 9 CIM_PCLK -
2878// 10 CIM_VSYNC -
2879// 11 CIM_HSYNC -
2880// 12 I2C_SDA -
2881// 13 I2C_SCK -
2882// 14 - -
2883// 15 - -
2884// 16 UART1_RxD -
2885// 17 UART1_TxD -
2886// 18 UART1_CTS PCM_DIN
2887// 19 UART1_RTS PCM_DOUT
2888// 20 PWM0 PCM_CLK
2889// 21 PWM1 PCM_SYN
2890// 22 PWM2 SCLK_RSTN
2891// 23 PWM3 BCLK
2892// 24 PWM4 SYNC
2893// 25 PWM5 OWI
2894// 26 SDATO UART2_TxD
2895// 27 SDATI UART2_RxD
2896// 28 DCS1# -
2897// 29 - -
2898// 30 WKUP - Note6
2899// 31 - - Note7
2900//
2901// Note6: BIT30: it is only used as input and interrupt, and with no pull-up and pull-down
2902//
2903// Note7: BIT31: it is used to select the function of UART or JTAG set by PESEL[31]
2904// PESEL[31] = 0, select JTAG function
2905// PESEL[31] = 1, select UART function
2906//
2907//------------------------------------------------------
2908// PORT 5:
2909//
2910// PIN/BIT N FUNC0 FUNC1 NOTE
2911// 0 MSC0_D0 -
2912// 1 MSC0_D1 -
2913// 2 MSC0_D2 DREQ
2914// 3 MSC0_D3 DACK
2915// 4 MSC0_D4 UART0_RxD
2916// 5 MSC0_D5 UART0_TxD
2917// 6 MSC0_D6 UART0_CTS
2918// 7 MSC0_D7 UART0_RTS
2919// 8 MSC0_CLK -
2920// 9 MSC0_CMD -
2921// 10 MSC1_D0 -
2922// 11 MSC1_D1 -
2923// 12 MSC1_D2 -
2924// 13 MSC1_D3 -
2925// 14 MSC1_CLK -
2926// 15 MSC1_CMD -
2927// 16 UART3_RxD -
2928// 17 UART3_TxD -
2929// 18 UART3_CTS -
2930// 19 UART3_RTS -
2931// 20 TSCLK -
2932// 21 TSSTR -
2933// 22 TSFRM -
2934// 23 TSFAIL -
2935// 24 - -
2936// 25 - -
2937// 26 - -
2938// 27 - -
2939// 28 - -
2940// 29 - -
2941// 30 - -
2942// 31 - -
2943//
2944//////////////////////////////////////////////////////////
2945
2946/*----------------------------------------------------------------
2947 * p is the port number (0,1,2,3)
2948 * o is the pin offset (0-31) inside the port
2949 * n is the absolute number of a pin (0-127), regardless of the port
2950 */
2951
2952//----------------------------------------------------------------
2953// Function Pins Mode
2954
2955#define __gpio_as_func0(n) \
2956do { \
2957    unsigned int p, o; \
2958    p = (n) / 32; \
2959    o = (n) % 32; \
2960    REG_GPIO_PXFUNS(p) = (1 << o); \
2961    REG_GPIO_PXSELC(p) = (1 << o); \
2962} while (0)
2963
2964#define __gpio_as_func1(n) \
2965do { \
2966    unsigned int p, o; \
2967    p = (n) / 32; \
2968    o = (n) % 32; \
2969    REG_GPIO_PXFUNS(p) = (1 << o); \
2970    REG_GPIO_PXSELS(p) = (1 << o); \
2971} while (0)
2972
2973/*
2974 * D0 ~ D31, A0 ~ A14, DCS0#, RAS#, CAS#,
2975 * RDWE#, WE0#, WE1#, WE2#, WE3#, CKO#, CKE#
2976 */
2977#define __gpio_as_sdram_32bit() \
2978do { \
2979    REG_GPIO_PXFUNS(0) = 0xffffffff; \
2980    REG_GPIO_PXSELC(0) = 0xffffffff; \
2981    REG_GPIO_PXPES(0) = 0xffffffff; \
2982    REG_GPIO_PXFUNS(1) = 0x03ff7fff; \
2983    REG_GPIO_PXSELC(1) = 0x03ff7fff; \
2984    REG_GPIO_PXPES(1) = 0x03ff7fff; \
2985} while (0)
2986
2987/*
2988 * D0 ~ D31, A0 ~ A14, DCS0#, RAS#, CAS#,
2989 * RDWE#, WE0#, WE1#, WE2#, WE3#, CKO#, CKE#
2990 * !!!!DCS1#
2991 */
2992#define __gpio_as_sdram_x2_32bit() \
2993do { \
2994    REG_GPIO_PXFUNS(0) = 0xffffffff; \
2995    REG_GPIO_PXSELC(0) = 0xffffffff; \
2996    REG_GPIO_PXPES(0) = 0xffffffff; \
2997    REG_GPIO_PXFUNS(1) = 0x03ff7fff; \
2998    REG_GPIO_PXSELC(1) = 0x03ff7fff; \
2999    REG_GPIO_PXPES(1) = 0x03ff7fff; \
3000    REG_GPIO_PXFUNS(4) = 0x10000000; \
3001    REG_GPIO_PXSELC(4) = 0x10000000; \
3002    REG_GPIO_PXPES(4) = 0x10000000; \
3003} while (0)
3004/*
3005 * D0 ~ D15, A0 ~ A14, DCS0#, RAS#, CAS#,
3006 * RDWE#, WE0#, WE1#, WE2#, WE3#, CKO#, CKE#
3007 */
3008#define __gpio_as_sdram_16bit() \
3009do { \
3010    REG_GPIO_PXFUNS(0) = 0x0000ffff; \
3011    REG_GPIO_PXSELC(0) = 0x0000ffff; \
3012    REG_GPIO_PXPES(0) = 0x0000ffff; \
3013    REG_GPIO_PXFUNS(1) = 0x03ff7fff; \
3014    REG_GPIO_PXSELC(1) = 0x03ff7fff; \
3015    REG_GPIO_PXPES(1) = 0x03ff7fff; \
3016} while (0)
3017
3018/*
3019 * UART1_TxD, UART1_RxD
3020 */
3021#define __gpio_as_uart1() \
3022do { \
3023    REG_GPIO_PXFUNS(4) = 0x00030000; \
3024    REG_GPIO_PXSELC(4) = 0x00030000; \
3025    REG_GPIO_PXPES(4) = 0x00030000; \
3026} while (0)
3027
3028/*
3029 * UART1_TxD, UART1_RxD, UART1_CTS, UART1_RTS
3030 */
3031#define __gpio_as_uart1_ctsrts() \
3032do { \
3033    REG_GPIO_PXFUNS(4) = 0x000f0000; \
3034    REG_GPIO_PXSELC(4) = 0x000f0000; \
3035    REG_GPIO_PXPES(4) = 0x000f0000; \
3036} while (0)
3037
3038/*
3039 * D0 ~ D7, CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
3040 */
3041#define __gpio_as_nand_8bit() \
3042do { \
3043    REG_GPIO_PXFUNS(0) = 0x000000ff; \
3044    REG_GPIO_PXSELC(0) = 0x000000ff; \
3045    REG_GPIO_PXPES(0) = 0x000000ff; \
3046    REG_GPIO_PXFUNS(1) = 0x00088000; \
3047    REG_GPIO_PXSELC(1) = 0x00088000; \
3048    REG_GPIO_PXPES(1) = 0x00088000; \
3049    REG_GPIO_PXFUNS(2) = 0x30210000; \
3050    REG_GPIO_PXSELC(2) = 0x30210000; \
3051    REG_GPIO_PXPES(2) = 0x30210000; \
3052    REG_GPIO_PXFUNC(2) = 0x08000000; \
3053    REG_GPIO_PXSELC(2) = 0x08000000; \
3054    REG_GPIO_PXDIRC(2) = 0x08000000; \
3055    REG_GPIO_PXPES(2) = 0x08000000; \
3056} while (0)
3057
3058/*
3059 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
3060 */
3061#define __gpio_as_nor_8bit() \
3062do { \
3063    REG_GPIO_PXFUNS(0) = 0x000000ff; \
3064    REG_GPIO_PXSELC(0) = 0x000000ff; \
3065    REG_GPIO_PXPES(0) = 0x000000ff; \
3066    REG_GPIO_PXFUNS(1) = 0x0000ffff; \
3067    REG_GPIO_PXSELC(1) = 0x0000ffff; \
3068    REG_GPIO_PXPES(1) = 0x0000ffff; \
3069    REG_GPIO_PXFUNS(2) = 0x07110007; \
3070    REG_GPIO_PXSELC(2) = 0x07110007; \
3071    REG_GPIO_PXPES(2) = 0x07110007; \
3072    REG_GPIO_PXFUNS(2) = 0x000e0000; \
3073    REG_GPIO_PXSELS(2) = 0x000e0000; \
3074    REG_GPIO_PXPES(2) = 0x000e0000; \
3075} while (0)
3076
3077/*
3078 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
3079 */
3080#define __gpio_as_nor_16bit() \
3081do { \
3082    REG_GPIO_PXFUNS(0) = 0x0000ffff; \
3083    REG_GPIO_PXSELC(0) = 0x0000ffff; \
3084    REG_GPIO_PXPES(0) = 0x0000ffff; \
3085    REG_GPIO_PXFUNS(1) = 0x0000ffff; \
3086    REG_GPIO_PXSELC(1) = 0x0000ffff; \
3087    REG_GPIO_PXPES(1) = 0x0000ffff; \
3088    REG_GPIO_PXFUNS(2) = 0x07110007; \
3089    REG_GPIO_PXSELC(2) = 0x07110007; \
3090    REG_GPIO_PXPES(2) = 0x07110007; \
3091    REG_GPIO_PXFUNS(2) = 0x000e0000; \
3092    REG_GPIO_PXSELS(2) = 0x000e0000; \
3093    REG_GPIO_PXPES(2) = 0x000e0000; \
3094} while (0)
3095
3096#define __gpio_as_uart2() \
3097do { \
3098    REG_GPIO_PXFUNS(4) = 0x0c000000; \
3099    REG_GPIO_PXSELS(4) = 0x0c000000; \
3100    REG_GPIO_PXPES(4) = 0x0c000000; \
3101} while (0)
3102
3103/*
3104 * UART3_TxD, UART3_RxD
3105 */
3106#define __gpio_as_uart3() \
3107do { \
3108    REG_GPIO_PXFUNS(5) = 0x00030000; \
3109    REG_GPIO_PXSELC(5) = 0x00030000; \
3110    REG_GPIO_PXPES(5) = 0x00030000; \
3111} while (0)
3112
3113/*
3114 * UART3_TxD, UART3_RxD, UART3_CTS, UART3_RTS
3115 */
3116#define __gpio_as_uart3_ctsrts() \
3117do { \
3118    REG_GPIO_PXFUNS(5) = 0x000f0000; \
3119    REG_GPIO_PXSELC(5) = 0x000f0000; \
3120    REG_GPIO_PXPES(5) = 0x000f0000; \
3121} while (0)
3122
3123/*
3124 * UART0_TxD, UART_RxD0
3125 */
3126#define __gpio_as_uart0() \
3127do { \
3128    REG_GPIO_PXFUNS(5) = 0x00000030; \
3129    REG_GPIO_PXSELS(5) = 0x00000030; \
3130    REG_GPIO_PXPES(5) = 0x00000030; \
3131} while (0)
3132
3133/*
3134 * UART0_CTS, UART0_RTS
3135 */
3136#define __gpio_as_ctsrts() \
3137do { \
3138    REG_GPIO_PXFUNS(5) = 0x000000c0; \
3139    REG_GPIO_PXSELS(5) = 0x000000c0; \
3140    REG_GPIO_PXPES(5) = 0x000000c0; \
3141} while (0)
3142
3143/*
3144 * LCD_D0~LCD_D7, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
3145 */
3146#define __gpio_as_lcd_8bit() \
3147do { \
3148    REG_GPIO_PXFUNS(3) = 0x003c00ff; \
3149    REG_GPIO_PXSELC(3) = 0x003c00ff; \
3150    REG_GPIO_PXPES(3) = 0x003c00ff; \
3151} while (0)
3152
3153/*
3154 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
3155 */
3156#define __gpio_as_lcd_16bit() \
3157do { \
3158    REG_GPIO_PXFUNS(3) = 0x003cffff; \
3159    REG_GPIO_PXSELC(3) = 0x003cffff; \
3160    REG_GPIO_PXPES(3) = 0x003cffff; \
3161} while (0)
3162
3163/*
3164 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
3165 */
3166#define __gpio_as_lcd_18bit() \
3167do { \
3168    REG_GPIO_PXFUNS(3) = 0x003fffff; \
3169    REG_GPIO_PXSELC(3) = 0x003fffff; \
3170    REG_GPIO_PXPES(3) = 0x003fffff; \
3171} while (0)
3172
3173/*
3174 * LCD_CLS, LCD_SPL, LCD_PS, LCD_REV
3175 */
3176#define __gpio_as_lcd_special() \
3177do { \
3178    REG_GPIO_PXFUNS(3) = 0x03C00000; \
3179    REG_GPIO_PXSELC(3) = 0x03C00000; \
3180    REG_GPIO_PXPES(3) = 0x03C00000; \
3181} while (0)
3182
3183/*
3184 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
3185 */
3186#define __gpio_as_cim() \
3187do { \
3188    REG_GPIO_PXFUNS(4) = 0x00000fff; \
3189    REG_GPIO_PXSELC(4) = 0x00000fff; \
3190    REG_GPIO_PXPES(4) = 0x00000fff; \
3191} while (0)
3192
3193/*
3194 * SDATO, SDATI, BCLK, SYNC, SCLK_RSTN(gpio sepc) or
3195 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET(aic spec)
3196 */
3197#define __gpio_as_aic() \
3198do { \
3199    REG_GPIO_PXFUNS(4) = 0x0c000000; \
3200    REG_GPIO_PXSELS(4) = 0x0c000000; \
3201    REG_GPIO_PXPES(4) = 0x0c000000; \
3202    REG_GPIO_PXFUNS(4) = 0x00e00000; \
3203    REG_GPIO_PXSELC(4) = 0x00e00000; \
3204    REG_GPIO_PXPES(4) = 0x00e00000; \
3205} while (0)
3206
3207/*
3208 * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3
3209 */
3210#define __gpio_as_msc0_4bit() \
3211do { \
3212    REG_GPIO_PXFUNS(5) = 0x0000030f; \
3213    REG_GPIO_PXSELC(5) = 0x0000030f; \
3214    REG_GPIO_PXPES(5) = 0x0000030f; \
3215} while (0)
3216
3217/*
3218 * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D7
3219 */
3220#define __gpio_as_msc0_8bit() \
3221do { \
3222    REG_GPIO_PXFUNS(5) = 0x000003ff; \
3223    REG_GPIO_PXSELC(5) = 0x000003ff; \
3224    REG_GPIO_PXPES(5) = 0x000003ff; \
3225} while (0)
3226
3227/*
3228 * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3
3229 */
3230#define __gpio_as_msc1_4bit() \
3231do { \
3232    REG_GPIO_PXFUNS(5) = 0x0000fc00; \
3233    REG_GPIO_PXSELC(5) = 0x0000fc00; \
3234    REG_GPIO_PXPES(5) = 0x0000fc00; \
3235} while (0)
3236
3237#define __gpio_as_msc __gpio_as_msc0_8bit /* default as msc0 8bit */
3238#define __gpio_as_msc0 __gpio_as_msc0_8bit /* msc0 default as 8bit */
3239#define __gpio_as_msc1 __gpio_as_msc1_4bit /* msc1 only support 4bit */
3240
3241/*
3242 * SSI0_CE0, SSI0_CE1#_GPC, SSI0_CE2, SSI0_CLK, SSI0_DT, SSI0_DR
3243 */
3244#define __gpio_as_ssi0() \
3245do { \
3246    REG_GPIO_PXFUNS(1) = 0xfc000000; \
3247    REG_GPIO_PXSELC(1) = 0xfc000000; \
3248    REG_GPIO_PXPES(1) = 0xfc000000; \
3249} while (0)
3250
3251/*
3252 * SSI1_CE0, SSI1_CE1, SSI1_CLK, SSI1_DT, SSI1_DR
3253 */
3254#define __gpio_as_ssi1() \
3255do { \
3256    REG_GPIO_PXFUNS(3) = 0x7c000000; \
3257    REG_GPIO_PXSELC(3) = 0x7c000000; \
3258    REG_GPIO_PXPES(3) = 0x7c000000; \
3259} while (0)
3260
3261/* n = 0(SSI0), 1(SSI1) */
3262#define __gpio_as_ssi(n) __gpio_as_ssi##n()
3263
3264/*
3265 * I2C_SCK, I2C_SDA
3266 */
3267#define __gpio_as_i2c() \
3268do { \
3269    REG_GPIO_PXFUNS(4) = 0x00003000; \
3270    REG_GPIO_PXSELC(4) = 0x00003000; \
3271    REG_GPIO_PXPES(4) = 0x00003000; \
3272} while (0)
3273
3274/*
3275 * PWM0
3276 */
3277#define __gpio_as_pwm0() \
3278do { \
3279    REG_GPIO_PXFUNS(4) = 0x00100000; \
3280    REG_GPIO_PXSELC(4) = 0x00100000; \
3281    REG_GPIO_PXPES(4) = 0x00100000; \
3282} while (0)
3283
3284/*
3285 * PWM1
3286 */
3287#define __gpio_as_pwm1() \
3288do { \
3289    REG_GPIO_PXFUNS(4) = 0x00200000; \
3290    REG_GPIO_PXSELC(4) = 0x00200000; \
3291    REG_GPIO_PXPES(4) = 0x00200000; \
3292} while (0)
3293
3294/*
3295 * PWM2
3296 */
3297#define __gpio_as_pwm2() \
3298do { \
3299    REG_GPIO_PXFUNS(4) = 0x00400000; \
3300    REG_GPIO_PXSELC(4) = 0x00400000; \
3301    REG_GPIO_PXPES(4) = 0x00400000; \
3302} while (0)
3303
3304/*
3305 * PWM3
3306 */
3307#define __gpio_as_pwm3() \
3308do { \
3309    REG_GPIO_PXFUNS(4) = 0x00800000; \
3310    REG_GPIO_PXSELC(4) = 0x00800000; \
3311    REG_GPIO_PXPES(4) = 0x00800000; \
3312} while (0)
3313
3314/*
3315 * PWM4
3316 */
3317#define __gpio_as_pwm4() \
3318do { \
3319    REG_GPIO_PXFUNS(4) = 0x01000000; \
3320    REG_GPIO_PXSELC(4) = 0x01000000; \
3321    REG_GPIO_PXPES(4) = 0x01000000; \
3322} while (0)
3323
3324/*
3325 * PWM5
3326 */
3327#define __gpio_as_pwm5() \
3328do { \
3329    REG_GPIO_PXFUNS(4) = 0x02000000; \
3330    REG_GPIO_PXSELC(4) = 0x02000000; \
3331    REG_GPIO_PXPES(4) = 0x02000000; \
3332} while (0)
3333
3334/*
3335 * n = 0 ~ 5
3336 */
3337#define __gpio_as_pwm(n) __gpio_as_pwm##n()
3338
3339//-------------------------------------------
3340// GPIO or Interrupt Mode
3341
3342#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
3343
3344#define __gpio_port_as_output(p, o) \
3345do { \
3346    REG_GPIO_PXFUNC(p) = (1 << (o)); \
3347    REG_GPIO_PXSELC(p) = (1 << (o)); \
3348    REG_GPIO_PXDIRS(p) = (1 << (o)); \
3349} while (0)
3350
3351#define __gpio_port_as_input(p, o) \
3352do { \
3353    REG_GPIO_PXFUNC(p) = (1 << (o)); \
3354    REG_GPIO_PXSELC(p) = (1 << (o)); \
3355    REG_GPIO_PXDIRC(p) = (1 << (o)); \
3356} while (0)
3357
3358#define __gpio_as_output(n) \
3359do { \
3360    unsigned int p, o; \
3361    p = (n) / 32; \
3362    o = (n) % 32; \
3363    __gpio_port_as_output(p, o); \
3364} while (0)
3365
3366#define __gpio_as_input(n) \
3367do { \
3368    unsigned int p, o; \
3369    p = (n) / 32; \
3370    o = (n) % 32; \
3371    __gpio_port_as_input(p, o); \
3372} while (0)
3373
3374#define __gpio_set_pin(n) \
3375do { \
3376    unsigned int p, o; \
3377    p = (n) / 32; \
3378    o = (n) % 32; \
3379    REG_GPIO_PXDATS(p) = (1 << o); \
3380} while (0)
3381
3382#define __gpio_clear_pin(n) \
3383do { \
3384    unsigned int p, o; \
3385    p = (n) / 32; \
3386    o = (n) % 32; \
3387    REG_GPIO_PXDATC(p) = (1 << o); \
3388} while (0)
3389
3390#define __gpio_get_pin(n) \
3391({ \
3392    unsigned int p, o, v; \
3393    p = (n) / 32; \
3394    o = (n) % 32; \
3395    if (__gpio_get_port(p) & (1 << o)) \
3396        v = 1; \
3397    else \
3398        v = 0; \
3399    v; \
3400})
3401
3402#define __gpio_as_irq_high_level(n) \
3403do { \
3404    unsigned int p, o; \
3405    p = (n) / 32; \
3406    o = (n) % 32; \
3407    REG_GPIO_PXIMS(p) = (1 << o); \
3408    REG_GPIO_PXTRGC(p) = (1 << o); \
3409    REG_GPIO_PXFUNC(p) = (1 << o); \
3410    REG_GPIO_PXSELS(p) = (1 << o); \
3411    REG_GPIO_PXDIRS(p) = (1 << o); \
3412    REG_GPIO_PXFLGC(p) = (1 << o); \
3413    REG_GPIO_PXIMC(p) = (1 << o); \
3414} while (0)
3415
3416#define __gpio_as_irq_low_level(n) \
3417do { \
3418    unsigned int p, o; \
3419    p = (n) / 32; \
3420    o = (n) % 32; \
3421    REG_GPIO_PXIMS(p) = (1 << o); \
3422    REG_GPIO_PXTRGC(p) = (1 << o); \
3423    REG_GPIO_PXFUNC(p) = (1 << o); \
3424    REG_GPIO_PXSELS(p) = (1 << o); \
3425    REG_GPIO_PXDIRC(p) = (1 << o); \
3426    REG_GPIO_PXFLGC(p) = (1 << o); \
3427    REG_GPIO_PXIMC(p) = (1 << o); \
3428} while (0)
3429
3430#define __gpio_as_irq_rise_edge(n) \
3431do { \
3432    unsigned int p, o; \
3433    p = (n) / 32; \
3434    o = (n) % 32; \
3435    REG_GPIO_PXIMS(p) = (1 << o); \
3436    REG_GPIO_PXTRGS(p) = (1 << o); \
3437    REG_GPIO_PXFUNC(p) = (1 << o); \
3438    REG_GPIO_PXSELS(p) = (1 << o); \
3439    REG_GPIO_PXDIRS(p) = (1 << o); \
3440    REG_GPIO_PXFLGC(p) = (1 << o); \
3441    REG_GPIO_PXIMC(p) = (1 << o); \
3442} while (0)
3443
3444#define __gpio_as_irq_fall_edge(n) \
3445do { \
3446    unsigned int p, o; \
3447    p = (n) / 32; \
3448    o = (n) % 32; \
3449    REG_GPIO_PXIMS(p) = (1 << o); \
3450    REG_GPIO_PXTRGS(p) = (1 << o); \
3451    REG_GPIO_PXFUNC(p) = (1 << o); \
3452    REG_GPIO_PXSELS(p) = (1 << o); \
3453    REG_GPIO_PXDIRC(p) = (1 << o); \
3454    REG_GPIO_PXFLGC(p) = (1 << o); \
3455    REG_GPIO_PXIMC(p) = (1 << o); \
3456} while (0)
3457
3458#define __gpio_mask_irq(n) \
3459do { \
3460    unsigned int p, o; \
3461    p = (n) / 32; \
3462    o = (n) % 32; \
3463    REG_GPIO_PXIMS(p) = (1 << o); \
3464} while (0)
3465
3466#define __gpio_unmask_irq(n) \
3467do { \
3468    unsigned int p, o; \
3469    p = (n) / 32; \
3470    o = (n) % 32; \
3471    REG_GPIO_PXIMC(p) = (1 << o); \
3472} while (0)
3473
3474#define __gpio_ack_irq(n) \
3475do { \
3476    unsigned int p, o; \
3477    p = (n) / 32; \
3478    o = (n) % 32; \
3479    REG_GPIO_PXFLGC(p) = (1 << o); \
3480} while (0)
3481
3482#define __gpio_get_irq() \
3483({ \
3484    unsigned int p, i, tmp, v = 0; \
3485    for (p = 3; p >= 0; p--) { \
3486        tmp = REG_GPIO_PXFLG(p); \
3487        for (i = 0; i < 32; i++) \
3488            if (tmp & (1 << i)) \
3489                v = (32*p + i); \
3490    } \
3491    v; \
3492})
3493
3494#define __gpio_group_irq(n) \
3495({ \
3496    register int tmp, i; \
3497    tmp = REG_GPIO_PXFLG((n)); \
3498    for (i=31;i>=0;i--) \
3499        if (tmp & (1 << i)) \
3500            break; \
3501    i; \
3502})
3503
3504#define __gpio_enable_pull(n) \
3505do { \
3506    unsigned int p, o; \
3507    p = (n) / 32; \
3508    o = (n) % 32; \
3509    REG_GPIO_PXPEC(p) = (1 << o); \
3510} while (0)
3511
3512#define __gpio_disable_pull(n) \
3513do { \
3514    unsigned int p, o; \
3515    p = (n) / 32; \
3516    o = (n) % 32; \
3517    REG_GPIO_PXPES(p) = (1 << o); \
3518} while (0)
3519
3520
3521/***************************************************************************
3522 * CPM
3523 ***************************************************************************/
3524#define __cpm_get_pllm() \
3525    ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
3526#define __cpm_get_plln() \
3527    ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
3528#define __cpm_get_pllod() \
3529    ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
3530
3531#define __cpm_get_cdiv() \
3532    ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
3533#define __cpm_get_hdiv() \
3534    ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
3535#define __cpm_get_pdiv() \
3536    ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
3537#define __cpm_get_mdiv() \
3538    ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
3539#define __cpm_get_ldiv() \
3540    ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
3541#define __cpm_get_udiv() \
3542    ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
3543#define __cpm_get_i2sdiv() \
3544    ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
3545#define __cpm_get_pixdiv() \
3546    ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
3547#define __cpm_get_mscdiv(n) \
3548    ((REG_CPM_MSCCDR(n) & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
3549#define __cpm_get_uhcdiv() \
3550    ((REG_CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT)
3551#define __cpm_get_ssidiv() \
3552    ((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
3553#define __cpm_get_pcmdiv(v) \
3554    ((REG_CPM_PCMCDR & CPM_PCMCDR_PCMCD_MASK) >> CPM_PCMCDR_PCMCD_BIT)
3555
3556#define __cpm_set_cdiv(v) \
3557    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
3558#define __cpm_set_hdiv(v) \
3559    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
3560#define __cpm_set_pdiv(v) \
3561    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
3562#define __cpm_set_mdiv(v) \
3563    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
3564#define __cpm_set_ldiv(v) \
3565    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
3566#define __cpm_set_udiv(v) \
3567    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
3568#define __cpm_set_i2sdiv(v) \
3569    (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
3570#define __cpm_set_pixdiv(v) \
3571    (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
3572#define __cpm_set_mscdiv(n, v) \
3573    (REG_CPM_MSCCDR(n) = (REG_CPM_MSCCDR(n) & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
3574#define __cpm_set_uhcdiv(v) \
3575    (REG_CPM_UHCCDR = (REG_CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | ((v) << (CPM_UHCCDR_UHCDIV_BIT)))
3576#define __cpm_set_ssidiv(v) \
3577    (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))
3578#define __cpm_set_pcmdiv(v) \
3579    (REG_CPM_PCMCDR = (REG_CPM_PCMCDR & ~CPM_PCMCDR_PCMCD_MASK) | ((v) << (CPM_PCMCDR_PCMCD_BIT)))
3580
3581#define __cpm_select_pcmclk_pll() (REG_CPM_PCMCDR |= CPM_PCMCDR_PCMS)
3582#define __cpm_select_pcmclk_exclk() (REG_CPM_PCMCDR &= ~CPM_PCMCDR_PCMS)
3583#define __cpm_select_pixclk_ext() (REG_CPM_LPCDR |= CPM_LPCDR_LPCS)
3584#define __cpm_select_pixclk_pll() (REG_CPM_LPCDR &= ~CPM_LPCDR_LPCS)
3585#define __cpm_select_tveclk_exclk() (REG_CPM_LPCDR |= CPM_CPCCR_LSCS)
3586#define __cpm_select_tveclk_pll() (REG_CPM_LPCDR &= ~CPM_LPCDR_LSCS)
3587#define __cpm_select_pixclk_lcd() (REG_CPM_LPCDR &= ~CPM_LPCDR_LTCS)
3588#define __cpm_select_pixclk_tve() (REG_CPM_LPCDR |= CPM_LPCDR_LTCS)
3589#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
3590#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
3591#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
3592#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
3593
3594#define __cpm_enable_cko()
3595#define __cpm_exclk_direct() (REG_CPM_CPCCR &= ~CPM_CPCCR_ECS)
3596#define __cpm_exclk_div2() (REG_CPM_CPCCR |= CPM_CPCCR_ECS)
3597#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
3598#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
3599#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
3600#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
3601
3602#define __cpm_pll_is_off() (REG_CPM_CPPSR & CPM_CPPSR_PLLOFF)
3603#define __cpm_pll_is_on() (REG_CPM_CPPSR & CPM_CPPSR_PLLON)
3604#define __cpm_pll_bypass() (REG_CPM_CPPSR |= CPM_CPPSR_PLLBP)
3605
3606#define __cpm_get_cclk_doze_duty() \
3607    ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
3608#define __cpm_set_cclk_doze_duty(v) \
3609    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
3610
3611#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
3612#define __cpm_idle_mode() \
3613    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
3614#define __cpm_sleep_mode() \
3615    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
3616
3617#define __cpm_stop_all() (REG_CPM_CLKGR = 0x1fffffff)
3618#define __cpm_stop_cimram() (REG_CPM_CLKGR |= CPM_CLKGR_CIMRAM)
3619#define __cpm_stop_idct() (REG_CPM_CLKGR |= CPM_CLKGR_IDCT)
3620#define __cpm_stop_db() (REG_CPM_CLKGR |= CPM_CLKGR_DB)
3621#define __cpm_stop_me() (REG_CPM_CLKGR |= CPM_CLKGR_ME)
3622#define __cpm_stop_mc() (REG_CPM_CLKGR |= CPM_CLKGR_MC)
3623#define __cpm_stop_tve() (REG_CPM_CLKGR |= CPM_CLKGR_TVE)
3624#define __cpm_stop_tssi() (REG_CPM_CLKGR |= CPM_CLKGR_TSSI)
3625#define __cpm_stop_owi() (REG_CPM_CLKGR |= CPM_CLKGR_OWI)
3626#define __cpm_stop_pcm() (REG_CPM_CLKGR |= CPM_CLKGR_PCM)
3627#define __cpm_stop_uart3() (REG_CPM_CLKGR |= CPM_CLKGR_UART3)
3628#define __cpm_stop_uart2() (REG_CPM_CLKGR |= CPM_CLKGR_UART2)
3629#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
3630#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
3631#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
3632#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
3633#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
3634#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
3635#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
3636#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
3637#define __cpm_stop_msc(n) (REG_CPM_CLKGR |= CPM_CLKGR_MSC##n)
3638#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
3639#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
3640#define __cpm_stop_ssi(n) (REG_CPM_CLKGR |= CPM_CLKGR_SSI##n)
3641#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
3642#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
3643#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
3644#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
3645
3646#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
3647#define __cpm_start_cimram() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIMRAM)
3648#define __cpm_start_idct() (REG_CPM_CLKGR &= ~CPM_CLKGR_IDCT)
3649#define __cpm_start_db() (REG_CPM_CLKGR &= ~CPM_CLKGR_DB)
3650#define __cpm_start_me() (REG_CPM_CLKGR &= ~CPM_CLKGR_ME)
3651#define __cpm_start_mc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MC)
3652#define __cpm_start_tve() (REG_CPM_CLKGR &= ~CPM_CLKGR_TVE)
3653#define __cpm_start_tssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_TSSI)
3654#define __cpm_start_owi() (REG_CPM_CLKGR &= ~CPM_CLKGR_OWI)
3655#define __cpm_start_pcm() (REG_CPM_CLKGR &= ~CPM_CLKGR_PCM)
3656#define __cpm_start_uart3() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART3)
3657#define __cpm_start_uart2() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART2)
3658#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
3659#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
3660#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
3661#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
3662#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
3663#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
3664#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
3665#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
3666#define __cpm_start_msc(n) (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC##n)
3667#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
3668#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
3669#define __cpm_start_ssi(n) (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI##n)
3670#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
3671#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
3672#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
3673#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
3674
3675#define __cpm_get_o1st() \
3676    ((REG_CPM_OPCR & CPM_OPCR_O1ST_MASK) >> CPM_OPCR_O1ST_BIT)
3677#define __cpm_set_o1st(v) \
3678    (REG_CPM_OPCR = (REG_CPM_OPCR & ~CPM_OPCR_O1ST_MASK) | ((v) << (CPM_OPCR_O1ST_BIT)))
3679#define __cpm_suspend_uhcphy() (REG_CPM_OPCR |= CPM_OPCR_UHCPHY_SUSPEND)
3680#define __cpm_suspend_udcphy() (REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE)
3681#define __cpm_enable_osc_in_sleep() (REG_CPM_OPCR |= CPM_OPCR_OSC_ENABLE)
3682#define __cpm_select_rtcclk_rtc() (REG_CPM_OPCR |= CPM_OPCR_ERCS)
3683#define __cpm_select_rtcclk_exclk() (REG_CPM_OPCR &= ~CPM_OPCR_ERCS)
3684
3685
3686#ifdef CFG_EXTAL
3687#define JZ_EXTAL CFG_EXTAL
3688#else
3689#define JZ_EXTAL 3686400
3690#endif
3691#define JZ_EXTAL2 32768 /* RTC clock */
3692
3693/* PLL output frequency */
3694static __inline__ unsigned int __cpm_get_pllout(void)
3695{
3696    unsigned long m, n, no, pllout;
3697    unsigned long cppcr = REG_CPM_CPPCR;
3698    unsigned long od[4] = {1, 2, 2, 4};
3699    if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
3700        m = __cpm_get_pllm() + 2;
3701        n = __cpm_get_plln() + 2;
3702        no = od[__cpm_get_pllod()];
3703        pllout = ((JZ_EXTAL) / (n * no)) * m;
3704    } else
3705        pllout = JZ_EXTAL;
3706    return pllout;
3707}
3708
3709/* PLL output frequency for MSC/I2S/LCD/USB */
3710static __inline__ unsigned int __cpm_get_pllout2(void)
3711{
3712    if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
3713        return __cpm_get_pllout();
3714    else
3715        return __cpm_get_pllout()/2;
3716}
3717
3718/* CPU core clock */
3719static __inline__ unsigned int __cpm_get_cclk(void)
3720{
3721    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3722
3723    return __cpm_get_pllout() / div[__cpm_get_cdiv()];
3724}
3725
3726/* AHB system bus clock */
3727static __inline__ unsigned int __cpm_get_hclk(void)
3728{
3729    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3730
3731    return __cpm_get_pllout() / div[__cpm_get_hdiv()];
3732}
3733
3734/* Memory bus clock */
3735static __inline__ unsigned int __cpm_get_mclk(void)
3736{
3737    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3738
3739    return __cpm_get_pllout() / div[__cpm_get_mdiv()];
3740}
3741
3742/* APB peripheral bus clock */
3743static __inline__ unsigned int __cpm_get_pclk(void)
3744{
3745    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3746
3747    return __cpm_get_pllout() / div[__cpm_get_pdiv()];
3748}
3749
3750/* LCDC module clock */
3751static __inline__ unsigned int __cpm_get_lcdclk(void)
3752{
3753    return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
3754}
3755
3756/* LCD pixel clock */
3757static __inline__ unsigned int __cpm_get_pixclk(void)
3758{
3759    return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
3760}
3761
3762/* I2S clock */
3763static __inline__ unsigned int __cpm_get_i2sclk(void)
3764{
3765    if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
3766        return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
3767    }
3768    else {
3769        return JZ_EXTAL;
3770    }
3771}
3772
3773/* USB clock */
3774static __inline__ unsigned int __cpm_get_usbclk(void)
3775{
3776    if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
3777        return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
3778    }
3779    else {
3780        return JZ_EXTAL;
3781    }
3782}
3783
3784/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
3785static __inline__ unsigned int __cpm_get_extalclk(void)
3786{
3787    return JZ_EXTAL;
3788}
3789
3790/* RTC clock for CPM,INTC,RTC,TCU,WDT */
3791static __inline__ unsigned int __cpm_get_rtcclk(void)
3792{
3793    return JZ_EXTAL2;
3794}
3795
3796/***************************************************************************
3797 * TCU
3798 ***************************************************************************/
3799// where 'n' is the TCU channel
3800#define __tcu_select_extalclk(n) \
3801    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
3802#define __tcu_select_rtcclk(n) \
3803    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
3804#define __tcu_select_pclk(n) \
3805    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
3806
3807#define __tcu_select_clk_div1(n) \
3808    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
3809#define __tcu_select_clk_div4(n) \
3810    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
3811#define __tcu_select_clk_div16(n) \
3812    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
3813#define __tcu_select_clk_div64(n) \
3814    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
3815#define __tcu_select_clk_div256(n) \
3816    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
3817#define __tcu_select_clk_div1024(n) \
3818    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
3819
3820#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
3821#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
3822
3823#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
3824#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
3825
3826#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
3827#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
3828
3829#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
3830#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
3831
3832#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
3833#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
3834#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
3835#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
3836#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
3837#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
3838#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
3839#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
3840#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
3841#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
3842
3843#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
3844#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
3845
3846#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
3847#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
3848
3849#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
3850#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
3851
3852#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
3853#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
3854#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
3855#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
3856
3857
3858/***************************************************************************
3859 * WDT
3860 ***************************************************************************/
3861#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
3862#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
3863#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
3864#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
3865
3866#define __wdt_select_extalclk() \
3867    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
3868#define __wdt_select_rtcclk() \
3869    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
3870#define __wdt_select_pclk() \
3871    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
3872
3873#define __wdt_select_clk_div1() \
3874    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
3875#define __wdt_select_clk_div4() \
3876    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
3877#define __wdt_select_clk_div16() \
3878    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
3879#define __wdt_select_clk_div64() \
3880    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
3881#define __wdt_select_clk_div256() \
3882    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
3883#define __wdt_select_clk_div1024() \
3884    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
3885
3886
3887/***************************************************************************
3888 * UART
3889 ***************************************************************************/
3890
3891#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
3892#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
3893
3894#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
3895#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
3896
3897#define __uart_enable_receive_irq() \
3898  ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
3899#define __uart_disable_receive_irq() \
3900  ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
3901
3902#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
3903#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
3904
3905#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
3906
3907#define __uart_set_baud(devclk, baud) \
3908  do { \
3909    REG8(UART0_LCR) |= UARTLCR_DLAB; \
3910    REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
3911    REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
3912    REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
3913  } while (0)
3914
3915#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
3916#define __uart_clear_errors() \
3917  ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
3918
3919#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
3920#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
3921#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
3922#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3923#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3924#define __uart_receive_char() REG8(UART0_RDR)
3925#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
3926#define __uart_enable_irda() \
3927  /* Tx high pulse as 0, Rx low pulse as 0 */ \
3928  ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
3929
3930
3931/***************************************************************************
3932 * DMAC
3933 ***************************************************************************/
3934
3935/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
3936
3937#define __dmac_enable_module(m) \
3938    ( REG_DMAC_DMACR(m) |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_012345 )
3939#define __dmac_disable_module(m) \
3940    ( REG_DMAC_DMACR(m) &= ~DMAC_DMACR_DMAE )
3941
3942/* p=0,1,2,3 */
3943#define __dmac_set_priority(m,p) \
3944do { \
3945    REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK; \
3946    REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT); \
3947} while (0)
3948
3949#define __dmac_test_halt_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_HLT )
3950#define __dmac_test_addr_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_AR )
3951
3952#define __dmac_enable_descriptor(n) \
3953  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
3954#define __dmac_disable_descriptor(n) \
3955  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
3956
3957#define __dmac_enable_channel(n) \
3958  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
3959#define __dmac_disable_channel(n) \
3960  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
3961#define __dmac_channel_enabled(n) \
3962  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
3963
3964#define __dmac_channel_enable_irq(n) \
3965  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
3966#define __dmac_channel_disable_irq(n) \
3967  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
3968
3969#define __dmac_channel_transmit_halt_detected(n) \
3970  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
3971#define __dmac_channel_transmit_end_detected(n) \
3972  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
3973#define __dmac_channel_address_error_detected(n) \
3974  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
3975#define __dmac_channel_count_terminated_detected(n) \
3976  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
3977#define __dmac_channel_descriptor_invalid_detected(n) \
3978  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
3979
3980#define __dmac_channel_clear_transmit_halt(n) \
3981  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
3982#define __dmac_channel_clear_transmit_end(n) \
3983  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
3984#define __dmac_channel_clear_address_error(n) \
3985  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
3986#define __dmac_channel_clear_count_terminated(n) \
3987  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
3988#define __dmac_channel_clear_descriptor_invalid(n) \
3989  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
3990
3991#define __dmac_channel_set_transfer_unit_32bit(n) \
3992do { \
3993    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3994    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
3995} while (0)
3996
3997#define __dmac_channel_set_transfer_unit_16bit(n) \
3998do { \
3999    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
4000    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
4001} while (0)
4002
4003#define __dmac_channel_set_transfer_unit_8bit(n) \
4004do { \
4005    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
4006    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
4007} while (0)
4008
4009#define __dmac_channel_set_transfer_unit_16byte(n) \
4010do { \
4011    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
4012    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
4013} while (0)
4014
4015#define __dmac_channel_set_transfer_unit_32byte(n) \
4016do { \
4017    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
4018    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
4019} while (0)
4020
4021/* w=8,16,32 */
4022#define __dmac_channel_set_dest_port_width(n,w) \
4023do { \
4024    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
4025    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
4026} while (0)
4027
4028/* w=8,16,32 */
4029#define __dmac_channel_set_src_port_width(n,w) \
4030do { \
4031    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
4032    REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
4033} while (0)
4034
4035/* v=0-15 */
4036#define __dmac_channel_set_rdil(n,v) \
4037do { \
4038    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
4039    REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
4040} while (0)
4041
4042#define __dmac_channel_dest_addr_fixed(n) \
4043  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
4044#define __dmac_channel_dest_addr_increment(n) \
4045  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
4046
4047#define __dmac_channel_src_addr_fixed(n) \
4048  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
4049#define __dmac_channel_src_addr_increment(n) \
4050  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
4051
4052#define __dmac_channel_set_doorbell(m,n) \
4053    ( REG_DMAC_DMADBSR(m) = (1 << (n)) )
4054
4055#define __dmac_channel_irq_detected(m,n) ( REG_DMAC_DMAIPR(m) & (1 << (n)) )
4056#define __dmac_channel_ack_irq(m,n) ( REG_DMAC_DMAIPR(m) &= ~(1 << (n)) )
4057
4058static __inline__ int __dmac_get_irq(void)
4059{
4060    int i;
4061    for (i = 0; i < MAX_DMA_NUM; i++)
4062        if (__dmac_channel_irq_detected(i/HALF_DMA_NUM, i-i/HALF_DMA_NUM*HALF_DMA_NUM))
4063            return i;
4064    return -1;
4065}
4066
4067
4068/***************************************************************************
4069 * AIC (AC'97 & I2S Controller)
4070 ***************************************************************************/
4071
4072#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
4073#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
4074
4075#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
4076#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
4077
4078#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
4079#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
4080#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
4081
4082#define __aic_reset() \
4083do { \
4084        REG_AIC_FR |= AIC_FR_RST; \
4085} while(0)
4086
4087
4088#define __aic_set_transmit_trigger(n) \
4089do { \
4090    REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
4091    REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
4092} while(0)
4093
4094#define __aic_set_receive_trigger(n) \
4095do { \
4096    REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
4097    REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
4098} while(0)
4099
4100#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
4101#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
4102#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
4103#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
4104#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
4105#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
4106
4107#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
4108#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
4109
4110#define __aic_enable_transmit_intr() \
4111  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
4112#define __aic_disable_transmit_intr() \
4113  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
4114#define __aic_enable_receive_intr() \
4115  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
4116#define __aic_disable_receive_intr() \
4117  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
4118
4119#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
4120#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
4121#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
4122#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
4123
4124#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
4125#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
4126#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
4127#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
4128#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
4129#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
4130
4131#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
4132#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
4133#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
4134#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
4135#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
4136#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
4137
4138#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
4139#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
4140#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
4141#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
4142#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
4143#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
4144
4145#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
4146#define __ac97_set_xs_mono() \
4147do { \
4148    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
4149    REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
4150} while(0)
4151#define __ac97_set_xs_stereo() \
4152do { \
4153    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
4154    REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
4155} while(0)
4156
4157/* In fact, only stereo is support now. */
4158#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
4159#define __ac97_set_rs_mono() \
4160do { \
4161    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
4162    REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
4163} while(0)
4164#define __ac97_set_rs_stereo() \
4165do { \
4166    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
4167    REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
4168} while(0)
4169
4170#define __ac97_warm_reset_codec() \
4171 do { \
4172    REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
4173    REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
4174    udelay(2); \
4175    REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
4176    REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
4177 } while (0)
4178
4179#define __ac97_cold_reset_codec() \
4180 do { \
4181    REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
4182    udelay(2); \
4183    REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
4184 } while (0)
4185
4186/* n=8,16,18,20 */
4187#define __ac97_set_iass(n) \
4188 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
4189#define __ac97_set_oass(n) \
4190 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
4191
4192#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
4193#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
4194
4195/* n=8,16,18,20,24 */
4196/*#define __i2s_set_sample_size(n) \
4197 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
4198
4199#define __i2s_set_oss_sample_size(n) \
4200 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
4201#define __i2s_set_iss_sample_size(n) \
4202 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
4203
4204#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
4205#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
4206
4207#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
4208#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
4209#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
4210#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
4211
4212#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
4213
4214#define __aic_get_transmit_resident() \
4215  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
4216#define __aic_get_receive_count() \
4217  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
4218
4219#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
4220#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
4221#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
4222#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
4223#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
4224#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
4225#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
4226
4227#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
4228
4229#define CODEC_READ_CMD (1 << 19)
4230#define CODEC_WRITE_CMD (0 << 19)
4231#define CODEC_REG_INDEX_BIT 12
4232#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
4233#define CODEC_REG_DATA_BIT 4
4234#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
4235
4236#define __ac97_out_rcmd_addr(reg) \
4237do { \
4238    REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
4239} while (0)
4240
4241#define __ac97_out_wcmd_addr(reg) \
4242do { \
4243    REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
4244} while (0)
4245
4246#define __ac97_out_data(value) \
4247do { \
4248    REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
4249} while (0)
4250
4251#define __ac97_in_data() \
4252 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
4253
4254#define __ac97_in_status_addr() \
4255 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
4256
4257#define __i2s_set_sample_rate(i2sclk, sync) \
4258  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
4259
4260#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
4261#define __aic_read_rfifo() ( REG_AIC_DR )
4262
4263#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
4264#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
4265
4266//
4267// Define next ops for AC97 compatible
4268//
4269
4270#define AC97_ACSR AIC_ACSR
4271
4272#define __ac97_enable() __aic_enable(); __aic_select_ac97()
4273#define __ac97_disable() __aic_disable()
4274#define __ac97_reset() __aic_reset()
4275
4276#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
4277#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
4278
4279#define __ac97_enable_record() __aic_enable_record()
4280#define __ac97_disable_record() __aic_disable_record()
4281#define __ac97_enable_replay() __aic_enable_replay()
4282#define __ac97_disable_replay() __aic_disable_replay()
4283#define __ac97_enable_loopback() __aic_enable_loopback()
4284#define __ac97_disable_loopback() __aic_disable_loopback()
4285
4286#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
4287#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
4288#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
4289#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
4290
4291#define __ac97_transmit_request() __aic_transmit_request()
4292#define __ac97_receive_request() __aic_receive_request()
4293#define __ac97_transmit_underrun() __aic_transmit_underrun()
4294#define __ac97_receive_overrun() __aic_receive_overrun()
4295
4296#define __ac97_clear_errors() __aic_clear_errors()
4297
4298#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
4299#define __ac97_get_receive_count() __aic_get_receive_count()
4300
4301#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
4302#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
4303#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
4304#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
4305
4306#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
4307#define __ac97_read_rfifo() __aic_read_rfifo()
4308
4309//
4310// Define next ops for I2S compatible
4311//
4312
4313#define I2S_ACSR AIC_I2SSR
4314
4315#define __i2s_enable() __aic_enable(); __aic_select_i2s()
4316#define __i2s_disable() __aic_disable()
4317#define __i2s_reset() __aic_reset()
4318
4319#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
4320#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
4321
4322#define __i2s_enable_record() __aic_enable_record()
4323#define __i2s_disable_record() __aic_disable_record()
4324#define __i2s_enable_replay() __aic_enable_replay()
4325#define __i2s_disable_replay() __aic_disable_replay()
4326#define __i2s_enable_loopback() __aic_enable_loopback()
4327#define __i2s_disable_loopback() __aic_disable_loopback()
4328
4329#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
4330#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
4331#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
4332#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
4333
4334#define __i2s_transmit_request() __aic_transmit_request()
4335#define __i2s_receive_request() __aic_receive_request()
4336#define __i2s_transmit_underrun() __aic_transmit_underrun()
4337#define __i2s_receive_overrun() __aic_receive_overrun()
4338
4339#define __i2s_clear_errors() __aic_clear_errors()
4340
4341#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
4342#define __i2s_get_receive_count() __aic_get_receive_count()
4343
4344#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
4345#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
4346#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
4347#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
4348
4349#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
4350#define __i2s_read_rfifo() __aic_read_rfifo()
4351
4352#define __i2s_reset_codec() \
4353 do { \
4354 } while (0)
4355
4356
4357/***************************************************************************
4358 * ICDC
4359 ***************************************************************************/
4360#define __i2s_internal_codec() __aic_internal_codec()
4361#define __i2s_external_codec() __aic_external_codec()
4362
4363/***************************************************************************
4364 * INTC
4365 ***************************************************************************/
4366#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
4367#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
4368#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
4369
4370
4371/***************************************************************************
4372 * I2C
4373 ***************************************************************************/
4374
4375#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
4376#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
4377
4378#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
4379#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
4380#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
4381#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
4382
4383#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
4384#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
4385#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
4386
4387#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
4388#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
4389#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
4390
4391#define __i2c_set_clk(dev_clk, i2c_clk) \
4392  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
4393
4394#define __i2c_read() ( REG_I2C_DR )
4395#define __i2c_write(val) ( REG_I2C_DR = (val) )
4396
4397
4398/***************************************************************************
4399 * MSC
4400 ***************************************************************************/
4401
4402#define __msc_start_op() \
4403  ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
4404
4405#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
4406#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
4407#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
4408#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
4409#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
4410#define __msc_get_nob() ( REG_MSC_NOB )
4411#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
4412#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
4413#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
4414#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
4415
4416#define __msc_set_cmdat_bus_width1() \
4417do { \
4418    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4419    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
4420} while(0)
4421
4422#define __msc_set_cmdat_bus_width4() \
4423do { \
4424    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4425    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
4426} while(0)
4427
4428#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
4429#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
4430#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
4431#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
4432#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
4433#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
4434#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
4435#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
4436
4437/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
4438#define __msc_set_cmdat_res_format(r) \
4439do { \
4440    REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
4441    REG_MSC_CMDAT |= (r); \
4442} while(0)
4443
4444#define __msc_clear_cmdat() \
4445  REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
4446  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
4447  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
4448
4449#define __msc_get_imask() ( REG_MSC_IMASK )
4450#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
4451#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
4452#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
4453#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
4454#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
4455#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
4456#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
4457#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
4458#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
4459#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
4460#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
4461#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
4462
4463/* n=0,1,2,3,4,5,6,7 */
4464#define __msc_set_clkrt(n) \
4465do { \
4466    REG_MSC_CLKRT = n; \
4467} while(0)
4468
4469#define __msc_get_ireg() ( REG_MSC_IREG )
4470#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
4471#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
4472#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
4473#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
4474#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
4475#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
4476#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
4477#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
4478
4479#define __msc_get_stat() ( REG_MSC_STAT )
4480#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
4481#define __msc_stat_crc_err() \
4482  ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
4483#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
4484#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
4485#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
4486#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
4487#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
4488
4489#define __msc_rd_resfifo() ( REG_MSC_RES )
4490#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
4491#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
4492
4493#define __msc_reset() \
4494do { \
4495    REG_MSC_STRPCL = MSC_STRPCL_RESET; \
4496     while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
4497} while (0)
4498
4499#define __msc_start_clk() \
4500do { \
4501    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
4502} while (0)
4503
4504#define __msc_stop_clk() \
4505do { \
4506    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
4507} while (0)
4508
4509#define MMC_CLK 19169200
4510#define SD_CLK 24576000
4511
4512/* msc_clk should little than pclk and little than clk retrieve from card */
4513#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
4514do { \
4515    unsigned int rate, pclk, i; \
4516    pclk = dev_clk; \
4517    rate = type?SD_CLK:MMC_CLK; \
4518      if (msc_clk && msc_clk < pclk) \
4519            pclk = msc_clk; \
4520    i = 0; \
4521      while (pclk < rate) \
4522        { \
4523              i ++; \
4524              rate >>= 1; \
4525        } \
4526      lv = i; \
4527} while(0)
4528
4529/* divide rate to little than or equal to 400kHz */
4530#define __msc_calc_slow_clk_divisor(type, lv) \
4531do { \
4532    unsigned int rate, i; \
4533    rate = (type?SD_CLK:MMC_CLK)/1000/400; \
4534    i = 0; \
4535    while (rate > 0) \
4536        { \
4537              rate >>= 1; \
4538              i ++; \
4539        } \
4540      lv = i; \
4541} while(0)
4542
4543
4544/***************************************************************************
4545 * SSI (Synchronous Serial Interface)
4546 ***************************************************************************/
4547/* n = 0, 1 (SSI0, SSI1) */
4548#define __ssi_enable(n) ( REG_SSI_CR0(n) |= SSI_CR0_SSIE )
4549#define __ssi_disable(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_SSIE )
4550#define __ssi_select_ce(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_FSEL )
4551
4552#define __ssi_normal_mode(n) ( REG_SSI_ITR(n) &= ~SSI_ITR_IVLTM_MASK )
4553
4554#define __ssi_select_ce2(n) \
4555do { \
4556    REG_SSI_CR0(n) |= SSI_CR0_FSEL; \
4557    REG_SSI_CR1(n) &= ~SSI_CR1_MULTS; \
4558} while (0)
4559
4560#define __ssi_select_gpc(n) \
4561do { \
4562    REG_SSI_CR0(n) &= ~SSI_CR0_FSEL; \
4563    REG_SSI_CR1(n) |= SSI_CR1_MULTS; \
4564} while (0)
4565
4566#define __ssi_underrun_auto_clear(n) \
4567do { \
4568    REG_SSI_CR0(n) |= SSI_CR0_EACLRUN; \
4569} while (0)
4570
4571#define __ssi_underrun_clear_manually(n) \
4572do { \
4573    REG_SSI_CR0(n) &= ~SSI_CR0_EACLRUN; \
4574} while (0)
4575
4576#define __ssi_enable_tx_intr(n) \
4577    ( REG_SSI_CR0(n) |= SSI_CR0_TIE | SSI_CR0_TEIE )
4578
4579#define __ssi_disable_tx_intr(n) \
4580    ( REG_SSI_CR0(n) &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
4581
4582#define __ssi_enable_rx_intr(n) \
4583    ( REG_SSI_CR0(n) |= SSI_CR0_RIE | SSI_CR0_REIE )
4584
4585#define __ssi_disable_rx_intr(n) \
4586    ( REG_SSI_CR0(n) &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
4587
4588#define __ssi_enable_txfifo_half_empty_intr(n) \
4589    ( REG_SSI_CR0(n) |= SSI_CR0_TIE )
4590#define __ssi_disable_txfifo_half_empty_intr(n) \
4591    ( REG_SSI_CR0(n) &= ~SSI_CR0_TIE )
4592#define __ssi_enable_tx_error_intr(n) \
4593    ( REG_SSI_CR0(n) |= SSI_CR0_TEIE )
4594#define __ssi_disable_tx_error_intr(n) \
4595    ( REG_SSI_CR0(n) &= ~SSI_CR0_TEIE )
4596#define __ssi_enable_rxfifo_half_full_intr(n) \
4597    ( REG_SSI_CR0(n) |= SSI_CR0_RIE )
4598#define __ssi_disable_rxfifo_half_full_intr(n) \
4599    ( REG_SSI_CR0(n) &= ~SSI_CR0_RIE )
4600#define __ssi_enable_rx_error_intr(n) \
4601    ( REG_SSI_CR0(n) |= SSI_CR0_REIE )
4602#define __ssi_disable_rx_error_intr(n) \
4603    ( REG_SSI_CR0(n) &= ~SSI_CR0_REIE )
4604
4605#define __ssi_enable_loopback(n) ( REG_SSI_CR0(n) |= SSI_CR0_LOOP )
4606#define __ssi_disable_loopback(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_LOOP )
4607
4608#define __ssi_enable_receive(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_DISREV )
4609#define __ssi_disable_receive(n) ( REG_SSI_CR0(n) |= SSI_CR0_DISREV )
4610
4611#define __ssi_finish_receive(n) \
4612    ( REG_SSI_CR0(n) |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
4613
4614#define __ssi_disable_recvfinish(n) \
4615    ( REG_SSI_CR0(n) &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
4616
4617#define __ssi_flush_txfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH )
4618#define __ssi_flush_rxfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_RFLUSH )
4619
4620#define __ssi_flush_fifo(n) \
4621    ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
4622
4623#define __ssi_finish_transmit(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_UNFIN )
4624#define __ssi_wait_transmit(n) ( REG_SSI_CR1(n) |= SSI_CR1_UNFIN )
4625#define __ssi_use_busy_wait_mode(n) __ssi_wait_transmit(n)
4626#define __ssi_unset_busy_wait_mode(n) __ssi_finish_transmit(n)
4627
4628#define __ssi_spi_format(n) \
4629    do { \
4630        REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \
4631        REG_SSI_CR1(n) |= SSI_CR1_FMAT_SPI; \
4632        REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
4633        REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
4634    } while (0)
4635
4636/* TI's SSP format, must clear SSI_CR1.UNFIN */
4637#define __ssi_ssp_format(n) \
4638    do { \
4639        REG_SSI_CR1(n) &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
4640        REG_SSI_CR1(n) |= SSI_CR1_FMAT_SSP; \
4641    } while (0)
4642
4643/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
4644#define __ssi_microwire_format(n) \
4645    do { \
4646        REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \
4647        REG_SSI_CR1(n) |= SSI_CR1_FMAT_MW1; \
4648        REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
4649        REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
4650        REG_SSI_CR0(n) &= ~SSI_CR0_RFINE; \
4651    } while (0)
4652
4653/* CE# level (FRMHL), CE# in interval time (ITFRM),
4654   clock phase and polarity (PHA POL),
4655   interval time (SSIITR), interval characters/frame (SSIICR) */
4656
4657/* frmhl,endian,mcom,flen,pha,pol MASK */
4658#define SSICR1_MISC_MASK \
4659    ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
4660      | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )
4661
4662#define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol) \
4663    do { \
4664        REG_SSI_CR1(n) &= ~SSICR1_MISC_MASK; \
4665        REG_SSI_CR1(n) |= ((frmhl) << 30) | ((endian) << 25) | \
4666            (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
4667            ((pha) << 1) | (pol); \
4668    } while(0)
4669
4670/* Transfer with MSB or LSB first */
4671#define __ssi_set_msb(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_LFST )
4672#define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST )
4673
4674#define __ssi_set_frame_length(n, m) \
4675    REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4)
4676
4677/* m = 1 - 16 */
4678#define __ssi_set_microwire_command_length(n,m) \
4679    ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##m##BIT) )
4680
4681/* Set the clock phase for SPI */
4682#define __ssi_set_spi_clock_phase(n, m) \
4683    ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_PHA) | (((m)&0x1)<< 1)))
4684
4685/* Set the clock polarity for SPI */
4686#define __ssi_set_spi_clock_polarity(n, p) \
4687    ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_POL) | ((p)&0x1)) )
4688
4689/* SSI tx trigger, m = i x 8 */
4690#define __ssi_set_tx_trigger(n, m) \
4691    do { \
4692        REG_SSI_CR1(n) &= ~SSI_CR1_TTRG_MASK; \
4693        REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_TTRG_BIT; \
4694    } while (0)
4695
4696/* SSI rx trigger, m = i x 8 */
4697#define __ssi_set_rx_trigger(n, m) \
4698    do { \
4699        REG_SSI_CR1(n) &= ~SSI_CR1_RTRG_MASK; \
4700        REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_RTRG_BIT; \
4701    } while (0)
4702
4703#define __ssi_get_txfifo_count(n) \
4704    ( (REG_SSI_SR(n) & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
4705
4706#define __ssi_get_rxfifo_count(n) \
4707    ( (REG_SSI_SR(n) & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
4708
4709#define __ssi_transfer_end(n) ( REG_SSI_SR(n) & SSI_SR_END )
4710#define __ssi_is_busy(n) ( REG_SSI_SR(n) & SSI_SR_BUSY )
4711
4712#define __ssi_txfifo_full(n) ( REG_SSI_SR(n) & SSI_SR_TFF )
4713#define __ssi_rxfifo_empty(n) ( REG_SSI_SR(n) & SSI_SR_RFE )
4714#define __ssi_rxfifo_half_full(n) ( REG_SSI_SR(n) & SSI_SR_RFHF )
4715#define __ssi_txfifo_half_empty(n) ( REG_SSI_SR(n) & SSI_SR_TFHE )
4716#define __ssi_underrun(n) ( REG_SSI_SR(n) & SSI_SR_UNDR )
4717#define __ssi_overrun(n) ( REG_SSI_SR(n) & SSI_SR_OVER )
4718#define __ssi_clear_underrun(n) ( REG_SSI_SR(n) = ~SSI_SR_UNDR )
4719#define __ssi_clear_overrun(n) ( REG_SSI_SR(n) = ~SSI_SR_OVER )
4720#define __ssi_clear_errors(n) ( REG_SSI_SR(n) &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
4721
4722#define __ssi_set_clk(n, dev_clk, ssi_clk) \
4723    ( REG_SSI_GR(n) = (dev_clk) / (2*(ssi_clk)) - 1 )
4724
4725#define __ssi_receive_data(n) REG_SSI_DR(n)
4726#define __ssi_transmit_data(n, v) (REG_SSI_DR(n) = (v))
4727
4728
4729/***************************************************************************
4730 * CIM
4731 ***************************************************************************/
4732
4733#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
4734#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
4735
4736#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
4737#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
4738
4739#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
4740#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
4741
4742#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
4743#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
4744
4745#define __cim_sample_data_at_pclk_falling_edge() \
4746  ( REG_CIM_CFG |= CIM_CFG_PCP )
4747#define __cim_sample_data_at_pclk_rising_edge() \
4748  ( REG_CIM_CFG &= ~CIM_CFG_PCP )
4749
4750#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
4751#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
4752
4753#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
4754#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
4755
4756/* n=0-7 */
4757#define __cim_set_data_packing_mode(n) \
4758do { \
4759    REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
4760    REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
4761} while (0)
4762
4763#define __cim_enable_ccir656_progressive_mode() \
4764do { \
4765    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4766    REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
4767} while (0)
4768
4769#define __cim_enable_ccir656_interlace_mode() \
4770do { \
4771    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4772    REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
4773} while (0)
4774
4775#define __cim_enable_gated_clock_mode() \
4776do { \
4777    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4778    REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
4779} while (0)
4780
4781#define __cim_enable_nongated_clock_mode() \
4782do { \
4783    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4784    REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
4785} while (0)
4786
4787/* sclk:system bus clock
4788 * mclk: CIM master clock
4789 */
4790#define __cim_set_master_clk(sclk, mclk) \
4791do { \
4792    REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
4793    REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
4794} while (0)
4795
4796#define __cim_enable_sof_intr() \
4797  ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
4798#define __cim_disable_sof_intr() \
4799  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
4800
4801#define __cim_enable_eof_intr() \
4802  ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
4803#define __cim_disable_eof_intr() \
4804  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
4805
4806#define __cim_enable_stop_intr() \
4807  ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
4808#define __cim_disable_stop_intr() \
4809  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
4810
4811#define __cim_enable_trig_intr() \
4812  ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
4813#define __cim_disable_trig_intr() \
4814  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
4815
4816#define __cim_enable_rxfifo_overflow_intr() \
4817  ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
4818#define __cim_disable_rxfifo_overflow_intr() \
4819  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
4820
4821/* n=1-16 */
4822#define __cim_set_frame_rate(n) \
4823do { \
4824    REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
4825    REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
4826} while (0)
4827
4828#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
4829#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
4830
4831#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
4832#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
4833
4834/* n=4,8,12,16,20,24,28,32 */
4835#define __cim_set_rxfifo_trigger(n) \
4836do { \
4837    REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
4838    REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
4839} while (0)
4840
4841#define __cim_clear_state() ( REG_CIM_STATE = 0 )
4842
4843#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
4844#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
4845#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
4846#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
4847#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
4848#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
4849#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
4850#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
4851
4852#define __cim_get_iid() ( REG_CIM_IID )
4853#define __cim_get_image_data() ( REG_CIM_RXFIFO )
4854#define __cim_get_dam_cmd() ( REG_CIM_CMD )
4855
4856#define __cim_set_da(a) ( REG_CIM_DA = (a) )
4857
4858/***************************************************************************
4859 * LCD
4860 ***************************************************************************/
4861#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
4862#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
4863
4864#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
4865#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
4866
4867#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
4868#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
4869
4870/* n=1,2,4,8,16 */
4871#define __lcd_set_bpp(n) \
4872  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
4873
4874/* n=4,8,16 */
4875#define __lcd_set_burst_length(n) \
4876do { \
4877    REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
4878    REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
4879} while (0)
4880
4881#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
4882#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
4883
4884#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
4885#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
4886
4887/* n=2,4,16 */
4888#define __lcd_set_stn_frc(n) \
4889do { \
4890    REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
4891    REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
4892} while (0)
4893
4894
4895#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
4896#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
4897
4898#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
4899#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
4900
4901#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
4902#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
4903
4904#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
4905#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
4906
4907#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
4908#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
4909
4910#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
4911#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
4912
4913#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
4914#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
4915
4916#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
4917#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
4918
4919#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
4920#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
4921
4922
4923/* LCD status register indication */
4924
4925#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
4926#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
4927#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
4928#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
4929#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
4930#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
4931#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
4932
4933#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
4934#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
4935#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
4936
4937#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
4938#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
4939
4940/* n=1,2,4,8 for single mono-STN
4941 * n=4,8 for dual mono-STN
4942 */
4943#define __lcd_set_panel_datawidth(n) \
4944do { \
4945    REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
4946    REG_LCD_CFG |= LCD_CFG_PDW_n##; \
4947} while (0)
4948
4949/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
4950#define __lcd_set_panel_mode(m) \
4951do { \
4952    REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
4953    REG_LCD_CFG |= (m); \
4954} while(0)
4955
4956/* n = 0-255 */
4957#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
4958#define __lcd_set_ac_bias(n) \
4959do { \
4960    REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
4961    REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
4962} while(0)
4963
4964#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
4965#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
4966
4967#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
4968#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
4969
4970#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
4971#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
4972
4973#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
4974#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
4975
4976#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
4977#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
4978
4979#define __lcd_vsync_get_vps() \
4980  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
4981
4982#define __lcd_vsync_get_vpe() \
4983  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
4984#define __lcd_vsync_set_vpe(n) \
4985do { \
4986    REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
4987    REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
4988} while (0)
4989
4990#define __lcd_hsync_get_hps() \
4991  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
4992#define __lcd_hsync_set_hps(n) \
4993do { \
4994    REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
4995    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
4996} while (0)
4997
4998#define __lcd_hsync_get_hpe() \
4999  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
5000#define __lcd_hsync_set_hpe(n) \
5001do { \
5002    REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
5003    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
5004} while (0)
5005
5006#define __lcd_vat_get_ht() \
5007  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
5008#define __lcd_vat_set_ht(n) \
5009do { \
5010    REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
5011    REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
5012} while (0)
5013
5014#define __lcd_vat_get_vt() \
5015  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
5016#define __lcd_vat_set_vt(n) \
5017do { \
5018    REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
5019    REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
5020} while (0)
5021
5022#define __lcd_dah_get_hds() \
5023  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
5024#define __lcd_dah_set_hds(n) \
5025do { \
5026    REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
5027    REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
5028} while (0)
5029
5030#define __lcd_dah_get_hde() \
5031  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
5032#define __lcd_dah_set_hde(n) \
5033do { \
5034    REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
5035    REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
5036} while (0)
5037
5038#define __lcd_dav_get_vds() \
5039  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
5040#define __lcd_dav_set_vds(n) \
5041do { \
5042    REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
5043    REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
5044} while (0)
5045
5046#define __lcd_dav_get_vde() \
5047  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
5048#define __lcd_dav_set_vde(n) \
5049do { \
5050    REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
5051    REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
5052} while (0)
5053
5054#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
5055#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
5056#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
5057#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
5058
5059#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
5060#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
5061#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
5062#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
5063
5064#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
5065#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
5066
5067#define __lcd_cmd0_get_len() \
5068  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
5069#define __lcd_cmd1_get_len() \
5070  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
5071
5072/***************************************************************************
5073 * RTC ops
5074 ***************************************************************************/
5075
5076#define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY )
5077#define __rtc_enabled() \
5078do{ \
5079      while(!__rtc_write_ready()); \
5080      REG_RTC_RCR |= RTC_RCR_RTCE ; \
5081}while(0) \
5082
5083#define __rtc_disabled() \
5084do{ \
5085      while(!__rtc_write_ready()); \
5086      REG_RTC_RCR &= ~RTC_RCR_RTCE; \
5087}while(0)
5088#define __rtc_enable_alarm() \
5089do{ \
5090      while(!__rtc_write_ready()); \
5091      REG_RTC_RCR |= RTC_RCR_AE; \
5092}while(0)
5093
5094#define __rtc_disable_alarm() \
5095do{ \
5096      while(!__rtc_write_ready()); \
5097      REG_RTC_RCR &= ~RTC_RCR_AE; \
5098}while(0)
5099
5100#define __rtc_enable_alarm_irq() \
5101do{ \
5102      while(!__rtc_write_ready()); \
5103      REG_RTC_RCR |= RTC_RCR_AIE; \
5104}while(0)
5105
5106#define __rtc_disable_alarm_irq() \
5107do{ \
5108      while(!__rtc_write_ready()); \
5109      REG_RTC_RCR &= ~RTC_RCR_AIE; \
5110}while(0)
5111#define __rtc_enable_Hz_irq() \
5112do{ \
5113      while(!__rtc_write_ready()); \
5114      REG_RTC_RCR |= RTC_RCR_HZIE; \
5115}while(0)
5116
5117#define __rtc_disable_Hz_irq() \
5118do{ \
5119      while(!__rtc_write_ready()); \
5120      REG_RTC_RCR &= ~RTC_RCR_HZIE; \
5121}while(0)
5122#define __rtc_get_1Hz_flag() \
5123do{ \
5124      while(!__rtc_write_ready()); \
5125      ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
5126}while(0)
5127#define __rtc_clear_1Hz_flag() \
5128do{ \
5129      while(!__rtc_write_ready()); \
5130      REG_RTC_RCR &= ~RTC_RCR_HZ; \
5131}while(0)
5132#define __rtc_get_alarm_flag() \
5133do{ \
5134       while(!__rtc_write_ready()); \
5135      ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \
5136while(0)
5137#define __rtc_clear_alarm_flag() \
5138do{ \
5139      while(!__rtc_write_ready()); \
5140      REG_RTC_RCR &= ~RTC_RCR_AF; \
5141}while(0)
5142#define __rtc_get_second() \
5143do{ \
5144       while(!__rtc_write_ready());\
5145       REG_RTC_RSR; \
5146}while(0)
5147
5148#define __rtc_set_second(v) \
5149do{ \
5150      while(!__rtc_write_ready()); \
5151      REG_RTC_RSR = v; \
5152}while(0)
5153
5154#define __rtc_get_alarm_second() \
5155do{ \
5156      while(!__rtc_write_ready()); \
5157      REG_RTC_RSAR; \
5158}while(0)
5159
5160
5161#define __rtc_set_alarm_second(v) \
5162do{ \
5163      while(!__rtc_write_ready()); \
5164      REG_RTC_RSAR = v; \
5165}while(0)
5166
5167#define __rtc_RGR_is_locked() \
5168do{ \
5169      while(!__rtc_write_ready()); \
5170      REG_RTC_RGR >> RTC_RGR_LOCK; \
5171}while(0)
5172#define __rtc_lock_RGR() \
5173do{ \
5174      while(!__rtc_write_ready()); \
5175      REG_RTC_RGR |= RTC_RGR_LOCK; \
5176}while(0)
5177
5178#define __rtc_unlock_RGR() \
5179do{ \
5180      while(!__rtc_write_ready()); \
5181      REG_RTC_RGR &= ~RTC_RGR_LOCK; \
5182}while(0)
5183
5184#define __rtc_get_adjc_val() \
5185do{ \
5186      while(!__rtc_write_ready()); \
5187      ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
5188}while(0)
5189#define __rtc_set_adjc_val(v) \
5190do{ \
5191      while(!__rtc_write_ready()); \
5192      ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \
5193}while(0)
5194
5195#define __rtc_get_nc1Hz_val() \
5196      while(!__rtc_write_ready()); \
5197      ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
5198
5199#define __rtc_set_nc1Hz_val(v) \
5200do{ \
5201      while(!__rtc_write_ready()); \
5202      ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \
5203}while(0)
5204#define __rtc_power_down() \
5205do{ \
5206      while(!__rtc_write_ready()); \
5207      REG_RTC_HCR |= RTC_HCR_PD; \
5208}while(0)
5209
5210#define __rtc_get_hwfcr_val() \
5211do{ \
5212      while(!__rtc_write_ready()); \
5213      REG_RTC_HWFCR & RTC_HWFCR_MASK; \
5214}while(0)
5215#define __rtc_set_hwfcr_val(v) \
5216do{ \
5217      while(!__rtc_write_ready()); \
5218      REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \
5219}while(0)
5220
5221#define __rtc_get_hrcr_val() \
5222do{ \
5223      while(!__rtc_write_ready()); \
5224      ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
5225}while(0)
5226#define __rtc_set_hrcr_val(v) \
5227do{ \
5228      while(!__rtc_write_ready()); \
5229      ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \
5230}while(0)
5231
5232#define __rtc_enable_alarm_wakeup() \
5233do{ \
5234      while(!__rtc_write_ready()); \
5235      ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \
5236}while(0)
5237
5238#define __rtc_disable_alarm_wakeup() \
5239do{ \
5240      while(!__rtc_write_ready()); \
5241      ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \
5242}while(0)
5243
5244#define __rtc_status_hib_reset_occur() \
5245do{ \
5246      while(!__rtc_write_ready()); \
5247    ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \
5248}while(0)
5249#define __rtc_status_ppr_reset_occur() \
5250do{ \
5251      while(!__rtc_write_ready()); \
5252   ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \
5253}while(0)
5254#define __rtc_status_wakeup_pin_waken_up() \
5255do{ \
5256      while(!__rtc_write_ready()); \
5257   ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
5258}while(0)
5259#define __rtc_status_alarm_waken_up() \
5260do{ \
5261      while(!__rtc_write_ready()); \
5262  ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
5263}while(0)
5264#define __rtc_clear_hib_stat_all() \
5265do{ \
5266      while(!__rtc_write_ready()); \
5267      ( REG_RTC_HWRSR = 0 ); \
5268}while(0)
5269
5270#define __rtc_get_scratch_pattern() \
5271      while(!__rtc_write_ready()); \
5272          (REG_RTC_HSPR)
5273#define __rtc_set_scratch_pattern(n) \
5274do{ \
5275      while(!__rtc_write_ready()); \
5276      (REG_RTC_HSPR = n ); \
5277}while(0)
5278
5279/*************************************************************************
5280 * BCH
5281 *************************************************************************/
5282#define __ecc_encoding_4bit() \
5283do { \
5284    REG_BCH_CRS = BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
5285    REG_BCH_CRC = BCH_CR_BSEL8; \
5286} while(0)
5287#define __ecc_decoding_4bit() \
5288do { \
5289    REG_BCH_CRS = BCH_CR_BRST | BCH_CR_BCHE; \
5290    REG_BCH_CRC = BCH_CR_ENCE | BCH_CR_BSEL8; \
5291} while(0)
5292#define __ecc_encoding_8bit() \
5293do { \
5294    REG_BCH_CRS = BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BSEL8 | BCH_CR_BCHE; \
5295} while(0)
5296#define __ecc_decoding_8bit() \
5297do { \
5298    REG_BCH_CRS = BCH_CR_BRST | BCH_CR_BSEL8 | BCH_CR_BCHE; \
5299    REG_BCH_CRC = BCH_CR_ENCE; \
5300} while(0)
5301#define __ecc_dma_enable() ( REG_BCH_CRS = BCH_CR_DMAE )
5302#define __ecc_disable() ( REG_BCH_CRC = BCH_CR_BCHE )
5303#define __ecc_encode_sync() while (!(REG_BCH_INTS & BCH_INTS_ENCF))
5304#define __ecc_decode_sync() while (!(REG_BCH_INTS & BCH_INTS_DECF))
5305#define __ecc_cnt_dec(n) \
5306do { \
5307        REG_BCH_CNT &= ~(BCH_CNT_DEC_MASK << BCH_CNT_DEC_BIT); \
5308        REG_BCH_CNT = (n) << BCH_CNT_DEC_BIT; \
5309} while(0)
5310#define __ecc_cnt_enc(n) \
5311do { \
5312        REG_BCH_CNT &= ~(BCH_CNT_ENC_MASK << BCH_CNT_ENC_BIT); \
5313        REG_BCH_CNT = (n) << BCH_CNT_ENC_BIT; \
5314} while(0)
5315
5316#endif /* !__ASSEMBLY__ */
5317
5318#endif /* __JZ4750_H__ */
usbboot/xburst_include/target/jz4760.h
1/*
2 * Include file for Ingenic Semiconductor's JZ4760 CPU.
3 */
4#ifndef __JZ4760_H__
5#define __JZ4760_H__
6
7#include "target/xburst_types.h"
8
9#if 0 /* if 0, for spl program */
10#define UCOS_CSP 0
11
12#if UCOS_CSP
13#define __KERNEL__
14#include <bsp.h>
15#include <types.h>
16
17#include <sysdefs.h>
18#include <cacheops.h>
19#define KSEG0 KSEG0BASE
20#else
21#include <asm/addrspace.h>
22#include <asm/cacheops.h>
23#endif
24
25#define cache_unroll(base,op) \
26    __asm__ __volatile__(" \
27        .set noreorder; \
28        .set mips3; \
29        cache %1, (%0); \
30        .set mips0; \
31        .set reorder" \
32        : \
33        : "r" (base), \
34          "i" (op));
35
36static inline void jz_flush_dcache(void)
37{
38    unsigned long start;
39    unsigned long end;
40
41    start = KSEG0;
42    end = start + CFG_DCACHE_SIZE;
43    while (start < end) {
44        cache_unroll(start,Index_Writeback_Inv_D);
45        start += CFG_CACHELINE_SIZE;
46    }
47}
48
49static inline void jz_flush_icache(void)
50{
51    unsigned long start;
52    unsigned long end;
53
54    start = KSEG0;
55    end = start + CFG_ICACHE_SIZE;
56    while(start < end) {
57        cache_unroll(start,Index_Invalidate_I);
58        start += CFG_CACHELINE_SIZE;
59    }
60}
61
62/* cpu pipeline flush */
63static inline void jz_sync(void)
64{
65    __asm__ volatile ("sync");
66}
67
68static inline void jz_writeb(u32 address, u8 value)
69{
70    *((volatile u8 *)address) = value;
71}
72
73static inline void jz_writew(u32 address, u16 value)
74{
75    *((volatile u16 *)address) = value;
76}
77
78static inline void jz_writel(u32 address, u32 value)
79{
80    *((volatile u32 *)address) = value;
81}
82
83static inline u8 jz_readb(u32 address)
84{
85    return *((volatile u8 *)address);
86}
87
88static inline u16 jz_readw(u32 address)
89{
90    return *((volatile u16 *)address);
91}
92
93static inline u32 jz_readl(u32 address)
94{
95    return *((volatile u32 *)address);
96}
97#endif
98
99//----------------------------------------------------------------------
100// Boot ROM Specification
101//
102
103/* NOR Boot config */
104#define JZ4760_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
105#define JZ4760_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
106#define JZ4760_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
107
108/* NAND Boot config */
109#define JZ4760_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
110#define JZ4760_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
111#define JZ4760_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
112#define JZ4760_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
113
114
115//----------------------------------------------------------------------
116// Register Definitions
117//
118/* AHB0 BUS Devices Base */
119#define HARB0_BASE 0xB3000000
120#define EMC_BASE 0xB3010000
121#define DDRC_BASE 0xB3020000
122#define MDMAC_BASE 0xB3030000
123#define LCD_BASE 0xB3050000
124#define TVE_BASE 0xB3050000
125#define SLCD_BASE 0xB3050000
126#define CIM_BASE 0xB3060000
127#define IPU_BASE 0xB3080000
128/* AHB1 BUS Devices Base */
129#define HARB1_BASE 0xB3200000
130#define DMAGP0_BASE 0xB3210000
131#define DMAGP1_BASE 0xB3220000
132#define DMAGP2_BASE 0xB3230000
133#define MC_BASE 0xB3250000
134#define ME_BASE 0xB3260000
135#define DEBLK_BASE 0xB3270000
136#define IDCT_BASE 0xB3280000
137#define CABAC_BASE 0xB3290000
138#define TCSM0_BASE 0xB32B0000
139#define TCSM1_BASE 0xB32C0000
140#define SRAM_BASE 0xB32D0000
141/* AHB2 BUS Devices Base */
142#define HARB2_BASE 0xB3400000
143#define NEMC_BASE 0xB3410000
144#define DMAC_BASE 0xB3420000
145#define UHC_BASE 0xB3430000
146#define UDC_BASE 0xB3440000
147#define GPS_BASE 0xB3480000
148#define ETHC_BASE 0xB34B0000
149#define BCH_BASE 0xB34D0000
150/* APB BUS Devices Base */
151#define CPM_BASE 0xB0000000
152#define INTC_BASE 0xB0001000
153#define TCU_BASE 0xB0002000
154#define OST_BASE 0xB0002000
155#define WDT_BASE 0xB0002000
156#define RTC_BASE 0xB0003000
157#define GPIO_BASE 0xB0010000
158#define AIC_BASE 0xB0020000
159#define ICDC_BASE 0xB0020000
160#define MSC0_BASE 0xB0021000
161#define MSC1_BASE 0xB0022000
162#define MSC2_BASE 0xB0023000
163#define UART0_BASE 0xB0030000
164#define UART1_BASE 0xB0031000
165#define UART2_BASE 0xB0032000
166#define UART3_BASE 0xB0033000
167#define SCC_BASE 0xB0040000
168#define SSI0_BASE 0xB0043000
169#define SSI1_BASE 0xB0044000
170#define SSI2_BASE 0xB0045000
171#define I2C0_BASE 0xB0050000
172#define I2C1_BASE 0xB0051000
173#define PS2_BASE 0xB0060000
174#define SADC_BASE 0xB0070000
175#define OWI_BASE 0xB0072000
176#define TSSI_BASE 0xB0073000
177
178/*************************************************************************
179 * INTC (Interrupt Controller)
180 *************************************************************************/
181#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20)
182#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20)
183#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20)
184#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20)
185#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20)
186
187#define REG_INTC_ISR(n) REG32(INTC_ISR((n)))
188#define REG_INTC_IMR(n) REG32(INTC_IMR((n)))
189#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n)))
190#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n)))
191#define REG_INTC_IPR(n) REG32(INTC_IPR((n)))
192
193
194// 1st-level interrupts
195#define IRQ_I2C1 0
196#define IRQ_I2C0 1
197#define IRQ_UART3 2
198#define IRQ_UART2 3
199#define IRQ_UART1 4
200#define IRQ_UART0 5
201#define IRQ_SSI2 6
202#define IRQ_SSI1 7
203#define IRQ_SSI0 8
204#define IRQ_TSSI 9
205#define IRQ_BDMA 10
206#define IRQ_KBC 11
207#define IRQ_GPIO5 12
208#define IRQ_GPIO4 13
209#define IRQ_GPIO3 14
210#define IRQ_GPIO2 15
211#define IRQ_GPIO1 16
212#define IRQ_GPIO0 17
213#define IRQ_SADC 18
214#define IRQ_ETH 19
215#define IRQ_UHC 20
216#define IRQ_OTG 21
217#define IRQ_MDMA 22
218#define IRQ_DMAC1 23
219#define IRQ_DMAC0 24
220#define IRQ_TCU2 25
221#define IRQ_TCU1 26
222#define IRQ_TCU0 27
223#define IRQ_GPS 28
224#define IRQ_IPU 29
225#define IRQ_CIM 30
226#define IRQ_LCD 31
227
228#define IRQ_RTC 32
229#define IRQ_OWI 33
230#define IRQ_AIC 34
231#define IRQ_MSC2 35
232#define IRQ_MSC1 36
233#define IRQ_MSC0 37
234#define IRQ_SCC 38
235#define IRQ_BCH 39
236#define IRQ_PCM 40
237
238// 2nd-level interrupts
239#define IRQ_DMA_0 64 /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */
240#define IRQ_DMA_1 (IRQ_DMA_0 + HALF_DMA_NUM) /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */
241#define IRQ_MDMA_0 (IRQ_DMA_0 + MAX_DMA_NUM) /* 64 ~ 66 for MDMAC channel 0 ~ 2 */
242
243#define IRQ_GPIO_0 96 /* 96 to 287 for GPIO pin 0 to 127 */
244
245#define NUM_INTC 41
246#define NUM_DMA MAX_DMA_NUM /* 12 */
247#define NUM_MDMA MAX_MDMA_NUM /* 3 */
248#define NUM_GPIO MAX_GPIO_NUM /* GPIO NUM: 192, Jz4760 real num GPIO 178 */
249
250/*************************************************************************
251 * RTC
252 *************************************************************************/
253#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
254#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
255#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
256#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
257
258#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
259#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
260#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
261#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
262#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
263#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
264#define RTC_WENR (RTC_BASE + 0x3c) /* Write enable pattern register */
265
266#define REG_RTC_RCR REG32(RTC_RCR)
267#define REG_RTC_RSR REG32(RTC_RSR)
268#define REG_RTC_RSAR REG32(RTC_RSAR)
269#define REG_RTC_RGR REG32(RTC_RGR)
270#define REG_RTC_HCR REG32(RTC_HCR)
271#define REG_RTC_HWFCR REG32(RTC_HWFCR)
272#define REG_RTC_HRCR REG32(RTC_HRCR)
273#define REG_RTC_HWCR REG32(RTC_HWCR)
274#define REG_RTC_HWRSR REG32(RTC_HWRSR)
275#define REG_RTC_HSPR REG32(RTC_HSPR)
276#define REG_RTC_WENR REG32(RTC_WENR)
277
278/* RTC Control Register */
279#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
280#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
281#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
282#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
283#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
284#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
285#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
286
287/* RTC Regulator Register */
288#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
289#define RTC_RGR_ADJC_BIT 16
290#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
291#define RTC_RGR_NC1HZ_BIT 0
292#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
293
294/* Hibernate Control Register */
295#define RTC_HCR_PD (1 << 0) /* Power Down */
296
297/* Hibernate Wakeup Filter Counter Register */
298#define RTC_HWFCR_BIT 5
299#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
300
301/* Hibernate Reset Counter Register */
302#define RTC_HRCR_BIT 5
303#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
304
305/* Hibernate Wakeup Control Register */
306#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
307
308/* Hibernate Wakeup Status Register */
309#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
310#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
311#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
312#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
313
314/* Write enable pattern register */
315#define RTC_WENR_WEN (1 << 31) /* write has been enabled */
316#define RTC_WENR_WENPAT_BIT 0
317#define RTC_WENR_WENPAT_MASK (0xffff << RTC_WENR_WENPAT_BIT) /* The write enable pattern. */
318
319
320/*************************************************************************
321 * CPM (Clock reset and Power control Management)
322 *************************************************************************/
323#define CPM_CPCCR (CPM_BASE+0x00) /* Clock control register */
324#define CPM_CPPCR (CPM_BASE+0x10) /* PLL control register 0 */
325#define CPM_CPPSR (CPM_BASE+0x14) /* PLL switch and status Register */
326#define CPM_CPPCR1 (CPM_BASE+0x30) /* PLL control register 1 */
327#define CPM_CPSPR (CPM_BASE+0x34) /* CPM scratch pad register */
328#define CPM_CPSPPR (CPM_BASE+0x38) /* CPM scratch protected register */
329#define CPM_USBPCR (CPM_BASE+0x3c) /* USB parameter control register */
330#define CPM_USBRDT (CPM_BASE+0x40) /* USB reset detect timer register */
331#define CPM_USBVBFIL (CPM_BASE+0x44) /* USB jitter filter register */
332#define CPM_USBCDR (CPM_BASE+0x50) /* USB OTG PHY clock divider register */
333#define CPM_I2SCDR (CPM_BASE+0x60) /* I2S device clock divider register */
334#define CPM_LPCDR (CPM_BASE+0x64) /* LCD pix clock divider register */
335#define CPM_MSCCDR (CPM_BASE+0x68) /* MSC clock divider register */
336#define CPM_UHCCDR (CPM_BASE+0x6C) /* UHC 48M clock divider register */
337#define CPM_SSICDR (CPM_BASE+0x74) /* SSI clock divider register */
338#define CPM_CIMCDR (CPM_BASE+0x7c) /* CIM MCLK clock divider register */
339#define CPM_GPSCDR (CPM_BASE+0x80) /* GPS clock divider register */
340#define CPM_PCMCDR (CPM_BASE+0x84) /* PCM device clock divider register */
341#define CPM_GPUCDR (CPM_BASE+0x88) /* GPU clock divider register */
342
343#define CPM_LCR (CPM_BASE+0x04)
344#define CPM_PSWCST(n) (CPM_BASE+0x4*(n)+0x90)
345#define CPM_CLKGR0 (CPM_BASE+0x20) /* Clock Gate Register0 */
346#define CPM_CLKGR1 (CPM_BASE+0x28) /* Clock Gate Register1 */
347#define CPM_OPCR (CPM_BASE+0x24) /* Oscillator and Power Control Register */
348
349#define CPM_RSR (CPM_BASE+0x08)
350
351
352#define REG_CPM_CPCCR REG32(CPM_CPCCR)
353#define REG_CPM_CPPCR REG32(CPM_CPPCR)
354#define REG_CPM_CPPSR REG32(CPM_CPPSR)
355#define REG_CPM_CPPCR1 REG32(CPM_CPPCR1)
356#define REG_CPM_CPSPR REG32(CPM_CPSPR)
357#define REG_CPM_CPSPPR REG32(CPM_CPSPPR)
358#define REG_CPM_USBPCR REG32(CPM_USBPCR)
359#define REG_CPM_USBRDT REG32(CPM_USBRDT)
360#define REG_CPM_USBVBFIL REG32(CPM_USBVBFIL)
361#define REG_CPM_USBCDR REG32(CPM_USBCDR)
362#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
363#define REG_CPM_LPCDR REG32(CPM_LPCDR)
364#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
365#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
366#define REG_CPM_SSICDR REG32(CPM_SSICDR)
367#define REG_CPM_CIMCDR REG32(CPM_CIMCDR)
368#define REG_CPM_GPSCDR REG32(CPM_GPSCDR)
369#define REG_CPM_PCMCDR REG32(CPM_PCMCDR)
370#define REG_CPM_GPUCDR REG32(CPM_GPUCDR)
371
372#define REG_CPM_LCR REG32(CPM_LCR)
373#define REG_CPM_CLKGR0 REG32(CPM_CLKGR0)
374#define REG_CPM_CLKGR1 REG32(CPM_CLKGR1)
375#define REG_CPM_OPCR REG32(CPM_OPCR)
376
377#define REG_CPM_RSR REG32(CPM_RSR)
378/* Clock control register */
379#define CPM_CPCCR_ECS (0x01 << 31)
380#define CPM_CPCCR_MEM (0x01 << 30)
381#define CPM_CPCCR_SDIV_BIT 24
382#define CPM_CPCCR_SDIV_MASK (0x0f << CPM_CPCCR_SDIV_BIT)
383#define CPM_CPCCR_CE (0x01 << 22)
384#define CPM_CPCCR_PCS (0x01 << 21)
385#define CPM_CPCCR_H2DIV_BIT 16
386#define CPM_CPCCR_H2DIV_MASK (0x0f << CPM_CPCCR_H2DIV_BIT)
387#define CPM_CPCCR_MDIV_BIT 12
388#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
389#define CPM_CPCCR_PDIV_BIT 8
390#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
391#define CPM_CPCCR_HDIV_BIT 4
392#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
393#define CPM_CPCCR_CDIV_BIT 0
394#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
395
396/* PLL control register 0 */
397#define CPM_CPPCR_PLLM_BIT 24
398#define CPM_CPPCR_PLLM_MASK (0x7f << CPM_CPPCR_PLLM_BIT)
399#define CPM_CPPCR_PLLN_BIT 18
400#define CPM_CPPCR_PLLN_MASK (0x0f << CPM_CPPCR_PLLN_BIT)
401#define CPM_CPPCR_PLLOD_BIT 16
402#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
403#define CPM_CPPCR_LOCK0 (1 << 15)
404#define CPM_CPPCR_ENLOCK (1 << 14)
405#define CPM_CPPCR_PLLS (1 << 10)
406#define CPM_CPPCR_PLLBP (1 << 9)
407#define CPM_CPPCR_PLLEN (1 << 8)
408#define CPM_CPPCR_PLLST_BIT 0
409#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
410
411/* PLL control register 1 */
412#define CPM_CPPCR1_PLL1M_BIT 24
413#define CPM_CPPCR1_PLL1M_MASK (0x7f << CPM_CPPCR1_PLL1M_BIT)
414#define CPM_CPPCR1_PLL1N_BIT 18
415#define CPM_CPPCR1_PLL1N_MASK (0x0f << CPM_CPPCR1_PLL1N_BIT)
416#define CPM_CPPCR1_PLL1OD_BIT 16
417#define CPM_CPPCR1_PLL1OD_MASK (0x03 << CPM_CPPCR1_PLL1OD_BIT)
418#define CPM_CPPCR1_P1SCS (1 << 15)
419#define CPM_CPPCR1_P1SDIV_BIT 9
420#define CPM_CPPCR1_P1SDIV_MASK (0x3f << CPM_CPPCR1_P1SDIV_BIT)
421#define CPM_CPPCR1_PLL1EN (1 << 7)
422#define CPM_CPPCR1_PLL1S (1 << 6)
423#define CPM_CPPCR1_LOCK1 (1 << 2)
424#define CPM_CPPCR1_PLL1OFF (1 << 1)
425#define CPM_CPPCR1_PLL1ON (1 << 0)
426
427/* PLL switch and status Register */
428#define CPM_CPPSR_PLLOFF (1 << 31)
429#define CPM_CPPSR_PLLBP (1 << 30)
430#define CPM_CPPSR_PLLON (1 << 29)
431#define CPM_CPPSR_PS (1 << 28)
432#define CPM_CPPSR_FS (1 << 27)
433#define CPM_CPPSR_CS (1 << 26)
434#define CPM_CPPSR_SM (1 << 2)
435#define CPM_CPPSR_PM (1 << 1)
436#define CPM_CPPSR_FM (1 << 0)
437
438/* CPM scratch protected register */
439#define CPM_CPSPPR_BIT 0
440#define CPM_CPSPPR_MASK (0xffff << CPM_CPSPPR_BIT)
441
442/* USB parameter control register */
443#define CPM_USBPCR_USB_MODE (1 << 31) /* 1: OTG, 0: UDC*/
444#define CPM_USBPCR_AVLD_REG (1 << 30)
445#define CPM_USBPCR_IDPULLUP_MASK_BIT 28
446#define CPM_USBPCR_IDPULLUP_MASK_MASK (0x02 << IDPULLUP_MASK_BIT)
447#define CPM_USBPCR_INCR_MASK (1 << 27)
448#define CPM_USBPCR_CLK12_EN (1 << 26)
449#define CPM_USBPCR_COMMONONN (1 << 25)
450#define CPM_USBPCR_VBUSVLDEXT (1 << 24)
451#define CPM_USBPCR_VBUSVLDEXTSEL (1 << 23)
452#define CPM_USBPCR_POR (1 << 22)
453#define CPM_USBPCR_SIDDQ (1 << 21)
454#define CPM_USBPCR_OTG_DISABLE (1 << 20)
455#define CPM_USBPCR_COMPDISTUNE_BIT 17
456#define CPM_USBPCR_COMPDISTUNE_MASK (0x07 << COMPDISTUNE_BIT)
457#define CPM_USBPCR_OTGTUNE_BIT 14
458#define CPM_USBPCR_OTGTUNE_MASK (0x07 << OTGTUNE_BIT)
459#define CPM_USBPCR_SQRXTUNE_BIT 11
460#define CPM_USBPCR_SQRXTUNE_MASK (0x7x << SQRXTUNE_BIT)
461#define CPM_USBPCR_TXFSLSTUNE_BIT 7
462#define CPM_USBPCR_TXFSLSTUNE_MASK (0x0f << TXFSLSTUNE_BIT)
463#define CPM_USBPCR_TXPREEMPHTUNE (1 << 6)
464#define CPM_USBPCR_TXRISETUNE_BIT 4
465#define CPM_USBPCR_TXRISETUNE_MASK (0x03 << TXRISETUNE_BIT)
466#define CPM_USBPCR_TXVREFTUNE_BIT 0
467#define CPM_USBPCR_TXVREFTUNE_MASK (0x0f << TXVREFTUNE_BIT)
468
469/* USB reset detect timer register */
470#define CPM_USBRDT_VBFIL_LD_EN (1 << 25)
471#define CPM_USBRDT_IDDIG_EN (1 << 24)
472#define CPM_USBRDT_IDDIG_REG (1 << 23)
473#define CPM_USBRDT_USBRDT_BIT 0
474#define CPM_USBRDT_USBRDT_MASK (0x7fffff << CPM_USBRDT_USBRDT_BIT)
475
476/* USB OTG PHY clock divider register */
477#define CPM_USBCDR_UCS (1 << 31)
478#define CPM_USBCDR_UPCS (1 << 30)
479#define CPM_USBCDR_OTGDIV_BIT 0
480#define CPM_USBCDR_OTGDIV_MASK (0x3f << CPM_USBCDR_OTGDIV_BIT)
481
482/* I2S device clock divider register */
483#define CPM_I2SCDR_I2CS (1 << 31)
484#define CPM_I2SCDR_I2PCS (1 << 30)
485#define CPM_I2SCDR_I2SDIV_BIT 0
486#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
487
488/* LCD pix clock divider register */
489#define CPM_LPCDR_LSCS (1 << 31)
490#define CPM_LPCDR_LTCS (1 << 30)
491#define CPM_LPCDR_LPCS (1 << 29)
492#define CPM_LPCDR_PIXDIV_BIT 0
493#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
494
495/* MSC clock divider register */
496#define CPM_MSCCDR_MCS (1 << 31)
497#define CPM_MSCCDR_MSCDIV_BIT 0
498#define CPM_MSCCDR_MSCDIV_MASK (0x3f << CPM_MSCCDR_PIXDIV_BIT)
499
500/* UHC 48M clock divider register */
501#define CPM_UHCCDR_UHPCS (1 << 31)
502#define CPM_UHCCDR_UHCDIV_BIT 0
503#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
504
505/* SSI clock divider register */
506#define CPM_SSICDR_SCS (1 << 31)
507#define CPM_SSICDR_SSIDIV_BIT 0
508#define CPM_SSICDR_SSIDIV_MASK (0x3f << CPM_SSICDR_SSIDIV_BIT)
509
510/* CIM MCLK clock divider register */
511#define CPM_CIMCDR_CIMDIV_BIT 0
512#define CPM_CIMCDR_CIMDIV_MASK (0xff << CPM_CIMCDR_CIMDIV_BIT)
513
514/* GPS clock divider register */
515#define CPM_GPSCDR_GPCS (1 << 31)
516#define CPM_GPSCDR_GPSDIV_BIT 0
517#define CPM_GSPCDR_GPSDIV_MASK (0xf << CPM_GPSCDR_GPSDIV_BIT)
518
519/* PCM device clock divider register */
520#define CPM_PCMCDR_PCMS (1 << 31)
521#define CPM_PCMCDR_PCMPCS (1 << 30)
522#define CPM_PCMCDR_PCMDIV_BIT 0
523#define CPM_PCMCDR_PCMDIV_MASK (0x1ff << CPM_PCMCDR_PCMDIV_BIT)
524
525/* GPU clock divider register */
526#define CPM_GPUCDR_GPCS (1 << 31)
527#define CPM_GPUCDR_GPUDIV_BIT 0
528#define CPM_GPUCDR_GPUDIV_MASK (0x7 << CPM_GPUCDR_GPUDIV_BIT)
529
530/* Low Power Control Register */
531#define CPM_LCR_PD_AHB1 (1 << 30)
532#define CPM_LCR_VBAT_IR (1 << 29)
533#define CPM_LCR_PD_GPS (1 << 28)
534#define CPM_LCR_PD_AHB1S (1 << 26)
535#define CPM_LCR_PD_GPSS (1 << 24)
536#define CPM_LCR_PST_BIT 8
537#define CPM_LCR_PST_MASK (0xfff << CPM_LCR_PST_BIT)
538#define CPM_LCR_DOZE_DUTY_BIT 3
539#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
540#define CPM_LCR_DOZE_ON (1 << 2)
541#define CPM_LCR_LPM_BIT 0
542#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
543  #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
544  #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
545
546/* Clock Gate Register0 */
547#define CPM_CLKGR0_EMC (1 << 31)
548#define CPM_CLKGR0_DDR (1 << 30)
549#define CPM_CLKGR0_IPU (1 << 29)
550#define CPM_CLKGR0_LCD (1 << 28)
551#define CPM_CLKGR0_TVE (1 << 27)
552#define CPM_CLKGR0_CIM (1 << 26)
553#define CPM_CLKGR0_MDMA (1 << 25)
554#define CPM_CLKGR0_UHC (1 << 24)
555#define CPM_CLKGR0_MAC (1 << 23)
556#define CPM_CLKGR0_GPS (1 << 22)
557#define CPM_CLKGR0_DMAC (1 << 21)
558#define CPM_CLKGR0_SSI2 (1 << 20)
559#define CPM_CLKGR0_SSI1 (1 << 19)
560#define CPM_CLKGR0_UART3 (1 << 18)
561#define CPM_CLKGR0_UART2 (1 << 17)
562#define CPM_CLKGR0_UART1 (1 << 16)
563#define CPM_CLKGR0_UART0 (1 << 15)
564#define CPM_CLKGR0_SADC (1 << 14)
565#define CPM_CLKGR0_KBC (1 << 13)
566#define CPM_CLKGR0_MSC2 (1 << 12)
567#define CPM_CLKGR0_MSC1 (1 << 11)
568#define CPM_CLKGR0_OWI (1 << 10)
569#define CPM_CLKGR0_TSSI (1 << 9)
570#define CPM_CLKGR0_AIC (1 << 8)
571#define CPM_CLKGR0_SCC (1 << 7)
572#define CPM_CLKGR0_I2C1 (1 << 6)
573#define CPM_CLKGR0_I2C0 (1 << 5)
574#define CPM_CLKGR0_SSI0 (1 << 4)
575#define CPM_CLKGR0_MSC0 (1 << 3)
576#define CPM_CLKGR0_OTG (1 << 2)
577#define CPM_CLKGR0_BCH (1 << 1)
578#define CPM_CLKGR0_NEMC (1 << 0)
579
580/* Clock Gate Register1 */
581#define CPM_CLKGR1_GPU (1 << 9)
582#define CPM_CLKGR1_PCM (1 << 8)
583#define CPM_CLKGR1_AHB1 (1 << 7)
584#define CPM_CLKGR1_CABAC (1 << 6)
585#define CPM_CLKGR1_SRAM (1 << 5)
586#define CPM_CLKGR1_DCT (1 << 4)
587#define CPM_CLKGR1_ME (1 << 3)
588#define CPM_CLKGR1_DBLK (1 << 2)
589#define CPM_CLKGR1_MC (1 << 1)
590#define CPM_CLKGR1_BDMA (1 << 0)
591
592/* Oscillator and Power Control Register */
593#define CPM_OPCR_O1ST_BIT 8
594#define CPM_OPCR_O1ST_MASK (0xff << CPM_OPCR_O1ST_BIT)
595#define CPM_OPCR_SPENDN (1 << 7)
596#define CPM_OPCR_GPSEN (1 << 6)
597#define CPM_OPCR_SPENDH (1 << 5)
598#define CPM_OPCR_O1SE (1 << 4) /* */
599#define CPM_OPCR_ERCS (1 << 2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
600#define CPM_OPCR_USBM (1 << 0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
601
602
603/* Reset Status Register */
604#define CPM_RSR_P0R (1 << 2)
605#define CPM_RSR_WR (1 << 1)
606#define CPM_RSR_PR (1 << 0)
607
608
609/*************************************************************************
610 * TCU (Timer Counter Unit)
611 *************************************************************************/
612#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
613#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
614#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
615#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
616#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
617#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
618#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
619#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
620#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
621#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
622#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
623#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
624#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
625#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
626#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
627#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
628#define TCU_TDFR1 (TCU_BASE + 0x50)
629#define TCU_TDHR1 (TCU_BASE + 0x54)
630#define TCU_TCNT1 (TCU_BASE + 0x58)
631#define TCU_TCSR1 (TCU_BASE + 0x5C)
632#define TCU_TDFR2 (TCU_BASE + 0x60)
633#define TCU_TDHR2 (TCU_BASE + 0x64)
634#define TCU_TCNT2 (TCU_BASE + 0x68)
635#define TCU_TCSR2 (TCU_BASE + 0x6C)
636#define TCU_TDFR3 (TCU_BASE + 0x70)
637#define TCU_TDHR3 (TCU_BASE + 0x74)
638#define TCU_TCNT3 (TCU_BASE + 0x78)
639#define TCU_TCSR3 (TCU_BASE + 0x7C)
640#define TCU_TDFR4 (TCU_BASE + 0x80)
641#define TCU_TDHR4 (TCU_BASE + 0x84)
642#define TCU_TCNT4 (TCU_BASE + 0x88)
643#define TCU_TCSR4 (TCU_BASE + 0x8C)
644#define TCU_TDFR5 (TCU_BASE + 0x90)
645#define TCU_TDHR5 (TCU_BASE + 0x94)
646#define TCU_TCNT5 (TCU_BASE + 0x98)
647#define TCU_TCSR5 (TCU_BASE + 0x9C)
648
649#define REG_TCU_TSR REG32(TCU_TSR)
650#define REG_TCU_TSSR REG32(TCU_TSSR)
651#define REG_TCU_TSCR REG32(TCU_TSCR)
652#define REG_TCU_TER REG8(TCU_TER)
653#define REG_TCU_TESR REG8(TCU_TESR)
654#define REG_TCU_TECR REG8(TCU_TECR)
655#define REG_TCU_TFR REG32(TCU_TFR)
656#define REG_TCU_TFSR REG32(TCU_TFSR)
657#define REG_TCU_TFCR REG32(TCU_TFCR)
658#define REG_TCU_TMR REG32(TCU_TMR)
659#define REG_TCU_TMSR REG32(TCU_TMSR)
660#define REG_TCU_TMCR REG32(TCU_TMCR)
661#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
662#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
663#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
664#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
665#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
666#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
667#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
668#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
669#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
670#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
671#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
672#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
673#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
674#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
675#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
676#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
677#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
678#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
679#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
680#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
681
682// n = 0,1,2,3,4,5
683#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
684#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
685#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
686#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
687
688#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
689#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
690#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
691#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
692
693// Register definitions
694#define TCU_TCSR_PWM_SD (1 << 9)
695#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
696#define TCU_TCSR_PWM_EN (1 << 7)
697#define TCU_TCSR_PRESCALE_BIT 3
698#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
699  #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
700  #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
701  #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
702  #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
703  #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
704  #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
705#define TCU_TCSR_EXT_EN (1 << 2)
706#define TCU_TCSR_RTC_EN (1 << 1)
707#define TCU_TCSR_PCK_EN (1 << 0)
708
709#define TCU_TER_TCEN5 (1 << 5)
710#define TCU_TER_TCEN4 (1 << 4)
711#define TCU_TER_TCEN3 (1 << 3)
712#define TCU_TER_TCEN2 (1 << 2)
713#define TCU_TER_TCEN1 (1 << 1)
714#define TCU_TER_TCEN0 (1 << 0)
715
716#define TCU_TESR_TCST5 (1 << 5)
717#define TCU_TESR_TCST4 (1 << 4)
718#define TCU_TESR_TCST3 (1 << 3)
719#define TCU_TESR_TCST2 (1 << 2)
720#define TCU_TESR_TCST1 (1 << 1)
721#define TCU_TESR_TCST0 (1 << 0)
722
723#define TCU_TECR_TCCL5 (1 << 5)
724#define TCU_TECR_TCCL4 (1 << 4)
725#define TCU_TECR_TCCL3 (1 << 3)
726#define TCU_TECR_TCCL2 (1 << 2)
727#define TCU_TECR_TCCL1 (1 << 1)
728#define TCU_TECR_TCCL0 (1 << 0)
729
730#define TCU_TFR_HFLAG5 (1 << 21)
731#define TCU_TFR_HFLAG4 (1 << 20)
732#define TCU_TFR_HFLAG3 (1 << 19)
733#define TCU_TFR_HFLAG2 (1 << 18)
734#define TCU_TFR_HFLAG1 (1 << 17)
735#define TCU_TFR_HFLAG0 (1 << 16)
736#define TCU_TFR_FFLAG5 (1 << 5)
737#define TCU_TFR_FFLAG4 (1 << 4)
738#define TCU_TFR_FFLAG3 (1 << 3)
739#define TCU_TFR_FFLAG2 (1 << 2)
740#define TCU_TFR_FFLAG1 (1 << 1)
741#define TCU_TFR_FFLAG0 (1 << 0)
742
743#define TCU_TFSR_HFLAG5 (1 << 21)
744#define TCU_TFSR_HFLAG4 (1 << 20)
745#define TCU_TFSR_HFLAG3 (1 << 19)
746#define TCU_TFSR_HFLAG2 (1 << 18)
747#define TCU_TFSR_HFLAG1 (1 << 17)
748#define TCU_TFSR_HFLAG0 (1 << 16)
749#define TCU_TFSR_FFLAG5 (1 << 5)
750#define TCU_TFSR_FFLAG4 (1 << 4)
751#define TCU_TFSR_FFLAG3 (1 << 3)
752#define TCU_TFSR_FFLAG2 (1 << 2)
753#define TCU_TFSR_FFLAG1 (1 << 1)
754#define TCU_TFSR_FFLAG0 (1 << 0)
755
756#define TCU_TFCR_HFLAG5 (1 << 21)
757#define TCU_TFCR_HFLAG4 (1 << 20)
758#define TCU_TFCR_HFLAG3 (1 << 19)
759#define TCU_TFCR_HFLAG2 (1 << 18)
760#define TCU_TFCR_HFLAG1 (1 << 17)
761#define TCU_TFCR_HFLAG0 (1 << 16)
762#define TCU_TFCR_FFLAG5 (1 << 5)
763#define TCU_TFCR_FFLAG4 (1 << 4)
764#define TCU_TFCR_FFLAG3 (1 << 3)
765#define TCU_TFCR_FFLAG2 (1 << 2)
766#define TCU_TFCR_FFLAG1 (1 << 1)
767#define TCU_TFCR_FFLAG0 (1 << 0)
768
769#define TCU_TMR_HMASK5 (1 << 21)
770#define TCU_TMR_HMASK4 (1 << 20)
771#define TCU_TMR_HMASK3 (1 << 19)
772#define TCU_TMR_HMASK2 (1 << 18)
773#define TCU_TMR_HMASK1 (1 << 17)
774#define TCU_TMR_HMASK0 (1 << 16)
775#define TCU_TMR_FMASK5 (1 << 5)
776#define TCU_TMR_FMASK4 (1 << 4)
777#define TCU_TMR_FMASK3 (1 << 3)
778#define TCU_TMR_FMASK2 (1 << 2)
779#define TCU_TMR_FMASK1 (1 << 1)
780#define TCU_TMR_FMASK0 (1 << 0)
781
782#define TCU_TMSR_HMST5 (1 << 21)
783#define TCU_TMSR_HMST4 (1 << 20)
784#define TCU_TMSR_HMST3 (1 << 19)
785#define TCU_TMSR_HMST2 (1 << 18)
786#define TCU_TMSR_HMST1 (1 << 17)
787#define TCU_TMSR_HMST0 (1 << 16)
788#define TCU_TMSR_FMST5 (1 << 5)
789#define TCU_TMSR_FMST4 (1 << 4)
790#define TCU_TMSR_FMST3 (1 << 3)
791#define TCU_TMSR_FMST2 (1 << 2)
792#define TCU_TMSR_FMST1 (1 << 1)
793#define TCU_TMSR_FMST0 (1 << 0)
794
795#define TCU_TMCR_HMCL5 (1 << 21)
796#define TCU_TMCR_HMCL4 (1 << 20)
797#define TCU_TMCR_HMCL3 (1 << 19)
798#define TCU_TMCR_HMCL2 (1 << 18)
799#define TCU_TMCR_HMCL1 (1 << 17)
800#define TCU_TMCR_HMCL0 (1 << 16)
801#define TCU_TMCR_FMCL5 (1 << 5)
802#define TCU_TMCR_FMCL4 (1 << 4)
803#define TCU_TMCR_FMCL3 (1 << 3)
804#define TCU_TMCR_FMCL2 (1 << 2)
805#define TCU_TMCR_FMCL1 (1 << 1)
806#define TCU_TMCR_FMCL0 (1 << 0)
807
808#define TCU_TSR_WDTS (1 << 16)
809#define TCU_TSR_STOP5 (1 << 5)
810#define TCU_TSR_STOP4 (1 << 4)
811#define TCU_TSR_STOP3 (1 << 3)
812#define TCU_TSR_STOP2 (1 << 2)
813#define TCU_TSR_STOP1 (1 << 1)
814#define TCU_TSR_STOP0 (1 << 0)
815
816#define TCU_TSSR_WDTSS (1 << 16)
817#define TCU_TSSR_STPS5 (1 << 5)
818#define TCU_TSSR_STPS4 (1 << 4)
819#define TCU_TSSR_STPS3 (1 << 3)
820#define TCU_TSSR_STPS2 (1 << 2)
821#define TCU_TSSR_STPS1 (1 << 1)
822#define TCU_TSSR_STPS0 (1 << 0)
823
824#define TCU_TSSR_WDTSC (1 << 16)
825#define TCU_TSSR_STPC5 (1 << 5)
826#define TCU_TSSR_STPC4 (1 << 4)
827#define TCU_TSSR_STPC3 (1 << 3)
828#define TCU_TSSR_STPC2 (1 << 2)
829#define TCU_TSSR_STPC1 (1 << 1)
830#define TCU_TSSR_STPC0 (1 << 0)
831
832
833/*************************************************************************
834 * WDT (WatchDog Timer)
835 *************************************************************************/
836#define WDT_TDR (WDT_BASE + 0x00)
837#define WDT_TCER (WDT_BASE + 0x04)
838#define WDT_TCNT (WDT_BASE + 0x08)
839#define WDT_TCSR (WDT_BASE + 0x0C)
840
841#define REG_WDT_TDR REG16(WDT_TDR)
842#define REG_WDT_TCER REG8(WDT_TCER)
843#define REG_WDT_TCNT REG16(WDT_TCNT)
844#define REG_WDT_TCSR REG16(WDT_TCSR)
845
846// Register definition
847#define WDT_TCSR_PRESCALE_BIT 3
848#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
849  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
850  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
851  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
852  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
853  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
854  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
855#define WDT_TCSR_EXT_EN (1 << 2)
856#define WDT_TCSR_RTC_EN (1 << 1)
857#define WDT_TCSR_PCK_EN (1 << 0)
858
859#define WDT_TCER_TCEN (1 << 0)
860
861/*************************************************************************
862 * MDMAC (MEM Copy DMA Controller)
863 *************************************************************************/
864
865#define MAX_MDMA_NUM 3 /* max 3 channels */
866
867/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
868
869#define MDMAC_DSAR(n) (MDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
870#define MDMAC_DTAR(n) (MDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
871#define MDMAC_DTCR(n) (MDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
872#define MDMAC_DRSR(n) (MDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
873#define MDMAC_DCCSR(n) (MDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
874#define MDMAC_DCMD(n) (MDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
875#define MDMAC_DDA(n) (MDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
876#define MDMAC_DSD(n) (MDMAC_BASE + (0xc0 + (n) * 0x04)) /* DMA Stride Address */
877
878#define MDMAC_DMACR (MDMAC_BASE + 0x0300) /* DMA control register */
879#define MDMAC_DMAIPR (MDMAC_BASE + 0x0304) /* DMA interrupt pending */
880#define MDMAC_DMADBR (MDMAC_BASE + 0x0308) /* DMA doorbell */
881#define MDMAC_DMADBSR (MDMAC_BASE + 0x030C) /* DMA doorbell set */
882#define MDMAC_DMACKE (MDMAC_BASE + 0x0310)
883
884#define REG_MDMAC_DSAR(n) REG32(MDMAC_DSAR((n)))
885#define REG_MDMAC_DTAR(n) REG32(MDMAC_DTAR((n)))
886#define REG_MDMAC_DTCR(n) REG32(MDMAC_DTCR((n)))
887#define REG_MDMAC_DRSR(n) REG32(MDMAC_DRSR((n)))
888#define REG_MDMAC_DCCSR(n) REG32(MDMAC_DCCSR((n)))
889#define REG_MDMAC_DCMD(n) REG32(MDMAC_DCMD((n)))
890#define REG_MDMAC_DDA(n) REG32(MDMAC_DDA((n)))
891#define REG_MDMAC_DSD(n) REG32(MDMAC_DSD(n))
892#define REG_MDMAC_DMACR REG32(MDMAC_DMACR)
893#define REG_MDMAC_DMAIPR REG32(MDMAC_DMAIPR)
894#define REG_MDMAC_DMADBR REG32(MDMAC_DMADBR)
895#define REG_MDMAC_DMADBSR REG32(MDMAC_DMADBSR)
896#define REG_MDMAC_DMACKE REG32(MDMAC_DMACKE)
897
898
899/*************************************************************************
900 * DMAC (DMA Controller)
901 *************************************************************************/
902
903#define MAX_DMA_NUM 12 /* max 12 channels */
904#define HALF_DMA_NUM 6 /* the number of one dma controller's channels */
905
906/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
907
908#define DMAC_DSAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x00 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA source address */
909#define DMAC_DTAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x04 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA target address */
910#define DMAC_DTCR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x08 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA transfer count */
911#define DMAC_DRSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x0c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA request source */
912#define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */
913#define DMAC_DCMD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */
914#define DMAC_DDA(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */
915#define DMAC_DSD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0xc0 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */
916
917#define DMAC_DMACR(m) (DMAC_BASE + 0x0300 + 0x100 * m) /* DMA control register */
918#define DMAC_DMAIPR(m) (DMAC_BASE + 0x0304 + 0x100 * m) /* DMA interrupt pending */
919#define DMAC_DMADBR(m) (DMAC_BASE + 0x0308 + 0x100 * m) /* DMA doorbell */
920#define DMAC_DMADBSR(m) (DMAC_BASE + 0x030C + 0x100 * m) /* DMA doorbell set */
921#define DMAC_DMADCKE(m) (DMAC_BASE + 0x0310 + 0x100 * m)
922
923#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
924#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
925#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
926#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
927#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
928#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
929#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
930#define REG_DMAC_DSD(n) REG32(DMAC_DSD(n))
931#define REG_DMAC_DMACR(m) REG32(DMAC_DMACR(m))
932#define REG_DMAC_DMAIPR(m) REG32(DMAC_DMAIPR(m))
933#define REG_DMAC_DMADBR(m) REG32(DMAC_DMADBR(m))
934#define REG_DMAC_DMADBSR(m) REG32(DMAC_DMADBSR(m))
935#define REG_DMAC_DMADCKE(m) REG32(DMAC_DMADCKE(m))
936
937// DMA request source register
938#define DMAC_DRSR_RS_BIT 0
939#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
940  #define DMAC_DRSR_RS_EXT (0 << DMAC_DRSR_RS_BIT)
941  #define DMAC_DRSR_RS_NAND (1 << DMAC_DRSR_RS_BIT)
942  #define DMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT)
943  #define DMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT)
944  #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
945  #define DMAC_DRSR_RS_TSSIIN (9 << DMAC_DRSR_RS_BIT)
946  #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT)
947  #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT)
948  #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT)
949  #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT)
950  #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT)
951  #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT)
952  #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
953  #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
954  #define DMAC_DRSR_RS_SSI0OUT (22 << DMAC_DRSR_RS_BIT)
955  #define DMAC_DRSR_RS_SSI0IN (23 << DMAC_DRSR_RS_BIT)
956  #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
957  #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
958  #define DMAC_DRSR_RS_MSC0OUT (26 << DMAC_DRSR_RS_BIT)
959  #define DMAC_DRSR_RS_MSC0IN (27 << DMAC_DRSR_RS_BIT)
960  #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
961  #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
962  #define DMAC_DRSR_RS_MSC1OUT (30 << DMAC_DRSR_RS_BIT)
963  #define DMAC_DRSR_RS_MSC1IN (31 << DMAC_DRSR_RS_BIT)
964  #define DMAC_DRSR_RS_SSI1OUT (32 << DMAC_DRSR_RS_BIT)
965  #define DMAC_DRSR_RS_SSI1IN (33 << DMAC_DRSR_RS_BIT)
966  #define DMAC_DRSR_RS_PMOUT (34 << DMAC_DRSR_RS_BIT)
967  #define DMAC_DRSR_RS_PMIN (35 << DMAC_DRSR_RS_BIT)
968
969// DMA channel control/status register
970#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
971#define DMAC_DCCSR_DES8 (1 << 30) /* Descriptor 8 Word */
972#define DMAC_DCCSR_DES4 (0 << 30) /* Descriptor 4 Word */
973#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
974#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
975#define DMAC_DCCSR_BERR (1 << 7) /* BCH error within this transfer, Only for channel 0 */
976#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
977#define DMAC_DCCSR_AR (1 << 4) /* address error */
978#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
979#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
980#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
981#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
982
983// DMA channel command register
984#define DMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */
985#define DMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */
986#define DMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */
987#define DMAC_DCMD_EACKM_READ (0 << 30) /* External DACK Output Mode Select, output in read cycle */
988#define DMAC_DCMD_ERDM_BIT 28 /* External DREQ Detection Mode Select */
989#define DMAC_DCMD_ERDM_MASK (0x03 << DMAC_DCMD_ERDM_BIT)
990  #define DMAC_DCMD_ERDM_LOW (0 << DMAC_DCMD_ERDM_BIT)
991  #define DMAC_DCMD_ERDM_FALL (1 << DMAC_DCMD_ERDM_BIT)
992  #define DMAC_DCMD_ERDM_HIGH (2 << DMAC_DCMD_ERDM_BIT)
993  #define DMAC_DCMD_ERDM_RISE (3 << DMAC_DCMD_ERDM_BIT)
994#define DMAC_DCMD_BLAST (1 << 25) /* BCH last */
995#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
996#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
997#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
998#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
999  #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
1000  #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
1001  #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
1002  #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
1003  #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
1004  #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
1005  #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
1006  #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
1007  #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
1008  #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
1009  #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
1010  #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
1011  #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
1012  #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
1013  #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
1014  #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
1015#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
1016#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
1017  #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
1018  #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
1019  #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
1020#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
1021#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
1022  #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
1023  #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
1024  #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
1025#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
1026#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
1027  #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
1028  #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
1029  #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
1030  #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
1031  #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
1032  #define DMAC_DCMD_DS_64BYTE (5 << DMAC_DCMD_DS_BIT)
1033#define DMAC_DCMD_STDE (1 << 5) /* Stride Disable/Enable */
1034#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
1035#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
1036#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
1037#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
1038#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
1039
1040// DMA descriptor address register
1041#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
1042#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
1043#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
1044#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
1045
1046// DMA stride address register
1047#define DMAC_DSD_TSD_BIT 16 /* target stride address */
1048#define DMAC_DSD_TSD_MASK (0xffff << DMAC_DSD_TSD_BIT)
1049#define DMAC_DSD_SSD_BIT 0 /* source stride address */
1050#define DMAC_DSD_SSD_MASK (0xffff << DMAC_DSD_SSD_BIT)
1051
1052// DMA control register
1053#define DMAC_DMACR_FMSC (1 << 31) /* MSC Fast DMA mode */
1054#define DMAC_DMACR_FSSI (1 << 30) /* SSI Fast DMA mode */
1055#define DMAC_DMACR_FTSSI (1 << 29) /* TSSI Fast DMA mode */
1056#define DMAC_DMACR_FUART (1 << 28) /* UART Fast DMA mode */
1057#define DMAC_DMACR_FAIC (1 << 27) /* AIC Fast DMA mode */
1058#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
1059#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
1060  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
1061  #define DMAC_DMACR_PR_120345 (1 << DMAC_DMACR_PR_BIT)
1062  #define DMAC_DMACR_PR_230145 (2 << DMAC_DMACR_PR_BIT)
1063  #define DMAC_DMACR_PR_340125 (3 << DMAC_DMACR_PR_BIT)
1064#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
1065#define DMAC_DMACR_AR (1 << 2) /* address error flag */
1066#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
1067
1068// DMA doorbell register
1069#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
1070#define DMAC_DMADBR_DB4 (1 << 4) /* doorbell for channel 4 */
1071#define DMAC_DMADBR_DB3 (1 << 3) /* doorbell for channel 3 */
1072#define DMAC_DMADBR_DB2 (1 << 2) /* doorbell for channel 2 */
1073#define DMAC_DMADBR_DB1 (1 << 1) /* doorbell for channel 1 */
1074#define DMAC_DMADBR_DB0 (1 << 0) /* doorbell for channel 0 */
1075
1076// DMA doorbell set register
1077#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
1078#define DMAC_DMADBSR_DBS4 (1 << 4) /* enable doorbell for channel 4 */
1079#define DMAC_DMADBSR_DBS3 (1 << 3) /* enable doorbell for channel 3 */
1080#define DMAC_DMADBSR_DBS2 (1 << 2) /* enable doorbell for channel 2 */
1081#define DMAC_DMADBSR_DBS1 (1 << 1) /* enable doorbell for channel 1 */
1082#define DMAC_DMADBSR_DBS0 (1 << 0) /* enable doorbell for channel 0 */
1083
1084// DMA interrupt pending register
1085#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
1086#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
1087#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
1088#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
1089#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
1090#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
1091
1092
1093/*************************************************************************
1094 * GPIO (General-Purpose I/O Ports)
1095 *************************************************************************/
1096#define MAX_GPIO_NUM 192
1097
1098//n = 0,1,2,3,4,5
1099#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
1100#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
1101#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
1102#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
1103#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
1104#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
1105#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
1106#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Disable Register */
1107#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Disable Set Reg. */
1108#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Disable Clear Reg. */
1109#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
1110#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
1111#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
1112#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
1113#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
1114#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
1115#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
1116#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
1117#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
1118#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
1119#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
1120#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Clear Register */
1121#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
1122#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
1123
1124#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
1125#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
1126#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
1127#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
1128#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
1129#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
1130#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
1131#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
1132#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
1133#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
1134#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO/INTR, 1:FUNC */
1135#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
1136#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
1137#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
1138#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
1139#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
1140#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
1141#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
1142#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
1143#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:Level-trigger/Fun0, 1:Edge-trigger/Fun1 */
1144#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
1145#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
1146#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
1147#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
1148
1149
1150/*************************************************************************
1151 * UART
1152 *************************************************************************/
1153
1154#define IRDA_BASE UART0_BASE
1155//#define UART_BASE UART0_BASE
1156#define UART_OFF 0x1000
1157
1158/* Register Offset */
1159#define OFF_RDR (0x00) /* R 8b H'xx */
1160#define OFF_TDR (0x00) /* W 8b H'xx */
1161#define OFF_DLLR (0x00) /* RW 8b H'00 */
1162#define OFF_DLHR (0x04) /* RW 8b H'00 */
1163#define OFF_IER (0x04) /* RW 8b H'00 */
1164#define OFF_ISR (0x08) /* R 8b H'01 */
1165#define OFF_FCR (0x08) /* W 8b H'00 */
1166#define OFF_LCR (0x0C) /* RW 8b H'00 */
1167#define OFF_MCR (0x10) /* RW 8b H'00 */
1168#define OFF_LSR (0x14) /* R 8b H'00 */
1169#define OFF_MSR (0x18) /* R 8b H'00 */
1170#define OFF_SPR (0x1C) /* RW 8b H'00 */
1171#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
1172#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
1173#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
1174
1175/* Register Address */
1176#define UART0_RDR (UART0_BASE + OFF_RDR)
1177#define UART0_TDR (UART0_BASE + OFF_TDR)
1178#define UART0_DLLR (UART0_BASE + OFF_DLLR)
1179#define UART0_DLHR (UART0_BASE + OFF_DLHR)
1180#define UART0_IER (UART0_BASE + OFF_IER)
1181#define UART0_ISR (UART0_BASE + OFF_ISR)
1182#define UART0_FCR (UART0_BASE + OFF_FCR)
1183#define UART0_LCR (UART0_BASE + OFF_LCR)
1184#define UART0_MCR (UART0_BASE + OFF_MCR)
1185#define UART0_LSR (UART0_BASE + OFF_LSR)
1186#define UART0_MSR (UART0_BASE + OFF_MSR)
1187#define UART0_SPR (UART0_BASE + OFF_SPR)
1188#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
1189#define UART0_UMR (UART0_BASE + OFF_UMR)
1190#define UART0_UACR (UART0_BASE + OFF_UACR)
1191
1192/*
1193 * Define macros for UART_IER
1194 * UART Interrupt Enable Register
1195 */
1196#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
1197#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
1198#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
1199#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
1200#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
1201
1202/*
1203 * Define macros for UART_ISR
1204 * UART Interrupt Status Register
1205 */
1206#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
1207#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
1208#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
1209#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
1210#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
1211#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
1212#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
1213#define UART_ISR_FFMS_NO_FIFO (0 << 6)
1214#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
1215
1216/*
1217 * Define macros for UART_FCR
1218 * UART FIFO Control Register
1219 */
1220#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
1221#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
1222#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
1223#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
1224#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
1225#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
1226#define UART_FCR_RTRG_1 (0 << 6)
1227#define UART_FCR_RTRG_4 (1 << 6)
1228#define UART_FCR_RTRG_8 (2 << 6)
1229#define UART_FCR_RTRG_15 (3 << 6)
1230
1231/*
1232 * Define macros for UART_LCR
1233 * UART Line Control Register
1234 */
1235#define UART_LCR_WLEN (3 << 0) /* word length */
1236#define UART_LCR_WLEN_5 (0 << 0)
1237#define UART_LCR_WLEN_6 (1 << 0)
1238#define UART_LCR_WLEN_7 (2 << 0)
1239#define UART_LCR_WLEN_8 (3 << 0)
1240#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1241                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1242#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1243                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1244#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1245                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1246
1247#define UART_LCR_PE (1 << 3)