| 1 | /* |
| 2 | * Include file for Ingenic Semiconductor's JZ4740 CPU. |
| 3 | * |
| 4 | * Copyright 2009 (C) Qi Hardware Inc., |
| 5 | * Author: Xiangfu Liu <xiangfu@sharism.cc> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * version 3 as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 19 | * Boston, MA 02110-1301, USA |
| 20 | */ |
| 21 | #ifndef __JZ4740_H__ |
| 22 | #define __JZ4740_H__ |
| 23 | |
| 24 | #include "common.h" |
| 25 | |
| 26 | #define cache_unroll(base,op) \ |
| 27 | __asm__ __volatile__(" \ |
| 28 | .set noreorder; \ |
| 29 | .set mips3; \ |
| 30 | cache %1, (%0); \ |
| 31 | .set mips0; \ |
| 32 | .set reorder" \ |
| 33 | : \ |
| 34 | : "r" (base), \ |
| 35 | "i" (op)); |
| 36 | |
| 37 | /* cpu pipeline flush */ |
| 38 | static inline void jz_sync(void) |
| 39 | { |
| 40 | __asm__ volatile ("sync"); |
| 41 | } |
| 42 | |
| 43 | static inline void jz_writeb(u32 address, u8 value) |
| 44 | { |
| 45 | *((volatile u8 *)address) = value; |
| 46 | } |
| 47 | |
| 48 | static inline void jz_writew(u32 address, u16 value) |
| 49 | { |
| 50 | *((volatile u16 *)address) = value; |
| 51 | } |
| 52 | |
| 53 | static inline void jz_writel(u32 address, u32 value) |
| 54 | { |
| 55 | *((volatile u32 *)address) = value; |
| 56 | } |
| 57 | |
| 58 | static inline u8 jz_readb(u32 address) |
| 59 | { |
| 60 | return *((volatile u8 *)address); |
| 61 | } |
| 62 | |
| 63 | static inline u16 jz_readw(u32 address) |
| 64 | { |
| 65 | return *((volatile u16 *)address); |
| 66 | } |
| 67 | |
| 68 | static inline u32 jz_readl(u32 address) |
| 69 | { |
| 70 | return *((volatile u32 *)address); |
| 71 | } |
| 72 | |
| 73 | |
| 74 | /* Boot ROM Specification */ |
| 75 | |
| 76 | /* NOR Boot config */ |
| 77 | #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ |
| 78 | #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ |
| 79 | #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ |
| 80 | |
| 81 | /* NAND Boot config */ |
| 82 | #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ |
| 83 | #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ |
| 84 | #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ |
| 85 | #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ |
| 86 | |
| 87 | |
| 88 | /* Register Definitions */ |
| 89 | #define CPM_BASE 0xB0000000 |
| 90 | #define INTC_BASE 0xB0001000 |
| 91 | #define TCU_BASE 0xB0002000 |
| 92 | #define WDT_BASE 0xB0002000 |
| 93 | #define RTC_BASE 0xB0003000 |
| 94 | #define GPIO_BASE 0xB0010000 |
| 95 | #define AIC_BASE 0xB0020000 |
| 96 | #define ICDC_BASE 0xB0020000 |
| 97 | #define MSC_BASE 0xB0021000 |
| 98 | #define UART0_BASE 0xB0030000 |
| 99 | #define I2C_BASE 0xB0042000 |
| 100 | #define SSI_BASE 0xB0043000 |
| 101 | #define SADC_BASE 0xB0070000 |
| 102 | #define EMC_BASE 0xB3010000 |
| 103 | #define DMAC_BASE 0xB3020000 |
| 104 | #define UHC_BASE 0xB3030000 |
| 105 | #define UDC_BASE 0xB3040000 |
| 106 | #define LCD_BASE 0xB3050000 |
| 107 | #define SLCD_BASE 0xB3050000 |
| 108 | #define CIM_BASE 0xB3060000 |
| 109 | #define ETH_BASE 0xB3100000 |
| 110 | |
| 111 | |
| 112 | /************************************************************************* |
| 113 | * INTC (Interrupt Controller) |
| 114 | *************************************************************************/ |
| 115 | #define INTC_ISR (INTC_BASE + 0x00) |
| 116 | #define INTC_IMR (INTC_BASE + 0x04) |
| 117 | #define INTC_IMSR (INTC_BASE + 0x08) |
| 118 | #define INTC_IMCR (INTC_BASE + 0x0c) |
| 119 | #define INTC_IPR (INTC_BASE + 0x10) |
| 120 | |
| 121 | #define REG_INTC_ISR REG32(INTC_ISR) |
| 122 | #define REG_INTC_IMR REG32(INTC_IMR) |
| 123 | #define REG_INTC_IMSR REG32(INTC_IMSR) |
| 124 | #define REG_INTC_IMCR REG32(INTC_IMCR) |
| 125 | #define REG_INTC_IPR REG32(INTC_IPR) |
| 126 | |
| 127 | /* 1st-level interrupts */ |
| 128 | #define IRQ_I2C 1 |
| 129 | #define IRQ_UHC 3 |
| 130 | #define IRQ_UART0 9 |
| 131 | #define IRQ_SADC 12 |
| 132 | #define IRQ_MSC 14 |
| 133 | #define IRQ_RTC 15 |
| 134 | #define IRQ_SSI 16 |
| 135 | #define IRQ_CIM 17 |
| 136 | #define IRQ_AIC 18 |
| 137 | #define IRQ_ETH 19 |
| 138 | #define IRQ_DMAC 20 |
| 139 | #define IRQ_TCU2 21 |
| 140 | #define IRQ_TCU1 22 |
| 141 | #define IRQ_TCU0 23 |
| 142 | #define IRQ_UDC 24 |
| 143 | #define IRQ_GPIO3 25 |
| 144 | #define IRQ_GPIO2 26 |
| 145 | #define IRQ_GPIO1 27 |
| 146 | #define IRQ_GPIO0 28 |
| 147 | #define IRQ_IPU 29 |
| 148 | #define IRQ_LCD 30 |
| 149 | |
| 150 | /* 2nd-level interrupts */ |
| 151 | #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ |
| 152 | #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ |
| 153 | |
| 154 | |
| 155 | /************************************************************************* |
| 156 | * RTC |
| 157 | *************************************************************************/ |
| 158 | #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ |
| 159 | #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ |
| 160 | #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ |
| 161 | #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ |
| 162 | |
| 163 | #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ |
| 164 | #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ |
| 165 | #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ |
| 166 | #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ |
| 167 | #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ |
| 168 | #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ |
| 169 | |
| 170 | #define REG_RTC_RCR REG32(RTC_RCR) |
| 171 | #define REG_RTC_RSR REG32(RTC_RSR) |
| 172 | #define REG_RTC_RSAR REG32(RTC_RSAR) |
| 173 | #define REG_RTC_RGR REG32(RTC_RGR) |
| 174 | #define REG_RTC_HCR REG32(RTC_HCR) |
| 175 | #define REG_RTC_HWFCR REG32(RTC_HWFCR) |
| 176 | #define REG_RTC_HRCR REG32(RTC_HRCR) |
| 177 | #define REG_RTC_HWCR REG32(RTC_HWCR) |
| 178 | #define REG_RTC_HWRSR REG32(RTC_HWRSR) |
| 179 | #define REG_RTC_HSPR REG32(RTC_HSPR) |
| 180 | |
| 181 | /* RTC Control Register */ |
| 182 | #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ |
| 183 | #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ |
| 184 | #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ |
| 185 | #define RTC_RCR_AF (1 << 4) /* Alarm Flag */ |
| 186 | #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ |
| 187 | #define RTC_RCR_AE (1 << 2) /* Alarm Enable */ |
| 188 | #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ |
| 189 | |
| 190 | /* RTC Regulator Register */ |
| 191 | #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ |
| 192 | #define RTC_RGR_ADJC_BIT 16 |
| 193 | #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) |
| 194 | #define RTC_RGR_NC1HZ_BIT 0 |
| 195 | #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) |
| 196 | |
| 197 | /* Hibernate Control Register */ |
| 198 | #define RTC_HCR_PD (1 << 0) /* Power Down */ |
| 199 | |
| 200 | /* Hibernate Wakeup Filter Counter Register */ |
| 201 | #define RTC_HWFCR_BIT 5 |
| 202 | #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) |
| 203 | |
| 204 | /* Hibernate Reset Counter Register */ |
| 205 | #define RTC_HRCR_BIT 5 |
| 206 | #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) |
| 207 | |
| 208 | /* Hibernate Wakeup Control Register */ |
| 209 | #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ |
| 210 | |
| 211 | /* Hibernate Wakeup Status Register */ |
| 212 | #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ |
| 213 | #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ |
| 214 | #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ |
| 215 | #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ |
| 216 | |
| 217 | |
| 218 | /************************************************************************* |
| 219 | * CPM (Clock reset and Power control Management) |
| 220 | *************************************************************************/ |
| 221 | #define CPM_CPCCR (CPM_BASE+0x00) |
| 222 | #define CPM_CPPCR (CPM_BASE+0x10) |
| 223 | #define CPM_I2SCDR (CPM_BASE+0x60) |
| 224 | #define CPM_LPCDR (CPM_BASE+0x64) |
| 225 | #define CPM_MSCCDR (CPM_BASE+0x68) |
| 226 | #define CPM_UHCCDR (CPM_BASE+0x6C) |
| 227 | |
| 228 | #define CPM_LCR (CPM_BASE+0x04) |
| 229 | #define CPM_CLKGR (CPM_BASE+0x20) |
| 230 | #define CPM_SCR (CPM_BASE+0x24) |
| 231 | |
| 232 | #define CPM_HCR (CPM_BASE+0x30) |
| 233 | #define CPM_HWFCR (CPM_BASE+0x34) |
| 234 | #define CPM_HRCR (CPM_BASE+0x38) |
| 235 | #define CPM_HWCR (CPM_BASE+0x3c) |
| 236 | #define CPM_HWSR (CPM_BASE+0x40) |
| 237 | #define CPM_HSPR (CPM_BASE+0x44) |
| 238 | |
| 239 | #define CPM_RSR (CPM_BASE+0x08) |
| 240 | |
| 241 | |
| 242 | #define REG_CPM_CPCCR REG32(CPM_CPCCR) |
| 243 | #define REG_CPM_CPPCR REG32(CPM_CPPCR) |
| 244 | #define REG_CPM_I2SCDR REG32(CPM_I2SCDR) |
| 245 | #define REG_CPM_LPCDR REG32(CPM_LPCDR) |
| 246 | #define REG_CPM_MSCCDR REG32(CPM_MSCCDR) |
| 247 | #define REG_CPM_UHCCDR REG32(CPM_UHCCDR) |
| 248 | |
| 249 | #define REG_CPM_LCR REG32(CPM_LCR) |
| 250 | #define REG_CPM_CLKGR REG32(CPM_CLKGR) |
| 251 | #define REG_CPM_SCR REG32(CPM_SCR) |
| 252 | #define REG_CPM_HCR REG32(CPM_HCR) |
| 253 | #define REG_CPM_HWFCR REG32(CPM_HWFCR) |
| 254 | #define REG_CPM_HRCR REG32(CPM_HRCR) |
| 255 | #define REG_CPM_HWCR REG32(CPM_HWCR) |
| 256 | #define REG_CPM_HWSR REG32(CPM_HWSR) |
| 257 | #define REG_CPM_HSPR REG32(CPM_HSPR) |
| 258 | |
| 259 | #define REG_CPM_RSR REG32(CPM_RSR) |
| 260 | |
| 261 | |
| 262 | /* Clock Control Register */ |
| 263 | #define CPM_CPCCR_I2CS (1 << 31) |
| 264 | #define CPM_CPCCR_CLKOEN (1 << 30) |
| 265 | #define CPM_CPCCR_UCS (1 << 29) |
| 266 | #define CPM_CPCCR_UDIV_BIT 23 |
| 267 | #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) |
| 268 | #define CPM_CPCCR_CE (1 << 22) |
| 269 | #define CPM_CPCCR_PCS (1 << 21) |
| 270 | #define CPM_CPCCR_LDIV_BIT 16 |
| 271 | #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) |
| 272 | #define CPM_CPCCR_MDIV_BIT 12 |
| 273 | #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) |
| 274 | #define CPM_CPCCR_PDIV_BIT 8 |
| 275 | #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) |
| 276 | #define CPM_CPCCR_HDIV_BIT 4 |
| 277 | #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) |
| 278 | #define CPM_CPCCR_CDIV_BIT 0 |
| 279 | #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) |
| 280 | |
| 281 | /* I2S Clock Divider Register */ |
| 282 | #define CPM_I2SCDR_I2SDIV_BIT 0 |
| 283 | #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) |
| 284 | |
| 285 | /* LCD Pixel Clock Divider Register */ |
| 286 | #define CPM_LPCDR_PIXDIV_BIT 0 |
| 287 | #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) |
| 288 | |
| 289 | /* MSC Clock Divider Register */ |
| 290 | #define CPM_MSCCDR_MSCDIV_BIT 0 |
| 291 | #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) |
| 292 | |
| 293 | /* PLL Control Register */ |
| 294 | #define CPM_CPPCR_PLLM_BIT 23 |
| 295 | #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) |
| 296 | #define CPM_CPPCR_PLLN_BIT 18 |
| 297 | #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) |
| 298 | #define CPM_CPPCR_PLLOD_BIT 16 |
| 299 | #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) |
| 300 | #define CPM_CPPCR_PLLS (1 << 10) |
| 301 | #define CPM_CPPCR_PLLBP (1 << 9) |
| 302 | #define CPM_CPPCR_PLLEN (1 << 8) |
| 303 | #define CPM_CPPCR_PLLST_BIT 0 |
| 304 | #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) |
| 305 | |
| 306 | /* Low Power Control Register */ |
| 307 | #define CPM_LCR_DOZE_DUTY_BIT 3 |
| 308 | #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) |
| 309 | #define CPM_LCR_DOZE_ON (1 << 2) |
| 310 | #define CPM_LCR_LPM_BIT 0 |
| 311 | #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) |
| 312 | #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) |
| 313 | #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) |
| 314 | |
| 315 | /* Clock Gate Register */ |
| 316 | #define CPM_CLKGR_UART1 (1 << 15) |
| 317 | #define CPM_CLKGR_UHC (1 << 14) |
| 318 | #define CPM_CLKGR_IPU (1 << 13) |
| 319 | #define CPM_CLKGR_DMAC (1 << 12) |
| 320 | #define CPM_CLKGR_UDC (1 << 11) |
| 321 | #define CPM_CLKGR_LCD (1 << 10) |
| 322 | #define CPM_CLKGR_CIM (1 << 9) |
| 323 | #define CPM_CLKGR_SADC (1 << 8) |
| 324 | #define CPM_CLKGR_MSC (1 << 7) |
| 325 | #define CPM_CLKGR_AIC1 (1 << 6) |
| 326 | #define CPM_CLKGR_AIC2 (1 << 5) |
| 327 | #define CPM_CLKGR_SSI (1 << 4) |
| 328 | #define CPM_CLKGR_I2C (1 << 3) |
| 329 | #define CPM_CLKGR_RTC (1 << 2) |
| 330 | #define CPM_CLKGR_TCU (1 << 1) |
| 331 | #define CPM_CLKGR_UART0 (1 << 0) |
| 332 | |
| 333 | /* Sleep Control Register */ |
| 334 | #define CPM_SCR_O1ST_BIT 8 |
| 335 | #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) |
| 336 | #define CPM_SCR_USBPHY_ENABLE (1 << 6) |
| 337 | #define CPM_SCR_OSC_ENABLE (1 << 4) |
| 338 | |
| 339 | /* Hibernate Control Register */ |
| 340 | #define CPM_HCR_PD (1 << 0) |
| 341 | |
| 342 | /* Wakeup Filter Counter Register in Hibernate Mode */ |
| 343 | #define CPM_HWFCR_TIME_BIT 0 |
| 344 | #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) |
| 345 | |
| 346 | /* Reset Counter Register in Hibernate Mode */ |
| 347 | #define CPM_HRCR_TIME_BIT 0 |
| 348 | #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) |
| 349 | |
| 350 | /* Wakeup Control Register in Hibernate Mode */ |
| 351 | #define CPM_HWCR_WLE_LOW (0 << 2) |
| 352 | #define CPM_HWCR_WLE_HIGH (1 << 2) |
| 353 | #define CPM_HWCR_PIN_WAKEUP (1 << 1) |
| 354 | #define CPM_HWCR_RTC_WAKEUP (1 << 0) |
| 355 | |
| 356 | /* Wakeup Status Register in Hibernate Mode */ |
| 357 | #define CPM_HWSR_WSR_PIN (1 << 1) |
| 358 | #define CPM_HWSR_WSR_RTC (1 << 0) |
| 359 | |
| 360 | /* Reset Status Register */ |
| 361 | #define CPM_RSR_HR (1 << 2) |
| 362 | #define CPM_RSR_WR (1 << 1) |
| 363 | #define CPM_RSR_PR (1 << 0) |
| 364 | |
| 365 | |
| 366 | /************************************************************************* |
| 367 | * TCU (Timer Counter Unit) |
| 368 | *************************************************************************/ |
| 369 | #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ |
| 370 | #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ |
| 371 | #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ |
| 372 | #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ |
| 373 | #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ |
| 374 | #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ |
| 375 | #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ |
| 376 | #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ |
| 377 | #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ |
| 378 | #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ |
| 379 | #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ |
| 380 | #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ |
| 381 | #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ |
| 382 | #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ |
| 383 | #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ |
| 384 | #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ |
| 385 | #define TCU_TDFR1 (TCU_BASE + 0x50) |
| 386 | #define TCU_TDHR1 (TCU_BASE + 0x54) |
| 387 | #define TCU_TCNT1 (TCU_BASE + 0x58) |
| 388 | #define TCU_TCSR1 (TCU_BASE + 0x5C) |
| 389 | #define TCU_TDFR2 (TCU_BASE + 0x60) |
| 390 | #define TCU_TDHR2 (TCU_BASE + 0x64) |
| 391 | #define TCU_TCNT2 (TCU_BASE + 0x68) |
| 392 | #define TCU_TCSR2 (TCU_BASE + 0x6C) |
| 393 | #define TCU_TDFR3 (TCU_BASE + 0x70) |
| 394 | #define TCU_TDHR3 (TCU_BASE + 0x74) |
| 395 | #define TCU_TCNT3 (TCU_BASE + 0x78) |
| 396 | #define TCU_TCSR3 (TCU_BASE + 0x7C) |
| 397 | #define TCU_TDFR4 (TCU_BASE + 0x80) |
| 398 | #define TCU_TDHR4 (TCU_BASE + 0x84) |
| 399 | #define TCU_TCNT4 (TCU_BASE + 0x88) |
| 400 | #define TCU_TCSR4 (TCU_BASE + 0x8C) |
| 401 | #define TCU_TDFR5 (TCU_BASE + 0x90) |
| 402 | #define TCU_TDHR5 (TCU_BASE + 0x94) |
| 403 | #define TCU_TCNT5 (TCU_BASE + 0x98) |
| 404 | #define TCU_TCSR5 (TCU_BASE + 0x9C) |
| 405 | |
| 406 | #define REG_TCU_TSR REG32(TCU_TSR) |
| 407 | #define REG_TCU_TSSR REG32(TCU_TSSR) |
| 408 | #define REG_TCU_TSCR REG32(TCU_TSCR) |
| 409 | #define REG_TCU_TER REG8(TCU_TER) |
| 410 | #define REG_TCU_TESR REG8(TCU_TESR) |
| 411 | #define REG_TCU_TECR REG8(TCU_TECR) |
| 412 | #define REG_TCU_TFR REG32(TCU_TFR) |
| 413 | #define REG_TCU_TFSR REG32(TCU_TFSR) |
| 414 | #define REG_TCU_TFCR REG32(TCU_TFCR) |
| 415 | #define REG_TCU_TMR REG32(TCU_TMR) |
| 416 | #define REG_TCU_TMSR REG32(TCU_TMSR) |
| 417 | #define REG_TCU_TMCR REG32(TCU_TMCR) |
| 418 | #define REG_TCU_TDFR0 REG16(TCU_TDFR0) |
| 419 | #define REG_TCU_TDHR0 REG16(TCU_TDHR0) |
| 420 | #define REG_TCU_TCNT0 REG16(TCU_TCNT0) |
| 421 | #define REG_TCU_TCSR0 REG16(TCU_TCSR0) |
| 422 | #define REG_TCU_TDFR1 REG16(TCU_TDFR1) |
| 423 | #define REG_TCU_TDHR1 REG16(TCU_TDHR1) |
| 424 | #define REG_TCU_TCNT1 REG16(TCU_TCNT1) |
| 425 | #define REG_TCU_TCSR1 REG16(TCU_TCSR1) |
| 426 | #define REG_TCU_TDFR2 REG16(TCU_TDFR2) |
| 427 | #define REG_TCU_TDHR2 REG16(TCU_TDHR2) |
| 428 | #define REG_TCU_TCNT2 REG16(TCU_TCNT2) |
| 429 | #define REG_TCU_TCSR2 REG16(TCU_TCSR2) |
| 430 | #define REG_TCU_TDFR3 REG16(TCU_TDFR3) |
| 431 | #define REG_TCU_TDHR3 REG16(TCU_TDHR3) |
| 432 | #define REG_TCU_TCNT3 REG16(TCU_TCNT3) |
| 433 | #define REG_TCU_TCSR3 REG16(TCU_TCSR3) |
| 434 | #define REG_TCU_TDFR4 REG16(TCU_TDFR4) |
| 435 | #define REG_TCU_TDHR4 REG16(TCU_TDHR4) |
| 436 | #define REG_TCU_TCNT4 REG16(TCU_TCNT4) |
| 437 | #define REG_TCU_TCSR4 REG16(TCU_TCSR4) |
| 438 | |
| 439 | /* n = 0,1,2,3,4,5 */ |
| 440 | #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ |
| 441 | #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ |
| 442 | #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ |
| 443 | #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ |
| 444 | |
| 445 | #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) |
| 446 | #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) |
| 447 | #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) |
| 448 | #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) |
| 449 | |
| 450 | /* Register definitions */ |
| 451 | #define TCU_TCSR_PWM_SD (1 << 9) |
| 452 | #define TCU_TCSR_PWM_INITL_HIGH (1 << 8) |
| 453 | #define TCU_TCSR_PWM_EN (1 << 7) |
| 454 | #define TCU_TCSR_PRESCALE_BIT 3 |
| 455 | #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) |
| 456 | #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) |
| 457 | #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) |
| 458 | #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) |
| 459 | #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) |
| 460 | #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) |
| 461 | #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) |
| 462 | #define TCU_TCSR_EXT_EN (1 << 2) |
| 463 | #define TCU_TCSR_RTC_EN (1 << 1) |
| 464 | #define TCU_TCSR_PCK_EN (1 << 0) |
| 465 | |
| 466 | #define TCU_TER_TCEN5 (1 << 5) |
| 467 | #define TCU_TER_TCEN4 (1 << 4) |
| 468 | #define TCU_TER_TCEN3 (1 << 3) |
| 469 | #define TCU_TER_TCEN2 (1 << 2) |
| 470 | #define TCU_TER_TCEN1 (1 << 1) |
| 471 | #define TCU_TER_TCEN0 (1 << 0) |
| 472 | |
| 473 | #define TCU_TESR_TCST5 (1 << 5) |
| 474 | #define TCU_TESR_TCST4 (1 << 4) |
| 475 | #define TCU_TESR_TCST3 (1 << 3) |
| 476 | #define TCU_TESR_TCST2 (1 << 2) |
| 477 | #define TCU_TESR_TCST1 (1 << 1) |
| 478 | #define TCU_TESR_TCST0 (1 << 0) |
| 479 | |
| 480 | #define TCU_TECR_TCCL5 (1 << 5) |
| 481 | #define TCU_TECR_TCCL4 (1 << 4) |
| 482 | #define TCU_TECR_TCCL3 (1 << 3) |
| 483 | #define TCU_TECR_TCCL2 (1 << 2) |
| 484 | #define TCU_TECR_TCCL1 (1 << 1) |
| 485 | #define TCU_TECR_TCCL0 (1 << 0) |
| 486 | |
| 487 | #define TCU_TFR_HFLAG5 (1 << 21) |
| 488 | #define TCU_TFR_HFLAG4 (1 << 20) |
| 489 | #define TCU_TFR_HFLAG3 (1 << 19) |
| 490 | #define TCU_TFR_HFLAG2 (1 << 18) |
| 491 | #define TCU_TFR_HFLAG1 (1 << 17) |
| 492 | #define TCU_TFR_HFLAG0 (1 << 16) |
| 493 | #define TCU_TFR_FFLAG5 (1 << 5) |
| 494 | #define TCU_TFR_FFLAG4 (1 << 4) |
| 495 | #define TCU_TFR_FFLAG3 (1 << 3) |
| 496 | #define TCU_TFR_FFLAG2 (1 << 2) |
| 497 | #define TCU_TFR_FFLAG1 (1 << 1) |
| 498 | #define TCU_TFR_FFLAG0 (1 << 0) |
| 499 | |
| 500 | #define TCU_TFSR_HFLAG5 (1 << 21) |
| 501 | #define TCU_TFSR_HFLAG4 (1 << 20) |
| 502 | #define TCU_TFSR_HFLAG3 (1 << 19) |
| 503 | #define TCU_TFSR_HFLAG2 (1 << 18) |
| 504 | #define TCU_TFSR_HFLAG1 (1 << 17) |
| 505 | #define TCU_TFSR_HFLAG0 (1 << 16) |
| 506 | #define TCU_TFSR_FFLAG5 (1 << 5) |
| 507 | #define TCU_TFSR_FFLAG4 (1 << 4) |
| 508 | #define TCU_TFSR_FFLAG3 (1 << 3) |
| 509 | #define TCU_TFSR_FFLAG2 (1 << 2) |
| 510 | #define TCU_TFSR_FFLAG1 (1 << 1) |
| 511 | #define TCU_TFSR_FFLAG0 (1 << 0) |
| 512 | |
| 513 | #define TCU_TFCR_HFLAG5 (1 << 21) |
| 514 | #define TCU_TFCR_HFLAG4 (1 << 20) |
| 515 | #define TCU_TFCR_HFLAG3 (1 << 19) |
| 516 | #define TCU_TFCR_HFLAG2 (1 << 18) |
| 517 | #define TCU_TFCR_HFLAG1 (1 << 17) |
| 518 | #define TCU_TFCR_HFLAG0 (1 << 16) |
| 519 | #define TCU_TFCR_FFLAG5 (1 << 5) |
| 520 | #define TCU_TFCR_FFLAG4 (1 << 4) |
| 521 | #define TCU_TFCR_FFLAG3 (1 << 3) |
| 522 | #define TCU_TFCR_FFLAG2 (1 << 2) |
| 523 | #define TCU_TFCR_FFLAG1 (1 << 1) |
| 524 | #define TCU_TFCR_FFLAG0 (1 << 0) |
| 525 | |
| 526 | #define TCU_TMR_HMASK5 (1 << 21) |
| 527 | #define TCU_TMR_HMASK4 (1 << 20) |
| 528 | #define TCU_TMR_HMASK3 (1 << 19) |
| 529 | #define TCU_TMR_HMASK2 (1 << 18) |
| 530 | #define TCU_TMR_HMASK1 (1 << 17) |
| 531 | #define TCU_TMR_HMASK0 (1 << 16) |
| 532 | #define TCU_TMR_FMASK5 (1 << 5) |
| 533 | #define TCU_TMR_FMASK4 (1 << 4) |
| 534 | #define TCU_TMR_FMASK3 (1 << 3) |
| 535 | #define TCU_TMR_FMASK2 (1 << 2) |
| 536 | #define TCU_TMR_FMASK1 (1 << 1) |
| 537 | #define TCU_TMR_FMASK0 (1 << 0) |
| 538 | |
| 539 | #define TCU_TMSR_HMST5 (1 << 21) |
| 540 | #define TCU_TMSR_HMST4 (1 << 20) |
| 541 | #define TCU_TMSR_HMST3 (1 << 19) |
| 542 | #define TCU_TMSR_HMST2 (1 << 18) |
| 543 | #define TCU_TMSR_HMST1 (1 << 17) |
| 544 | #define TCU_TMSR_HMST0 (1 << 16) |
| 545 | #define TCU_TMSR_FMST5 (1 << 5) |
| 546 | #define TCU_TMSR_FMST4 (1 << 4) |
| 547 | #define TCU_TMSR_FMST3 (1 << 3) |
| 548 | #define TCU_TMSR_FMST2 (1 << 2) |
| 549 | #define TCU_TMSR_FMST1 (1 << 1) |
| 550 | #define TCU_TMSR_FMST0 (1 << 0) |
| 551 | |
| 552 | #define TCU_TMCR_HMCL5 (1 << 21) |
| 553 | #define TCU_TMCR_HMCL4 (1 << 20) |
| 554 | #define TCU_TMCR_HMCL3 (1 << 19) |
| 555 | #define TCU_TMCR_HMCL2 (1 << 18) |
| 556 | #define TCU_TMCR_HMCL1 (1 << 17) |
| 557 | #define TCU_TMCR_HMCL0 (1 << 16) |
| 558 | #define TCU_TMCR_FMCL5 (1 << 5) |
| 559 | #define TCU_TMCR_FMCL4 (1 << 4) |
| 560 | #define TCU_TMCR_FMCL3 (1 << 3) |
| 561 | #define TCU_TMCR_FMCL2 (1 << 2) |
| 562 | #define TCU_TMCR_FMCL1 (1 << 1) |
| 563 | #define TCU_TMCR_FMCL0 (1 << 0) |
| 564 | |
| 565 | #define TCU_TSR_WDTS (1 << 16) |
| 566 | #define TCU_TSR_STOP5 (1 << 5) |
| 567 | #define TCU_TSR_STOP4 (1 << 4) |
| 568 | #define TCU_TSR_STOP3 (1 << 3) |
| 569 | #define TCU_TSR_STOP2 (1 << 2) |
| 570 | #define TCU_TSR_STOP1 (1 << 1) |
| 571 | #define TCU_TSR_STOP0 (1 << 0) |
| 572 | |
| 573 | #define TCU_TSSR_WDTSS (1 << 16) |
| 574 | #define TCU_TSSR_STPS5 (1 << 5) |
| 575 | #define TCU_TSSR_STPS4 (1 << 4) |
| 576 | #define TCU_TSSR_STPS3 (1 << 3) |
| 577 | #define TCU_TSSR_STPS2 (1 << 2) |
| 578 | #define TCU_TSSR_STPS1 (1 << 1) |
| 579 | #define TCU_TSSR_STPS0 (1 << 0) |
| 580 | |
| 581 | #define TCU_TSSR_WDTSC (1 << 16) |
| 582 | #define TCU_TSSR_STPC5 (1 << 5) |
| 583 | #define TCU_TSSR_STPC4 (1 << 4) |
| 584 | #define TCU_TSSR_STPC3 (1 << 3) |
| 585 | #define TCU_TSSR_STPC2 (1 << 2) |
| 586 | #define TCU_TSSR_STPC1 (1 << 1) |
| 587 | #define TCU_TSSR_STPC0 (1 << 0) |
| 588 | |
| 589 | |
| 590 | /************************************************************************* |
| 591 | * WDT (WatchDog Timer) |
| 592 | *************************************************************************/ |
| 593 | #define WDT_TDR (WDT_BASE + 0x00) |
| 594 | #define WDT_TCER (WDT_BASE + 0x04) |
| 595 | #define WDT_TCNT (WDT_BASE + 0x08) |
| 596 | #define WDT_TCSR (WDT_BASE + 0x0C) |
| 597 | |
| 598 | #define REG_WDT_TDR REG16(WDT_TDR) |
| 599 | #define REG_WDT_TCER REG8(WDT_TCER) |
| 600 | #define REG_WDT_TCNT REG16(WDT_TCNT) |
| 601 | #define REG_WDT_TCSR REG16(WDT_TCSR) |
| 602 | |
| 603 | /* Register definition */ |
| 604 | #define WDT_TCSR_PRESCALE_BIT 3 |
| 605 | #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) |
| 606 | #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) |
| 607 | #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) |
| 608 | #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) |
| 609 | #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) |
| 610 | #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) |
| 611 | #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) |
| 612 | #define WDT_TCSR_EXT_EN (1 << 2) |
| 613 | #define WDT_TCSR_RTC_EN (1 << 1) |
| 614 | #define WDT_TCSR_PCK_EN (1 << 0) |
| 615 | |
| 616 | #define WDT_TCER_TCEN (1 << 0) |
| 617 | |
| 618 | |
| 619 | /************************************************************************* |
| 620 | * DMAC (DMA Controller) |
| 621 | *************************************************************************/ |
| 622 | |
| 623 | #define MAX_DMA_NUM 6 /* max 6 channels */ |
| 624 | |
| 625 | #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ |
| 626 | #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ |
| 627 | #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ |
| 628 | #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ |
| 629 | #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ |
| 630 | #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ |
| 631 | #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ |
| 632 | #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ |
| 633 | #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ |
| 634 | #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ |
| 635 | #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ |
| 636 | |
| 637 | /* channel 0 */ |
| 638 | #define DMAC_DSAR0 DMAC_DSAR(0) |
| 639 | #define DMAC_DTAR0 DMAC_DTAR(0) |
| 640 | #define DMAC_DTCR0 DMAC_DTCR(0) |
| 641 | #define DMAC_DRSR0 DMAC_DRSR(0) |
| 642 | #define DMAC_DCCSR0 DMAC_DCCSR(0) |
| 643 | #define DMAC_DCMD0 DMAC_DCMD(0) |
| 644 | #define DMAC_DDA0 DMAC_DDA(0) |
| 645 | |
| 646 | /* channel 1 */ |
| 647 | #define DMAC_DSAR1 DMAC_DSAR(1) |
| 648 | #define DMAC_DTAR1 DMAC_DTAR(1) |
| 649 | #define DMAC_DTCR1 DMAC_DTCR(1) |
| 650 | #define DMAC_DRSR1 DMAC_DRSR(1) |
| 651 | #define DMAC_DCCSR1 DMAC_DCCSR(1) |
| 652 | #define DMAC_DCMD1 DMAC_DCMD(1) |
| 653 | #define DMAC_DDA1 DMAC_DDA(1) |
| 654 | |
| 655 | /* channel 2 */ |
| 656 | #define DMAC_DSAR2 DMAC_DSAR(2) |
| 657 | #define DMAC_DTAR2 DMAC_DTAR(2) |
| 658 | #define DMAC_DTCR2 DMAC_DTCR(2) |
| 659 | #define DMAC_DRSR2 DMAC_DRSR(2) |
| 660 | #define DMAC_DCCSR2 DMAC_DCCSR(2) |
| 661 | #define DMAC_DCMD2 DMAC_DCMD(2) |
| 662 | #define DMAC_DDA2 DMAC_DDA(2) |
| 663 | |
| 664 | /* channel 3 */ |
| 665 | #define DMAC_DSAR3 DMAC_DSAR(3) |
| 666 | #define DMAC_DTAR3 DMAC_DTAR(3) |
| 667 | #define DMAC_DTCR3 DMAC_DTCR(3) |
| 668 | #define DMAC_DRSR3 DMAC_DRSR(3) |
| 669 | #define DMAC_DCCSR3 DMAC_DCCSR(3) |
| 670 | #define DMAC_DCMD3 DMAC_DCMD(3) |
| 671 | #define DMAC_DDA3 DMAC_DDA(3) |
| 672 | |
| 673 | /* channel 4 */ |
| 674 | #define DMAC_DSAR4 DMAC_DSAR(4) |
| 675 | #define DMAC_DTAR4 DMAC_DTAR(4) |
| 676 | #define DMAC_DTCR4 DMAC_DTCR(4) |
| 677 | #define DMAC_DRSR4 DMAC_DRSR(4) |
| 678 | #define DMAC_DCCSR4 DMAC_DCCSR(4) |
| 679 | #define DMAC_DCMD4 DMAC_DCMD(4) |
| 680 | #define DMAC_DDA4 DMAC_DDA(4) |
| 681 | |
| 682 | /* channel 5 */ |
| 683 | #define DMAC_DSAR5 DMAC_DSAR(5) |
| 684 | #define DMAC_DTAR5 DMAC_DTAR(5) |
| 685 | #define DMAC_DTCR5 DMAC_DTCR(5) |
| 686 | #define DMAC_DRSR5 DMAC_DRSR(5) |
| 687 | #define DMAC_DCCSR5 DMAC_DCCSR(5) |
| 688 | #define DMAC_DCMD5 DMAC_DCMD(5) |
| 689 | #define DMAC_DDA5 DMAC_DDA(5) |
| 690 | |
| 691 | #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) |
| 692 | #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) |
| 693 | #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) |
| 694 | #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) |
| 695 | #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) |
| 696 | #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) |
| 697 | #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) |
| 698 | #define REG_DMAC_DMACR REG32(DMAC_DMACR) |
| 699 | #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) |
| 700 | #define REG_DMAC_DMADBR REG32(DMAC_DMADBR) |
| 701 | #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) |
| 702 | |
| 703 | /* DMA request source register */ |
| 704 | #define DMAC_DRSR_RS_BIT 0 |
| 705 | #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) |
| 706 | #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) |
| 707 | #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) |
| 708 | #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) |
| 709 | #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) |
| 710 | #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) |
| 711 | #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) |
| 712 | #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) |
| 713 | #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) |
| 714 | #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) |
| 715 | #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) |
| 716 | #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) |
| 717 | #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) |
| 718 | |
| 719 | /* DMA channel control/status register */ |
| 720 | #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ |
| 721 | #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ |
| 722 | #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) |
| 723 | #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ |
| 724 | #define DMAC_DCCSR_AR (1 << 4) /* address error */ |
| 725 | #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ |
| 726 | #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ |
| 727 | #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ |
| 728 | #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ |
| 729 | |
| 730 | /* DMA channel command register */ |
| 731 | #define DMAC_DCMD_SAI (1 << 23) /* source address increment */ |
| 732 | #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ |
| 733 | #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ |
| 734 | #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) |
| 735 | #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) |
| 736 | #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) |
| 737 | #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) |
| 738 | #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) |
| 739 | #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) |
| 740 | #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) |
| 741 | #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) |
| 742 | #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) |
| 743 | #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) |
| 744 | #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) |
| 745 | #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) |
| 746 | #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) |
| 747 | #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) |
| 748 | #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) |
| 749 | #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) |
| 750 | #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) |
| 751 | #define DMAC_DCMD_SWDH_BIT 14 /* source port width */ |
| 752 | #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) |
| 753 | #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) |
| 754 | #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) |
| 755 | #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) |
| 756 | #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ |
| 757 | #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) |
| 758 | #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) |
| 759 | #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) |
| 760 | #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) |
| 761 | #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ |
| 762 | #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) |
| 763 | #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) |
| 764 | #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) |
| 765 | #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) |
| 766 | #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) |
| 767 | #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) |
| 768 | #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ |
| 769 | #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ |
| 770 | #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ |
| 771 | #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ |
| 772 | #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ |
| 773 | #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ |
| 774 | |
| 775 | /* DMA descriptor address register */ |
| 776 | #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ |
| 777 | #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) |
| 778 | #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ |
| 779 | #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) |
| 780 | |
| 781 | /* DMA control register */ |
| 782 | #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ |
| 783 | #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) |
| 784 | #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) |
| 785 | #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) |
| 786 | #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) |
| 787 | #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ |
| 788 | #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ |
| 789 | #define DMAC_DMACR_AR (1 << 2) /* address error flag */ |
| 790 | #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ |
| 791 | |
| 792 | /* DMA doorbell register */ |
| 793 | #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ |
| 794 | #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ |
| 795 | #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ |
| 796 | #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ |
| 797 | #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ |
| 798 | #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ |
| 799 | |
| 800 | /* DMA doorbell set register */ |
| 801 | #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ |
| 802 | #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ |
| 803 | #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ |
| 804 | #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ |
| 805 | #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ |
| 806 | #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ |
| 807 | |
| 808 | /* DMA interrupt pending register */ |
| 809 | #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ |
| 810 | #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ |
| 811 | #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ |
| 812 | #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ |
| 813 | #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ |
| 814 | #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ |
| 815 | |
| 816 | |
| 817 | /************************************************************************* |
| 818 | * GPIO (General-Purpose I/O Ports) |
| 819 | *************************************************************************/ |
| 820 | #define MAX_GPIO_NUM 128 |
| 821 | |
| 822 | /*n = 0,1,2,3 */ |
| 823 | #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ |
| 824 | #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ |
| 825 | #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ |
| 826 | #define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ |
| 827 | #define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ |
| 828 | #define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ |
| 829 | #define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ |
| 830 | #define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ |
| 831 | #define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ |
| 832 | #define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ |
| 833 | #define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ |
| 834 | #define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ |
| 835 | #define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ |
| 836 | #define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ |
| 837 | #define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ |
| 838 | #define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ |
| 839 | #define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ |
| 840 | #define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ |
| 841 | #define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ |
| 842 | #define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ |
| 843 | #define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ |
| 844 | #define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ |
| 845 | #define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ |
| 846 | #define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */ |
| 847 | |
| 848 | #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ |
| 849 | #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ |
| 850 | #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) |
| 851 | #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) |
| 852 | #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ |
| 853 | #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) |
| 854 | #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) |
| 855 | #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ |
| 856 | #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) |
| 857 | #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) |
| 858 | #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ |
| 859 | #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) |
| 860 | #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) |
| 861 | #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ |
| 862 | #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) |
| 863 | #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) |
| 864 | #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ |
| 865 | #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) |
| 866 | #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) |
| 867 | #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ |
| 868 | #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) |
| 869 | #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) |
| 870 | #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ |
| 871 | #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */ |
| 872 | |
| 873 | |
| 874 | /************************************************************************* |
| 875 | * UART |
| 876 | *************************************************************************/ |
| 877 | |
| 878 | #define IRDA_BASE UART0_BASE |
| 879 | /*#define UART_BASE UART0_BASE */ |
| 880 | #define UART_OFF 0x1000 |
| 881 | |
| 882 | /* Register Offset */ |
| 883 | #define OFF_RDR (0x00) /* R 8b H'xx */ |
| 884 | #define OFF_TDR (0x00) /* W 8b H'xx */ |
| 885 | #define OFF_DLLR (0x00) /* RW 8b H'00 */ |
| 886 | #define OFF_DLHR (0x04) /* RW 8b H'00 */ |
| 887 | #define OFF_IER (0x04) /* RW 8b H'00 */ |
| 888 | #define OFF_ISR (0x08) /* R 8b H'01 */ |
| 889 | #define OFF_FCR (0x08) /* W 8b H'00 */ |
| 890 | #define OFF_LCR (0x0C) /* RW 8b H'00 */ |
| 891 | #define OFF_MCR (0x10) /* RW 8b H'00 */ |
| 892 | #define OFF_LSR (0x14) /* R 8b H'00 */ |
| 893 | #define OFF_MSR (0x18) /* R 8b H'00 */ |
| 894 | #define OFF_SPR (0x1C) /* RW 8b H'00 */ |
| 895 | #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ |
| 896 | #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ |
| 897 | #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ |
| 898 | |
| 899 | /* Register Address */ |
| 900 | #define UART0_RDR (UART0_BASE + OFF_RDR) |
| 901 | #define UART0_TDR (UART0_BASE + OFF_TDR) |
| 902 | #define UART0_DLLR (UART0_BASE + OFF_DLLR) |
| 903 | #define UART0_DLHR (UART0_BASE + OFF_DLHR) |
| 904 | #define UART0_IER (UART0_BASE + OFF_IER) |
| 905 | #define UART0_ISR (UART0_BASE + OFF_ISR) |
| 906 | #define UART0_FCR (UART0_BASE + OFF_FCR) |
| 907 | #define UART0_LCR (UART0_BASE + OFF_LCR) |
| 908 | #define UART0_MCR (UART0_BASE + OFF_MCR) |
| 909 | #define UART0_LSR (UART0_BASE + OFF_LSR) |
| 910 | #define UART0_MSR (UART0_BASE + OFF_MSR) |
| 911 | #define UART0_SPR (UART0_BASE + OFF_SPR) |
| 912 | #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) |
| 913 | #define UART0_UMR (UART0_BASE + OFF_UMR) |
| 914 | #define UART0_UACR (UART0_BASE + OFF_UACR) |
| 915 | |
| 916 | /* |
| 917 | * Define macros for UART_IER |
| 918 | * UART Interrupt Enable Register |
| 919 | */ |
| 920 | #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ |
| 921 | #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ |
| 922 | #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ |
| 923 | #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ |
| 924 | #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ |
| 925 | |
| 926 | /* |
| 927 | * Define macros for UART_ISR |
| 928 | * UART Interrupt Status Register |
| 929 | */ |
| 930 | #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ |
| 931 | #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ |
| 932 | #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ |
| 933 | #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ |
| 934 | #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ |
| 935 | #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ |
| 936 | #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ |
| 937 | #define UART_ISR_FFMS_NO_FIFO (0 << 6) |
| 938 | #define UART_ISR_FFMS_FIFO_MODE (3 << 6) |
| 939 | |
| 940 | /* |
| 941 | * Define macros for UART_FCR |
| 942 | * UART FIFO Control Register |
| 943 | */ |
| 944 | #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ |
| 945 | #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ |
| 946 | #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ |
| 947 | #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ |
| 948 | #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ |
| 949 | #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ |
| 950 | #define UART_FCR_RTRG_1 (0 << 6) |
| 951 | #define UART_FCR_RTRG_4 (1 << 6) |
| 952 | #define UART_FCR_RTRG_8 (2 << 6) |
| 953 | #define UART_FCR_RTRG_15 (3 << 6) |
| 954 | |
| 955 | /* |
| 956 | * Define macros for UART_LCR |
| 957 | * UART Line Control Register |
| 958 | */ |
| 959 | #define UART_LCR_WLEN (3 << 0) /* word length */ |
| 960 | #define UART_LCR_WLEN_5 (0 << 0) |
| 961 | #define UART_LCR_WLEN_6 (1 << 0) |
| 962 | #define UART_LCR_WLEN_7 (2 << 0) |
| 963 | #define UART_LCR_WLEN_8 (3 << 0) |
| 964 | #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| 965 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| 966 | #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| 967 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| 968 | #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| 969 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| 970 | |
| 971 | #define UART_LCR_PE (1 << 3) /* 0: parity disable */ |
| 972 | #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ |
| 973 | #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ |
| 974 | #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ |
| 975 | #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ |
| 976 | |
| 977 | /* |
| 978 | * Define macros for UART_LSR |
| 979 | * UART Line Status Register |
| 980 | */ |
| 981 | #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ |
| 982 | #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ |
| 983 | #define UART_LSR_PER (1 << 2) /* 0: no parity error */ |
| 984 | #define UART_LSR_FER (1 << 3) /* 0; no framing error */ |
| 985 | #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ |
| 986 | #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ |
| 987 | #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ |
| 988 | #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ |
| 989 | |
| 990 | /* |
| 991 | * Define macros for UART_MCR |
| 992 | * UART Modem Control Register |
| 993 | */ |
| 994 | #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ |
| 995 | #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ |
| 996 | #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ |
| 997 | #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ |
| 998 | #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ |
| 999 | #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ |
| 1000 | |
| 1001 | /* |
| 1002 | * Define macros for UART_MSR |
| 1003 | * UART Modem Status Register |
| 1004 | */ |
| 1005 | #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ |
| 1006 | #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ |
| 1007 | #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ |
| 1008 | #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ |
| 1009 | #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ |
| 1010 | #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ |
| 1011 | #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ |
| 1012 | #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ |
| 1013 | |
| 1014 | /* |
| 1015 | * Define macros for SIRCR |
| 1016 | * Slow IrDA Control Register |
| 1017 | */ |
| 1018 | #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ |
| 1019 | #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ |
| 1020 | #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length |
| 1021 | 1: 0 pulse width is 1.6us for 115.2Kbps */ |
| 1022 | #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ |
| 1023 | #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ |
| 1024 | |
| 1025 | |
| 1026 | /************************************************************************* |
| 1027 | * AIC (AC97/I2S Controller) |
| 1028 | *************************************************************************/ |
| 1029 | #define AIC_FR (AIC_BASE + 0x000) |
| 1030 | #define AIC_CR (AIC_BASE + 0x004) |
| 1031 | #define AIC_ACCR1 (AIC_BASE + 0x008) |
| 1032 | #define AIC_ACCR2 (AIC_BASE + 0x00C) |
| 1033 | #define AIC_I2SCR (AIC_BASE + 0x010) |
| 1034 | #define AIC_SR (AIC_BASE + 0x014) |
| 1035 | #define AIC_ACSR (AIC_BASE + 0x018) |
| 1036 | #define AIC_I2SSR (AIC_BASE + 0x01C) |
| 1037 | #define AIC_ACCAR (AIC_BASE + 0x020) |
| 1038 | #define AIC_ACCDR (AIC_BASE + 0x024) |
| 1039 | #define AIC_ACSAR (AIC_BASE + 0x028) |
| 1040 | #define AIC_ACSDR (AIC_BASE + 0x02C) |
| 1041 | #define AIC_I2SDIV (AIC_BASE + 0x030) |
| 1042 | #define AIC_DR (AIC_BASE + 0x034) |
| 1043 | |
| 1044 | #define REG_AIC_FR REG32(AIC_FR) |
| 1045 | #define REG_AIC_CR REG32(AIC_CR) |
| 1046 | #define REG_AIC_ACCR1 REG32(AIC_ACCR1) |
| 1047 | #define REG_AIC_ACCR2 REG32(AIC_ACCR2) |
| 1048 | #define REG_AIC_I2SCR REG32(AIC_I2SCR) |
| 1049 | #define REG_AIC_SR REG32(AIC_SR) |
| 1050 | #define REG_AIC_ACSR REG32(AIC_ACSR) |
| 1051 | #define REG_AIC_I2SSR REG32(AIC_I2SSR) |
| 1052 | #define REG_AIC_ACCAR REG32(AIC_ACCAR) |
| 1053 | #define REG_AIC_ACCDR REG32(AIC_ACCDR) |
| 1054 | #define REG_AIC_ACSAR REG32(AIC_ACSAR) |
| 1055 | #define REG_AIC_ACSDR REG32(AIC_ACSDR) |
| 1056 | #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) |
| 1057 | #define REG_AIC_DR REG32(AIC_DR) |
| 1058 | |
| 1059 | /* AIC Controller Configuration Register (AIC_FR) */ |
| 1060 | |
| 1061 | #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ |
| 1062 | #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) |
| 1063 | #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ |
| 1064 | #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) |
| 1065 | #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ |
| 1066 | #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ |
| 1067 | #define AIC_FR_RST (1 << 3) /* AIC registers reset */ |
| 1068 | #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ |
| 1069 | #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ |
| 1070 | #define AIC_FR_ENB (1 << 0) /* AIC enable bit */ |
| 1071 | |
| 1072 | /* AIC Controller Common Control Register (AIC_CR) */ |
| 1073 | |
| 1074 | #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ |
| 1075 | #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) |
| 1076 | #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) |
| 1077 | #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) |
| 1078 | #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) |
| 1079 | #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) |
| 1080 | #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) |
| 1081 | #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ |
| 1082 | #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) |
| 1083 | #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) |
| 1084 | #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) |
| 1085 | #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) |
| 1086 | #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) |
| 1087 | #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) |
| 1088 | #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ |
| 1089 | #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ |
| 1090 | #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ |
| 1091 | #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ |
| 1092 | #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ |
| 1093 | #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ |
| 1094 | #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ |
| 1095 | #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ |
| 1096 | #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ |
| 1097 | #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ |
| 1098 | #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ |
| 1099 | #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ |
| 1100 | #define AIC_CR_EREC (1 << 0) /* Enable Record Function */ |
| 1101 | |
| 1102 | /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ |
| 1103 | |
| 1104 | #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ |
| 1105 | #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) |
| 1106 | #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ |
| 1107 | #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ |
| 1108 | #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ |
| 1109 | #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ |
| 1110 | #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ |
| 1111 | #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ |
| 1112 | #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ |
| 1113 | #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ |
| 1114 | #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ |
| 1115 | #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ |
| 1116 | #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ |
| 1117 | #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) |
| 1118 | #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ |
| 1119 | #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ |
| 1120 | #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ |
| 1121 | #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ |
| 1122 | #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ |
| 1123 | #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ |
| 1124 | #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ |
| 1125 | #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ |
| 1126 | #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ |
| 1127 | #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ |
| 1128 | |
| 1129 | /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ |
| 1130 | |
| 1131 | #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ |
| 1132 | #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ |
| 1133 | #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ |
| 1134 | #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ |
| 1135 | #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) |
| 1136 | #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ |
| 1137 | #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ |
| 1138 | #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ |
| 1139 | #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ |
| 1140 | #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ |
| 1141 | #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) |
| 1142 | #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ |
| 1143 | #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ |
| 1144 | #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ |
| 1145 | #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ |
| 1146 | #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ |
| 1147 | #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ |
| 1148 | #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ |
| 1149 | #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ |
| 1150 | |
| 1151 | /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ |
| 1152 | |
| 1153 | #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ |
| 1154 | #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ |
| 1155 | #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) |
| 1156 | #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ |
| 1157 | #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ |
| 1158 | #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ |
| 1159 | #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ |
| 1160 | #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ |
| 1161 | #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ |
| 1162 | |
| 1163 | /* AIC Controller FIFO Status Register (AIC_SR) */ |
| 1164 | |
| 1165 | #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ |
| 1166 | #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) |
| 1167 | #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ |
| 1168 | #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) |
| 1169 | #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ |
| 1170 | #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ |
| 1171 | #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ |
| 1172 | #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ |
| 1173 | |
| 1174 | /* AIC Controller AC-link Status Register (AIC_ACSR) */ |
| 1175 | |
| 1176 | #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ |
| 1177 | #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ |
| 1178 | #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ |
| 1179 | #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ |
| 1180 | #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ |
| 1181 | #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ |
| 1182 | |
| 1183 | /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ |
| 1184 | |
| 1185 | #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ |
| 1186 | |
| 1187 | /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ |
| 1188 | |
| 1189 | #define AIC_ACCAR_CAR_BIT 0 |
| 1190 | #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) |
| 1191 | |
| 1192 | /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ |
| 1193 | |
| 1194 | #define AIC_ACCDR_CDR_BIT 0 |
| 1195 | #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) |
| 1196 | |
| 1197 | /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ |
| 1198 | |
| 1199 | #define AIC_ACSAR_SAR_BIT 0 |
| 1200 | #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) |
| 1201 | |
| 1202 | /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ |
| 1203 | |
| 1204 | #define AIC_ACSDR_SDR_BIT 0 |
| 1205 | #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) |
| 1206 | |
| 1207 | /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ |
| 1208 | |
| 1209 | #define AIC_I2SDIV_DIV_BIT 0 |
| 1210 | #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) |
| 1211 | #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ |
| 1212 | #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ |
| 1213 | #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ |
| 1214 | #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ |
| 1215 | #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ |
| 1216 | #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ |
| 1217 | |
| 1218 | |
| 1219 | /************************************************************************* |
| 1220 | * ICDC (Internal CODEC) |
| 1221 | *************************************************************************/ |
| 1222 | #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ |
| 1223 | #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ |
| 1224 | #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ |
| 1225 | #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ |
| 1226 | #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ |
| 1227 | #define ICDC_CDCCR1 (ICDC_BASE + 0x0080) |
| 1228 | #define ICDC_CDCCR2 (ICDC_BASE + 0x0084) |
| 1229 | |
| 1230 | #define REG_ICDC_CR REG32(ICDC_CR) |
| 1231 | #define REG_ICDC_APWAIT REG32(ICDC_APWAIT) |
| 1232 | #define REG_ICDC_APPRE REG32(ICDC_APPRE) |
| 1233 | #define REG_ICDC_APHPEN REG32(ICDC_APHPEN) |
| 1234 | #define REG_ICDC_APSR REG32(ICDC_APSR) |
| 1235 | #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) |
| 1236 | #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) |
| 1237 | |
| 1238 | /* ICDC Control Register */ |
| 1239 | #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ |
| 1240 | #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) |
| 1241 | #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ |
| 1242 | #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) |
| 1243 | #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) |
| 1244 | #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) |
| 1245 | #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) |
| 1246 | #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) |
| 1247 | #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) |
| 1248 | #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) |
| 1249 | #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) |
| 1250 | #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) |
| 1251 | #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) |
| 1252 | #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ |
| 1253 | #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) |
| 1254 | #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) |
| 1255 | #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) |
| 1256 | #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) |
| 1257 | #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) |
| 1258 | #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ |
| 1259 | #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) |
| 1260 | #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) |
| 1261 | #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) |
| 1262 | #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) |
| 1263 | #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) |
| 1264 | #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ |
| 1265 | #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ |
| 1266 | #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ |
| 1267 | #define ICDC_CR_EADC (1 << 10) /* Enable ADC */ |
| 1268 | #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ |
| 1269 | #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ |
| 1270 | #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ |
| 1271 | #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ |
| 1272 | #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ |
| 1273 | #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ |
| 1274 | #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ |
| 1275 | #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ |
| 1276 | |
| 1277 | /* Anti-Pop WAIT Stage Timing Control Register */ |
| 1278 | #define ICDC_APWAIT_WAITSN_BIT 0 |
| 1279 | #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) |
| 1280 | |
| 1281 | /* Anti-Pop HPEN-PRE Stage Timing Control Register */ |
| 1282 | #define ICDC_APPRE_PRESN_BIT 0 |
| 1283 | #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) |
| 1284 | |
| 1285 | /* Anti-Pop HPEN Stage Timing Control Register */ |
| 1286 | #define ICDC_APHPEN_HPENSN_BIT 0 |
| 1287 | #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) |
| 1288 | |
| 1289 | /* Anti-Pop Status Register */ |
| 1290 | #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ |
| 1291 | #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) |
| 1292 | #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ |
| 1293 | #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ |
| 1294 | #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ |
| 1295 | #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ |
| 1296 | #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ |
| 1297 | #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ |
| 1298 | #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ |
| 1299 | #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ |
| 1300 | #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ |
| 1301 | #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) |
| 1302 | |
| 1303 | |
| 1304 | /************************************************************************* |
| 1305 | * I2C |
| 1306 | *************************************************************************/ |
| 1307 | #define I2C_DR (I2C_BASE + 0x000) |
| 1308 | #define I2C_CR (I2C_BASE + 0x004) |
| 1309 | #define I2C_SR (I2C_BASE + 0x008) |
| 1310 | #define I2C_GR (I2C_BASE + 0x00C) |
| 1311 | |
| 1312 | #define REG_I2C_DR REG8(I2C_DR) |
| 1313 | #define REG_I2C_CR REG8(I2C_CR) |
| 1314 | #define REG_I2C_SR REG8(I2C_SR) |
| 1315 | #define REG_I2C_GR REG16(I2C_GR) |
| 1316 | |
| 1317 | /* I2C Control Register (I2C_CR) */ |
| 1318 | |
| 1319 | #define I2C_CR_IEN (1 << 4) |
| 1320 | #define I2C_CR_STA (1 << 3) |
| 1321 | #define I2C_CR_STO (1 << 2) |
| 1322 | #define I2C_CR_AC (1 << 1) |
| 1323 | #define I2C_CR_I2CE (1 << 0) |
| 1324 | |
| 1325 | /* I2C Status Register (I2C_SR) */ |
| 1326 | |
| 1327 | #define I2C_SR_STX (1 << 4) |
| 1328 | #define I2C_SR_BUSY (1 << 3) |
| 1329 | #define I2C_SR_TEND (1 << 2) |
| 1330 | #define I2C_SR_DRF (1 << 1) |
| 1331 | #define I2C_SR_ACKF (1 << 0) |
| 1332 | |
| 1333 | |
| 1334 | /************************************************************************* |
| 1335 | * SSI |
| 1336 | *************************************************************************/ |
| 1337 | #define SSI_DR (SSI_BASE + 0x000) |
| 1338 | #define SSI_CR0 (SSI_BASE + 0x004) |
| 1339 | #define SSI_CR1 (SSI_BASE + 0x008) |
| 1340 | #define SSI_SR (SSI_BASE + 0x00C) |
| 1341 | #define SSI_ITR (SSI_BASE + 0x010) |
| 1342 | #define SSI_ICR (SSI_BASE + 0x014) |
| 1343 | #define SSI_GR (SSI_BASE + 0x018) |
| 1344 | |
| 1345 | #define REG_SSI_DR REG32(SSI_DR) |
| 1346 | #define REG_SSI_CR0 REG16(SSI_CR0) |
| 1347 | #define REG_SSI_CR1 REG32(SSI_CR1) |
| 1348 | #define REG_SSI_SR REG32(SSI_SR) |
| 1349 | #define REG_SSI_ITR REG16(SSI_ITR) |
| 1350 | #define REG_SSI_ICR REG8(SSI_ICR) |
| 1351 | #define REG_SSI_GR REG16(SSI_GR) |
| 1352 | |
| 1353 | /* SSI Data Register (SSI_DR) */ |
| 1354 | |
| 1355 | #define SSI_DR_GPC_BIT 0 |
| 1356 | #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) |
| 1357 | |
| 1358 | /* SSI Control Register 0 (SSI_CR0) */ |
| 1359 | |
| 1360 | #define SSI_CR0_SSIE (1 << 15) |
| 1361 | #define SSI_CR0_TIE (1 << 14) |
| 1362 | #define SSI_CR0_RIE (1 << 13) |
| 1363 | #define SSI_CR0_TEIE (1 << 12) |
| 1364 | #define SSI_CR0_REIE (1 << 11) |
| 1365 | #define SSI_CR0_LOOP (1 << 10) |
| 1366 | #define SSI_CR0_RFINE (1 << 9) |
| 1367 | #define SSI_CR0_RFINC (1 << 8) |
| 1368 | #define SSI_CR0_FSEL (1 << 6) |
| 1369 | #define SSI_CR0_TFLUSH (1 << 2) |
| 1370 | #define SSI_CR0_RFLUSH (1 << 1) |
| 1371 | #define SSI_CR0_DISREV (1 << 0) |
| 1372 | |
| 1373 | /* SSI Control Register 1 (SSI_CR1) */ |
| 1374 | |
| 1375 | #define SSI_CR1_FRMHL_BIT 30 |
| 1376 | #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) |
| 1377 | #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ |
| 1378 | #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ |
| 1379 | #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ |
| 1380 | #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ |
| 1381 | #define SSI_CR1_TFVCK_BIT 28 |
| 1382 | #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) |
| 1383 | #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) |
| 1384 | #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) |
| 1385 | #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) |
| 1386 | #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) |
| 1387 | #define SSI_CR1_TCKFI_BIT 26 |
| 1388 | #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) |
| 1389 | #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) |
| 1390 | #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) |
| 1391 | #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) |
| 1392 | #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) |
| 1393 | #define SSI_CR1_LFST (1 << 25) |
| 1394 | #define SSI_CR1_ITFRM (1 << 24) |
| 1395 | #define SSI_CR1_UNFIN (1 << 23) |
| 1396 | #define SSI_CR1_MULTS (1 << 22) |
| 1397 | #define SSI_CR1_FMAT_BIT 20 |
| 1398 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) |
| 1399 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ |
| 1400 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ |
| 1401 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ |
| 1402 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ |
| 1403 | #define SSI_CR1_TTRG_BIT 16 |
| 1404 | #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) |
| 1405 | #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) |
| 1406 | #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) |
| 1407 | #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) |
| 1408 | #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) |
| 1409 | #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) |
| 1410 | #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) |
| 1411 | #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) |
| 1412 | #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) |
| 1413 | #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) |
| 1414 | #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) |
| 1415 | #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) |
| 1416 | #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) |
| 1417 | #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) |
| 1418 | #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) |
| 1419 | #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) |
| 1420 | #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) |
| 1421 | #define SSI_CR1_MCOM_BIT 12 |
| 1422 | #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) |
| 1423 | #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ |
| 1424 | #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ |
| 1425 | #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ |
| 1426 | #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ |
| 1427 | #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ |
| 1428 | #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ |
| 1429 | #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ |
| 1430 | #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ |
| 1431 | #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ |
| 1432 | #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ |
| 1433 | #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ |
| 1434 | #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ |
| 1435 | #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ |
| 1436 | #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ |
| 1437 | #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ |
| 1438 | #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ |
| 1439 | #define SSI_CR1_RTRG_BIT 8 |
| 1440 | #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) |
| 1441 | #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) |
| 1442 | #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) |
| 1443 | #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) |
| 1444 | #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) |
| 1445 | #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) |
| 1446 | #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) |
| 1447 | #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) |
| 1448 | #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) |
| 1449 | #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) |
| 1450 | #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) |
| 1451 | #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) |
| 1452 | #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) |
| 1453 | #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) |
| 1454 | #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) |
| 1455 | #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) |
| 1456 | #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) |
| 1457 | #define SSI_CR1_FLEN_BIT 4 |
| 1458 | #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) |
| 1459 | #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) |
| 1460 | #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) |
| 1461 | #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) |
| 1462 | #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) |
| 1463 | #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) |
| 1464 | #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) |
| 1465 | #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) |
| 1466 | #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) |
| 1467 | #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) |
| 1468 | #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) |
| 1469 | #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) |
| 1470 | #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) |
| 1471 | #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) |
| 1472 | #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) |
| 1473 | #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) |
| 1474 | #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) |
| 1475 | #define SSI_CR1_PHA (1 << 1) |
| 1476 | #define SSI_CR1_POL (1 << 0) |
| 1477 | |
| 1478 | /* SSI Status Register (SSI_SR) */ |
| 1479 | |
| 1480 | #define SSI_SR_TFIFONUM_BIT 16 |
| 1481 | #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) |
| 1482 | #define SSI_SR_RFIFONUM_BIT 8 |
| 1483 | #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) |
| 1484 | #define SSI_SR_END (1 << 7) |
| 1485 | #define SSI_SR_BUSY (1 << 6) |
| 1486 | #define SSI_SR_TFF (1 << 5) |
| 1487 | #define SSI_SR_RFE (1 << 4) |
| 1488 | #define SSI_SR_TFHE (1 << 3) |
| 1489 | #define SSI_SR_RFHF (1 << 2) |
| 1490 | #define SSI_SR_UNDR (1 << 1) |
| 1491 | #define SSI_SR_OVER (1 << 0) |
| 1492 | |
| 1493 | /* SSI Interval Time Control Register (SSI_ITR) */ |
| 1494 | |
| 1495 | #define SSI_ITR_CNTCLK (1 << 15) |
| 1496 | #define SSI_ITR_IVLTM_BIT 0 |
| 1497 | #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) |
| 1498 | |
| 1499 | |
| 1500 | /************************************************************************* |
| 1501 | * MSC |
| 1502 | *************************************************************************/ |
| 1503 | #define MSC_STRPCL (MSC_BASE + 0x000) |
| 1504 | #define MSC_STAT (MSC_BASE + 0x004) |
| 1505 | #define MSC_CLKRT (MSC_BASE + 0x008) |
| 1506 | #define MSC_CMDAT (MSC_BASE + 0x00C) |
| 1507 | #define MSC_RESTO (MSC_BASE + 0x010) |
| 1508 | #define MSC_RDTO (MSC_BASE + 0x014) |
| 1509 | #define MSC_BLKLEN (MSC_BASE + 0x018) |
| 1510 | #define MSC_NOB (MSC_BASE + 0x01C) |
| 1511 | #define MSC_SNOB (MSC_BASE + 0x020) |
| 1512 | #define MSC_IMASK (MSC_BASE + 0x024) |
| 1513 | #define MSC_IREG (MSC_BASE + 0x028) |
| 1514 | #define MSC_CMD (MSC_BASE + 0x02C) |
| 1515 | #define MSC_ARG (MSC_BASE + 0x030) |
| 1516 | #define MSC_RES (MSC_BASE + 0x034) |
| 1517 | #define MSC_RXFIFO (MSC_BASE + 0x038) |
| 1518 | #define MSC_TXFIFO (MSC_BASE + 0x03C) |
| 1519 | |
| 1520 | #define REG_MSC_STRPCL REG16(MSC_STRPCL) |
| 1521 | #define REG_MSC_STAT REG32(MSC_STAT) |
| 1522 | #define REG_MSC_CLKRT REG16(MSC_CLKRT) |
| 1523 | #define REG_MSC_CMDAT REG32(MSC_CMDAT) |
| 1524 | #define REG_MSC_RESTO REG16(MSC_RESTO) |
| 1525 | #define REG_MSC_RDTO REG16(MSC_RDTO) |
| 1526 | #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) |
| 1527 | #define REG_MSC_NOB REG16(MSC_NOB) |
| 1528 | #define REG_MSC_SNOB REG16(MSC_SNOB) |
| 1529 | #define REG_MSC_IMASK REG16(MSC_IMASK) |
| 1530 | #define REG_MSC_IREG REG16(MSC_IREG) |
| 1531 | #define REG_MSC_CMD REG8(MSC_CMD) |
| 1532 | #define REG_MSC_ARG REG32(MSC_ARG) |
| 1533 | #define REG_MSC_RES REG16(MSC_RES) |
| 1534 | #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) |
| 1535 | #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) |
| 1536 | |
| 1537 | /* MSC Clock and Control Register (MSC_STRPCL) */ |
| 1538 | |
| 1539 | #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) |
| 1540 | #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) |
| 1541 | #define MSC_STRPCL_START_READWAIT (1 << 5) |
| 1542 | #define MSC_STRPCL_STOP_READWAIT (1 << 4) |
| 1543 | #define MSC_STRPCL_RESET (1 << 3) |
| 1544 | #define MSC_STRPCL_START_OP (1 << 2) |
| 1545 | #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 |
| 1546 | #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) |
| 1547 | #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ |
| 1548 | #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ |
| 1549 | |
| 1550 | /* MSC Status Register (MSC_STAT) */ |
| 1551 | |
| 1552 | #define MSC_STAT_IS_RESETTING (1 << 15) |
| 1553 | #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) |
| 1554 | #define MSC_STAT_PRG_DONE (1 << 13) |
| 1555 | #define MSC_STAT_DATA_TRAN_DONE (1 << 12) |
| 1556 | #define MSC_STAT_END_CMD_RES (1 << 11) |
| 1557 | #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) |
| 1558 | #define MSC_STAT_IS_READWAIT (1 << 9) |
| 1559 | #define MSC_STAT_CLK_EN (1 << 8) |
| 1560 | #define MSC_STAT_DATA_FIFO_FULL (1 << 7) |
| 1561 | #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) |
| 1562 | #define MSC_STAT_CRC_RES_ERR (1 << 5) |
| 1563 | #define MSC_STAT_CRC_READ_ERROR (1 << 4) |
| 1564 | #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 |
| 1565 | #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) |
| 1566 | #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ |
| 1567 | #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ |
| 1568 | #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ |
| 1569 | #define MSC_STAT_TIME_OUT_RES (1 << 1) |
| 1570 | #define MSC_STAT_TIME_OUT_READ (1 << 0) |
| 1571 | |
| 1572 | /* MSC Bus Clock Control Register (MSC_CLKRT) */ |
| 1573 | |
| 1574 | #define MSC_CLKRT_CLK_RATE_BIT 0 |
| 1575 | #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) |
| 1576 | #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ |
| 1577 | #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ |
| 1578 | #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ |
| 1579 | #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ |
| 1580 | #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ |
| 1581 | #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ |
| 1582 | #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ |
| 1583 | #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ |
| 1584 | |
| 1585 | /* MSC Command Sequence Control Register (MSC_CMDAT) */ |
| 1586 | |
| 1587 | #define MSC_CMDAT_IO_ABORT (1 << 11) |
| 1588 | #define MSC_CMDAT_BUS_WIDTH_BIT 9 |
| 1589 | #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 1590 | #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ |
| 1591 | #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ |
| 1592 | #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 1593 | #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 1594 | #define MSC_CMDAT_DMA_EN (1 << 8) |
| 1595 | #define MSC_CMDAT_INIT (1 << 7) |
| 1596 | #define MSC_CMDAT_BUSY (1 << 6) |
| 1597 | #define MSC_CMDAT_STREAM_BLOCK (1 << 5) |
| 1598 | #define MSC_CMDAT_WRITE (1 << 4) |
| 1599 | #define MSC_CMDAT_READ (0 << 4) |
| 1600 | #define MSC_CMDAT_DATA_EN (1 << 3) |
| 1601 | #define MSC_CMDAT_RESPONSE_BIT 0 |
| 1602 | #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) |
| 1603 | #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ |
| 1604 | #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ |
| 1605 | #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ |
| 1606 | #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ |
| 1607 | #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ |
| 1608 | #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ |
| 1609 | #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ |
| 1610 | |
| 1611 | #define CMDAT_DMA_EN (1 << 8) |
| 1612 | #define CMDAT_INIT (1 << 7) |
| 1613 | #define CMDAT_BUSY (1 << 6) |
| 1614 | #define CMDAT_STREAM (1 << 5) |
| 1615 | #define CMDAT_WRITE (1 << 4) |
| 1616 | #define CMDAT_DATA_EN (1 << 3) |
| 1617 | |
| 1618 | /* MSC Interrupts Mask Register (MSC_IMASK) */ |
| 1619 | |
| 1620 | #define MSC_IMASK_SDIO (1 << 7) |
| 1621 | #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) |
| 1622 | #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) |
| 1623 | #define MSC_IMASK_END_CMD_RES (1 << 2) |
| 1624 | #define MSC_IMASK_PRG_DONE (1 << 1) |
| 1625 | #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) |
| 1626 | |
| 1627 | |
| 1628 | /* MSC Interrupts Status Register (MSC_IREG) */ |
| 1629 | |
| 1630 | #define MSC_IREG_SDIO (1 << 7) |
| 1631 | #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) |
| 1632 | #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) |
| 1633 | #define MSC_IREG_END_CMD_RES (1 << 2) |
| 1634 | #define MSC_IREG_PRG_DONE (1 << 1) |
| 1635 | #define MSC_IREG_DATA_TRAN_DONE (1 << 0) |
| 1636 | |
| 1637 | |
| 1638 | /************************************************************************* |
| 1639 | * EMC (External Memory Controller) |
| 1640 | *************************************************************************/ |
| 1641 | #define EMC_BCR (EMC_BASE + 0x0) /* BCR */ |
| 1642 | |
| 1643 | #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ |
| 1644 | #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ |
| 1645 | #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ |
| 1646 | #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ |
| 1647 | #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ |
| 1648 | #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ |
| 1649 | #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ |
| 1650 | #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ |
| 1651 | #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ |
| 1652 | #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ |
| 1653 | |
| 1654 | #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ |
| 1655 | #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ |
| 1656 | #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ |
| 1657 | #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ |
| 1658 | #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ |
| 1659 | #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ |
| 1660 | #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ |
| 1661 | #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ |
| 1662 | #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ |
| 1663 | #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ |
| 1664 | #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ |
| 1665 | #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ |
| 1666 | |
| 1667 | #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ |
| 1668 | #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ |
| 1669 | #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ |
| 1670 | #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ |
| 1671 | #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ |
| 1672 | #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ |
| 1673 | |
| 1674 | #define REG_EMC_BCR REG32(EMC_BCR) |
| 1675 | |
| 1676 | #define REG_EMC_SMCR0 REG32(EMC_SMCR0) |
| 1677 | #define REG_EMC_SMCR1 REG32(EMC_SMCR1) |
| 1678 | #define REG_EMC_SMCR2 REG32(EMC_SMCR2) |
| 1679 | #define REG_EMC_SMCR3 REG32(EMC_SMCR3) |
| 1680 | #define REG_EMC_SMCR4 REG32(EMC_SMCR4) |
| 1681 | #define REG_EMC_SACR0 REG32(EMC_SACR0) |
| 1682 | #define REG_EMC_SACR1 REG32(EMC_SACR1) |
| 1683 | #define REG_EMC_SACR2 REG32(EMC_SACR2) |
| 1684 | #define REG_EMC_SACR3 REG32(EMC_SACR3) |
| 1685 | #define REG_EMC_SACR4 REG32(EMC_SACR4) |
| 1686 | |
| 1687 | #define REG_EMC_NFCSR REG32(EMC_NFCSR) |
| 1688 | #define REG_EMC_NFECR REG32(EMC_NFECR) |
| 1689 | #define REG_EMC_NFECC REG32(EMC_NFECC) |
| 1690 | #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) |
| 1691 | #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) |
| 1692 | #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) |
| 1693 | #define REG_EMC_NFINTS REG32(EMC_NFINTS) |
| 1694 | #define REG_EMC_NFINTE REG32(EMC_NFINTE) |
| 1695 | #define REG_EMC_NFERR0 REG32(EMC_NFERR0) |
| 1696 | #define REG_EMC_NFERR1 REG32(EMC_NFERR1) |
| 1697 | #define REG_EMC_NFERR2 REG32(EMC_NFERR2) |
| 1698 | #define REG_EMC_NFERR3 REG32(EMC_NFERR3) |
| 1699 | |
| 1700 | #define REG_EMC_DMCR REG32(EMC_DMCR) |
| 1701 | #define REG_EMC_RTCSR REG16(EMC_RTCSR) |
| 1702 | #define REG_EMC_RTCNT REG16(EMC_RTCNT) |
| 1703 | #define REG_EMC_RTCOR REG16(EMC_RTCOR) |
| 1704 | #define REG_EMC_DMAR0 REG32(EMC_DMAR0) |
| 1705 | |
| 1706 | /* Static Memory Control Register */ |
| 1707 | #define EMC_SMCR_STRV_BIT 24 |
| 1708 | #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) |
| 1709 | #define EMC_SMCR_TAW_BIT 20 |
| 1710 | #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) |
| 1711 | #define EMC_SMCR_TBP_BIT 16 |
| 1712 | #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) |
| 1713 | #define EMC_SMCR_TAH_BIT 12 |
| 1714 | #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) |
| 1715 | #define EMC_SMCR_TAS_BIT 8 |
| 1716 | #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) |
| 1717 | #define EMC_SMCR_BW_BIT 6 |
| 1718 | #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) |
| 1719 | #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) |
| 1720 | #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) |
| 1721 | #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) |
| 1722 | #define EMC_SMCR_BCM (1 << 3) |
| 1723 | #define EMC_SMCR_BL_BIT 1 |
| 1724 | #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) |
| 1725 | #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) |
| 1726 | #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) |
| 1727 | #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) |
| 1728 | #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) |
| 1729 | #define EMC_SMCR_SMT (1 << 0) |
| 1730 | |
| 1731 | /* Static Memory Bank Addr Config Reg */ |
| 1732 | #define EMC_SACR_BASE_BIT 8 |
| 1733 | #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) |
| 1734 | #define EMC_SACR_MASK_BIT 0 |
| 1735 | #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) |
| 1736 | |
| 1737 | /* NAND Flash Control/Status Register */ |
| 1738 | #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ |
| 1739 | #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ |
| 1740 | #define EMC_NFCSR_NFCE3 (1 << 5) |
| 1741 | #define EMC_NFCSR_NFE3 (1 << 4) |
| 1742 | #define EMC_NFCSR_NFCE2 (1 << 3) |
| 1743 | #define EMC_NFCSR_NFE2 (1 << 2) |
| 1744 | #define EMC_NFCSR_NFCE1 (1 << 1) |
| 1745 | #define EMC_NFCSR_NFE1 (1 << 0) |
| 1746 | |
| 1747 | /* NAND Flash ECC Control Register */ |
| 1748 | #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ |
| 1749 | #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ |
| 1750 | #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ |
| 1751 | #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ |
| 1752 | #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ |
| 1753 | #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ |
| 1754 | #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ |
| 1755 | |
| 1756 | /* NAND Flash ECC Data Register */ |
| 1757 | #define EMC_NFECC_ECC2_BIT 16 |
| 1758 | #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) |
| 1759 | #define EMC_NFECC_ECC1_BIT 8 |
| 1760 | #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) |
| 1761 | #define EMC_NFECC_ECC0_BIT 0 |
| 1762 | #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) |
| 1763 | |
| 1764 | /* NAND Flash Interrupt Status Register */ |
| 1765 | #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ |
| 1766 | #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) |
| 1767 | #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ |
| 1768 | #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ |
| 1769 | #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ |
| 1770 | #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ |
| 1771 | #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ |
| 1772 | |
| 1773 | /* NAND Flash Interrupt Enable Register */ |
| 1774 | #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ |
| 1775 | #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ |
| 1776 | #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ |
| 1777 | #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ |
| 1778 | #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ |
| 1779 | |
| 1780 | /* NAND Flash RS Error Report Register */ |
| 1781 | #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ |
| 1782 | #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) |
| 1783 | #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ |
| 1784 | #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) |
| 1785 | |
| 1786 | |
| 1787 | /* DRAM Control Register */ |
| 1788 | #define EMC_DMCR_BW_BIT 31 |
| 1789 | #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) |
| 1790 | #define EMC_DMCR_CA_BIT 26 |
| 1791 | #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) |
| 1792 | #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) |
| 1793 | #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) |
| 1794 | #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) |
| 1795 | #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) |
| 1796 | #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) |
| 1797 | #define EMC_DMCR_RMODE (1 << 25) |
| 1798 | #define EMC_DMCR_RFSH (1 << 24) |
| 1799 | #define EMC_DMCR_MRSET (1 << 23) |
| 1800 | #define EMC_DMCR_RA_BIT 20 |
| 1801 | #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) |
| 1802 | #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) |
| 1803 | #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) |
| 1804 | #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) |
| 1805 | #define EMC_DMCR_BA_BIT 19 |
| 1806 | #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) |
| 1807 | #define EMC_DMCR_PDM (1 << 18) |
| 1808 | #define EMC_DMCR_EPIN (1 << 17) |
| 1809 | #define EMC_DMCR_TRAS_BIT 13 |
| 1810 | #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) |
| 1811 | #define EMC_DMCR_RCD_BIT 11 |
| 1812 | #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) |
| 1813 | #define EMC_DMCR_TPC_BIT 8 |
| 1814 | #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) |
| 1815 | #define EMC_DMCR_TRWL_BIT 5 |
| 1816 | #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) |
| 1817 | #define EMC_DMCR_TRC_BIT 2 |
| 1818 | #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) |
| 1819 | #define EMC_DMCR_TCL_BIT 0 |
| 1820 | #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) |
| 1821 | |
| 1822 | /* Refresh Time Control/Status Register */ |
| 1823 | #define EMC_RTCSR_CMF (1 << 7) |
| 1824 | #define EMC_RTCSR_CKS_BIT 0 |
| 1825 | #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) |
| 1826 | #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) |
| 1827 | #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) |
| 1828 | #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) |
| 1829 | #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) |
| 1830 | #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) |
| 1831 | #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) |
| 1832 | #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) |
| 1833 | #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) |
| 1834 | |
| 1835 | /* SDRAM Bank Address Configuration Register */ |
| 1836 | #define EMC_DMAR_BASE_BIT 8 |
| 1837 | #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) |
| 1838 | #define EMC_DMAR_MASK_BIT 0 |
| 1839 | #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) |
| 1840 | |
| 1841 | /* Mode Register of SDRAM bank 0 */ |
| 1842 | #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ |
| 1843 | #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ |
| 1844 | #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) |
| 1845 | #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) |
| 1846 | #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ |
| 1847 | #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) |
| 1848 | #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) |
| 1849 | #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) |
| 1850 | #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) |
| 1851 | #define EMC_SDMR_BT_BIT 3 /* Burst Type */ |
| 1852 | #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) |
| 1853 | #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ |
| 1854 | #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ |
| 1855 | #define EMC_SDMR_BL_BIT 0 /* Burst Length */ |
| 1856 | #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) |
| 1857 | #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) |
| 1858 | #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) |
| 1859 | #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) |
| 1860 | #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) |
| 1861 | |
| 1862 | #define EMC_SDMR_CAS2_16BIT \ |
| 1863 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| 1864 | #define EMC_SDMR_CAS2_32BIT \ |
| 1865 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| 1866 | #define EMC_SDMR_CAS3_16BIT \ |
| 1867 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| 1868 | #define EMC_SDMR_CAS3_32BIT \ |
| 1869 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| 1870 | |
| 1871 | |
| 1872 | /************************************************************************* |
| 1873 | * CIM |
| 1874 | *************************************************************************/ |
| 1875 | #define CIM_CFG (CIM_BASE + 0x0000) |
| 1876 | #define CIM_CTRL (CIM_BASE + 0x0004) |
| 1877 | #define CIM_STATE (CIM_BASE + 0x0008) |
| 1878 | #define CIM_IID (CIM_BASE + 0x000C) |
| 1879 | #define CIM_RXFIFO (CIM_BASE + 0x0010) |
| 1880 | #define CIM_DA (CIM_BASE + 0x0020) |
| 1881 | #define CIM_FA (CIM_BASE + 0x0024) |
| 1882 | #define CIM_FID (CIM_BASE + 0x0028) |
| 1883 | #define CIM_CMD (CIM_BASE + 0x002C) |
| 1884 | |
| 1885 | #define REG_CIM_CFG REG32(CIM_CFG) |
| 1886 | #define REG_CIM_CTRL REG32(CIM_CTRL) |
| 1887 | #define REG_CIM_STATE REG32(CIM_STATE) |
| 1888 | #define REG_CIM_IID REG32(CIM_IID) |
| 1889 | #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) |
| 1890 | #define REG_CIM_DA REG32(CIM_DA) |
| 1891 | #define REG_CIM_FA REG32(CIM_FA) |
| 1892 | #define REG_CIM_FID REG32(CIM_FID) |
| 1893 | #define REG_CIM_CMD REG32(CIM_CMD) |
| 1894 | |
| 1895 | /* CIM Configuration Register (CIM_CFG) */ |
| 1896 | |
| 1897 | #define CIM_CFG_INV_DAT (1 << 15) |
| 1898 | #define CIM_CFG_VSP (1 << 14) |
| 1899 | #define CIM_CFG_HSP (1 << 13) |
| 1900 | #define CIM_CFG_PCP (1 << 12) |
| 1901 | #define CIM_CFG_DUMMY_ZERO (1 << 9) |
| 1902 | #define CIM_CFG_EXT_VSYNC (1 << 8) |
| 1903 | #define CIM_CFG_PACK_BIT 4 |
| 1904 | #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) |
| 1905 | #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) |
| 1906 | #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) |
| 1907 | #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) |
| 1908 | #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) |
| 1909 | #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) |
| 1910 | #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) |
| 1911 | #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) |
| 1912 | #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) |
| 1913 | #define CIM_CFG_DSM_BIT 0 |
| 1914 | #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) |
| 1915 | #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ |
| 1916 | #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ |
| 1917 | #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ |
| 1918 | #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ |
| 1919 | |
| 1920 | /* CIM Control Register (CIM_CTRL) */ |
| 1921 | |
| 1922 | #define CIM_CTRL_MCLKDIV_BIT 24 |
| 1923 | #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) |
| 1924 | #define CIM_CTRL_FRC_BIT 16 |
| 1925 | #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) |
| 1926 | #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ |
| 1927 | #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ |
| 1928 | #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ |
| 1929 | #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ |
| 1930 | #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ |
| 1931 | #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ |
| 1932 | #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ |
| 1933 | #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ |
| 1934 | #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ |
| 1935 | #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ |
| 1936 | #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ |
| 1937 | #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ |
| 1938 | #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ |
| 1939 | #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ |
| 1940 | #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ |
| 1941 | #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ |
| 1942 | #define CIM_CTRL_VDDM (1 << 13) |
| 1943 | #define CIM_CTRL_DMA_SOFM (1 << 12) |
| 1944 | #define CIM_CTRL_DMA_EOFM (1 << 11) |
| 1945 | #define CIM_CTRL_DMA_STOPM (1 << 10) |
| 1946 | #define CIM_CTRL_RXF_TRIGM (1 << 9) |
| 1947 | #define CIM_CTRL_RXF_OFM (1 << 8) |
| 1948 | #define CIM_CTRL_RXF_TRIG_BIT 4 |
| 1949 | #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) |
| 1950 | #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ |
| 1951 | #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ |
| 1952 | #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ |
| 1953 | #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ |
| 1954 | #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ |
| 1955 | #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ |
| 1956 | #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ |
| 1957 | #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ |
| 1958 | #define CIM_CTRL_DMA_EN (1 << 2) |
| 1959 | #define CIM_CTRL_RXF_RST (1 << 1) |
| 1960 | #define CIM_CTRL_ENA (1 << 0) |
| 1961 | |
| 1962 | /* CIM State Register (CIM_STATE) */ |
| 1963 | |
| 1964 | #define CIM_STATE_DMA_SOF (1 << 6) |
| 1965 | #define CIM_STATE_DMA_EOF (1 << 5) |
| 1966 | #define CIM_STATE_DMA_STOP (1 << 4) |
| 1967 | #define CIM_STATE_RXF_OF (1 << 3) |
| 1968 | #define CIM_STATE_RXF_TRIG (1 << 2) |
| 1969 | #define CIM_STATE_RXF_EMPTY (1 << 1) |
| 1970 | #define CIM_STATE_VDD (1 << 0) |
| 1971 | |
| 1972 | /* CIM DMA Command Register (CIM_CMD) */ |
| 1973 | |
| 1974 | #define CIM_CMD_SOFINT (1 << 31) |
| 1975 | #define CIM_CMD_EOFINT (1 << 30) |
| 1976 | #define CIM_CMD_STOP (1 << 28) |
| 1977 | #define CIM_CMD_LEN_BIT 0 |
| 1978 | #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) |
| 1979 | |
| 1980 | |
| 1981 | /************************************************************************* |
| 1982 | * SADC (Smart A/D Controller) |
| 1983 | *************************************************************************/ |
| 1984 | |
| 1985 | #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ |
| 1986 | #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ |
| 1987 | #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ |
| 1988 | #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ |
| 1989 | #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ |
| 1990 | #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ |
| 1991 | #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ |
| 1992 | #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ |
| 1993 | #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ |
| 1994 | |
| 1995 | #define REG_SADC_ENA REG8(SADC_ENA) |
| 1996 | #define REG_SADC_CFG REG32(SADC_CFG) |
| 1997 | #define REG_SADC_CTRL REG8(SADC_CTRL) |
| 1998 | #define REG_SADC_STATE REG8(SADC_STATE) |
| 1999 | #define REG_SADC_SAMETIME REG16(SADC_SAMETIME) |
| 2000 | #define REG_SADC_WAITTIME REG16(SADC_WAITTIME) |
| 2001 | #define REG_SADC_TSDAT REG32(SADC_TSDAT) |
| 2002 | #define REG_SADC_BATDAT REG16(SADC_BATDAT) |
| 2003 | #define REG_SADC_SADDAT REG16(SADC_SADDAT) |
| 2004 | |
| 2005 | /* ADC Enable Register */ |
| 2006 | #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ |
| 2007 | #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ |
| 2008 | #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ |
| 2009 | #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ |
| 2010 | |
| 2011 | /* ADC Configure Register */ |
| 2012 | #define SADC_CFG_CLKOUT_NUM_BIT 16 |
| 2013 | #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) |
| 2014 | #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ |
| 2015 | #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ |
| 2016 | #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) |
| 2017 | #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) |
| 2018 | #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) |
| 2019 | #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) |
| 2020 | #define SADC_CFG_SNUM_BIT 10 /* Sample Number */ |
| 2021 | #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) |
| 2022 | #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) |
| 2023 | #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) |
| 2024 | #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) |
| 2025 | #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) |
| 2026 | #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) |
| 2027 | #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) |
| 2028 | #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) |
| 2029 | #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) |
| 2030 | #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ |
| 2031 | #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) |
| 2032 | #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ |
| 2033 | #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ |
| 2034 | #define SADC_CFG_CMD_BIT 0 /* ADC Command */ |
| 2035 | #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) |
| 2036 | #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ |
| 2037 | #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ |
| 2038 | #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ |
| 2039 | #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ |
| 2040 | #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ |
| 2041 | #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ |
| 2042 | #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ |
| 2043 | #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ |
| 2044 | #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ |
| 2045 | #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ |
| 2046 | #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ |
| 2047 | #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ |
| 2048 | #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ |
| 2049 | |
| 2050 | /* ADC Control Register */ |
| 2051 | #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ |
| 2052 | #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ |
| 2053 | #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ |
| 2054 | #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ |
| 2055 | #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ |
| 2056 | |
| 2057 | /* ADC Status Register */ |
| 2058 | #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ |
| 2059 | #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ |
| 2060 | #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ |
| 2061 | #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ |
| 2062 | #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ |
| 2063 | #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ |
| 2064 | #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ |
| 2065 | #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ |
| 2066 | |
| 2067 | /* ADC Touch Screen Data Register */ |
| 2068 | #define SADC_TSDAT_DATA0_BIT 0 |
| 2069 | #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) |
| 2070 | #define SADC_TSDAT_TYPE0 (1 << 15) |
| 2071 | #define SADC_TSDAT_DATA1_BIT 16 |
| 2072 | #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) |
| 2073 | #define SADC_TSDAT_TYPE1 (1 << 31) |
| 2074 | |
| 2075 | |
| 2076 | /************************************************************************* |
| 2077 | * SLCD (Smart LCD Controller) |
| 2078 | *************************************************************************/ |
| 2079 | |
| 2080 | #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ |
| 2081 | #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ |
| 2082 | #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ |
| 2083 | #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ |
| 2084 | #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ |
| 2085 | |
| 2086 | #define REG_SLCD_CFG REG32(SLCD_CFG) |
| 2087 | #define REG_SLCD_CTRL REG8(SLCD_CTRL) |
| 2088 | #define REG_SLCD_STATE REG8(SLCD_STATE) |
| 2089 | #define REG_SLCD_DATA REG32(SLCD_DATA) |
| 2090 | #define REG_SLCD_FIFO REG32(SLCD_FIFO) |
| 2091 | |
| 2092 | /* SLCD Configure Register */ |
| 2093 | #define SLCD_CFG_BURST_BIT 14 |
| 2094 | #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) |
| 2095 | #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) |
| 2096 | #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) |
| 2097 | #define SLCD_CFG_DWIDTH_BIT 10 |
| 2098 | #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) |
| 2099 | #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) |
| 2100 | #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) |
| 2101 | #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) |
| 2102 | #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) |
| 2103 | #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT) |
| 2104 | #define SLCD_CFG_CWIDTH_16BIT (0 << 8) |
| 2105 | #define SLCD_CFG_CWIDTH_8BIT (1 << 8) |
| 2106 | #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) |
| 2107 | #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) |
| 2108 | #define SLCD_CFG_RS_CMD_LOW (0 << 3) |
| 2109 | #define SLCD_CFG_RS_CMD_HIGH (1 << 3) |
| 2110 | #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) |
| 2111 | #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) |
| 2112 | #define SLCD_CFG_TYPE_PARALLEL (0 << 0) |
| 2113 | #define SLCD_CFG_TYPE_SERIAL (1 << 0) |
| 2114 | |
| 2115 | /* SLCD Control Register */ |
| 2116 | #define SLCD_CTRL_DMA_EN (1 << 0) |
| 2117 | |
| 2118 | /* SLCD Status Register */ |
| 2119 | #define SLCD_STATE_BUSY (1 << 0) |
| 2120 | |
| 2121 | /* SLCD Data Register */ |
| 2122 | #define SLCD_DATA_RS_DATA (0 << 31) |
| 2123 | #define SLCD_DATA_RS_COMMAND (1 << 31) |
| 2124 | |
| 2125 | /* SLCD FIFO Register */ |
| 2126 | #define SLCD_FIFO_RS_DATA (0 << 31) |
| 2127 | #define SLCD_FIFO_RS_COMMAND (1 << 31) |
| 2128 | |
| 2129 | |
| 2130 | /************************************************************************* |
| 2131 | * LCD (LCD Controller) |
| 2132 | *************************************************************************/ |
| 2133 | #define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */ |
| 2134 | #define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */ |
| 2135 | #define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */ |
| 2136 | #define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */ |
| 2137 | #define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */ |
| 2138 | #define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */ |
| 2139 | #define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */ |
| 2140 | #define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */ |
| 2141 | #define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */ |
| 2142 | #define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */ |
| 2143 | #define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */ |
| 2144 | #define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */ |
| 2145 | #define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */ |
| 2146 | #define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */ |
| 2147 | #define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */ |
| 2148 | #define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */ |
| 2149 | #define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */ |
| 2150 | #define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */ |
| 2151 | #define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */ |
| 2152 | #define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */ |
| 2153 | #define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */ |
| 2154 | |
| 2155 | #define REG_LCD_CFG REG32(LCD_CFG) |
| 2156 | #define REG_LCD_VSYNC REG32(LCD_VSYNC) |
| 2157 | #define REG_LCD_HSYNC REG32(LCD_HSYNC) |
| 2158 | #define REG_LCD_VAT REG32(LCD_VAT) |
| 2159 | #define REG_LCD_DAH REG32(LCD_DAH) |
| 2160 | #define REG_LCD_DAV REG32(LCD_DAV) |
| 2161 | #define REG_LCD_PS REG32(LCD_PS) |
| 2162 | #define REG_LCD_CLS REG32(LCD_CLS) |
| 2163 | #define REG_LCD_SPL REG32(LCD_SPL) |
| 2164 | #define REG_LCD_REV REG32(LCD_REV) |
| 2165 | #define REG_LCD_CTRL REG32(LCD_CTRL) |
| 2166 | #define REG_LCD_STATE REG32(LCD_STATE) |
| 2167 | #define REG_LCD_IID REG32(LCD_IID) |
| 2168 | #define REG_LCD_DA0 REG32(LCD_DA0) |
| 2169 | #define REG_LCD_SA0 REG32(LCD_SA0) |
| 2170 | #define REG_LCD_FID0 REG32(LCD_FID0) |
| 2171 | #define REG_LCD_CMD0 REG32(LCD_CMD0) |
| 2172 | #define REG_LCD_DA1 REG32(LCD_DA1) |
| 2173 | #define REG_LCD_SA1 REG32(LCD_SA1) |
| 2174 | #define REG_LCD_FID1 REG32(LCD_FID1) |
| 2175 | #define REG_LCD_CMD1 REG32(LCD_CMD1) |
| 2176 | |
| 2177 | /* LCD Configure Register */ |
| 2178 | #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ |
| 2179 | #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) |
| 2180 | #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) |
| 2181 | #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) |
| 2182 | #define LCD_CFG_PSM (1 << 23) /* PS signal mode */ |
| 2183 | #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ |
| 2184 | #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ |
| 2185 | #define LCD_CFG_REVM (1 << 20) /* REV signal mode */ |
| 2186 | #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ |
| 2187 | #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ |
| 2188 | #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ |
| 2189 | #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ |
| 2190 | #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ |
| 2191 | #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ |
| 2192 | #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ |
| 2193 | #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ |
| 2194 | #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ |
| 2195 | #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ |
| 2196 | #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ |
| 2197 | #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ |
| 2198 | #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ |
| 2199 | #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) |
| 2200 | #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ |
| 2201 | #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ |
| 2202 | #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ |
| 2203 | #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ |
| 2204 | #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ |
| 2205 | #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) |
| 2206 | #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ |
| 2207 | #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) |
| 2208 | #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) |
| 2209 | #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) |
| 2210 | #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) |
| 2211 | #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) |
| 2212 | #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) |
| 2213 | #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) |
| 2214 | #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) |
| 2215 | #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) |
| 2216 | #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) |
| 2217 | #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) |
| 2218 | /* JZ47XX defines */ |
| 2219 | #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) |
| 2220 | #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) |
| 2221 | #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) |
| 2222 | |
| 2223 | |
| 2224 | |
| 2225 | /* Vertical Synchronize Register */ |
| 2226 | #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ |
| 2227 | #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
| 2228 | #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ |
| 2229 | #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
| 2230 | |
| 2231 | /* Horizontal Synchronize Register */ |
| 2232 | #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ |
| 2233 | #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) |
| 2234 | #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ |
| 2235 | #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) |
| 2236 | |
| 2237 | /* Virtual Area Setting Register */ |
| 2238 | #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ |
| 2239 | #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) |
| 2240 | #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ |
| 2241 | #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) |
| 2242 | |
| 2243 | /* Display Area Horizontal Start/End Point Register */ |
| 2244 | #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ |
| 2245 | #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) |
| 2246 | #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ |
| 2247 | #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) |
| 2248 | |
| 2249 | /* Display Area Vertical Start/End Point Register */ |
| 2250 | #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ |
| 2251 | #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) |
| 2252 | #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ |
| 2253 | #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) |
| 2254 | |
| 2255 | /* PS Signal Setting */ |
| 2256 | #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ |
| 2257 | #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) |
| 2258 | #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ |
| 2259 | #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) |
| 2260 | |
| 2261 | /* CLS Signal Setting */ |
| 2262 | #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ |
| 2263 | #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) |
| 2264 | #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ |
| 2265 | #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) |
| 2266 | |
| 2267 | /* SPL Signal Setting */ |
| 2268 | #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ |
| 2269 | #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) |
| 2270 | #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ |
| 2271 | #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) |
| 2272 | |
| 2273 | /* REV Signal Setting */ |
| 2274 | #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ |
| 2275 | #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) |
| 2276 | |
| 2277 | /* LCD Control Register */ |
| 2278 | #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ |
| 2279 | #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) |
| 2280 | #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ |
| 2281 | #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ |
| 2282 | #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ |
| 2283 | #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ |
| 2284 | #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ |
| 2285 | #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ |
| 2286 | #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ |
| 2287 | #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) |
| 2288 | #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ |
| 2289 | #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ |
| 2290 | #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ |
| 2291 | #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ |
| 2292 | #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) |
| 2293 | #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ |
| 2294 | #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ |
| 2295 | #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ |
| 2296 | #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ |
| 2297 | #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ |
| 2298 | #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ |
| 2299 | #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ |
| 2300 | #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ |
| 2301 | #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ |
| 2302 | #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ |
| 2303 | #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ |
| 2304 | #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ |
| 2305 | #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) |
| 2306 | #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ |
| 2307 | #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ |
| 2308 | #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ |
| 2309 | #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ |
| 2310 | #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ |
| 2311 | #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ |
| 2312 | |
| 2313 | /* LCD Status Register */ |
| 2314 | #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ |
| 2315 | #define LCD_STATE_EOF (1 << 5) /* EOF Flag */ |
| 2316 | #define LCD_STATE_SOF (1 << 4) /* SOF Flag */ |
| 2317 | #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ |
| 2318 | #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ |
| 2319 | #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ |
| 2320 | #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ |
| 2321 | |
| 2322 | /* DMA Command Register */ |
| 2323 | #define LCD_CMD_SOFINT (1 << 31) |
| 2324 | #define LCD_CMD_EOFINT (1 << 30) |
| 2325 | #define LCD_CMD_PAL (1 << 28) |
| 2326 | #define LCD_CMD_LEN_BIT 0 |
| 2327 | #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) |
| 2328 | |
| 2329 | |
| 2330 | /************************************************************************* |
| 2331 | * USB Device |
| 2332 | *************************************************************************/ |
| 2333 | #define USB_BASE UDC_BASE |
| 2334 | |
| 2335 | #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ |
| 2336 | #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ |
| 2337 | #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ |
| 2338 | #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ |
| 2339 | #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ |
| 2340 | #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ |
| 2341 | #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ |
| 2342 | #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ |
| 2343 | #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ |
| 2344 | #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ |
| 2345 | #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ |
| 2346 | |
| 2347 | #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ |
| 2348 | #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ |
| 2349 | #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ |
| 2350 | #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ |
| 2351 | #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ |
| 2352 | #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ |
| 2353 | #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ |
| 2354 | #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ |
| 2355 | |
| 2356 | #define USB_FIFO_EP0 (USB_BASE + 0x20) |
| 2357 | #define USB_FIFO_EP1 (USB_BASE + 0x24) |
| 2358 | #define USB_FIFO_EP2 (USB_BASE + 0x28) |
| 2359 | |
| 2360 | #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ |
| 2361 | #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ |
| 2362 | |
| 2363 | #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ |
| 2364 | #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ |
| 2365 | #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ |
| 2366 | #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ |
| 2367 | #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ |
| 2368 | #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ |
| 2369 | #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ |
| 2370 | |
| 2371 | |
| 2372 | /* Power register bit masks */ |
| 2373 | #define USB_POWER_SUSPENDM 0x01 |
| 2374 | #define USB_POWER_RESUME 0x04 |
| 2375 | #define USB_POWER_HSMODE 0x10 |
| 2376 | #define USB_POWER_HSENAB 0x20 |
| 2377 | #define USB_POWER_SOFTCONN 0x40 |
| 2378 | |
| 2379 | /* Interrupt register bit masks */ |
| 2380 | #define USB_INTR_SUSPEND 0x01 |
| 2381 | #define USB_INTR_RESUME 0x02 |
| 2382 | #define USB_INTR_RESET 0x04 |
| 2383 | |
| 2384 | #define USB_INTR_EP0 0x0001 |
| 2385 | #define USB_INTR_INEP1 0x0002 |
| 2386 | #define USB_INTR_INEP2 0x0004 |
| 2387 | #define USB_INTR_OUTEP1 0x0002 |
| 2388 | |
| 2389 | /* CSR0 bit masks */ |
| 2390 | #define USB_CSR0_OUTPKTRDY 0x01 |
| 2391 | #define USB_CSR0_INPKTRDY 0x02 |
| 2392 | #define USB_CSR0_SENTSTALL 0x04 |
| 2393 | #define USB_CSR0_DATAEND 0x08 |
| 2394 | #define USB_CSR0_SETUPEND 0x10 |
| 2395 | #define USB_CSR0_SENDSTALL 0x20 |
| 2396 | #define USB_CSR0_SVDOUTPKTRDY 0x40 |
| 2397 | #define USB_CSR0_SVDSETUPEND 0x80 |
| 2398 | |
| 2399 | /* Endpoint CSR register bits */ |
| 2400 | #define USB_INCSRH_AUTOSET 0x80 |
| 2401 | #define USB_INCSRH_ISO 0x40 |
| 2402 | #define USB_INCSRH_MODE 0x20 |
| 2403 | #define USB_INCSRH_DMAREQENAB 0x10 |
| 2404 | #define USB_INCSRH_DMAREQMODE 0x04 |
| 2405 | #define USB_INCSR_CDT 0x40 |
| 2406 | #define USB_INCSR_SENTSTALL 0x20 |
| 2407 | #define USB_INCSR_SENDSTALL 0x10 |
| 2408 | #define USB_INCSR_FF 0x08 |
| 2409 | #define USB_INCSR_UNDERRUN 0x04 |
| 2410 | #define USB_INCSR_FFNOTEMPT 0x02 |
| 2411 | #define USB_INCSR_INPKTRDY 0x01 |
| 2412 | #define USB_OUTCSRH_AUTOCLR 0x80 |
| 2413 | #define USB_OUTCSRH_ISO 0x40 |
| 2414 | #define USB_OUTCSRH_DMAREQENAB 0x20 |
| 2415 | #define USB_OUTCSRH_DNYT 0x10 |
| 2416 | #define USB_OUTCSRH_DMAREQMODE 0x08 |
| 2417 | #define USB_OUTCSR_CDT 0x80 |
| 2418 | #define USB_OUTCSR_SENTSTALL 0x40 |
| 2419 | #define USB_OUTCSR_SENDSTALL 0x20 |
| 2420 | #define USB_OUTCSR_FF 0x10 |
| 2421 | #define USB_OUTCSR_DATAERR 0x08 |
| 2422 | #define USB_OUTCSR_OVERRUN 0x04 |
| 2423 | #define USB_OUTCSR_FFFULL 0x02 |
| 2424 | #define USB_OUTCSR_OUTPKTRDY 0x01 |
| 2425 | |
| 2426 | /* Testmode register bits */ |
| 2427 | #define USB_TEST_SE0NAK 0x01 |
| 2428 | #define USB_TEST_J 0x02 |
| 2429 | #define USB_TEST_K 0x04 |
| 2430 | #define USB_TEST_PACKET 0x08 |
| 2431 | |
| 2432 | /* DMA control bits */ |
| 2433 | #define USB_CNTL_ENA 0x01 |
| 2434 | #define USB_CNTL_DIR_IN 0x02 |
| 2435 | #define USB_CNTL_MODE_1 0x04 |
| 2436 | #define USB_CNTL_INTR_EN 0x08 |
| 2437 | #define USB_CNTL_EP(n) ((n) << 4) |
| 2438 | #define USB_CNTL_BURST_0 (0 << 9) |
| 2439 | #define USB_CNTL_BURST_4 (1 << 9) |
| 2440 | #define USB_CNTL_BURST_8 (2 << 9) |
| 2441 | #define USB_CNTL_BURST_16 (3 << 9) |
| 2442 | |
| 2443 | |
| 2444 | /* Module Operation Definitions */ |
| 2445 | #ifndef __ASSEMBLY__ |
| 2446 | |
| 2447 | /*************************************************************************** |
| 2448 | * GPIO |
| 2449 | ***************************************************************************/ |
| 2450 | |
| 2451 | //------------------------------------------------------ |
| 2452 | // GPIO Pins Description |
| 2453 | // |
| 2454 | // PORT 0: |
| 2455 | // |
| 2456 | // PIN/BIT N FUNC0 FUNC1 |
| 2457 | // 0 D0 - |
| 2458 | // 1 D1 - |
| 2459 | // 2 D2 - |
| 2460 | // 3 D3 - |
| 2461 | // 4 D4 - |
| 2462 | // 5 D5 - |
| 2463 | // 6 D6 - |
| 2464 | // 7 D7 - |
| 2465 | // 8 D8 - |
| 2466 | // 9 D9 - |
| 2467 | // 10 D10 - |
| 2468 | // 11 D11 - |
| 2469 | // 12 D12 - |
| 2470 | // 13 D13 - |
| 2471 | // 14 D14 - |
| 2472 | // 15 D15 - |
| 2473 | // 16 D16 - |
| 2474 | // 17 D17 - |
| 2475 | // 18 D18 - |
| 2476 | // 19 D19 - |
| 2477 | // 20 D20 - |
| 2478 | // 21 D21 - |
| 2479 | // 22 D22 - |
| 2480 | // 23 D23 - |
| 2481 | // 24 D24 - |
| 2482 | // 25 D25 - |
| 2483 | // 26 D26 - |
| 2484 | // 27 D27 - |
| 2485 | // 28 D28 - |
| 2486 | // 29 D29 - |
| 2487 | // 30 D30 - |
| 2488 | // 31 D31 - |
| 2489 | // |
| 2490 | //------------------------------------------------------ |
| 2491 | // PORT 1: |
| 2492 | // |
| 2493 | // PIN/BIT N FUNC0 FUNC1 |
| 2494 | // 0 A0 - |
| 2495 | // 1 A1 - |
| 2496 | // 2 A2 - |
| 2497 | // 3 A3 - |
| 2498 | // 4 A4 - |
| 2499 | // 5 A5 - |
| 2500 | // 6 A6 - |
| 2501 | // 7 A7 - |
| 2502 | // 8 A8 - |
| 2503 | // 9 A9 - |
| 2504 | // 10 A10 - |
| 2505 | // 11 A11 - |
| 2506 | // 12 A12 - |
| 2507 | // 13 A13 - |
| 2508 | // 14 A14 - |
| 2509 | // 15 A15/CL - |
| 2510 | // 16 A16/AL - |
| 2511 | // 17 LCD_CLS A21 |
| 2512 | // 18 LCD_SPL A22 |
| 2513 | // 19 DCS# - |
| 2514 | // 20 RAS# - |
| 2515 | // 21 CAS# - |
| 2516 | // 22 RDWE#/BUFD# - |
| 2517 | // 23 CKE - |
| 2518 | // 24 CKO - |
| 2519 | // 25 CS1# - |
| 2520 | // 26 CS2# - |
| 2521 | // 27 CS3# - |
| 2522 | // 28 CS4# - |
| 2523 | // 29 RD# - |
| 2524 | // 30 WR# - |
| 2525 | // 31 WE0# - |
| 2526 | // |
| 2527 | // Note: PIN15&16 are CL&AL when connecting to NAND flash. |
| 2528 | //------------------------------------------------------ |
| 2529 | // PORT 2: |
| 2530 | // |
| 2531 | // PIN/BIT N FUNC0 FUNC1 |
| 2532 | // 0 LCD_D0 - |
| 2533 | // 1 LCD_D1 - |
| 2534 | // 2 LCD_D2 - |
| 2535 | // 3 LCD_D3 - |
| 2536 | // 4 LCD_D4 - |
| 2537 | // 5 LCD_D5 - |
| 2538 | // 6 LCD_D6 - |
| 2539 | // 7 LCD_D7 - |
| 2540 | // 8 LCD_D8 - |
| 2541 | // 9 LCD_D9 - |
| 2542 | // 10 LCD_D10 - |
| 2543 | // 11 LCD_D11 - |
| 2544 | // 12 LCD_D12 - |
| 2545 | // 13 LCD_D13 - |
| 2546 | // 14 LCD_D14 - |
| 2547 | // 15 LCD_D15 - |
| 2548 | // 16 LCD_D16 - |
| 2549 | // 17 LCD_D17 - |
| 2550 | // 18 LCD_PCLK - |
| 2551 | // 19 LCD_HSYNC - |
| 2552 | // 20 LCD_VSYNC - |
| 2553 | // 21 LCD_DE - |
| 2554 | // 22 LCD_PS A19 |
| 2555 | // 23 LCD_REV A20 |
| 2556 | // 24 WE1# - |
| 2557 | // 25 WE2# - |
| 2558 | // 26 WE3# - |
| 2559 | // 27 WAIT# - |
| 2560 | // 28 FRE# - |
| 2561 | // 29 FWE# - |
| 2562 | // 30(NOTE:FRB#) - - |
| 2563 | // 31 - - |
| 2564 | // |
| 2565 | // NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. |
| 2566 | //------------------------------------------------------ |
| 2567 | // PORT 3: |
| 2568 | // |
| 2569 | // PIN/BIT N FUNC0 FUNC1 |
| 2570 | // 0 CIM_D0 - |
| 2571 | // 1 CIM_D1 - |
| 2572 | // 2 CIM_D2 - |
| 2573 | // 3 CIM_D3 - |
| 2574 | // 4 CIM_D4 - |
| 2575 | // 5 CIM_D5 - |
| 2576 | // 6 CIM_D6 - |
| 2577 | // 7 CIM_D7 - |
| 2578 | // 8 MSC_CMD - |
| 2579 | // 9 MSC_CLK - |
| 2580 | // 10 MSC_D0 - |
| 2581 | // 11 MSC_D1 - |
| 2582 | // 12 MSC_D2 - |
| 2583 | // 13 MSC_D3 - |
| 2584 | // 14 CIM_MCLK - |
| 2585 | // 15 CIM_PCLK - |
| 2586 | // 16 CIM_VSYNC - |
| 2587 | // 17 CIM_HSYNC - |
| 2588 | // 18 SSI_CLK SCLK_RSTN |
| 2589 | // 19 SSI_CE0# BIT_CLK(AIC) |
| 2590 | // 20 SSI_DT SDATA_OUT(AIC) |
| 2591 | // 21 SSI_DR SDATA_IN(AIC) |
| 2592 | // 22 SSI_CE1#&GPC SYNC(AIC) |
| 2593 | // 23 PWM0 I2C_SDA |
| 2594 | // 24 PWM1 I2C_SCK |
| 2595 | // 25 PWM2 UART0_TxD |
| 2596 | // 26 PWM3 UART0_RxD |
| 2597 | // 27 PWM4 A17 |
| 2598 | // 28 PWM5 A18 |
| 2599 | // 29 - - |
| 2600 | // 30 PWM6 UART0_CTS/UART1_RxD |
| 2601 | // 31 PWM7 UART0_RTS/UART1_TxD |
| 2602 | // |
| 2603 | ////////////////////////////////////////////////////////// |
| 2604 | |
| 2605 | /* |
| 2606 | * p is the port number (0,1,2,3) |
| 2607 | * o is the pin offset (0-31) inside the port |
| 2608 | * n is the absolute number of a pin (0-127), regardless of the port |
| 2609 | */ |
| 2610 | |
| 2611 | //------------------------------------------- |
| 2612 | // Function Pins Mode |
| 2613 | |
| 2614 | #define __gpio_as_func0(n) \ |
| 2615 | do { \ |
| 2616 | unsigned int p, o; \ |
| 2617 | p = (n) / 32; \ |
| 2618 | o = (n) % 32; \ |
| 2619 | REG_GPIO_PXFUNS(p) = (1 << o); \ |
| 2620 | REG_GPIO_PXSELC(p) = (1 << o); \ |
| 2621 | } while (0) |
| 2622 | |
| 2623 | #define __gpio_as_func1(n) \ |
| 2624 | do { \ |
| 2625 | unsigned int p, o; \ |
| 2626 | p = (n) / 32; \ |
| 2627 | o = (n) % 32; \ |
| 2628 | REG_GPIO_PXFUNS(p) = (1 << o); \ |
| 2629 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| 2630 | } while (0) |
| 2631 | |
| 2632 | /* |
| 2633 | * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, |
| 2634 | * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# |
| 2635 | */ |
| 2636 | #define __gpio_as_sdram_32bit() \ |
| 2637 | do { \ |
| 2638 | REG_GPIO_PXFUNS(0) = 0xffffffff; \ |
| 2639 | REG_GPIO_PXSELC(0) = 0xffffffff; \ |
| 2640 | REG_GPIO_PXPES(0) = 0xffffffff; \ |
| 2641 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ |
| 2642 | REG_GPIO_PXSELC(1) = 0x81f9ffff; \ |
| 2643 | REG_GPIO_PXPES(1) = 0x81f9ffff; \ |
| 2644 | REG_GPIO_PXFUNS(2) = 0x07000000; \ |
| 2645 | REG_GPIO_PXSELC(2) = 0x07000000; \ |
| 2646 | REG_GPIO_PXPES(2) = 0x07000000; \ |
| 2647 | } while (0) |
| 2648 | |
| 2649 | /* |
| 2650 | * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, |
| 2651 | * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# |
| 2652 | */ |
| 2653 | #define __gpio_as_sdram_16bit() \ |
| 2654 | do { \ |
| 2655 | REG_GPIO_PXFUNS(0) = 0x5442bfaa; \ |
| 2656 | REG_GPIO_PXSELC(0) = 0x5442bfaa; \ |
| 2657 | REG_GPIO_PXPES(0) = 0x5442bfaa; \ |
| 2658 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ |
| 2659 | REG_GPIO_PXSELC(1) = 0x81f9ffff; \ |
| 2660 | REG_GPIO_PXPES(1) = 0x81f9ffff; \ |
| 2661 | REG_GPIO_PXFUNS(2) = 0x01000000; \ |
| 2662 | REG_GPIO_PXSELC(2) = 0x01000000; \ |
| 2663 | REG_GPIO_PXPES(2) = 0x01000000; \ |
| 2664 | } while (0) |
| 2665 | |
| 2666 | /* |
| 2667 | * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# |
| 2668 | */ |
| 2669 | #define __gpio_as_nand() \ |
| 2670 | do { \ |
| 2671 | REG_GPIO_PXFUNS(1) = 0x02018000; \ |
| 2672 | REG_GPIO_PXSELC(1) = 0x02018000; \ |
| 2673 | REG_GPIO_PXPES(1) = 0x02018000; \ |
| 2674 | REG_GPIO_PXFUNS(2) = 0x30000000; \ |
| 2675 | REG_GPIO_PXSELC(2) = 0x30000000; \ |
| 2676 | REG_GPIO_PXPES(2) = 0x30000000; \ |
| 2677 | REG_GPIO_PXFUNC(2) = 0x40000000; \ |
| 2678 | REG_GPIO_PXSELC(2) = 0x40000000; \ |
| 2679 | REG_GPIO_PXDIRC(2) = 0x40000000; \ |
| 2680 | REG_GPIO_PXPES(2) = 0x40000000; \ |
| 2681 | REG_GPIO_PXFUNS(1) = 0x00400000; \ |
| 2682 | REG_GPIO_PXSELC(1) = 0x00400000; \ |
| 2683 | } while (0) |
| 2684 | |
| 2685 | /* |
| 2686 | * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 |
| 2687 | */ |
| 2688 | #define __gpio_as_nor_8bit() \ |
| 2689 | do { \ |
| 2690 | REG_GPIO_PXFUNS(0) = 0x000000ff; \ |
| 2691 | REG_GPIO_PXSELC(0) = 0x000000ff; \ |
| 2692 | REG_GPIO_PXPES(0) = 0x000000ff; \ |
| 2693 | REG_GPIO_PXFUNS(1) = 0x7041ffff; \ |
| 2694 | REG_GPIO_PXSELC(1) = 0x7041ffff; \ |
| 2695 | REG_GPIO_PXPES(1) = 0x7041ffff; \ |
| 2696 | REG_GPIO_PXFUNS(1) = 0x00060000; \ |
| 2697 | REG_GPIO_PXSELS(1) = 0x00060000; \ |
| 2698 | REG_GPIO_PXPES(1) = 0x00060000; \ |
| 2699 | REG_GPIO_PXFUNS(2) = 0x08000000; \ |
| 2700 | REG_GPIO_PXSELC(2) = 0x08000000; \ |
| 2701 | REG_GPIO_PXPES(2) = 0x08000000; \ |
| 2702 | REG_GPIO_PXFUNS(2) = 0x00c00000; \ |
| 2703 | REG_GPIO_PXSELS(2) = 0x00c00000; \ |
| 2704 | REG_GPIO_PXPES(2) = 0x00c00000; \ |
| 2705 | REG_GPIO_PXFUNS(3) = 0x18000000; \ |
| 2706 | REG_GPIO_PXSELS(3) = 0x18000000; \ |
| 2707 | REG_GPIO_PXPES(3) = 0x18000000; \ |
| 2708 | } while (0) |
| 2709 | |
| 2710 | /* |
| 2711 | * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 |
| 2712 | */ |
| 2713 | #define __gpio_as_nor_16bit() \ |
| 2714 | do { \ |
| 2715 | REG_GPIO_PXFUNS(0) = 0x0000ffff; \ |
| 2716 | REG_GPIO_PXSELC(0) = 0x0000ffff; \ |
| 2717 | REG_GPIO_PXPES(0) = 0x0000ffff; \ |
| 2718 | REG_GPIO_PXFUNS(1) = 0x7041ffff; \ |
| 2719 | REG_GPIO_PXSELC(1) = 0x7041ffff; \ |
| 2720 | REG_GPIO_PXPES(1) = 0x7041ffff; \ |
| 2721 | REG_GPIO_PXFUNS(1) = 0x00060000; \ |
| 2722 | REG_GPIO_PXSELS(1) = 0x00060000; \ |
| 2723 | REG_GPIO_PXPES(1) = 0x00060000; \ |
| 2724 | REG_GPIO_PXFUNS(2) = 0x08000000; \ |
| 2725 | REG_GPIO_PXSELC(2) = 0x08000000; \ |
| 2726 | REG_GPIO_PXPES(2) = 0x08000000; \ |
| 2727 | REG_GPIO_PXFUNS(2) = 0x00c00000; \ |
| 2728 | REG_GPIO_PXSELS(2) = 0x00c00000; \ |
| 2729 | REG_GPIO_PXPES(2) = 0x00c00000; \ |
| 2730 | REG_GPIO_PXFUNS(3) = 0x18000000; \ |
| 2731 | REG_GPIO_PXSELS(3) = 0x18000000; \ |
| 2732 | REG_GPIO_PXPES(3) = 0x18000000; \ |
| 2733 | } while (0) |
| 2734 | |
| 2735 | /* |
| 2736 | * UART0_TxD, UART_RxD0 |
| 2737 | */ |
| 2738 | #define __gpio_as_uart0() \ |
| 2739 | do { \ |
| 2740 | REG_GPIO_PXFUNS(3) = 0x06000000; \ |
| 2741 | REG_GPIO_PXSELS(3) = 0x06000000; \ |
| 2742 | REG_GPIO_PXPES(3) = 0x06000000; \ |
| 2743 | } while (0) |
| 2744 | |
| 2745 | /* |
| 2746 | * UART0_CTS, UART0_RTS |
| 2747 | */ |
| 2748 | #define __gpio_as_ctsrts() \ |
| 2749 | do { \ |
| 2750 | REG_GPIO_PXFUNS(3) = 0xc0000000; \ |
| 2751 | REG_GPIO_PXSELS(3) = 0xc0000000; \ |
| 2752 | REG_GPIO_PXTRGC(3) = 0xc0000000; \ |
| 2753 | REG_GPIO_PXPES(3) = 0xc0000000; \ |
| 2754 | } while (0) |
| 2755 | |
| 2756 | /* |
| 2757 | * UART1_TxD, UART1_RxD1 |
| 2758 | */ |
| 2759 | #define __gpio_as_uart1() \ |
| 2760 | do { \ |
| 2761 | REG_GPIO_PXFUNS(3) = 0xc0000000; \ |
| 2762 | REG_GPIO_PXSELC(3) = 0xc0000000; \ |
| 2763 | REG_GPIO_PXTRGS(3) = 0xc0000000; \ |
| 2764 | REG_GPIO_PXPES(3) = 0xc0000000; \ |
| 2765 | } while (0) |
| 2766 | |
| 2767 | /* |
| 2768 | * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE |
| 2769 | */ |
| 2770 | #define __gpio_as_lcd_16bit() \ |
| 2771 | do { \ |
| 2772 | REG_GPIO_PXFUNS(2) = 0x003cffff; \ |
| 2773 | REG_GPIO_PXSELC(2) = 0x003cffff; \ |
| 2774 | REG_GPIO_PXPES(2) = 0x003cffff; \ |
| 2775 | } while (0) |
| 2776 | |
| 2777 | /* |
| 2778 | * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE |
| 2779 | */ |
| 2780 | #define __gpio_as_lcd_18bit() \ |
| 2781 | do { \ |
| 2782 | REG_GPIO_PXFUNS(2) = 0x003fffff; \ |
| 2783 | REG_GPIO_PXSELC(2) = 0x003fffff; \ |
| 2784 | REG_GPIO_PXPES(2) = 0x003fffff; \ |
| 2785 | } while (0) |
| 2786 | |
| 2787 | /* |
| 2788 | * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC |
| 2789 | */ |
| 2790 | #define __gpio_as_cim() \ |
| 2791 | do { \ |
| 2792 | REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ |
| 2793 | REG_GPIO_PXSELC(3) = 0x0003c0ff; \ |
| 2794 | REG_GPIO_PXPES(3) = 0x0003c0ff; \ |
| 2795 | } while (0) |
| 2796 | |
| 2797 | /* |
| 2798 | * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET |
| 2799 | */ |
| 2800 | #define __gpio_as_aic() \ |
| 2801 | do { \ |
| 2802 | REG_GPIO_PXFUNS(3) = 0x007c0000; \ |
| 2803 | REG_GPIO_PXSELS(3) = 0x007c0000; \ |
| 2804 | REG_GPIO_PXPES(3) = 0x007c0000; \ |
| 2805 | } while (0) |
| 2806 | |
| 2807 | /* |
| 2808 | * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 |
| 2809 | */ |
| 2810 | #define __gpio_as_msc() \ |
| 2811 | do { \ |
| 2812 | REG_GPIO_PXFUNS(3) = 0x00003f00; \ |
| 2813 | REG_GPIO_PXSELC(3) = 0x00003f00; \ |
| 2814 | REG_GPIO_PXPES(3) = 0x00003f00; \ |
| 2815 | } while (0) |
| 2816 | |
| 2817 | /* |
| 2818 | * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR |
| 2819 | */ |
| 2820 | #define __gpio_as_ssi() \ |
| 2821 | do { \ |
| 2822 | REG_GPIO_PXFUNS(3) = 0x003c0000; \ |
| 2823 | REG_GPIO_PXSELC(3) = 0x003c0000; \ |
| 2824 | REG_GPIO_PXPES(3) = 0x003c0000; \ |
| 2825 | } while (0) |
| 2826 | |
| 2827 | /* |
| 2828 | * I2C_SCK, I2C_SDA |
| 2829 | */ |
| 2830 | #define __gpio_as_i2c() \ |
| 2831 | do { \ |
| 2832 | REG_GPIO_PXFUNS(3) = 0x01800000; \ |
| 2833 | REG_GPIO_PXSELS(3) = 0x01800000; \ |
| 2834 | REG_GPIO_PXPES(3) = 0x01800000; \ |
| 2835 | } while (0) |
| 2836 | |
| 2837 | /* |
| 2838 | * PWM0 |
| 2839 | */ |
| 2840 | #define __gpio_as_pwm0() \ |
| 2841 | do { \ |
| 2842 | REG_GPIO_PXFUNS(3) = 0x00800000; \ |
| 2843 | REG_GPIO_PXSELC(3) = 0x00800000; \ |
| 2844 | REG_GPIO_PXPES(3) = 0x00800000; \ |
| 2845 | } while (0) |
| 2846 | |
| 2847 | /* |
| 2848 | * PWM1 |
| 2849 | */ |
| 2850 | #define __gpio_as_pwm1() \ |
| 2851 | do { \ |
| 2852 | REG_GPIO_PXFUNS(3) = 0x01000000; \ |
| 2853 | REG_GPIO_PXSELC(3) = 0x01000000; \ |
| 2854 | REG_GPIO_PXPES(3) = 0x01000000; \ |
| 2855 | } while (0) |
| 2856 | |
| 2857 | /* |
| 2858 | * PWM2 |
| 2859 | */ |
| 2860 | #define __gpio_as_pwm2() \ |
| 2861 | do { \ |
| 2862 | REG_GPIO_PXFUNS(3) = 0x02000000; \ |
| 2863 | REG_GPIO_PXSELC(3) = 0x02000000; \ |
| 2864 | REG_GPIO_PXPES(3) = 0x02000000; \ |
| 2865 | } while (0) |
| 2866 | |
| 2867 | /* |
| 2868 | * PWM3 |
| 2869 | */ |
| 2870 | #define __gpio_as_pwm3() \ |
| 2871 | do { \ |
| 2872 | REG_GPIO_PXFUNS(3) = 0x04000000; \ |
| 2873 | REG_GPIO_PXSELC(3) = 0x04000000; \ |
| 2874 | REG_GPIO_PXPES(3) = 0x04000000; \ |
| 2875 | } while (0) |
| 2876 | |
| 2877 | /* |
| 2878 | * PWM4 |
| 2879 | */ |
| 2880 | #define __gpio_as_pwm4() \ |
| 2881 | do { \ |
| 2882 | REG_GPIO_PXFUNS(3) = 0x08000000; \ |
| 2883 | REG_GPIO_PXSELC(3) = 0x08000000; \ |
| 2884 | REG_GPIO_PXPES(3) = 0x08000000; \ |
| 2885 | } while (0) |
| 2886 | |
| 2887 | /* |
| 2888 | * PWM5 |
| 2889 | */ |
| 2890 | #define __gpio_as_pwm5() \ |
| 2891 | do { \ |
| 2892 | REG_GPIO_PXFUNS(3) = 0x10000000; \ |
| 2893 | REG_GPIO_PXSELC(3) = 0x10000000; \ |
| 2894 | REG_GPIO_PXPES(3) = 0x10000000; \ |
| 2895 | } while (0) |
| 2896 | |
| 2897 | /* |
| 2898 | * PWM6 |
| 2899 | */ |
| 2900 | #define __gpio_as_pwm6() \ |
| 2901 | do { \ |
| 2902 | REG_GPIO_PXFUNS(3) = 0x40000000; \ |
| 2903 | REG_GPIO_PXSELC(3) = 0x40000000; \ |
| 2904 | REG_GPIO_PXPES(3) = 0x40000000; \ |
| 2905 | } while (0) |
| 2906 | |
| 2907 | /* |
| 2908 | * PWM7 |
| 2909 | */ |
| 2910 | #define __gpio_as_pwm7() \ |
| 2911 | do { \ |
| 2912 | REG_GPIO_PXFUNS(3) = 0x80000000; \ |
| 2913 | REG_GPIO_PXSELC(3) = 0x80000000; \ |
| 2914 | REG_GPIO_PXPES(3) = 0x80000000; \ |
| 2915 | } while (0) |
| 2916 | |
| 2917 | /* |
| 2918 | * n = 0 ~ 7 |
| 2919 | */ |
| 2920 | #define __gpio_as_pwm(n) __gpio_as_pwm##n() |
| 2921 | |
| 2922 | //------------------------------------------- |
| 2923 | // GPIO or Interrupt Mode |
| 2924 | |
| 2925 | #define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) |
| 2926 | |
| 2927 | #define __gpio_port_as_output(p, o) \ |
| 2928 | do { \ |
| 2929 | REG_GPIO_PXFUNC(p) = (1 << (o)); \ |
| 2930 | REG_GPIO_PXSELC(p) = (1 << (o)); \ |
| 2931 | REG_GPIO_PXDIRS(p) = (1 << (o)); \ |
| 2932 | } while (0) |
| 2933 | |
| 2934 | #define __gpio_port_as_input(p, o) \ |
| 2935 | do { \ |
| 2936 | REG_GPIO_PXFUNC(p) = (1 << (o)); \ |
| 2937 | REG_GPIO_PXSELC(p) = (1 << (o)); \ |
| 2938 | REG_GPIO_PXDIRC(p) = (1 << (o)); \ |
| 2939 | } while (0) |
| 2940 | |
| 2941 | #define __gpio_as_output(n) \ |
| 2942 | do { \ |
| 2943 | unsigned int p, o; \ |
| 2944 | p = (n) / 32; \ |
| 2945 | o = (n) % 32; \ |
| 2946 | __gpio_port_as_output(p, o); \ |
| 2947 | } while (0) |
| 2948 | |
| 2949 | #define __gpio_as_input(n) \ |
| 2950 | do { \ |
| 2951 | unsigned int p, o; \ |
| 2952 | p = (n) / 32; \ |
| 2953 | o = (n) % 32; \ |
| 2954 | __gpio_port_as_input(p, o); \ |
| 2955 | } while (0) |
| 2956 | |
| 2957 | #define __gpio_set_pin(n) \ |
| 2958 | do { \ |
| 2959 | unsigned int p, o; \ |
| 2960 | p = (n) / 32; \ |
| 2961 | o = (n) % 32; \ |
| 2962 | REG_GPIO_PXDATS(p) = (1 << o); \ |
| 2963 | } while (0) |
| 2964 | |
| 2965 | #define __gpio_clear_pin(n) \ |
| 2966 | do { \ |
| 2967 | unsigned int p, o; \ |
| 2968 | p = (n) / 32; \ |
| 2969 | o = (n) % 32; \ |
| 2970 | REG_GPIO_PXDATC(p) = (1 << o); \ |
| 2971 | } while (0) |
| 2972 | |
| 2973 | #define __gpio_get_pin(n) \ |
| 2974 | ({ \ |
| 2975 | unsigned int p, o, v; \ |
| 2976 | p = (n) / 32; \ |
| 2977 | o = (n) % 32; \ |
| 2978 | if (__gpio_get_port(p) & (1 << o)) \ |
| 2979 | v = 1; \ |
| 2980 | else \ |
| 2981 | v = 0; \ |
| 2982 | v; \ |
| 2983 | }) |
| 2984 | |
| 2985 | #define __gpio_as_irq_high_level(n) \ |
| 2986 | do { \ |
| 2987 | unsigned int p, o; \ |
| 2988 | p = (n) / 32; \ |
| 2989 | o = (n) % 32; \ |
| 2990 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| 2991 | REG_GPIO_PXTRGC(p) = (1 << o); \ |
| 2992 | REG_GPIO_PXFUNC(p) = (1 << o); \ |
| 2993 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| 2994 | REG_GPIO_PXDIRS(p) = (1 << o); \ |
| 2995 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| 2996 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| 2997 | } while (0) |
| 2998 | |
| 2999 | #define __gpio_as_irq_low_level(n) \ |
| 3000 | do { \ |
| 3001 | unsigned int p, o; \ |
| 3002 | p = (n) / 32; \ |
| 3003 | o = (n) % 32; \ |
| 3004 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| 3005 | REG_GPIO_PXTRGC(p) = (1 << o); \ |
| 3006 | REG_GPIO_PXFUNC(p) = (1 << o); \ |
| 3007 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| 3008 | REG_GPIO_PXDIRC(p) = (1 << o); \ |
| 3009 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| 3010 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| 3011 | } while (0) |
| 3012 | |
| 3013 | #define __gpio_as_irq_rise_edge(n) \ |
| 3014 | do { \ |
| 3015 | unsigned int p, o; \ |
| 3016 | p = (n) / 32; \ |
| 3017 | o = (n) % 32; \ |
| 3018 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| 3019 | REG_GPIO_PXTRGS(p) = (1 << o); \ |
| 3020 | REG_GPIO_PXFUNC(p) = (1 << o); \ |
| 3021 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| 3022 | REG_GPIO_PXDIRS(p) = (1 << o); \ |
| 3023 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| 3024 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| 3025 | } while (0) |
| 3026 | |
| 3027 | #define __gpio_as_irq_fall_edge(n) \ |
| 3028 | do { \ |
| 3029 | unsigned int p, o; \ |
| 3030 | p = (n) / 32; \ |
| 3031 | o = (n) % 32; \ |
| 3032 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| 3033 | REG_GPIO_PXTRGS(p) = (1 << o); \ |
| 3034 | REG_GPIO_PXFUNC(p) = (1 << o); \ |
| 3035 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| 3036 | REG_GPIO_PXDIRC(p) = (1 << o); \ |
| 3037 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| 3038 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| 3039 | } while (0) |
| 3040 | |
| 3041 | #define __gpio_mask_irq(n) \ |
| 3042 | do { \ |
| 3043 | unsigned int p, o; \ |
| 3044 | p = (n) / 32; \ |
| 3045 | o = (n) % 32; \ |
| 3046 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| 3047 | } while (0) |
| 3048 | |
| 3049 | #define __gpio_unmask_irq(n) \ |
| 3050 | do { \ |
| 3051 | unsigned int p, o; \ |
| 3052 | p = (n) / 32; \ |
| 3053 | o = (n) % 32; \ |
| 3054 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| 3055 | } while (0) |
| 3056 | |
| 3057 | #define __gpio_ack_irq(n) \ |
| 3058 | do { \ |
| 3059 | unsigned int p, o; \ |
| 3060 | p = (n) / 32; \ |
| 3061 | o = (n) % 32; \ |
| 3062 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| 3063 | } while (0) |
| 3064 | |
| 3065 | #define __gpio_get_irq() \ |
| 3066 | ({ \ |
| 3067 | unsigned int p, i, tmp, v = 0; \ |
| 3068 | for (p = 3; p >= 0; p--) { \ |
| 3069 | tmp = REG_GPIO_PXFLG(p); \ |
| 3070 | for (i = 0; i < 32; i++) \ |
| 3071 | if (tmp & (1 << i)) \ |
| 3072 | v = (32*p + i); \ |
| 3073 | } \ |
| 3074 | v; \ |
| 3075 | }) |
| 3076 | |
| 3077 | #define __gpio_group_irq(n) \ |
| 3078 | ({ \ |
| 3079 | register int tmp, i; \ |
| 3080 | tmp = REG_GPIO_PXFLG((n)); \ |
| 3081 | for (i=31;i>=0;i--) \ |
| 3082 | if (tmp & (1 << i)) \ |
| 3083 | break; \ |
| 3084 | i; \ |
| 3085 | }) |
| 3086 | |
| 3087 | #define __gpio_enable_pull(n) \ |
| 3088 | do { \ |
| 3089 | unsigned int p, o; \ |
| 3090 | p = (n) / 32; \ |
| 3091 | o = (n) % 32; \ |
| 3092 | REG_GPIO_PXPEC(p) = (1 << o); \ |
| 3093 | } while (0) |
| 3094 | |
| 3095 | #define __gpio_disable_pull(n) \ |
| 3096 | do { \ |
| 3097 | unsigned int p, o; \ |
| 3098 | p = (n) / 32; \ |
| 3099 | o = (n) % 32; \ |
| 3100 | REG_GPIO_PXPES(p) = (1 << o); \ |
| 3101 | } while (0) |
| 3102 | |
| 3103 | |
| 3104 | /*************************************************************************** |
| 3105 | * CPM |
| 3106 | ***************************************************************************/ |
| 3107 | #define __cpm_get_pllm() \ |
| 3108 | ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) |
| 3109 | #define __cpm_get_plln() \ |
| 3110 | ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) |
| 3111 | #define __cpm_get_pllod() \ |
| 3112 | ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) |
| 3113 | |
| 3114 | #define __cpm_get_cdiv() \ |
| 3115 | ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) |
| 3116 | #define __cpm_get_hdiv() \ |
| 3117 | ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) |
| 3118 | #define __cpm_get_pdiv() \ |
| 3119 | ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) |
| 3120 | #define __cpm_get_mdiv() \ |
| 3121 | ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) |
| 3122 | #define __cpm_get_ldiv() \ |
| 3123 | ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) |
| 3124 | #define __cpm_get_udiv() \ |
| 3125 | ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) |
| 3126 | #define __cpm_get_i2sdiv() \ |
| 3127 | ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) |
| 3128 | #define __cpm_get_pixdiv() \ |
| 3129 | ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) |
| 3130 | #define __cpm_get_mscdiv() \ |
| 3131 | ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) |
| 3132 | |
| 3133 | #define __cpm_set_cdiv(v) \ |
| 3134 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) |
| 3135 | #define __cpm_set_hdiv(v) \ |
| 3136 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT))) |
| 3137 | #define __cpm_set_pdiv(v) \ |
| 3138 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) |
| 3139 | #define __cpm_set_mdiv(v) \ |
| 3140 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) |
| 3141 | #define __cpm_set_ldiv(v) \ |
| 3142 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) |
| 3143 | #define __cpm_set_udiv(v) \ |
| 3144 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) |
| 3145 | #define __cpm_set_i2sdiv(v) \ |
| 3146 | (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) |
| 3147 | #define __cpm_set_pixdiv(v) \ |
| 3148 | (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) |
| 3149 | #define __cpm_set_mscdiv(v) \ |
| 3150 | (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) |
| 3151 | |
| 3152 | #define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) |
| 3153 | #define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) |
| 3154 | #define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN) |
| 3155 | #define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) |
| 3156 | #define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) |
| 3157 | #define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) |
| 3158 | #define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) |
| 3159 | #define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) |
| 3160 | |
| 3161 | #define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS) |
| 3162 | #define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP) |
| 3163 | #define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) |
| 3164 | |
| 3165 | #define __cpm_get_cclk_doze_duty() \ |
| 3166 | ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) |
| 3167 | #define __cpm_set_cclk_doze_duty(v) \ |
| 3168 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) |
| 3169 | |
| 3170 | #define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON) |
| 3171 | #define __cpm_idle_mode() \ |
| 3172 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) |
| 3173 | #define __cpm_sleep_mode() \ |
| 3174 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) |
| 3175 | |
| 3176 | #define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff) |
| 3177 | #define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) |
| 3178 | #define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) |
| 3179 | #define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) |
| 3180 | #define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) |
| 3181 | #define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) |
| 3182 | #define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) |
| 3183 | #define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) |
| 3184 | #define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) |
| 3185 | #define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) |
| 3186 | #define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) |
| 3187 | #define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) |
| 3188 | #define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) |
| 3189 | #define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) |
| 3190 | #define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) |
| 3191 | #define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) |
| 3192 | #define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) |
| 3193 | |
| 3194 | #define __cpm_start_all() (REG_CPM_CLKGR = 0x0) |
| 3195 | #define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) |
| 3196 | #define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) |
| 3197 | #define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) |
| 3198 | #define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) |
| 3199 | #define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) |
| 3200 | #define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) |
| 3201 | #define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) |
| 3202 | #define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) |
| 3203 | #define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) |
| 3204 | #define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) |
| 3205 | #define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) |
| 3206 | #define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) |
| 3207 | #define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) |
| 3208 | #define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) |
| 3209 | #define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) |
| 3210 | #define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) |
| 3211 | |
| 3212 | #define __cpm_get_o1st() \ |
| 3213 | ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) |
| 3214 | #define __cpm_set_o1st(v) \ |
| 3215 | (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) |
| 3216 | #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND) |
| 3217 | #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) |
| 3218 | |
| 3219 | |
| 3220 | #ifdef CFG_EXTAL |
| 3221 | #define JZ_EXTAL CFG_EXTAL |
| 3222 | #else |
| 3223 | #define JZ_EXTAL 3686400 |
| 3224 | #endif |
| 3225 | #define JZ_EXTAL2 32768 /* RTC clock */ |
| 3226 | |
| 3227 | /* PLL output frequency */ |
| 3228 | static __inline__ unsigned int __cpm_get_pllout(void) |
| 3229 | { |
| 3230 | unsigned long m, n, no, pllout; |
| 3231 | unsigned long cppcr = REG_CPM_CPPCR; |
| 3232 | unsigned long od[4] = {1, 2, 2, 4}; |
| 3233 | if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { |
| 3234 | m = __cpm_get_pllm() + 2; |
| 3235 | n = __cpm_get_plln() + 2; |
| 3236 | no = od[__cpm_get_pllod()]; |
| 3237 | pllout = ((JZ_EXTAL) / (n * no)) * m; |
| 3238 | } else |
| 3239 | pllout = JZ_EXTAL; |
| 3240 | return pllout; |
| 3241 | } |
| 3242 | |
| 3243 | /* PLL output frequency for MSC/I2S/LCD/USB */ |
| 3244 | static __inline__ unsigned int __cpm_get_pllout2(void) |
| 3245 | { |
| 3246 | if (REG_CPM_CPCCR & CPM_CPCCR_PCS) |
| 3247 | return __cpm_get_pllout(); |
| 3248 | else |
| 3249 | return __cpm_get_pllout()/2; |
| 3250 | } |
| 3251 | |
| 3252 | /* CPU core clock */ |
| 3253 | static __inline__ unsigned int __cpm_get_cclk(void) |
| 3254 | { |
| 3255 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| 3256 | |
| 3257 | return __cpm_get_pllout() / div[__cpm_get_cdiv()]; |
| 3258 | } |
| 3259 | |
| 3260 | /* AHB system bus clock */ |
| 3261 | static __inline__ unsigned int __cpm_get_hclk(void) |
| 3262 | { |
| 3263 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| 3264 | |
| 3265 | return __cpm_get_pllout() / div[__cpm_get_hdiv()]; |
| 3266 | } |
| 3267 | |
| 3268 | /* Memory bus clock */ |
| 3269 | static __inline__ unsigned int __cpm_get_mclk(void) |
| 3270 | { |
| 3271 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| 3272 | |
| 3273 | return __cpm_get_pllout() / div[__cpm_get_mdiv()]; |
| 3274 | } |
| 3275 | |
| 3276 | /* APB peripheral bus clock */ |
| 3277 | static __inline__ unsigned int __cpm_get_pclk(void) |
| 3278 | { |
| 3279 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| 3280 | |
| 3281 | return __cpm_get_pllout() / div[__cpm_get_pdiv()]; |
| 3282 | } |
| 3283 | |
| 3284 | /* LCDC module clock */ |
| 3285 | static __inline__ unsigned int __cpm_get_lcdclk(void) |
| 3286 | { |
| 3287 | return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); |
| 3288 | } |
| 3289 | |
| 3290 | /* LCD pixel clock */ |
| 3291 | static __inline__ unsigned int __cpm_get_pixclk(void) |
| 3292 | { |
| 3293 | return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); |
| 3294 | } |
| 3295 | |
| 3296 | /* I2S clock */ |
| 3297 | static __inline__ unsigned int __cpm_get_i2sclk(void) |
| 3298 | { |
| 3299 | if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { |
| 3300 | return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); |
| 3301 | } |
| 3302 | else { |
| 3303 | return JZ_EXTAL; |
| 3304 | } |
| 3305 | } |
| 3306 | |
| 3307 | /* USB clock */ |
| 3308 | static __inline__ unsigned int __cpm_get_usbclk(void) |
| 3309 | { |
| 3310 | if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { |
| 3311 | return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); |
| 3312 | } |
| 3313 | else { |
| 3314 | return JZ_EXTAL; |
| 3315 | } |
| 3316 | } |
| 3317 | |
| 3318 | /* MSC clock */ |
| 3319 | static __inline__ unsigned int __cpm_get_mscclk(void) |
| 3320 | { |
| 3321 | return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); |
| 3322 | } |
| 3323 | |
| 3324 | /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ |
| 3325 | static __inline__ unsigned int __cpm_get_extalclk(void) |
| 3326 | { |
| 3327 | return JZ_EXTAL; |
| 3328 | } |
| 3329 | |
| 3330 | /* RTC clock for CPM,INTC,RTC,TCU,WDT */ |
| 3331 | static __inline__ unsigned int __cpm_get_rtcclk(void) |
| 3332 | { |
| 3333 | return JZ_EXTAL2; |
| 3334 | } |
| 3335 | |
| 3336 | /* |
| 3337 | * Output 24MHz for SD and 16MHz for MMC. |
| 3338 | */ |
| 3339 | static inline void __cpm_select_msc_clk(int sd) |
| 3340 | { |
| 3341 | unsigned int pllout2 = __cpm_get_pllout2(); |
| 3342 | unsigned int div = 0; |
| 3343 | |
| 3344 | if (sd) { |
| 3345 | div = pllout2 / 24000000; |
| 3346 | } |
| 3347 | else { |
| 3348 | div = pllout2 / 16000000; |
| 3349 | } |
| 3350 | |
| 3351 | REG_CPM_MSCCDR = div - 1; |
| 3352 | } |
| 3353 | |
| 3354 | /*************************************************************************** |
| 3355 | * TCU |
| 3356 | ***************************************************************************/ |
| 3357 | // where 'n' is the TCU channel |
| 3358 | #define __tcu_select_extalclk(n) \ |
| 3359 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) |
| 3360 | #define __tcu_select_rtcclk(n) \ |
| 3361 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) |
| 3362 | #define __tcu_select_pclk(n) \ |
| 3363 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) |
| 3364 | |
| 3365 | #define __tcu_select_clk_div1(n) \ |
| 3366 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) |
| 3367 | #define __tcu_select_clk_div4(n) \ |
| 3368 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) |
| 3369 | #define __tcu_select_clk_div16(n) \ |
| 3370 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) |
| 3371 | #define __tcu_select_clk_div64(n) \ |
| 3372 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) |
| 3373 | #define __tcu_select_clk_div256(n) \ |
| 3374 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) |
| 3375 | #define __tcu_select_clk_div1024(n) \ |
| 3376 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) |
| 3377 | |
| 3378 | #define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) |
| 3379 | #define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) |
| 3380 | |
| 3381 | #define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) |
| 3382 | #define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) |
| 3383 | |
| 3384 | #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) |
| 3385 | #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) |
| 3386 | |
| 3387 | #define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) |
| 3388 | #define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) |
| 3389 | |
| 3390 | #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) |
| 3391 | #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) |
| 3392 | #define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) |
| 3393 | #define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) |
| 3394 | #define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) |
| 3395 | #define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) |
| 3396 | #define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) |
| 3397 | #define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) |
| 3398 | #define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) |
| 3399 | #define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) |
| 3400 | |
| 3401 | #define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) |
| 3402 | #define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) |
| 3403 | |
| 3404 | #define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) |
| 3405 | #define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) |
| 3406 | |
| 3407 | #define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) |
| 3408 | #define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) |
| 3409 | |
| 3410 | #define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) |
| 3411 | #define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) |
| 3412 | #define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) |
| 3413 | #define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) |
| 3414 | |
| 3415 | |
| 3416 | /*************************************************************************** |
| 3417 | * WDT |
| 3418 | ***************************************************************************/ |
| 3419 | #define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) |
| 3420 | #define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) |
| 3421 | #define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) |
| 3422 | #define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) |
| 3423 | |
| 3424 | #define __wdt_select_extalclk() \ |
| 3425 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) |
| 3426 | #define __wdt_select_rtcclk() \ |
| 3427 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) |
| 3428 | #define __wdt_select_pclk() \ |
| 3429 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) |
| 3430 | |
| 3431 | #define __wdt_select_clk_div1() \ |
| 3432 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) |
| 3433 | #define __wdt_select_clk_div4() \ |
| 3434 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) |
| 3435 | #define __wdt_select_clk_div16() \ |
| 3436 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) |
| 3437 | #define __wdt_select_clk_div64() \ |
| 3438 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) |
| 3439 | #define __wdt_select_clk_div256() \ |
| 3440 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) |
| 3441 | #define __wdt_select_clk_div1024() \ |
| 3442 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) |
| 3443 | |
| 3444 | |
| 3445 | /*************************************************************************** |
| 3446 | * UART |
| 3447 | ***************************************************************************/ |
| 3448 | |
| 3449 | #define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) |
| 3450 | #define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) |
| 3451 | |
| 3452 | #define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) |
| 3453 | #define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) |
| 3454 | |
| 3455 | #define __uart_enable_receive_irq() \ |
| 3456 | ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) |
| 3457 | #define __uart_disable_receive_irq() \ |
| 3458 | ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) |
| 3459 | |
| 3460 | #define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) |
| 3461 | #define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) |
| 3462 | |
| 3463 | #define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) |
| 3464 | |
| 3465 | #define __uart_set_baud(devclk, baud) \ |
| 3466 | do { \ |
| 3467 | REG8(UART0_LCR) |= UARTLCR_DLAB; \ |
| 3468 | REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ |
| 3469 | REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ |
| 3470 | REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ |
| 3471 | } while (0) |
| 3472 | |
| 3473 | #define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) |
| 3474 | #define __uart_clear_errors() \ |
| 3475 | ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) |
| 3476 | |
| 3477 | #define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) |
| 3478 | #define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) |
| 3479 | #define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) |
| 3480 | #define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) |
| 3481 | #define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) |
| 3482 | #define __uart_receive_char() REG8(UART0_RDR) |
| 3483 | #define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) |
| 3484 | #define __uart_enable_irda() \ |
| 3485 | /* Tx high pulse as 0, Rx low pulse as 0 */ \ |
| 3486 | ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) |
| 3487 | |
| 3488 | |
| 3489 | /*************************************************************************** |
| 3490 | * DMAC |
| 3491 | ***************************************************************************/ |
| 3492 | |
| 3493 | /* n is the DMA channel (0 - 5) */ |
| 3494 | |
| 3495 | #define __dmac_enable_module() \ |
| 3496 | ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) |
| 3497 | #define __dmac_disable_module() \ |
| 3498 | ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) |
| 3499 | |
| 3500 | /* p=0,1,2,3 */ |
| 3501 | #define __dmac_set_priority(p) \ |
| 3502 | do { \ |
| 3503 | REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ |
| 3504 | REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ |
| 3505 | } while (0) |
| 3506 | |
| 3507 | #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) |
| 3508 | #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) |
| 3509 | |
| 3510 | #define __dmac_enable_descriptor(n) \ |
| 3511 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) |
| 3512 | #define __dmac_disable_descriptor(n) \ |
| 3513 | ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) |
| 3514 | |
| 3515 | #define __dmac_enable_channel(n) \ |
| 3516 | ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) |
| 3517 | #define __dmac_disable_channel(n) \ |
| 3518 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) |
| 3519 | #define __dmac_channel_enabled(n) \ |
| 3520 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) |
| 3521 | |
| 3522 | #define __dmac_channel_enable_irq(n) \ |
| 3523 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) |
| 3524 | #define __dmac_channel_disable_irq(n) \ |
| 3525 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) |
| 3526 | |
| 3527 | #define __dmac_channel_transmit_halt_detected(n) \ |
| 3528 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) |
| 3529 | #define __dmac_channel_transmit_end_detected(n) \ |
| 3530 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) |
| 3531 | #define __dmac_channel_address_error_detected(n) \ |
| 3532 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) |
| 3533 | #define __dmac_channel_count_terminated_detected(n) \ |
| 3534 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) |
| 3535 | #define __dmac_channel_descriptor_invalid_detected(n) \ |
| 3536 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) |
| 3537 | |
| 3538 | #define __dmac_channel_clear_transmit_halt(n) \ |
| 3539 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) |
| 3540 | #define __dmac_channel_clear_transmit_end(n) \ |
| 3541 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) |
| 3542 | #define __dmac_channel_clear_address_error(n) \ |
| 3543 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) |
| 3544 | #define __dmac_channel_clear_count_terminated(n) \ |
| 3545 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) |
| 3546 | #define __dmac_channel_clear_descriptor_invalid(n) \ |
| 3547 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) |
| 3548 | |
| 3549 | #define __dmac_channel_set_single_mode(n) \ |
| 3550 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) |
| 3551 | #define __dmac_channel_set_block_mode(n) \ |
| 3552 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) |
| 3553 | |
| 3554 | #define __dmac_channel_set_transfer_unit_32bit(n) \ |
| 3555 | do { \ |
| 3556 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| 3557 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ |
| 3558 | } while (0) |
| 3559 | |
| 3560 | #define __dmac_channel_set_transfer_unit_16bit(n) \ |
| 3561 | do { \ |
| 3562 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| 3563 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ |
| 3564 | } while (0) |
| 3565 | |
| 3566 | #define __dmac_channel_set_transfer_unit_8bit(n) \ |
| 3567 | do { \ |
| 3568 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| 3569 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ |
| 3570 | } while (0) |
| 3571 | |
| 3572 | #define __dmac_channel_set_transfer_unit_16byte(n) \ |
| 3573 | do { \ |
| 3574 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| 3575 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ |
| 3576 | } while (0) |
| 3577 | |
| 3578 | #define __dmac_channel_set_transfer_unit_32byte(n) \ |
| 3579 | do { \ |
| 3580 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| 3581 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ |
| 3582 | } while (0) |
| 3583 | |
| 3584 | /* w=8,16,32 */ |
| 3585 | #define __dmac_channel_set_dest_port_width(n,w) \ |
| 3586 | do { \ |
| 3587 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ |
| 3588 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ |
| 3589 | } while (0) |
| 3590 | |
| 3591 | /* w=8,16,32 */ |
| 3592 | #define __dmac_channel_set_src_port_width(n,w) \ |
| 3593 | do { \ |
| 3594 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ |
| 3595 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ |
| 3596 | } while (0) |
| 3597 | |
| 3598 | /* v=0-15 */ |
| 3599 | #define __dmac_channel_set_rdil(n,v) \ |
| 3600 | do { \ |
| 3601 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ |
| 3602 | REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ |
| 3603 | } while (0) |
| 3604 | |
| 3605 | #define __dmac_channel_dest_addr_fixed(n) \ |
| 3606 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) |
| 3607 | #define __dmac_channel_dest_addr_increment(n) \ |
| 3608 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) |
| 3609 | |
| 3610 | #define __dmac_channel_src_addr_fixed(n) \ |
| 3611 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) |
| 3612 | #define __dmac_channel_src_addr_increment(n) \ |
| 3613 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) |
| 3614 | |
| 3615 | #define __dmac_channel_set_doorbell(n) \ |
| 3616 | ( REG_DMAC_DMADBSR = (1 << (n)) ) |
| 3617 | |
| 3618 | #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) |
| 3619 | #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) |
| 3620 | |
| 3621 | static __inline__ int __dmac_get_irq(void) |
| 3622 | { |
| 3623 | int i; |
| 3624 | for (i = 0; i < MAX_DMA_NUM; i++) |
| 3625 | if (__dmac_channel_irq_detected(i)) |
| 3626 | return i; |
| 3627 | return -1; |
| 3628 | } |
| 3629 | |
| 3630 | |
| 3631 | /*************************************************************************** |
| 3632 | * AIC (AC'97 & I2S Controller) |
| 3633 | ***************************************************************************/ |
| 3634 | |
| 3635 | #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) |
| 3636 | #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) |
| 3637 | |
| 3638 | #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) |
| 3639 | #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) |
| 3640 | |
| 3641 | #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) |
| 3642 | #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) |
| 3643 | #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) |
| 3644 | |
| 3645 | #define __aic_reset() \ |
| 3646 | do { \ |
| 3647 | REG_AIC_FR |= AIC_FR_RST; \ |
| 3648 | } while(0) |
| 3649 | |
| 3650 | |
| 3651 | #define __aic_set_transmit_trigger(n) \ |
| 3652 | do { \ |
| 3653 | REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ |
| 3654 | REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ |
| 3655 | } while(0) |
| 3656 | |
| 3657 | #define __aic_set_receive_trigger(n) \ |
| 3658 | do { \ |
| 3659 | REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ |
| 3660 | REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ |
| 3661 | } while(0) |
| 3662 | |
| 3663 | #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) |
| 3664 | #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) |
| 3665 | #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) |
| 3666 | #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) |
| 3667 | #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) |
| 3668 | #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) |
| 3669 | |
| 3670 | #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) |
| 3671 | #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) |
| 3672 | |
| 3673 | #define __aic_enable_transmit_intr() \ |
| 3674 | ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) |
| 3675 | #define __aic_disable_transmit_intr() \ |
| 3676 | ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) |
| 3677 | #define __aic_enable_receive_intr() \ |
| 3678 | ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) |
| 3679 | #define __aic_disable_receive_intr() \ |
| 3680 | ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) |
| 3681 | |
| 3682 | #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) |
| 3683 | #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) |
| 3684 | #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) |
| 3685 | #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) |
| 3686 | |
| 3687 | #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) |
| 3688 | #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) |
| 3689 | #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) |
| 3690 | #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) |
| 3691 | #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) |
| 3692 | #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) |
| 3693 | |
| 3694 | #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 |
| 3695 | #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 |
| 3696 | #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 |
| 3697 | #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 |
| 3698 | #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 |
| 3699 | #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 |
| 3700 | |
| 3701 | #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 |
| 3702 | #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 |
| 3703 | #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 |
| 3704 | #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 |
| 3705 | #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 |
| 3706 | #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 |
| 3707 | |
| 3708 | #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) |
| 3709 | #define __ac97_set_xs_mono() \ |
| 3710 | do { \ |
| 3711 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ |
| 3712 | REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ |
| 3713 | } while(0) |
| 3714 | #define __ac97_set_xs_stereo() \ |
| 3715 | do { \ |
| 3716 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ |
| 3717 | REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ |
| 3718 | } while(0) |
| 3719 | |
| 3720 | /* In fact, only stereo is support now. */ |
| 3721 | #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) |
| 3722 | #define __ac97_set_rs_mono() \ |
| 3723 | do { \ |
| 3724 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ |
| 3725 | REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ |
| 3726 | } while(0) |
| 3727 | #define __ac97_set_rs_stereo() \ |
| 3728 | do { \ |
| 3729 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ |
| 3730 | REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ |
| 3731 | } while(0) |
| 3732 | |
| 3733 | #define __ac97_warm_reset_codec() \ |
| 3734 | do { \ |
| 3735 | REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ |
| 3736 | REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ |
| 3737 | udelay(2); \ |
| 3738 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ |
| 3739 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ |
| 3740 | } while (0) |
| 3741 | |
| 3742 | #define __ac97_cold_reset_codec() \ |
| 3743 | do { \ |
| 3744 | REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ |
| 3745 | udelay(2); \ |
| 3746 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ |
| 3747 | } while (0) |
| 3748 | |
| 3749 | /* n=8,16,18,20 */ |
| 3750 | #define __ac97_set_iass(n) \ |
| 3751 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) |
| 3752 | #define __ac97_set_oass(n) \ |
| 3753 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) |
| 3754 | |
| 3755 | #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) |
| 3756 | #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) |
| 3757 | |
| 3758 | /* n=8,16,18,20,24 */ |
| 3759 | /*#define __i2s_set_sample_size(n) \ |
| 3760 | ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ |
| 3761 | |
| 3762 | #define __i2s_set_oss_sample_size(n) \ |
| 3763 | ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) |
| 3764 | #define __i2s_set_iss_sample_size(n) \ |
| 3765 | ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) |
| 3766 | |
| 3767 | #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) |
| 3768 | #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) |
| 3769 | |
| 3770 | #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) |
| 3771 | #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) |
| 3772 | #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) |
| 3773 | #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) |
| 3774 | |
| 3775 | #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) |
| 3776 | |
| 3777 | #define __aic_get_transmit_resident() \ |
| 3778 | ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) |
| 3779 | #define __aic_get_receive_count() \ |
| 3780 | ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) |
| 3781 | |
| 3782 | #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) |
| 3783 | #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) |
| 3784 | #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) |
| 3785 | #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) |
| 3786 | #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) |
| 3787 | #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) |
| 3788 | #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) |
| 3789 | |
| 3790 | #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) |
| 3791 | |
| 3792 | #define CODEC_READ_CMD (1 << 19) |
| 3793 | #define CODEC_WRITE_CMD (0 << 19) |
| 3794 | #define CODEC_REG_INDEX_BIT 12 |
| 3795 | #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ |
| 3796 | #define CODEC_REG_DATA_BIT 4 |
| 3797 | #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ |
| 3798 | |
| 3799 | #define __ac97_out_rcmd_addr(reg) \ |
| 3800 | do { \ |
| 3801 | REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ |
| 3802 | } while (0) |
| 3803 | |
| 3804 | #define __ac97_out_wcmd_addr(reg) \ |
| 3805 | do { \ |
| 3806 | REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ |
| 3807 | } while (0) |
| 3808 | |
| 3809 | #define __ac97_out_data(value) \ |
| 3810 | do { \ |
| 3811 | REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ |
| 3812 | } while (0) |
| 3813 | |
| 3814 | #define __ac97_in_data() \ |
| 3815 | ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) |
| 3816 | |
| 3817 | #define __ac97_in_status_addr() \ |
| 3818 | ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) |
| 3819 | |
| 3820 | #define __i2s_set_sample_rate(i2sclk, sync) \ |
| 3821 | ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) |
| 3822 | |
| 3823 | #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) |
| 3824 | #define __aic_read_rfifo() ( REG_AIC_DR ) |
| 3825 | |
| 3826 | #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) |
| 3827 | #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) |
| 3828 | |
| 3829 | // |
| 3830 | // Define next ops for AC97 compatible |
| 3831 | // |
| 3832 | |
| 3833 | #define AC97_ACSR AIC_ACSR |
| 3834 | |
| 3835 | #define __ac97_enable() __aic_enable(); __aic_select_ac97() |
| 3836 | #define __ac97_disable() __aic_disable() |
| 3837 | #define __ac97_reset() __aic_reset() |
| 3838 | |
| 3839 | #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) |
| 3840 | #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) |
| 3841 | |
| 3842 | #define __ac97_enable_record() __aic_enable_record() |
| 3843 | #define __ac97_disable_record() __aic_disable_record() |
| 3844 | #define __ac97_enable_replay() __aic_enable_replay() |
| 3845 | #define __ac97_disable_replay() __aic_disable_replay() |
| 3846 | #define __ac97_enable_loopback() __aic_enable_loopback() |
| 3847 | #define __ac97_disable_loopback() __aic_disable_loopback() |
| 3848 | |
| 3849 | #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() |
| 3850 | #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() |
| 3851 | #define __ac97_enable_receive_dma() __aic_enable_receive_dma() |
| 3852 | #define __ac97_disable_receive_dma() __aic_disable_receive_dma() |
| 3853 | |
| 3854 | #define __ac97_transmit_request() __aic_transmit_request() |
| 3855 | #define __ac97_receive_request() __aic_receive_request() |
| 3856 | #define __ac97_transmit_underrun() __aic_transmit_underrun() |
| 3857 | #define __ac97_receive_overrun() __aic_receive_overrun() |
| 3858 | |
| 3859 | #define __ac97_clear_errors() __aic_clear_errors() |
| 3860 | |
| 3861 | #define __ac97_get_transmit_resident() __aic_get_transmit_resident() |
| 3862 | #define __ac97_get_receive_count() __aic_get_receive_count() |
| 3863 | |
| 3864 | #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() |
| 3865 | #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() |
| 3866 | #define __ac97_enable_receive_intr() __aic_enable_receive_intr() |
| 3867 | #define __ac97_disable_receive_intr() __aic_disable_receive_intr() |
| 3868 | |
| 3869 | #define __ac97_write_tfifo(v) __aic_write_tfifo(v) |
| 3870 | #define __ac97_read_rfifo() __aic_read_rfifo() |
| 3871 | |
| 3872 | // |
| 3873 | // Define next ops for I2S compatible |
| 3874 | // |
| 3875 | |
| 3876 | #define I2S_ACSR AIC_I2SSR |
| 3877 | |
| 3878 | #define __i2s_enable() __aic_enable(); __aic_select_i2s() |
| 3879 | #define __i2s_disable() __aic_disable() |
| 3880 | #define __i2s_reset() __aic_reset() |
| 3881 | |
| 3882 | #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) |
| 3883 | #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) |
| 3884 | |
| 3885 | #define __i2s_enable_record() __aic_enable_record() |
| 3886 | #define __i2s_disable_record() __aic_disable_record() |
| 3887 | #define __i2s_enable_replay() __aic_enable_replay() |
| 3888 | #define __i2s_disable_replay() __aic_disable_replay() |
| 3889 | #define __i2s_enable_loopback() __aic_enable_loopback() |
| 3890 | #define __i2s_disable_loopback() __aic_disable_loopback() |
| 3891 | |
| 3892 | #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() |
| 3893 | #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() |
| 3894 | #define __i2s_enable_receive_dma() __aic_enable_receive_dma() |
| 3895 | #define __i2s_disable_receive_dma() __aic_disable_receive_dma() |
| 3896 | |
| 3897 | #define __i2s_transmit_request() __aic_transmit_request() |
| 3898 | #define __i2s_receive_request() __aic_receive_request() |
| 3899 | #define __i2s_transmit_underrun() __aic_transmit_underrun() |
| 3900 | #define __i2s_receive_overrun() __aic_receive_overrun() |
| 3901 | |
| 3902 | #define __i2s_clear_errors() __aic_clear_errors() |
| 3903 | |
| 3904 | #define __i2s_get_transmit_resident() __aic_get_transmit_resident() |
| 3905 | #define __i2s_get_receive_count() __aic_get_receive_count() |
| 3906 | |
| 3907 | #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() |
| 3908 | #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() |
| 3909 | #define __i2s_enable_receive_intr() __aic_enable_receive_intr() |
| 3910 | #define __i2s_disable_receive_intr() __aic_disable_receive_intr() |
| 3911 | |
| 3912 | #define __i2s_write_tfifo(v) __aic_write_tfifo(v) |
| 3913 | #define __i2s_read_rfifo() __aic_read_rfifo() |
| 3914 | |
| 3915 | #define __i2s_reset_codec() \ |
| 3916 | do { \ |
| 3917 | } while (0) |
| 3918 | |
| 3919 | |
| 3920 | /*************************************************************************** |
| 3921 | * ICDC |
| 3922 | ***************************************************************************/ |
| 3923 | #define __i2s_internal_codec() __aic_internal_codec() |
| 3924 | #define __i2s_external_codec() __aic_external_codec() |
| 3925 | |
| 3926 | /*************************************************************************** |
| 3927 | * INTC |
| 3928 | ***************************************************************************/ |
| 3929 | #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) |
| 3930 | #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) |
| 3931 | #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) |
| 3932 | |
| 3933 | |
| 3934 | /*************************************************************************** |
| 3935 | * I2C |
| 3936 | ***************************************************************************/ |
| 3937 | |
| 3938 | #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) |
| 3939 | #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) |
| 3940 | |
| 3941 | #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) |
| 3942 | #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) |
| 3943 | #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) |
| 3944 | #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) |
| 3945 | |
| 3946 | #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) |
| 3947 | #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) |
| 3948 | #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) |
| 3949 | |
| 3950 | #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) |
| 3951 | #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) |
| 3952 | #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) |
| 3953 | |
| 3954 | #define __i2c_set_clk(dev_clk, i2c_clk) \ |
| 3955 | ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) |
| 3956 | |
| 3957 | #define __i2c_read() ( REG_I2C_DR ) |
| 3958 | #define __i2c_write(val) ( REG_I2C_DR = (val) ) |
| 3959 | |
| 3960 | |
| 3961 | /*************************************************************************** |
| 3962 | * MSC |
| 3963 | ***************************************************************************/ |
| 3964 | |
| 3965 | #define __msc_start_op() \ |
| 3966 | ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) |
| 3967 | |
| 3968 | #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) |
| 3969 | #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) |
| 3970 | #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) |
| 3971 | #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) |
| 3972 | #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) |
| 3973 | #define __msc_get_nob() ( REG_MSC_NOB ) |
| 3974 | #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) |
| 3975 | #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) |
| 3976 | #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) |
| 3977 | #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) |
| 3978 | |
| 3979 | #define __msc_set_cmdat_bus_width1() \ |
| 3980 | do { \ |
| 3981 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ |
| 3982 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ |
| 3983 | } while(0) |
| 3984 | |
| 3985 | #define __msc_set_cmdat_bus_width4() \ |
| 3986 | do { \ |
| 3987 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ |
| 3988 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ |
| 3989 | } while(0) |
| 3990 | |
| 3991 | #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) |
| 3992 | #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) |
| 3993 | #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) |
| 3994 | #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) |
| 3995 | #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) |
| 3996 | #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) |
| 3997 | #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) |
| 3998 | #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) |
| 3999 | |
| 4000 | /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ |
| 4001 | #define __msc_set_cmdat_res_format(r) \ |
| 4002 | do { \ |
| 4003 | REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ |
| 4004 | REG_MSC_CMDAT |= (r); \ |
| 4005 | } while(0) |
| 4006 | |
| 4007 | #define __msc_clear_cmdat() \ |
| 4008 | REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ |
| 4009 | MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ |
| 4010 | MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) |
| 4011 | |
| 4012 | #define __msc_get_imask() ( REG_MSC_IMASK ) |
| 4013 | #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) |
| 4014 | #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) |
| 4015 | #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) |
| 4016 | #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) |
| 4017 | #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) |
| 4018 | #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) |
| 4019 | #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) |
| 4020 | #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) |
| 4021 | #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) |
| 4022 | #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) |
| 4023 | #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) |
| 4024 | #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) |
| 4025 | |
| 4026 | /* n=0,1,2,3,4,5,6,7 */ |
| 4027 | #define __msc_set_clkrt(n) \ |
| 4028 | do { \ |
| 4029 | REG_MSC_CLKRT = n; \ |
| 4030 | } while(0) |
| 4031 | |
| 4032 | #define __msc_get_ireg() ( REG_MSC_IREG ) |
| 4033 | #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) |
| 4034 | #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) |
| 4035 | #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) |
| 4036 | #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) |
| 4037 | #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) |
| 4038 | #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) |
| 4039 | #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) |
| 4040 | #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) |
| 4041 | |
| 4042 | #define __msc_get_stat() ( REG_MSC_STAT ) |
| 4043 | #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) |
| 4044 | #define __msc_stat_crc_err() \ |
| 4045 | ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) |
| 4046 | #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) |
| 4047 | #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) |
| 4048 | #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) |
| 4049 | #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) |
| 4050 | #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) |
| 4051 | |
| 4052 | #define __msc_rd_resfifo() ( REG_MSC_RES ) |
| 4053 | #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) |
| 4054 | #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) |
| 4055 | |
| 4056 | #define __msc_reset() \ |
| 4057 | do { \ |
| 4058 | REG_MSC_STRPCL = MSC_STRPCL_RESET; \ |
| 4059 | while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ |
| 4060 | } while (0) |
| 4061 | |
| 4062 | #define __msc_start_clk() \ |
| 4063 | do { \ |
| 4064 | REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ |
| 4065 | } while (0) |
| 4066 | |
| 4067 | #define __msc_stop_clk() \ |
| 4068 | do { \ |
| 4069 | REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ |
| 4070 | } while (0) |
| 4071 | |
| 4072 | #define MMC_CLK 19169200 |
| 4073 | #define SD_CLK 24576000 |
| 4074 | |
| 4075 | /* msc_clk should little than pclk and little than clk retrieve from card */ |
| 4076 | #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ |
| 4077 | do { \ |
| 4078 | unsigned int rate, pclk, i; \ |
| 4079 | pclk = dev_clk; \ |
| 4080 | rate = type?SD_CLK:MMC_CLK; \ |
| 4081 | if (msc_clk && msc_clk < pclk) \ |
| 4082 | pclk = msc_clk; \ |
| 4083 | i = 0; \ |
| 4084 | while (pclk < rate) \ |
| 4085 | { \ |
| 4086 | i ++; \ |
| 4087 | rate >>= 1; \ |
| 4088 | } \ |
| 4089 | lv = i; \ |
| 4090 | } while(0) |
| 4091 | |
| 4092 | /* divide rate to little than or equal to 400kHz */ |
| 4093 | #define __msc_calc_slow_clk_divisor(type, lv) \ |
| 4094 | do { \ |
| 4095 | unsigned int rate, i; \ |
| 4096 | rate = (type?SD_CLK:MMC_CLK)/1000/400; \ |
| 4097 | i = 0; \ |
| 4098 | while (rate > 0) \ |
| 4099 | { \ |
| 4100 | rate >>= 1; \ |
| 4101 | i ++; \ |
| 4102 | } \ |
| 4103 | lv = i; \ |
| 4104 | } while(0) |
| 4105 | |
| 4106 | |
| 4107 | /*************************************************************************** |
| 4108 | * SSI |
| 4109 | ***************************************************************************/ |
| 4110 | |
| 4111 | #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) |
| 4112 | #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) |
| 4113 | #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) |
| 4114 | |
| 4115 | #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) |
| 4116 | |
| 4117 | #define __ssi_select_ce2() \ |
| 4118 | do { \ |
| 4119 | REG_SSI_CR0 |= SSI_CR0_FSEL; \ |
| 4120 | REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ |
| 4121 | } while (0) |
| 4122 | |
| 4123 | #define __ssi_select_gpc() \ |
| 4124 | do { \ |
| 4125 | REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ |
| 4126 | REG_SSI_CR1 |= SSI_CR1_MULTS; \ |
| 4127 | } while (0) |
| 4128 | |
| 4129 | #define __ssi_enable_tx_intr() \ |
| 4130 | ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) |
| 4131 | |
| 4132 | #define __ssi_disable_tx_intr() \ |
| 4133 | ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) |
| 4134 | |
| 4135 | #define __ssi_enable_rx_intr() \ |
| 4136 | ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) |
| 4137 | |
| 4138 | #define __ssi_disable_rx_intr() \ |
| 4139 | ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) |
| 4140 | |
| 4141 | #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) |
| 4142 | #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) |
| 4143 | |
| 4144 | #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) |
| 4145 | #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) |
| 4146 | |
| 4147 | #define __ssi_finish_receive() \ |
| 4148 | ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
| 4149 | |
| 4150 | #define __ssi_disable_recvfinish() \ |
| 4151 | ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
| 4152 | |
| 4153 | #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) |
| 4154 | #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) |
| 4155 | |
| 4156 | #define __ssi_flush_fifo() \ |
| 4157 | ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) |
| 4158 | |
| 4159 | #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) |
| 4160 | |
| 4161 | #define __ssi_spi_format() \ |
| 4162 | do { \ |
| 4163 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ |
| 4164 | REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ |
| 4165 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ |
| 4166 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ |
| 4167 | } while (0) |
| 4168 | |
| 4169 | /* TI's SSP format, must clear SSI_CR1.UNFIN */ |
| 4170 | #define __ssi_ssp_format() \ |
| 4171 | do { \ |
| 4172 | REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ |
| 4173 | REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ |
| 4174 | } while (0) |
| 4175 | |
| 4176 | /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ |
| 4177 | #define __ssi_microwire_format() \ |
| 4178 | do { \ |
| 4179 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ |
| 4180 | REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ |
| 4181 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ |
| 4182 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ |
| 4183 | REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ |
| 4184 | } while (0) |
| 4185 | |
| 4186 | /* CE# level (FRMHL), CE# in interval time (ITFRM), |
| 4187 | clock phase and polarity (PHA POL), |
| 4188 | interval time (SSIITR), interval characters/frame (SSIICR) */ |
| 4189 | |
| 4190 | /* frmhl,endian,mcom,flen,pha,pol MASK */ |
| 4191 | #define SSICR1_MISC_MASK \ |
| 4192 | ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ |
| 4193 | | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ |
| 4194 | |
| 4195 | #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ |
| 4196 | do { \ |
| 4197 | REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ |
| 4198 | REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ |
| 4199 | (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ |
| 4200 | ((pha) << 1) | (pol); \ |
| 4201 | } while(0) |
| 4202 | |
| 4203 | /* Transfer with MSB or LSB first */ |
| 4204 | #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) |
| 4205 | #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) |
| 4206 | |
| 4207 | #define __ssi_set_frame_length(n) \ |
| 4208 | REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) |
| 4209 | |
| 4210 | /* n = 1 - 16 */ |
| 4211 | #define __ssi_set_microwire_command_length(n) \ |
| 4212 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) |
| 4213 | |
| 4214 | /* Set the clock phase for SPI */ |
| 4215 | #define __ssi_set_spi_clock_phase(n) \ |
| 4216 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) |
| 4217 | |
| 4218 | /* Set the clock polarity for SPI */ |
| 4219 | #define __ssi_set_spi_clock_polarity(n) \ |
| 4220 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) |
| 4221 | |
| 4222 | /* n = ix8 */ |
| 4223 | #define __ssi_set_tx_trigger(n) \ |
| 4224 | do { \ |
| 4225 | REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ |
| 4226 | REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ |
| 4227 | } while (0) |
| 4228 | |
| 4229 | /* n = ix8 */ |
| 4230 | #define __ssi_set_rx_trigger(n) \ |
| 4231 | do { \ |
| 4232 | REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ |
| 4233 | REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ |
| 4234 | } while (0) |
| 4235 | |
| 4236 | #define __ssi_get_txfifo_count() \ |
| 4237 | ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) |
| 4238 | |
| 4239 | #define __ssi_get_rxfifo_count() \ |
| 4240 | ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) |
| 4241 | |
| 4242 | #define __ssi_clear_errors() \ |
| 4243 | ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) |
| 4244 | |
| 4245 | #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) |
| 4246 | #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) |
| 4247 | |
| 4248 | #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) |
| 4249 | #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) |
| 4250 | #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) |
| 4251 | |
| 4252 | #define __ssi_set_clk(dev_clk, ssi_clk) \ |
| 4253 | ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) |
| 4254 | |
| 4255 | #define __ssi_receive_data() REG_SSI_DR |
| 4256 | #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) |
| 4257 | |
| 4258 | |
| 4259 | /*************************************************************************** |
| 4260 | * CIM |
| 4261 | ***************************************************************************/ |
| 4262 | |
| 4263 | #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) |
| 4264 | #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) |
| 4265 | |
| 4266 | #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) |
| 4267 | #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) |
| 4268 | |
| 4269 | #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) |
| 4270 | #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) |
| 4271 | |
| 4272 | #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) |
| 4273 | #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) |
| 4274 | |
| 4275 | #define __cim_sample_data_at_pclk_falling_edge() \ |
| 4276 | ( REG_CIM_CFG |= CIM_CFG_PCP ) |
| 4277 | #define __cim_sample_data_at_pclk_rising_edge() \ |
| 4278 | ( REG_CIM_CFG &= ~CIM_CFG_PCP ) |
| 4279 | |
| 4280 | #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) |
| 4281 | #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) |
| 4282 | |
| 4283 | #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) |
| 4284 | #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) |
| 4285 | |
| 4286 | /* n=0-7 */ |
| 4287 | #define __cim_set_data_packing_mode(n) \ |
| 4288 | do { \ |
| 4289 | REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ |
| 4290 | REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ |
| 4291 | } while (0) |
| 4292 | |
| 4293 | #define __cim_enable_ccir656_progressive_mode() \ |
| 4294 | do { \ |
| 4295 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| 4296 | REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ |
| 4297 | } while (0) |
| 4298 | |
| 4299 | #define __cim_enable_ccir656_interlace_mode() \ |
| 4300 | do { \ |
| 4301 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| 4302 | REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ |
| 4303 | } while (0) |
| 4304 | |
| 4305 | #define __cim_enable_gated_clock_mode() \ |
| 4306 | do { \ |
| 4307 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| 4308 | REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ |
| 4309 | } while (0) |
| 4310 | |
| 4311 | #define __cim_enable_nongated_clock_mode() \ |
| 4312 | do { \ |
| 4313 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| 4314 | REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ |
| 4315 | } while (0) |
| 4316 | |
| 4317 | /* sclk:system bus clock |
| 4318 | * mclk: CIM master clock |
| 4319 | */ |
| 4320 | #define __cim_set_master_clk(sclk, mclk) \ |
| 4321 | do { \ |
| 4322 | REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ |
| 4323 | REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ |
| 4324 | } while (0) |
| 4325 | |
| 4326 | #define __cim_enable_sof_intr() \ |
| 4327 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) |
| 4328 | #define __cim_disable_sof_intr() \ |
| 4329 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) |
| 4330 | |
| 4331 | #define __cim_enable_eof_intr() \ |
| 4332 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) |
| 4333 | #define __cim_disable_eof_intr() \ |
| 4334 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) |
| 4335 | |
| 4336 | #define __cim_enable_stop_intr() \ |
| 4337 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) |
| 4338 | #define __cim_disable_stop_intr() \ |
| 4339 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) |
| 4340 | |
| 4341 | #define __cim_enable_trig_intr() \ |
| 4342 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) |
| 4343 | #define __cim_disable_trig_intr() \ |
| 4344 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) |
| 4345 | |
| 4346 | #define __cim_enable_rxfifo_overflow_intr() \ |
| 4347 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) |
| 4348 | #define __cim_disable_rxfifo_overflow_intr() \ |
| 4349 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) |
| 4350 | |
| 4351 | /* n=1-16 */ |
| 4352 | #define __cim_set_frame_rate(n) \ |
| 4353 | do { \ |
| 4354 | REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ |
| 4355 | REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ |
| 4356 | } while (0) |
| 4357 | |
| 4358 | #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) |
| 4359 | #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) |
| 4360 | |
| 4361 | #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) |
| 4362 | #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) |
| 4363 | |
| 4364 | /* n=4,8,12,16,20,24,28,32 */ |
| 4365 | #define __cim_set_rxfifo_trigger(n) \ |
| 4366 | do { \ |
| 4367 | REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ |
| 4368 | REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ |
| 4369 | } while (0) |
| 4370 | |
| 4371 | #define __cim_clear_state() ( REG_CIM_STATE = 0 ) |
| 4372 | |
| 4373 | #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) |
| 4374 | #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) |
| 4375 | #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) |
| 4376 | #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) |
| 4377 | #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) |
| 4378 | #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) |
| 4379 | #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) |
| 4380 | #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) |
| 4381 | |
| 4382 | #define __cim_get_iid() ( REG_CIM_IID ) |
| 4383 | #define __cim_get_image_data() ( REG_CIM_RXFIFO ) |
| 4384 | #define __cim_get_dam_cmd() ( REG_CIM_CMD ) |
| 4385 | |
| 4386 | #define __cim_set_da(a) ( REG_CIM_DA = (a) ) |
| 4387 | |
| 4388 | /*************************************************************************** |
| 4389 | * LCD |
| 4390 | ***************************************************************************/ |
| 4391 | #define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) ) |
| 4392 | #define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) ) |
| 4393 | |
| 4394 | #define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) |
| 4395 | #define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) |
| 4396 | |
| 4397 | #define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) |
| 4398 | #define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) |
| 4399 | |
| 4400 | /* n=1,2,4,8,16 */ |
| 4401 | #define __lcd_set_bpp(n) \ |
| 4402 | ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) |
| 4403 | |
| 4404 | /* n=4,8,16 */ |
| 4405 | #define __lcd_set_burst_length(n) \ |
| 4406 | do { \ |
| 4407 | REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ |
| 4408 | REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ |
| 4409 | } while (0) |
| 4410 | |
| 4411 | #define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) |
| 4412 | #define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) |
| 4413 | |
| 4414 | #define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) |
| 4415 | #define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) |
| 4416 | |
| 4417 | /* n=2,4,16 */ |
| 4418 | #define __lcd_set_stn_frc(n) \ |
| 4419 | do { \ |
| 4420 | REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ |
| 4421 | REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ |
| 4422 | } while (0) |
| 4423 | |
| 4424 | |
| 4425 | #define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) |
| 4426 | #define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) |
| 4427 | |
| 4428 | #define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) |
| 4429 | #define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) |
| 4430 | |
| 4431 | #define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) |
| 4432 | #define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) |
| 4433 | |
| 4434 | #define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) |
| 4435 | #define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) |
| 4436 | |
| 4437 | #define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) |
| 4438 | #define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) |
| 4439 | |
| 4440 | #define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) |
| 4441 | #define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) |
| 4442 | |
| 4443 | #define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) |
| 4444 | #define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) |
| 4445 | |
| 4446 | #define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) |
| 4447 | #define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) |
| 4448 | |
| 4449 | #define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) |
| 4450 | #define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) |
| 4451 | |
| 4452 | |
| 4453 | /* LCD status register indication */ |
| 4454 | |
| 4455 | #define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) |
| 4456 | #define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) |
| 4457 | #define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) |
| 4458 | #define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) |
| 4459 | #define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) |
| 4460 | #define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) |
| 4461 | #define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) |
| 4462 | |
| 4463 | #define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) |
| 4464 | #define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) |
| 4465 | #define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) |
| 4466 | |
| 4467 | #define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE ) |
| 4468 | #define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE ) |
| 4469 | |
| 4470 | /* n=1,2,4,8 for single mono-STN |
| 4471 | * n=4,8 for dual mono-STN |
| 4472 | */ |
| 4473 | #define __lcd_set_panel_datawidth(n) \ |
| 4474 | do { \ |
| 4475 | REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \ |
| 4476 | REG_LCD_CFG |= LCD_CFG_PDW_n##; \ |
| 4477 | } while (0) |
| 4478 | |
| 4479 | /* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */ |
| 4480 | #define __lcd_set_panel_mode(m) \ |
| 4481 | do { \ |
| 4482 | REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \ |
| 4483 | REG_LCD_CFG |= (m); \ |
| 4484 | } while(0) |
| 4485 | |
| 4486 | /* n = 0-255 */ |
| 4487 | #define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) |
| 4488 | #define __lcd_set_ac_bias(n) \ |
| 4489 | do { \ |
| 4490 | REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ |
| 4491 | REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ |
| 4492 | } while(0) |
| 4493 | |
| 4494 | #define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) |
| 4495 | #define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) |
| 4496 | |
| 4497 | #define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) |
| 4498 | #define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) |
| 4499 | |
| 4500 | #define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) |
| 4501 | #define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) |
| 4502 | |
| 4503 | #define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) |
| 4504 | #define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) |
| 4505 | |
| 4506 | #define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) |
| 4507 | #define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) |
| 4508 | |
| 4509 | #define __lcd_vsync_get_vps() \ |
| 4510 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) |
| 4511 | |
| 4512 | #define __lcd_vsync_get_vpe() \ |
| 4513 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) |
| 4514 | #define __lcd_vsync_set_vpe(n) \ |
| 4515 | do { \ |
| 4516 | REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ |
| 4517 | REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ |
| 4518 | } while (0) |
| 4519 | |
| 4520 | #define __lcd_hsync_get_hps() \ |
| 4521 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) |
| 4522 | #define __lcd_hsync_set_hps(n) \ |
| 4523 | do { \ |
| 4524 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ |
| 4525 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ |
| 4526 | } while (0) |
| 4527 | |
| 4528 | #define __lcd_hsync_get_hpe() \ |
| 4529 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) |
| 4530 | #define __lcd_hsync_set_hpe(n) \ |
| 4531 | do { \ |
| 4532 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ |
| 4533 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ |
| 4534 | } while (0) |
| 4535 | |
| 4536 | #define __lcd_vat_get_ht() \ |
| 4537 | ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) |
| 4538 | #define __lcd_vat_set_ht(n) \ |
| 4539 | do { \ |
| 4540 | REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ |
| 4541 | REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ |
| 4542 | } while (0) |
| 4543 | |
| 4544 | #define __lcd_vat_get_vt() \ |
| 4545 | ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) |
| 4546 | #define __lcd_vat_set_vt(n) \ |
| 4547 | do { \ |
| 4548 | REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ |
| 4549 | REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ |
| 4550 | } while (0) |
| 4551 | |
| 4552 | #define __lcd_dah_get_hds() \ |
| 4553 | ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) |
| 4554 | #define __lcd_dah_set_hds(n) \ |
| 4555 | do { \ |
| 4556 | REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ |
| 4557 | REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ |
| 4558 | } while (0) |
| 4559 | |
| 4560 | #define __lcd_dah_get_hde() \ |
| 4561 | ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) |
| 4562 | #define __lcd_dah_set_hde(n) \ |
| 4563 | do { \ |
| 4564 | REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ |
| 4565 | REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ |
| 4566 | } while (0) |
| 4567 | |
| 4568 | #define __lcd_dav_get_vds() \ |
| 4569 | ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) |
| 4570 | #define __lcd_dav_set_vds(n) \ |
| 4571 | do { \ |
| 4572 | REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ |
| 4573 | REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ |
| 4574 | } while (0) |
| 4575 | |
| 4576 | #define __lcd_dav_get_vde() \ |
| 4577 | ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) |
| 4578 | #define __lcd_dav_set_vde(n) \ |
| 4579 | do { \ |
| 4580 | REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ |
| 4581 | REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ |
| 4582 | } while (0) |
| 4583 | |
| 4584 | #define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) |
| 4585 | #define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) |
| 4586 | #define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) |
| 4587 | #define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) |
| 4588 | |
| 4589 | #define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) |
| 4590 | #define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) |
| 4591 | #define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) |
| 4592 | #define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) |
| 4593 | |
| 4594 | #define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) |
| 4595 | #define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) |
| 4596 | |
| 4597 | #define __lcd_cmd0_get_len() \ |
| 4598 | ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
| 4599 | #define __lcd_cmd1_get_len() \ |
| 4600 | ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
| 4601 | |
| 4602 | /*************************************************************************** |
| 4603 | * RTC ops |
| 4604 | ***************************************************************************/ |
| 4605 | |
| 4606 | #define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) |
| 4607 | #define __rtc_enabled() \ |
| 4608 | do{ \ |
| 4609 | while(!__rtc_write_ready()); \ |
| 4610 | REG_RTC_RCR |= RTC_RCR_RTCE ; \ |
| 4611 | }while(0) \ |
| 4612 | |
| 4613 | #define __rtc_disabled() \ |
| 4614 | do{ \ |
| 4615 | while(!__rtc_write_ready()); \ |
| 4616 | REG_RTC_RCR &= ~RTC_RCR_RTCE; \ |
| 4617 | }while(0) |
| 4618 | #define __rtc_enable_alarm() \ |
| 4619 | do{ \ |
| 4620 | while(!__rtc_write_ready()); \ |
| 4621 | REG_RTC_RCR |= RTC_RCR_AE; \ |
| 4622 | }while(0) |
| 4623 | |
| 4624 | #define __rtc_disable_alarm() \ |
| 4625 | do{ \ |
| 4626 | while(!__rtc_write_ready()); \ |
| 4627 | REG_RTC_RCR &= ~RTC_RCR_AE; \ |
| 4628 | }while(0) |
| 4629 | |
| 4630 | #define __rtc_enable_alarm_irq() \ |
| 4631 | do{ \ |
| 4632 | while(!__rtc_write_ready()); \ |
| 4633 | REG_RTC_RCR |= RTC_RCR_AIE; \ |
| 4634 | }while(0) |
| 4635 | |
| 4636 | #define __rtc_disable_alarm_irq() \ |
| 4637 | do{ \ |
| 4638 | while(!__rtc_write_ready()); \ |
| 4639 | REG_RTC_RCR &= ~RTC_RCR_AIE; \ |
| 4640 | }while(0) |
| 4641 | #define __rtc_enable_Hz_irq() \ |
| 4642 | do{ \ |
| 4643 | while(!__rtc_write_ready()); \ |
| 4644 | REG_RTC_RCR |= RTC_RCR_HZIE; \ |
| 4645 | }while(0) |
| 4646 | |
| 4647 | #define __rtc_disable_Hz_irq() \ |
| 4648 | do{ \ |
| 4649 | while(!__rtc_write_ready()); \ |
| 4650 | REG_RTC_RCR &= ~RTC_RCR_HZIE; \ |
| 4651 | }while(0) |
| 4652 | #define __rtc_get_1Hz_flag() \ |
| 4653 | do{ \ |
| 4654 | while(!__rtc_write_ready()); \ |
| 4655 | ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ |
| 4656 | }while(0) |
| 4657 | #define __rtc_clear_1Hz_flag() \ |
| 4658 | do{ \ |
| 4659 | while(!__rtc_write_ready()); \ |
| 4660 | REG_RTC_RCR &= ~RTC_RCR_HZ; \ |
| 4661 | }while(0) |
| 4662 | #define __rtc_get_alarm_flag() \ |
| 4663 | do{ \ |
| 4664 | while(!__rtc_write_ready()); \ |
| 4665 | ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \ |
| 4666 | while(0) |
| 4667 | #define __rtc_clear_alarm_flag() \ |
| 4668 | do{ \ |
| 4669 | while(!__rtc_write_ready()); \ |
| 4670 | REG_RTC_RCR &= ~RTC_RCR_AF; \ |
| 4671 | }while(0) |
| 4672 | #define __rtc_get_second() \ |
| 4673 | do{ \ |
| 4674 | while(!__rtc_write_ready());\ |
| 4675 | REG_RTC_RSR; \ |
| 4676 | }while(0) |
| 4677 | |
| 4678 | #define __rtc_set_second(v) \ |
| 4679 | do{ \ |
| 4680 | while(!__rtc_write_ready()); \ |
| 4681 | REG_RTC_RSR = v; \ |
| 4682 | }while(0) |
| 4683 | |
| 4684 | #define __rtc_get_alarm_second() \ |
| 4685 | do{ \ |
| 4686 | while(!__rtc_write_ready()); \ |
| 4687 | REG_RTC_RSAR; \ |
| 4688 | }while(0) |
| 4689 | |
| 4690 | |
| 4691 | #define __rtc_set_alarm_second(v) \ |
| 4692 | do{ \ |
| 4693 | while(!__rtc_write_ready()); \ |
| 4694 | REG_RTC_RSAR = v; \ |
| 4695 | }while(0) |
| 4696 | |
| 4697 | #define __rtc_RGR_is_locked() \ |
| 4698 | do{ \ |
| 4699 | while(!__rtc_write_ready()); \ |
| 4700 | REG_RTC_RGR >> RTC_RGR_LOCK; \ |
| 4701 | }while(0) |
| 4702 | #define __rtc_lock_RGR() \ |
| 4703 | do{ \ |
| 4704 | while(!__rtc_write_ready()); \ |
| 4705 | REG_RTC_RGR |= RTC_RGR_LOCK; \ |
| 4706 | }while(0) |
| 4707 | |
| 4708 | #define __rtc_unlock_RGR() \ |
| 4709 | do{ \ |
| 4710 | while(!__rtc_write_ready()); \ |
| 4711 | REG_RTC_RGR &= ~RTC_RGR_LOCK; \ |
| 4712 | }while(0) |
| 4713 | |
| 4714 | #define __rtc_get_adjc_val() \ |
| 4715 | do{ \ |
| 4716 | while(!__rtc_write_ready()); \ |
| 4717 | ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ |
| 4718 | }while(0) |
| 4719 | #define __rtc_set_adjc_val(v) \ |
| 4720 | do{ \ |
| 4721 | while(!__rtc_write_ready()); \ |
| 4722 | ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \ |
| 4723 | }while(0) |
| 4724 | |
| 4725 | #define __rtc_get_nc1Hz_val() \ |
| 4726 | while(!__rtc_write_ready()); \ |
| 4727 | ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) |
| 4728 | |
| 4729 | #define __rtc_set_nc1Hz_val(v) \ |
| 4730 | do{ \ |
| 4731 | while(!__rtc_write_ready()); \ |
| 4732 | ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \ |
| 4733 | }while(0) |
| 4734 | #define __rtc_power_down() \ |
| 4735 | do{ \ |
| 4736 | while(!__rtc_write_ready()); \ |
| 4737 | REG_RTC_HCR |= RTC_HCR_PD; \ |
| 4738 | }while(0) |
| 4739 | |
| 4740 | #define __rtc_get_hwfcr_val() \ |
| 4741 | do{ \ |
| 4742 | while(!__rtc_write_ready()); \ |
| 4743 | REG_RTC_HWFCR & RTC_HWFCR_MASK; \ |
| 4744 | }while(0) |
| 4745 | #define __rtc_set_hwfcr_val(v) \ |
| 4746 | do{ \ |
| 4747 | while(!__rtc_write_ready()); \ |
| 4748 | REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ |
| 4749 | }while(0) |
| 4750 | |
| 4751 | #define __rtc_get_hrcr_val() \ |
| 4752 | do{ \ |
| 4753 | while(!__rtc_write_ready()); \ |
| 4754 | ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ |
| 4755 | }while(0) |
| 4756 | #define __rtc_set_hrcr_val(v) \ |
| 4757 | do{ \ |
| 4758 | while(!__rtc_write_ready()); \ |
| 4759 | ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ |
| 4760 | }while(0) |
| 4761 | |
| 4762 | #define __rtc_enable_alarm_wakeup() \ |
| 4763 | do{ \ |
| 4764 | while(!__rtc_write_ready()); \ |
| 4765 | ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ |
| 4766 | }while(0) |
| 4767 | |
| 4768 | #define __rtc_disable_alarm_wakeup() \ |
| 4769 | do{ \ |
| 4770 | while(!__rtc_write_ready()); \ |
| 4771 | ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ |
| 4772 | }while(0) |
| 4773 | |
| 4774 | #define __rtc_status_hib_reset_occur() \ |
| 4775 | do{ \ |
| 4776 | while(!__rtc_write_ready()); \ |
| 4777 | ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \ |
| 4778 | }while(0) |
| 4779 | #define __rtc_status_ppr_reset_occur() \ |
| 4780 | do{ \ |
| 4781 | while(!__rtc_write_ready()); \ |
| 4782 | ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \ |
| 4783 | }while(0) |
| 4784 | #define __rtc_status_wakeup_pin_waken_up() \ |
| 4785 | do{ \ |
| 4786 | while(!__rtc_write_ready()); \ |
| 4787 | ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ |
| 4788 | }while(0) |
| 4789 | #define __rtc_status_alarm_waken_up() \ |
| 4790 | do{ \ |
| 4791 | while(!__rtc_write_ready()); \ |
| 4792 | ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ |
| 4793 | }while(0) |
| 4794 | #define __rtc_clear_hib_stat_all() \ |
| 4795 | do{ \ |
| 4796 | while(!__rtc_write_ready()); \ |
| 4797 | ( REG_RTC_HWRSR = 0 ); \ |
| 4798 | }while(0) |
| 4799 | |
| 4800 | #define __rtc_get_scratch_pattern() \ |
| 4801 | while(!__rtc_write_ready()); \ |
| 4802 | (REG_RTC_HSPR) |
| 4803 | #define __rtc_set_scratch_pattern(n) \ |
| 4804 | do{ \ |
| 4805 | while(!__rtc_write_ready()); \ |
| 4806 | (REG_RTC_HSPR = n ); \ |
| 4807 | }while(0) |
| 4808 | |
| 4809 | #endif /* !__ASSEMBLY__ */ |
| 4810 | |
| 4811 | #endif /* __JZ4740_H__ */ |
| 4812 | |
