Root/xbboot/target-common/jz4760.h

1/*
2 * Include file for Ingenic Semiconductor's JZ4760 CPU.
3 */
4#ifndef __JZ4760_H__
5#define __JZ4760_H__
6
7#if 0 /* if 0, for spl program */
8#define UCOS_CSP 0
9
10#if UCOS_CSP
11#define __KERNEL__
12#include <bsp.h>
13#include <types.h>
14
15#include <sysdefs.h>
16#include <cacheops.h>
17#define KSEG0 KSEG0BASE
18#else
19#include <asm/addrspace.h>
20#include <asm/cacheops.h>
21#endif
22
23#define cache_unroll(base,op) \
24    __asm__ __volatile__(" \
25        .set noreorder; \
26        .set mips3; \
27        cache %1, (%0); \
28        .set mips0; \
29        .set reorder" \
30        : \
31        : "r" (base), \
32          "i" (op));
33
34static inline void jz_flush_dcache(void)
35{
36    unsigned long start;
37    unsigned long end;
38
39    start = KSEG0;
40    end = start + CFG_DCACHE_SIZE;
41    while (start < end) {
42        cache_unroll(start,Index_Writeback_Inv_D);
43        start += CFG_CACHELINE_SIZE;
44    }
45}
46
47static inline void jz_flush_icache(void)
48{
49    unsigned long start;
50    unsigned long end;
51
52    start = KSEG0;
53    end = start + CFG_ICACHE_SIZE;
54    while(start < end) {
55        cache_unroll(start,Index_Invalidate_I);
56        start += CFG_CACHELINE_SIZE;
57    }
58}
59
60/* cpu pipeline flush */
61static inline void jz_sync(void)
62{
63    __asm__ volatile ("sync");
64}
65
66static inline void jz_writeb(u32 address, u8 value)
67{
68    *((volatile u8 *)address) = value;
69}
70
71static inline void jz_writew(u32 address, u16 value)
72{
73    *((volatile u16 *)address) = value;
74}
75
76static inline void jz_writel(u32 address, u32 value)
77{
78    *((volatile u32 *)address) = value;
79}
80
81static inline u8 jz_readb(u32 address)
82{
83    return *((volatile u8 *)address);
84}
85
86static inline u16 jz_readw(u32 address)
87{
88    return *((volatile u16 *)address);
89}
90
91static inline u32 jz_readl(u32 address)
92{
93    return *((volatile u32 *)address);
94}
95#endif
96
97//----------------------------------------------------------------------
98// Boot ROM Specification
99//
100
101/* NOR Boot config */
102#define JZ4760_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
103#define JZ4760_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
104#define JZ4760_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
105
106/* NAND Boot config */
107#define JZ4760_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
108#define JZ4760_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
109#define JZ4760_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
110#define JZ4760_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
111
112
113//----------------------------------------------------------------------
114// Register Definitions
115//
116/* AHB0 BUS Devices Base */
117#define HARB0_BASE 0xB3000000
118#define EMC_BASE 0xB3010000
119#define DDRC_BASE 0xB3020000
120#define MDMAC_BASE 0xB3030000
121#define LCD_BASE 0xB3050000
122#define TVE_BASE 0xB3050000
123#define SLCD_BASE 0xB3050000
124#define CIM_BASE 0xB3060000
125#define IPU_BASE 0xB3080000
126/* AHB1 BUS Devices Base */
127#define HARB1_BASE 0xB3200000
128#define DMAGP0_BASE 0xB3210000
129#define DMAGP1_BASE 0xB3220000
130#define DMAGP2_BASE 0xB3230000
131#define MC_BASE 0xB3250000
132#define ME_BASE 0xB3260000
133#define DEBLK_BASE 0xB3270000
134#define IDCT_BASE 0xB3280000
135#define CABAC_BASE 0xB3290000
136#define TCSM0_BASE 0xB32B0000
137#define TCSM1_BASE 0xB32C0000
138#define SRAM_BASE 0xB32D0000
139/* AHB2 BUS Devices Base */
140#define HARB2_BASE 0xB3400000
141#define NEMC_BASE 0xB3410000
142#define DMAC_BASE 0xB3420000
143#define UHC_BASE 0xB3430000
144#define UDC_BASE 0xB3440000
145#define GPS_BASE 0xB3480000
146#define ETHC_BASE 0xB34B0000
147#define BCH_BASE 0xB34D0000
148/* APB BUS Devices Base */
149#define CPM_BASE 0xB0000000
150#define INTC_BASE 0xB0001000
151#define TCU_BASE 0xB0002000
152#define OST_BASE 0xB0002000
153#define WDT_BASE 0xB0002000
154#define RTC_BASE 0xB0003000
155#define GPIO_BASE 0xB0010000
156#define AIC_BASE 0xB0020000
157#define ICDC_BASE 0xB0020000
158#define MSC0_BASE 0xB0021000
159#define MSC1_BASE 0xB0022000
160#define MSC2_BASE 0xB0023000
161#define UART0_BASE 0xB0030000
162#define UART1_BASE 0xB0031000
163#define UART2_BASE 0xB0032000
164#define UART3_BASE 0xB0033000
165#define SCC_BASE 0xB0040000
166#define SSI0_BASE 0xB0043000
167#define SSI1_BASE 0xB0044000
168#define SSI2_BASE 0xB0045000
169#define I2C0_BASE 0xB0050000
170#define I2C1_BASE 0xB0051000
171#define PS2_BASE 0xB0060000
172#define SADC_BASE 0xB0070000
173#define OWI_BASE 0xB0072000
174#define TSSI_BASE 0xB0073000
175
176/*************************************************************************
177 * INTC (Interrupt Controller)
178 *************************************************************************/
179#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20)
180#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20)
181#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20)
182#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20)
183#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20)
184
185#define REG_INTC_ISR(n) REG32(INTC_ISR((n)))
186#define REG_INTC_IMR(n) REG32(INTC_IMR((n)))
187#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n)))
188#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n)))
189#define REG_INTC_IPR(n) REG32(INTC_IPR((n)))
190
191
192// 1st-level interrupts
193#define IRQ_I2C1 0
194#define IRQ_I2C0 1
195#define IRQ_UART3 2
196#define IRQ_UART2 3
197#define IRQ_UART1 4
198#define IRQ_UART0 5
199#define IRQ_SSI2 6
200#define IRQ_SSI1 7
201#define IRQ_SSI0 8
202#define IRQ_TSSI 9
203#define IRQ_BDMA 10
204#define IRQ_KBC 11
205#define IRQ_GPIO5 12
206#define IRQ_GPIO4 13
207#define IRQ_GPIO3 14
208#define IRQ_GPIO2 15
209#define IRQ_GPIO1 16
210#define IRQ_GPIO0 17
211#define IRQ_SADC 18
212#define IRQ_ETH 19
213#define IRQ_UHC 20
214#define IRQ_OTG 21
215#define IRQ_MDMA 22
216#define IRQ_DMAC1 23
217#define IRQ_DMAC0 24
218#define IRQ_TCU2 25
219#define IRQ_TCU1 26
220#define IRQ_TCU0 27
221#define IRQ_GPS 28
222#define IRQ_IPU 29
223#define IRQ_CIM 30
224#define IRQ_LCD 31
225
226#define IRQ_RTC 32
227#define IRQ_OWI 33
228#define IRQ_AIC 34
229#define IRQ_MSC2 35
230#define IRQ_MSC1 36
231#define IRQ_MSC0 37
232#define IRQ_SCC 38
233#define IRQ_BCH 39
234#define IRQ_PCM 40
235
236// 2nd-level interrupts
237#define IRQ_DMA_0 64 /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */
238#define IRQ_DMA_1 (IRQ_DMA_0 + HALF_DMA_NUM) /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */
239#define IRQ_MDMA_0 (IRQ_DMA_0 + MAX_DMA_NUM) /* 64 ~ 66 for MDMAC channel 0 ~ 2 */
240
241#define IRQ_GPIO_0 96 /* 96 to 287 for GPIO pin 0 to 127 */
242
243#define NUM_INTC 41
244#define NUM_DMA MAX_DMA_NUM /* 12 */
245#define NUM_MDMA MAX_MDMA_NUM /* 3 */
246#define NUM_GPIO MAX_GPIO_NUM /* GPIO NUM: 192, Jz4760 real num GPIO 178 */
247
248/*************************************************************************
249 * RTC
250 *************************************************************************/
251#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
252#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
253#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
254#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
255
256#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
257#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
258#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
259#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
260#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
261#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
262#define RTC_WENR (RTC_BASE + 0x3c) /* Write enable pattern register */
263
264#define REG_RTC_RCR REG32(RTC_RCR)
265#define REG_RTC_RSR REG32(RTC_RSR)
266#define REG_RTC_RSAR REG32(RTC_RSAR)
267#define REG_RTC_RGR REG32(RTC_RGR)
268#define REG_RTC_HCR REG32(RTC_HCR)
269#define REG_RTC_HWFCR REG32(RTC_HWFCR)
270#define REG_RTC_HRCR REG32(RTC_HRCR)
271#define REG_RTC_HWCR REG32(RTC_HWCR)
272#define REG_RTC_HWRSR REG32(RTC_HWRSR)
273#define REG_RTC_HSPR REG32(RTC_HSPR)
274#define REG_RTC_WENR REG32(RTC_WENR)
275
276/* RTC Control Register */
277#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
278#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
279#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
280#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
281#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
282#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
283#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
284
285/* RTC Regulator Register */
286#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
287#define RTC_RGR_ADJC_BIT 16
288#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
289#define RTC_RGR_NC1HZ_BIT 0
290#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
291
292/* Hibernate Control Register */
293#define RTC_HCR_PD (1 << 0) /* Power Down */
294
295/* Hibernate Wakeup Filter Counter Register */
296#define RTC_HWFCR_BIT 5
297#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
298
299/* Hibernate Reset Counter Register */
300#define RTC_HRCR_BIT 5
301#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
302
303/* Hibernate Wakeup Control Register */
304#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
305
306/* Hibernate Wakeup Status Register */
307#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
308#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
309#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
310#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
311
312/* Write enable pattern register */
313#define RTC_WENR_WEN (1 << 31) /* write has been enabled */
314#define RTC_WENR_WENPAT_BIT 0
315#define RTC_WENR_WENPAT_MASK (0xffff << RTC_WENR_WENPAT_BIT) /* The write enable pattern. */
316
317
318/*************************************************************************
319 * CPM (Clock reset and Power control Management)
320 *************************************************************************/
321#define CPM_CPCCR (CPM_BASE+0x00) /* Clock control register */
322#define CPM_CPPCR (CPM_BASE+0x10) /* PLL control register 0 */
323#define CPM_CPPSR (CPM_BASE+0x14) /* PLL switch and status Register */
324#define CPM_CPPCR1 (CPM_BASE+0x30) /* PLL control register 1 */
325#define CPM_CPSPR (CPM_BASE+0x34) /* CPM scratch pad register */
326#define CPM_CPSPPR (CPM_BASE+0x38) /* CPM scratch protected register */
327#define CPM_USBPCR (CPM_BASE+0x3c) /* USB parameter control register */
328#define CPM_USBRDT (CPM_BASE+0x40) /* USB reset detect timer register */
329#define CPM_USBVBFIL (CPM_BASE+0x44) /* USB jitter filter register */
330#define CPM_USBCDR (CPM_BASE+0x50) /* USB OTG PHY clock divider register */
331#define CPM_I2SCDR (CPM_BASE+0x60) /* I2S device clock divider register */
332#define CPM_LPCDR (CPM_BASE+0x64) /* LCD pix clock divider register */
333#define CPM_MSCCDR (CPM_BASE+0x68) /* MSC clock divider register */
334#define CPM_UHCCDR (CPM_BASE+0x6C) /* UHC 48M clock divider register */
335#define CPM_SSICDR (CPM_BASE+0x74) /* SSI clock divider register */
336#define CPM_CIMCDR (CPM_BASE+0x7c) /* CIM MCLK clock divider register */
337#define CPM_GPSCDR (CPM_BASE+0x80) /* GPS clock divider register */
338#define CPM_PCMCDR (CPM_BASE+0x84) /* PCM device clock divider register */
339#define CPM_GPUCDR (CPM_BASE+0x88) /* GPU clock divider register */
340
341#define CPM_LCR (CPM_BASE+0x04)
342#define CPM_PSWCST(n) (CPM_BASE+0x4*(n)+0x90)
343#define CPM_CLKGR0 (CPM_BASE+0x20) /* Clock Gate Register0 */
344#define CPM_CLKGR1 (CPM_BASE+0x28) /* Clock Gate Register1 */
345#define CPM_OPCR (CPM_BASE+0x24) /* Oscillator and Power Control Register */
346
347#define CPM_RSR (CPM_BASE+0x08)
348
349
350#define REG_CPM_CPCCR REG32(CPM_CPCCR)
351#define REG_CPM_CPPCR REG32(CPM_CPPCR)
352#define REG_CPM_CPPSR REG32(CPM_CPPSR)
353#define REG_CPM_CPPCR1 REG32(CPM_CPPCR1)
354#define REG_CPM_CPSPR REG32(CPM_CPSPR)
355#define REG_CPM_CPSPPR REG32(CPM_CPSPPR)
356#define REG_CPM_USBPCR REG32(CPM_USBPCR)
357#define REG_CPM_USBRDT REG32(CPM_USBRDT)
358#define REG_CPM_USBVBFIL REG32(CPM_USBVBFIL)
359#define REG_CPM_USBCDR REG32(CPM_USBCDR)
360#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
361#define REG_CPM_LPCDR REG32(CPM_LPCDR)
362#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
363#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
364#define REG_CPM_SSICDR REG32(CPM_SSICDR)
365#define REG_CPM_CIMCDR REG32(CPM_CIMCDR)
366#define REG_CPM_GPSCDR REG32(CPM_GPSCDR)
367#define REG_CPM_PCMCDR REG32(CPM_PCMCDR)
368#define REG_CPM_GPUCDR REG32(CPM_GPUCDR)
369
370#define REG_CPM_LCR REG32(CPM_LCR)
371#define REG_CPM_CLKGR0 REG32(CPM_CLKGR0)
372#define REG_CPM_CLKGR1 REG32(CPM_CLKGR1)
373#define REG_CPM_OPCR REG32(CPM_OPCR)
374
375#define REG_CPM_RSR REG32(CPM_RSR)
376/* Clock control register */
377#define CPM_CPCCR_ECS (0x01 << 31)
378#define CPM_CPCCR_MEM (0x01 << 30)
379#define CPM_CPCCR_SDIV_BIT 24
380#define CPM_CPCCR_SDIV_MASK (0x0f << CPM_CPCCR_SDIV_BIT)
381#define CPM_CPCCR_CE (0x01 << 22)
382#define CPM_CPCCR_PCS (0x01 << 21)
383#define CPM_CPCCR_H2DIV_BIT 16
384#define CPM_CPCCR_H2DIV_MASK (0x0f << CPM_CPCCR_H2DIV_BIT)
385#define CPM_CPCCR_MDIV_BIT 12
386#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
387#define CPM_CPCCR_PDIV_BIT 8
388#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
389#define CPM_CPCCR_HDIV_BIT 4
390#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
391#define CPM_CPCCR_CDIV_BIT 0
392#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
393
394/* PLL control register 0 */
395#define CPM_CPPCR_PLLM_BIT 24
396#define CPM_CPPCR_PLLM_MASK (0x7f << CPM_CPPCR_PLLM_BIT)
397#define CPM_CPPCR_PLLN_BIT 18
398#define CPM_CPPCR_PLLN_MASK (0x0f << CPM_CPPCR_PLLN_BIT)
399#define CPM_CPPCR_PLLOD_BIT 16
400#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
401#define CPM_CPPCR_LOCK0 (1 << 15)
402#define CPM_CPPCR_ENLOCK (1 << 14)
403#define CPM_CPPCR_PLLS (1 << 10)
404#define CPM_CPPCR_PLLBP (1 << 9)
405#define CPM_CPPCR_PLLEN (1 << 8)
406#define CPM_CPPCR_PLLST_BIT 0
407#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
408
409/* PLL control register 1 */
410#define CPM_CPPCR1_PLL1M_BIT 24
411#define CPM_CPPCR1_PLL1M_MASK (0x7f << CPM_CPPCR1_PLL1M_BIT)
412#define CPM_CPPCR1_PLL1N_BIT 18
413#define CPM_CPPCR1_PLL1N_MASK (0x0f << CPM_CPPCR1_PLL1N_BIT)
414#define CPM_CPPCR1_PLL1OD_BIT 16
415#define CPM_CPPCR1_PLL1OD_MASK (0x03 << CPM_CPPCR1_PLL1OD_BIT)
416#define CPM_CPPCR1_P1SCS (1 << 15)
417#define CPM_CPPCR1_P1SDIV_BIT 9
418#define CPM_CPPCR1_P1SDIV_MASK (0x3f << CPM_CPPCR1_P1SDIV_BIT)
419#define CPM_CPPCR1_PLL1EN (1 << 7)
420#define CPM_CPPCR1_PLL1S (1 << 6)
421#define CPM_CPPCR1_LOCK1 (1 << 2)
422#define CPM_CPPCR1_PLL1OFF (1 << 1)
423#define CPM_CPPCR1_PLL1ON (1 << 0)
424
425/* PLL switch and status Register */
426#define CPM_CPPSR_PLLOFF (1 << 31)
427#define CPM_CPPSR_PLLBP (1 << 30)
428#define CPM_CPPSR_PLLON (1 << 29)
429#define CPM_CPPSR_PS (1 << 28)
430#define CPM_CPPSR_FS (1 << 27)
431#define CPM_CPPSR_CS (1 << 26)
432#define CPM_CPPSR_SM (1 << 2)
433#define CPM_CPPSR_PM (1 << 1)
434#define CPM_CPPSR_FM (1 << 0)
435
436/* CPM scratch protected register */
437#define CPM_CPSPPR_BIT 0
438#define CPM_CPSPPR_MASK (0xffff << CPM_CPSPPR_BIT)
439
440/* USB parameter control register */
441#define CPM_USBPCR_USB_MODE (1 << 31) /* 1: OTG, 0: UDC*/
442#define CPM_USBPCR_AVLD_REG (1 << 30)
443#define CPM_USBPCR_IDPULLUP_MASK_BIT 28
444#define CPM_USBPCR_IDPULLUP_MASK_MASK (0x02 << IDPULLUP_MASK_BIT)
445#define CPM_USBPCR_INCR_MASK (1 << 27)
446#define CPM_USBPCR_CLK12_EN (1 << 26)
447#define CPM_USBPCR_COMMONONN (1 << 25)
448#define CPM_USBPCR_VBUSVLDEXT (1 << 24)
449#define CPM_USBPCR_VBUSVLDEXTSEL (1 << 23)
450#define CPM_USBPCR_POR (1 << 22)
451#define CPM_USBPCR_SIDDQ (1 << 21)
452#define CPM_USBPCR_OTG_DISABLE (1 << 20)
453#define CPM_USBPCR_COMPDISTUNE_BIT 17
454#define CPM_USBPCR_COMPDISTUNE_MASK (0x07 << COMPDISTUNE_BIT)
455#define CPM_USBPCR_OTGTUNE_BIT 14
456#define CPM_USBPCR_OTGTUNE_MASK (0x07 << OTGTUNE_BIT)
457#define CPM_USBPCR_SQRXTUNE_BIT 11
458#define CPM_USBPCR_SQRXTUNE_MASK (0x7x << SQRXTUNE_BIT)
459#define CPM_USBPCR_TXFSLSTUNE_BIT 7
460#define CPM_USBPCR_TXFSLSTUNE_MASK (0x0f << TXFSLSTUNE_BIT)
461#define CPM_USBPCR_TXPREEMPHTUNE (1 << 6)
462#define CPM_USBPCR_TXRISETUNE_BIT 4
463#define CPM_USBPCR_TXRISETUNE_MASK (0x03 << TXRISETUNE_BIT)
464#define CPM_USBPCR_TXVREFTUNE_BIT 0
465#define CPM_USBPCR_TXVREFTUNE_MASK (0x0f << TXVREFTUNE_BIT)
466
467/* USB reset detect timer register */
468#define CPM_USBRDT_VBFIL_LD_EN (1 << 25)
469#define CPM_USBRDT_IDDIG_EN (1 << 24)
470#define CPM_USBRDT_IDDIG_REG (1 << 23)
471#define CPM_USBRDT_USBRDT_BIT 0
472#define CPM_USBRDT_USBRDT_MASK (0x7fffff << CPM_USBRDT_USBRDT_BIT)
473
474/* USB OTG PHY clock divider register */
475#define CPM_USBCDR_UCS (1 << 31)
476#define CPM_USBCDR_UPCS (1 << 30)
477#define CPM_USBCDR_OTGDIV_BIT 0
478#define CPM_USBCDR_OTGDIV_MASK (0x3f << CPM_USBCDR_OTGDIV_BIT)
479
480/* I2S device clock divider register */
481#define CPM_I2SCDR_I2CS (1 << 31)
482#define CPM_I2SCDR_I2PCS (1 << 30)
483#define CPM_I2SCDR_I2SDIV_BIT 0
484#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
485
486/* LCD pix clock divider register */
487#define CPM_LPCDR_LSCS (1 << 31)
488#define CPM_LPCDR_LTCS (1 << 30)
489#define CPM_LPCDR_LPCS (1 << 29)
490#define CPM_LPCDR_PIXDIV_BIT 0
491#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
492
493/* MSC clock divider register */
494#define CPM_MSCCDR_MCS (1 << 31)
495#define CPM_MSCCDR_MSCDIV_BIT 0
496#define CPM_MSCCDR_MSCDIV_MASK (0x3f << CPM_MSCCDR_PIXDIV_BIT)
497
498/* UHC 48M clock divider register */
499#define CPM_UHCCDR_UHPCS (1 << 31)
500#define CPM_UHCCDR_UHCDIV_BIT 0
501#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
502
503/* SSI clock divider register */
504#define CPM_SSICDR_SCS (1 << 31)
505#define CPM_SSICDR_SSIDIV_BIT 0
506#define CPM_SSICDR_SSIDIV_MASK (0x3f << CPM_SSICDR_SSIDIV_BIT)
507
508/* CIM MCLK clock divider register */
509#define CPM_CIMCDR_CIMDIV_BIT 0
510#define CPM_CIMCDR_CIMDIV_MASK (0xff << CPM_CIMCDR_CIMDIV_BIT)
511
512/* GPS clock divider register */
513#define CPM_GPSCDR_GPCS (1 << 31)
514#define CPM_GPSCDR_GPSDIV_BIT 0
515#define CPM_GSPCDR_GPSDIV_MASK (0xf << CPM_GPSCDR_GPSDIV_BIT)
516
517/* PCM device clock divider register */
518#define CPM_PCMCDR_PCMS (1 << 31)
519#define CPM_PCMCDR_PCMPCS (1 << 30)
520#define CPM_PCMCDR_PCMDIV_BIT 0
521#define CPM_PCMCDR_PCMDIV_MASK (0x1ff << CPM_PCMCDR_PCMDIV_BIT)
522
523/* GPU clock divider register */
524#define CPM_GPUCDR_GPCS (1 << 31)
525#define CPM_GPUCDR_GPUDIV_BIT 0
526#define CPM_GPUCDR_GPUDIV_MASK (0x7 << CPM_GPUCDR_GPUDIV_BIT)
527
528/* Low Power Control Register */
529#define CPM_LCR_PD_AHB1 (1 << 30)
530#define CPM_LCR_VBAT_IR (1 << 29)
531#define CPM_LCR_PD_GPS (1 << 28)
532#define CPM_LCR_PD_AHB1S (1 << 26)
533#define CPM_LCR_PD_GPSS (1 << 24)
534#define CPM_LCR_PST_BIT 8
535#define CPM_LCR_PST_MASK (0xfff << CPM_LCR_PST_BIT)
536#define CPM_LCR_DOZE_DUTY_BIT 3
537#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
538#define CPM_LCR_DOZE_ON (1 << 2)
539#define CPM_LCR_LPM_BIT 0
540#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
541  #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
542  #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
543
544/* Clock Gate Register0 */
545#define CPM_CLKGR0_EMC (1 << 31)
546#define CPM_CLKGR0_DDR (1 << 30)
547#define CPM_CLKGR0_IPU (1 << 29)
548#define CPM_CLKGR0_LCD (1 << 28)
549#define CPM_CLKGR0_TVE (1 << 27)
550#define CPM_CLKGR0_CIM (1 << 26)
551#define CPM_CLKGR0_MDMA (1 << 25)
552#define CPM_CLKGR0_UHC (1 << 24)
553#define CPM_CLKGR0_MAC (1 << 23)
554#define CPM_CLKGR0_GPS (1 << 22)
555#define CPM_CLKGR0_DMAC (1 << 21)
556#define CPM_CLKGR0_SSI2 (1 << 20)
557#define CPM_CLKGR0_SSI1 (1 << 19)
558#define CPM_CLKGR0_UART3 (1 << 18)
559#define CPM_CLKGR0_UART2 (1 << 17)
560#define CPM_CLKGR0_UART1 (1 << 16)
561#define CPM_CLKGR0_UART0 (1 << 15)
562#define CPM_CLKGR0_SADC (1 << 14)
563#define CPM_CLKGR0_KBC (1 << 13)
564#define CPM_CLKGR0_MSC2 (1 << 12)
565#define CPM_CLKGR0_MSC1 (1 << 11)
566#define CPM_CLKGR0_OWI (1 << 10)
567#define CPM_CLKGR0_TSSI (1 << 9)
568#define CPM_CLKGR0_AIC (1 << 8)
569#define CPM_CLKGR0_SCC (1 << 7)
570#define CPM_CLKGR0_I2C1 (1 << 6)
571#define CPM_CLKGR0_I2C0 (1 << 5)
572#define CPM_CLKGR0_SSI0 (1 << 4)
573#define CPM_CLKGR0_MSC0 (1 << 3)
574#define CPM_CLKGR0_OTG (1 << 2)
575#define CPM_CLKGR0_BCH (1 << 1)
576#define CPM_CLKGR0_NEMC (1 << 0)
577
578/* Clock Gate Register1 */
579#define CPM_CLKGR1_GPU (1 << 9)
580#define CPM_CLKGR1_PCM (1 << 8)
581#define CPM_CLKGR1_AHB1 (1 << 7)
582#define CPM_CLKGR1_CABAC (1 << 6)
583#define CPM_CLKGR1_SRAM (1 << 5)
584#define CPM_CLKGR1_DCT (1 << 4)
585#define CPM_CLKGR1_ME (1 << 3)
586#define CPM_CLKGR1_DBLK (1 << 2)
587#define CPM_CLKGR1_MC (1 << 1)
588#define CPM_CLKGR1_BDMA (1 << 0)
589
590/* Oscillator and Power Control Register */
591#define CPM_OPCR_O1ST_BIT 8
592#define CPM_OPCR_O1ST_MASK (0xff << CPM_OPCR_O1ST_BIT)
593#define CPM_OPCR_SPENDN (1 << 7)
594#define CPM_OPCR_GPSEN (1 << 6)
595#define CPM_OPCR_SPENDH (1 << 5)
596#define CPM_OPCR_O1SE (1 << 4) /* */
597#define CPM_OPCR_ERCS (1 << 2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
598#define CPM_OPCR_USBM (1 << 0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
599
600
601/* Reset Status Register */
602#define CPM_RSR_P0R (1 << 2)
603#define CPM_RSR_WR (1 << 1)
604#define CPM_RSR_PR (1 << 0)
605
606
607/*************************************************************************
608 * TCU (Timer Counter Unit)
609 *************************************************************************/
610#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
611#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
612#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
613#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
614#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
615#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
616#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
617#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
618#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
619#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
620#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
621#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
622#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
623#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
624#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
625#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
626#define TCU_TDFR1 (TCU_BASE + 0x50)
627#define TCU_TDHR1 (TCU_BASE + 0x54)
628#define TCU_TCNT1 (TCU_BASE + 0x58)
629#define TCU_TCSR1 (TCU_BASE + 0x5C)
630#define TCU_TDFR2 (TCU_BASE + 0x60)
631#define TCU_TDHR2 (TCU_BASE + 0x64)
632#define TCU_TCNT2 (TCU_BASE + 0x68)
633#define TCU_TCSR2 (TCU_BASE + 0x6C)
634#define TCU_TDFR3 (TCU_BASE + 0x70)
635#define TCU_TDHR3 (TCU_BASE + 0x74)
636#define TCU_TCNT3 (TCU_BASE + 0x78)
637#define TCU_TCSR3 (TCU_BASE + 0x7C)
638#define TCU_TDFR4 (TCU_BASE + 0x80)
639#define TCU_TDHR4 (TCU_BASE + 0x84)
640#define TCU_TCNT4 (TCU_BASE + 0x88)
641#define TCU_TCSR4 (TCU_BASE + 0x8C)
642#define TCU_TDFR5 (TCU_BASE + 0x90)
643#define TCU_TDHR5 (TCU_BASE + 0x94)
644#define TCU_TCNT5 (TCU_BASE + 0x98)
645#define TCU_TCSR5 (TCU_BASE + 0x9C)
646
647#define REG_TCU_TSR REG32(TCU_TSR)
648#define REG_TCU_TSSR REG32(TCU_TSSR)
649#define REG_TCU_TSCR REG32(TCU_TSCR)
650#define REG_TCU_TER REG8(TCU_TER)
651#define REG_TCU_TESR REG8(TCU_TESR)
652#define REG_TCU_TECR REG8(TCU_TECR)
653#define REG_TCU_TFR REG32(TCU_TFR)
654#define REG_TCU_TFSR REG32(TCU_TFSR)
655#define REG_TCU_TFCR REG32(TCU_TFCR)
656#define REG_TCU_TMR REG32(TCU_TMR)
657#define REG_TCU_TMSR REG32(TCU_TMSR)
658#define REG_TCU_TMCR REG32(TCU_TMCR)
659#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
660#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
661#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
662#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
663#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
664#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
665#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
666#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
667#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
668#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
669#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
670#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
671#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
672#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
673#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
674#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
675#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
676#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
677#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
678#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
679
680// n = 0,1,2,3,4,5
681#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
682#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
683#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
684#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
685
686#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
687#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
688#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
689#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
690
691// Register definitions
692#define TCU_TCSR_PWM_SD (1 << 9)
693#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
694#define TCU_TCSR_PWM_EN (1 << 7)
695#define TCU_TCSR_PRESCALE_BIT 3
696#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
697  #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
698  #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
699  #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
700  #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
701  #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
702  #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
703#define TCU_TCSR_EXT_EN (1 << 2)
704#define TCU_TCSR_RTC_EN (1 << 1)
705#define TCU_TCSR_PCK_EN (1 << 0)
706
707#define TCU_TER_TCEN5 (1 << 5)
708#define TCU_TER_TCEN4 (1 << 4)
709#define TCU_TER_TCEN3 (1 << 3)
710#define TCU_TER_TCEN2 (1 << 2)
711#define TCU_TER_TCEN1 (1 << 1)
712#define TCU_TER_TCEN0 (1 << 0)
713
714#define TCU_TESR_TCST5 (1 << 5)
715#define TCU_TESR_TCST4 (1 << 4)
716#define TCU_TESR_TCST3 (1 << 3)
717#define TCU_TESR_TCST2 (1 << 2)
718#define TCU_TESR_TCST1 (1 << 1)
719#define TCU_TESR_TCST0 (1 << 0)
720
721#define TCU_TECR_TCCL5 (1 << 5)
722#define TCU_TECR_TCCL4 (1 << 4)
723#define TCU_TECR_TCCL3 (1 << 3)
724#define TCU_TECR_TCCL2 (1 << 2)
725#define TCU_TECR_TCCL1 (1 << 1)
726#define TCU_TECR_TCCL0 (1 << 0)
727
728#define TCU_TFR_HFLAG5 (1 << 21)
729#define TCU_TFR_HFLAG4 (1 << 20)
730#define TCU_TFR_HFLAG3 (1 << 19)
731#define TCU_TFR_HFLAG2 (1 << 18)
732#define TCU_TFR_HFLAG1 (1 << 17)
733#define TCU_TFR_HFLAG0 (1 << 16)
734#define TCU_TFR_FFLAG5 (1 << 5)
735#define TCU_TFR_FFLAG4 (1 << 4)
736#define TCU_TFR_FFLAG3 (1 << 3)
737#define TCU_TFR_FFLAG2 (1 << 2)
738#define TCU_TFR_FFLAG1 (1 << 1)
739#define TCU_TFR_FFLAG0 (1 << 0)
740
741#define TCU_TFSR_HFLAG5 (1 << 21)
742#define TCU_TFSR_HFLAG4 (1 << 20)
743#define TCU_TFSR_HFLAG3 (1 << 19)
744#define TCU_TFSR_HFLAG2 (1 << 18)
745#define TCU_TFSR_HFLAG1 (1 << 17)
746#define TCU_TFSR_HFLAG0 (1 << 16)
747#define TCU_TFSR_FFLAG5 (1 << 5)
748#define TCU_TFSR_FFLAG4 (1 << 4)
749#define TCU_TFSR_FFLAG3 (1 << 3)
750#define TCU_TFSR_FFLAG2 (1 << 2)
751#define TCU_TFSR_FFLAG1 (1 << 1)
752#define TCU_TFSR_FFLAG0 (1 << 0)
753
754#define TCU_TFCR_HFLAG5 (1 << 21)
755#define TCU_TFCR_HFLAG4 (1 << 20)
756#define TCU_TFCR_HFLAG3 (1 << 19)
757#define TCU_TFCR_HFLAG2 (1 << 18)
758#define TCU_TFCR_HFLAG1 (1 << 17)
759#define TCU_TFCR_HFLAG0 (1 << 16)
760#define TCU_TFCR_FFLAG5 (1 << 5)
761#define TCU_TFCR_FFLAG4 (1 << 4)
762#define TCU_TFCR_FFLAG3 (1 << 3)
763#define TCU_TFCR_FFLAG2 (1 << 2)
764#define TCU_TFCR_FFLAG1 (1 << 1)
765#define TCU_TFCR_FFLAG0 (1 << 0)
766
767#define TCU_TMR_HMASK5 (1 << 21)
768#define TCU_TMR_HMASK4 (1 << 20)
769#define TCU_TMR_HMASK3 (1 << 19)
770#define TCU_TMR_HMASK2 (1 << 18)
771#define TCU_TMR_HMASK1 (1 << 17)
772#define TCU_TMR_HMASK0 (1 << 16)
773#define TCU_TMR_FMASK5 (1 << 5)
774#define TCU_TMR_FMASK4 (1 << 4)
775#define TCU_TMR_FMASK3 (1 << 3)
776#define TCU_TMR_FMASK2 (1 << 2)
777#define TCU_TMR_FMASK1 (1 << 1)
778#define TCU_TMR_FMASK0 (1 << 0)
779
780#define TCU_TMSR_HMST5 (1 << 21)
781#define TCU_TMSR_HMST4 (1 << 20)
782#define TCU_TMSR_HMST3 (1 << 19)
783#define TCU_TMSR_HMST2 (1 << 18)
784#define TCU_TMSR_HMST1 (1 << 17)
785#define TCU_TMSR_HMST0 (1 << 16)
786#define TCU_TMSR_FMST5 (1 << 5)
787#define TCU_TMSR_FMST4 (1 << 4)
788#define TCU_TMSR_FMST3 (1 << 3)
789#define TCU_TMSR_FMST2 (1 << 2)
790#define TCU_TMSR_FMST1 (1 << 1)
791#define TCU_TMSR_FMST0 (1 << 0)
792
793#define TCU_TMCR_HMCL5 (1 << 21)
794#define TCU_TMCR_HMCL4 (1 << 20)
795#define TCU_TMCR_HMCL3 (1 << 19)
796#define TCU_TMCR_HMCL2 (1 << 18)
797#define TCU_TMCR_HMCL1 (1 << 17)
798#define TCU_TMCR_HMCL0 (1 << 16)
799#define TCU_TMCR_FMCL5 (1 << 5)
800#define TCU_TMCR_FMCL4 (1 << 4)
801#define TCU_TMCR_FMCL3 (1 << 3)
802#define TCU_TMCR_FMCL2 (1 << 2)
803#define TCU_TMCR_FMCL1 (1 << 1)
804#define TCU_TMCR_FMCL0 (1 << 0)
805
806#define TCU_TSR_WDTS (1 << 16)
807#define TCU_TSR_STOP5 (1 << 5)
808#define TCU_TSR_STOP4 (1 << 4)
809#define TCU_TSR_STOP3 (1 << 3)
810#define TCU_TSR_STOP2 (1 << 2)
811#define TCU_TSR_STOP1 (1 << 1)
812#define TCU_TSR_STOP0 (1 << 0)
813
814#define TCU_TSSR_WDTSS (1 << 16)
815#define TCU_TSSR_STPS5 (1 << 5)
816#define TCU_TSSR_STPS4 (1 << 4)
817#define TCU_TSSR_STPS3 (1 << 3)
818#define TCU_TSSR_STPS2 (1 << 2)
819#define TCU_TSSR_STPS1 (1 << 1)
820#define TCU_TSSR_STPS0 (1 << 0)
821
822#define TCU_TSSR_WDTSC (1 << 16)
823#define TCU_TSSR_STPC5 (1 << 5)
824#define TCU_TSSR_STPC4 (1 << 4)
825#define TCU_TSSR_STPC3 (1 << 3)
826#define TCU_TSSR_STPC2 (1 << 2)
827#define TCU_TSSR_STPC1 (1 << 1)
828#define TCU_TSSR_STPC0 (1 << 0)
829
830
831/*************************************************************************
832 * WDT (WatchDog Timer)
833 *************************************************************************/
834#define WDT_TDR (WDT_BASE + 0x00)
835#define WDT_TCER (WDT_BASE + 0x04)
836#define WDT_TCNT (WDT_BASE + 0x08)
837#define WDT_TCSR (WDT_BASE + 0x0C)
838
839#define REG_WDT_TDR REG16(WDT_TDR)
840#define REG_WDT_TCER REG8(WDT_TCER)
841#define REG_WDT_TCNT REG16(WDT_TCNT)
842#define REG_WDT_TCSR REG16(WDT_TCSR)
843
844// Register definition
845#define WDT_TCSR_PRESCALE_BIT 3
846#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
847  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
848  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
849  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
850  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
851  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
852  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
853#define WDT_TCSR_EXT_EN (1 << 2)
854#define WDT_TCSR_RTC_EN (1 << 1)
855#define WDT_TCSR_PCK_EN (1 << 0)
856
857#define WDT_TCER_TCEN (1 << 0)
858
859/*************************************************************************
860 * MDMAC (MEM Copy DMA Controller)
861 *************************************************************************/
862
863#define MAX_MDMA_NUM 3 /* max 3 channels */
864
865/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
866
867#define MDMAC_DSAR(n) (MDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
868#define MDMAC_DTAR(n) (MDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
869#define MDMAC_DTCR(n) (MDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
870#define MDMAC_DRSR(n) (MDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
871#define MDMAC_DCCSR(n) (MDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
872#define MDMAC_DCMD(n) (MDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
873#define MDMAC_DDA(n) (MDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
874#define MDMAC_DSD(n) (MDMAC_BASE + (0xc0 + (n) * 0x04)) /* DMA Stride Address */
875
876#define MDMAC_DMACR (MDMAC_BASE + 0x0300) /* DMA control register */
877#define MDMAC_DMAIPR (MDMAC_BASE + 0x0304) /* DMA interrupt pending */
878#define MDMAC_DMADBR (MDMAC_BASE + 0x0308) /* DMA doorbell */
879#define MDMAC_DMADBSR (MDMAC_BASE + 0x030C) /* DMA doorbell set */
880#define MDMAC_DMACKE (MDMAC_BASE + 0x0310)
881
882#define REG_MDMAC_DSAR(n) REG32(MDMAC_DSAR((n)))
883#define REG_MDMAC_DTAR(n) REG32(MDMAC_DTAR((n)))
884#define REG_MDMAC_DTCR(n) REG32(MDMAC_DTCR((n)))
885#define REG_MDMAC_DRSR(n) REG32(MDMAC_DRSR((n)))
886#define REG_MDMAC_DCCSR(n) REG32(MDMAC_DCCSR((n)))
887#define REG_MDMAC_DCMD(n) REG32(MDMAC_DCMD((n)))
888#define REG_MDMAC_DDA(n) REG32(MDMAC_DDA((n)))
889#define REG_MDMAC_DSD(n) REG32(MDMAC_DSD(n))
890#define REG_MDMAC_DMACR REG32(MDMAC_DMACR)
891#define REG_MDMAC_DMAIPR REG32(MDMAC_DMAIPR)
892#define REG_MDMAC_DMADBR REG32(MDMAC_DMADBR)
893#define REG_MDMAC_DMADBSR REG32(MDMAC_DMADBSR)
894#define REG_MDMAC_DMACKE REG32(MDMAC_DMACKE)
895
896
897/*************************************************************************
898 * DMAC (DMA Controller)
899 *************************************************************************/
900
901#define MAX_DMA_NUM 12 /* max 12 channels */
902#define HALF_DMA_NUM 6 /* the number of one dma controller's channels */
903
904/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
905
906#define DMAC_DSAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x00 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA source address */
907#define DMAC_DTAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x04 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA target address */
908#define DMAC_DTCR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x08 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA transfer count */
909#define DMAC_DRSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x0c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA request source */
910#define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */
911#define DMAC_DCMD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */
912#define DMAC_DDA(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */
913#define DMAC_DSD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0xc0 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */
914
915#define DMAC_DMACR(m) (DMAC_BASE + 0x0300 + 0x100 * m) /* DMA control register */
916#define DMAC_DMAIPR(m) (DMAC_BASE + 0x0304 + 0x100 * m) /* DMA interrupt pending */
917#define DMAC_DMADBR(m) (DMAC_BASE + 0x0308 + 0x100 * m) /* DMA doorbell */
918#define DMAC_DMADBSR(m) (DMAC_BASE + 0x030C + 0x100 * m) /* DMA doorbell set */
919#define DMAC_DMADCKE(m) (DMAC_BASE + 0x0310 + 0x100 * m)
920
921#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
922#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
923#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
924#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
925#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
926#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
927#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
928#define REG_DMAC_DSD(n) REG32(DMAC_DSD(n))
929#define REG_DMAC_DMACR(m) REG32(DMAC_DMACR(m))
930#define REG_DMAC_DMAIPR(m) REG32(DMAC_DMAIPR(m))
931#define REG_DMAC_DMADBR(m) REG32(DMAC_DMADBR(m))
932#define REG_DMAC_DMADBSR(m) REG32(DMAC_DMADBSR(m))
933#define REG_DMAC_DMADCKE(m) REG32(DMAC_DMADCKE(m))
934
935// DMA request source register
936#define DMAC_DRSR_RS_BIT 0
937#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
938  #define DMAC_DRSR_RS_EXT (0 << DMAC_DRSR_RS_BIT)
939  #define DMAC_DRSR_RS_NAND (1 << DMAC_DRSR_RS_BIT)
940  #define DMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT)
941  #define DMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT)
942  #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
943  #define DMAC_DRSR_RS_TSSIIN (9 << DMAC_DRSR_RS_BIT)
944  #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT)
945  #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT)
946  #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT)
947  #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT)
948  #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT)
949  #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT)
950  #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
951  #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
952  #define DMAC_DRSR_RS_SSI0OUT (22 << DMAC_DRSR_RS_BIT)
953  #define DMAC_DRSR_RS_SSI0IN (23 << DMAC_DRSR_RS_BIT)
954  #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
955  #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
956  #define DMAC_DRSR_RS_MSC0OUT (26 << DMAC_DRSR_RS_BIT)
957  #define DMAC_DRSR_RS_MSC0IN (27 << DMAC_DRSR_RS_BIT)
958  #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
959  #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
960  #define DMAC_DRSR_RS_MSC1OUT (30 << DMAC_DRSR_RS_BIT)
961  #define DMAC_DRSR_RS_MSC1IN (31 << DMAC_DRSR_RS_BIT)
962  #define DMAC_DRSR_RS_SSI1OUT (32 << DMAC_DRSR_RS_BIT)
963  #define DMAC_DRSR_RS_SSI1IN (33 << DMAC_DRSR_RS_BIT)
964  #define DMAC_DRSR_RS_PMOUT (34 << DMAC_DRSR_RS_BIT)
965  #define DMAC_DRSR_RS_PMIN (35 << DMAC_DRSR_RS_BIT)
966
967// DMA channel control/status register
968#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
969#define DMAC_DCCSR_DES8 (1 << 30) /* Descriptor 8 Word */
970#define DMAC_DCCSR_DES4 (0 << 30) /* Descriptor 4 Word */
971#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
972#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
973#define DMAC_DCCSR_BERR (1 << 7) /* BCH error within this transfer, Only for channel 0 */
974#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
975#define DMAC_DCCSR_AR (1 << 4) /* address error */
976#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
977#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
978#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
979#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
980
981// DMA channel command register
982#define DMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */
983#define DMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */
984#define DMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */
985#define DMAC_DCMD_EACKM_READ (0 << 30) /* External DACK Output Mode Select, output in read cycle */
986#define DMAC_DCMD_ERDM_BIT 28 /* External DREQ Detection Mode Select */
987#define DMAC_DCMD_ERDM_MASK (0x03 << DMAC_DCMD_ERDM_BIT)
988  #define DMAC_DCMD_ERDM_LOW (0 << DMAC_DCMD_ERDM_BIT)
989  #define DMAC_DCMD_ERDM_FALL (1 << DMAC_DCMD_ERDM_BIT)
990  #define DMAC_DCMD_ERDM_HIGH (2 << DMAC_DCMD_ERDM_BIT)
991  #define DMAC_DCMD_ERDM_RISE (3 << DMAC_DCMD_ERDM_BIT)
992#define DMAC_DCMD_BLAST (1 << 25) /* BCH last */
993#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
994#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
995#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
996#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
997  #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
998  #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
999  #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
1000  #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
1001  #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
1002  #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
1003  #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
1004  #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
1005  #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
1006  #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
1007  #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
1008  #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
1009  #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
1010  #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
1011  #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
1012  #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
1013#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
1014#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
1015  #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
1016  #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
1017  #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
1018#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
1019#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
1020  #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
1021  #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
1022  #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
1023#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
1024#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
1025  #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
1026  #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
1027  #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
1028  #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
1029  #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
1030  #define DMAC_DCMD_DS_64BYTE (5 << DMAC_DCMD_DS_BIT)
1031#define DMAC_DCMD_STDE (1 << 5) /* Stride Disable/Enable */
1032#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
1033#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
1034#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
1035#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
1036#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
1037
1038// DMA descriptor address register
1039#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
1040#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
1041#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
1042#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
1043
1044// DMA stride address register
1045#define DMAC_DSD_TSD_BIT 16 /* target stride address */
1046#define DMAC_DSD_TSD_MASK (0xffff << DMAC_DSD_TSD_BIT)
1047#define DMAC_DSD_SSD_BIT 0 /* source stride address */
1048#define DMAC_DSD_SSD_MASK (0xffff << DMAC_DSD_SSD_BIT)
1049
1050// DMA control register
1051#define DMAC_DMACR_FMSC (1 << 31) /* MSC Fast DMA mode */
1052#define DMAC_DMACR_FSSI (1 << 30) /* SSI Fast DMA mode */
1053#define DMAC_DMACR_FTSSI (1 << 29) /* TSSI Fast DMA mode */
1054#define DMAC_DMACR_FUART (1 << 28) /* UART Fast DMA mode */
1055#define DMAC_DMACR_FAIC (1 << 27) /* AIC Fast DMA mode */
1056#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
1057#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
1058  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
1059  #define DMAC_DMACR_PR_120345 (1 << DMAC_DMACR_PR_BIT)
1060  #define DMAC_DMACR_PR_230145 (2 << DMAC_DMACR_PR_BIT)
1061  #define DMAC_DMACR_PR_340125 (3 << DMAC_DMACR_PR_BIT)
1062#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
1063#define DMAC_DMACR_AR (1 << 2) /* address error flag */
1064#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
1065
1066// DMA doorbell register
1067#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
1068#define DMAC_DMADBR_DB4 (1 << 4) /* doorbell for channel 4 */
1069#define DMAC_DMADBR_DB3 (1 << 3) /* doorbell for channel 3 */
1070#define DMAC_DMADBR_DB2 (1 << 2) /* doorbell for channel 2 */
1071#define DMAC_DMADBR_DB1 (1 << 1) /* doorbell for channel 1 */
1072#define DMAC_DMADBR_DB0 (1 << 0) /* doorbell for channel 0 */
1073
1074// DMA doorbell set register
1075#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
1076#define DMAC_DMADBSR_DBS4 (1 << 4) /* enable doorbell for channel 4 */
1077#define DMAC_DMADBSR_DBS3 (1 << 3) /* enable doorbell for channel 3 */
1078#define DMAC_DMADBSR_DBS2 (1 << 2) /* enable doorbell for channel 2 */
1079#define DMAC_DMADBSR_DBS1 (1 << 1) /* enable doorbell for channel 1 */
1080#define DMAC_DMADBSR_DBS0 (1 << 0) /* enable doorbell for channel 0 */
1081
1082// DMA interrupt pending register
1083#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
1084#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
1085#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
1086#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
1087#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
1088#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
1089
1090
1091/*************************************************************************
1092 * GPIO (General-Purpose I/O Ports)
1093 *************************************************************************/
1094#define MAX_GPIO_NUM 192
1095
1096//n = 0,1,2,3,4,5
1097#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
1098#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
1099#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
1100#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
1101#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
1102#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
1103#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
1104#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Disable Register */
1105#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Disable Set Reg. */
1106#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Disable Clear Reg. */
1107#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
1108#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
1109#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
1110#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
1111#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
1112#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
1113#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
1114#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
1115#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
1116#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
1117#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
1118#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Clear Register */
1119#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
1120#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
1121
1122#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
1123#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
1124#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
1125#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
1126#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
1127#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
1128#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
1129#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
1130#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
1131#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
1132#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO/INTR, 1:FUNC */
1133#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
1134#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
1135#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
1136#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
1137#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
1138#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
1139#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
1140#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
1141#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:Level-trigger/Fun0, 1:Edge-trigger/Fun1 */
1142#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
1143#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
1144#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
1145#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
1146
1147
1148/*************************************************************************
1149 * UART
1150 *************************************************************************/
1151
1152#define IRDA_BASE UART0_BASE
1153//#define UART_BASE UART0_BASE
1154#define UART_OFF 0x1000
1155
1156/* Register Offset */
1157#define OFF_RDR (0x00) /* R 8b H'xx */
1158#define OFF_TDR (0x00) /* W 8b H'xx */
1159#define OFF_DLLR (0x00) /* RW 8b H'00 */
1160#define OFF_DLHR (0x04) /* RW 8b H'00 */
1161#define OFF_IER (0x04) /* RW 8b H'00 */
1162#define OFF_ISR (0x08) /* R 8b H'01 */
1163#define OFF_FCR (0x08) /* W 8b H'00 */
1164#define OFF_LCR (0x0C) /* RW 8b H'00 */
1165#define OFF_MCR (0x10) /* RW 8b H'00 */
1166#define OFF_LSR (0x14) /* R 8b H'00 */
1167#define OFF_MSR (0x18) /* R 8b H'00 */
1168#define OFF_SPR (0x1C) /* RW 8b H'00 */
1169#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
1170#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
1171#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
1172
1173/* Register Address */
1174#define UART0_RDR (UART0_BASE + OFF_RDR)
1175#define UART0_TDR (UART0_BASE + OFF_TDR)
1176#define UART0_DLLR (UART0_BASE + OFF_DLLR)
1177#define UART0_DLHR (UART0_BASE + OFF_DLHR)
1178#define UART0_IER (UART0_BASE + OFF_IER)
1179#define UART0_ISR (UART0_BASE + OFF_ISR)
1180#define UART0_FCR (UART0_BASE + OFF_FCR)
1181#define UART0_LCR (UART0_BASE + OFF_LCR)
1182#define UART0_MCR (UART0_BASE + OFF_MCR)
1183#define UART0_LSR (UART0_BASE + OFF_LSR)
1184#define UART0_MSR (UART0_BASE + OFF_MSR)
1185#define UART0_SPR (UART0_BASE + OFF_SPR)
1186#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
1187#define UART0_UMR (UART0_BASE + OFF_UMR)
1188#define UART0_UACR (UART0_BASE + OFF_UACR)
1189
1190/*
1191 * Define macros for UART_IER
1192 * UART Interrupt Enable Register
1193 */
1194#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
1195#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
1196#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
1197#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
1198#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
1199
1200/*
1201 * Define macros for UART_ISR
1202 * UART Interrupt Status Register
1203 */
1204#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
1205#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
1206#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
1207#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
1208#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
1209#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
1210#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
1211#define UART_ISR_FFMS_NO_FIFO (0 << 6)
1212#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
1213
1214/*
1215 * Define macros for UART_FCR
1216 * UART FIFO Control Register
1217 */
1218#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
1219#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
1220#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
1221#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
1222#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
1223#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
1224#define UART_FCR_RTRG_1 (0 << 6)
1225#define UART_FCR_RTRG_4 (1 << 6)
1226#define UART_FCR_RTRG_8 (2 << 6)
1227#define UART_FCR_RTRG_15 (3 << 6)
1228
1229/*
1230 * Define macros for UART_LCR
1231 * UART Line Control Register
1232 */
1233#define UART_LCR_WLEN (3 << 0) /* word length */
1234#define UART_LCR_WLEN_5 (0 << 0)
1235#define UART_LCR_WLEN_6 (1 << 0)
1236#define UART_LCR_WLEN_7 (2 << 0)
1237#define UART_LCR_WLEN_8 (3 << 0)
1238#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1239                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1240#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1241                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1242#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1243                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1244
1245#define UART_LCR_PE (1 << 3) /* 0: parity disable */
1246#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
1247#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
1248#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
1249#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
1250
1251/*
1252 * Define macros for UART_LSR
1253 * UART Line Status Register
1254 */
1255#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
1256#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
1257#define UART_LSR_PER (1 << 2) /* 0: no parity error */
1258#define UART_LSR_FER (1 << 3) /* 0; no framing error */
1259#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
1260#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
1261#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
1262#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
1263
1264/*
1265 * Define macros for UART_MCR
1266 * UART Modem Control Register
1267 */
1268#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
1269#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
1270#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
1271#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
1272#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
1273#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
1274
1275/*
1276 * Define macros for UART_MSR
1277 * UART Modem Status Register
1278 */
1279#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
1280#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
1281#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
1282#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
1283#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
1284#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
1285#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
1286#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
1287
1288/*
1289 * Define macros for SIRCR
1290 * Slow IrDA Control Register
1291 */
1292#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
1293#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
1294#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1295                       1: 0 pulse width is 1.6us for 115.2Kbps */
1296#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1297#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1298
1299
1300/*************************************************************************
1301 * AIC (AC97/I2S Controller)
1302 *************************************************************************/
1303#define AIC_FR (AIC_BASE + 0x000)
1304#define AIC_CR (AIC_BASE + 0x004)
1305#define AIC_ACCR1 (AIC_BASE + 0x008)
1306#define AIC_ACCR2 (AIC_BASE + 0x00C)
1307#define AIC_I2SCR (AIC_BASE + 0x010)
1308#define AIC_SR (AIC_BASE + 0x014)
1309#define AIC_ACSR (AIC_BASE + 0x018)
1310#define AIC_I2SSR (AIC_BASE + 0x01C)
1311#define AIC_ACCAR (AIC_BASE + 0x020)
1312#define AIC_ACCDR (AIC_BASE + 0x024)
1313#define AIC_ACSAR (AIC_BASE + 0x028)
1314#define AIC_ACSDR (AIC_BASE + 0x02C)
1315#define AIC_I2SDIV (AIC_BASE + 0x030)
1316#define AIC_DR (AIC_BASE + 0x034)
1317
1318#define REG_AIC_FR REG32(AIC_FR)
1319#define REG_AIC_CR REG32(AIC_CR)
1320#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1321#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1322#define REG_AIC_I2SCR REG32(AIC_I2SCR)
1323#define REG_AIC_SR REG32(AIC_SR)
1324#define REG_AIC_ACSR REG32(AIC_ACSR)
1325#define REG_AIC_I2SSR REG32(AIC_I2SSR)
1326#define REG_AIC_ACCAR REG32(AIC_ACCAR)
1327#define REG_AIC_ACCDR REG32(AIC_ACCDR)
1328#define REG_AIC_ACSAR REG32(AIC_ACSAR)
1329#define REG_AIC_ACSDR REG32(AIC_ACSDR)
1330#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1331#define REG_AIC_DR REG32(AIC_DR)
1332
1333/* AIC Controller Configuration Register (AIC_FR) */
1334
1335#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1336#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1337#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1338#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1339#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1340#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1341#define AIC_FR_RST (1 << 3) /* AIC registers reset */
1342#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1343#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1344#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1345
1346/* AIC Controller Common Control Register (AIC_CR) */
1347
1348#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1349#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1350  #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1351  #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1352  #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1353  #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1354  #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1355#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1356#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1357  #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1358  #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1359  #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1360  #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1361  #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1362#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1363#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1364#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1365#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1366#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1367#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1368#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1369#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1370#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1371#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1372#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1373#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1374#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1375
1376/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1377
1378#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1379#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1380  #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1381  #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1382  #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1383  #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1384  #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1385  #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1386  #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1387  #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1388  #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1389  #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1390#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1391#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1392  #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1393  #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1394  #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1395  #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1396  #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1397  #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1398  #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1399  #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1400  #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1401  #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1402
1403/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1404
1405#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1406#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1407#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1408#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1409#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1410  #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1411  #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1412  #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1413  #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1414#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1415#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1416  #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1417  #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1418  #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1419  #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1420#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1421#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1422#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1423#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1424
1425/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1426
1427#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1428#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1429#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1430  #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1431  #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1432  #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1433  #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1434  #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1435#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1436
1437/* AIC Controller FIFO Status Register (AIC_SR) */
1438
1439#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1440#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1441#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1442#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1443#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1444#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1445#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1446#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1447
1448/* AIC Controller AC-link Status Register (AIC_ACSR) */
1449
1450#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1451#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1452#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1453#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1454#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1455#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1456
1457/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1458
1459#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1460
1461/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1462
1463#define AIC_ACCAR_CAR_BIT 0
1464#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1465
1466/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1467
1468#define AIC_ACCDR_CDR_BIT 0
1469#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1470
1471/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1472
1473#define AIC_ACSAR_SAR_BIT 0
1474#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1475
1476/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1477
1478#define AIC_ACSDR_SDR_BIT 0
1479#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1480
1481/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1482
1483#define AIC_I2SDIV_DIV_BIT 0
1484#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1485  #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1486  #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1487  #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1488  #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1489  #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1490  #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1491
1492
1493/*************************************************************************
1494 * ICDC (Internal CODEC)
1495 *************************************************************************/
1496#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1497#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1498#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1499#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1500#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1501#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1502#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1503
1504#define REG_ICDC_CR REG32(ICDC_CR)
1505#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1506#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1507#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1508#define REG_ICDC_APSR REG32(ICDC_APSR)
1509#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1510#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1511
1512/* ICDC Control Register */
1513#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1514#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1515#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1516#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1517  #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1518  #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1519  #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1520  #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1521  #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1522  #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1523  #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1524  #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1525  #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1526#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1527#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1528  #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1529  #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1530  #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1531  #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1532#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1533#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1534  #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1535  #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1536  #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1537  #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1538#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1539#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1540#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1541#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1542#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1543#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1544#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1545#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1546#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1547#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1548#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1549#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1550
1551/* Anti-Pop WAIT Stage Timing Control Register */
1552#define ICDC_APWAIT_WAITSN_BIT 0
1553#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1554
1555/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1556#define ICDC_APPRE_PRESN_BIT 0
1557#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1558
1559/* Anti-Pop HPEN Stage Timing Control Register */
1560#define ICDC_APHPEN_HPENSN_BIT 0
1561#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1562
1563/* Anti-Pop Status Register */
1564#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1565#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1566#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1567#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1568  #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1569#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1570  #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1571  #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1572  #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1573  #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1574#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1575#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1576
1577
1578/*************************************************************************
1579 * I2C
1580 *************************************************************************/
1581#define I2C_DR (I2C_BASE + 0x000)
1582#define I2C_CR (I2C_BASE + 0x004)
1583#define I2C_SR (I2C_BASE + 0x008)
1584#define I2C_GR (I2C_BASE + 0x00C)
1585
1586#define REG_I2C_DR REG8(I2C_DR)
1587#define REG_I2C_CR REG8(I2C_CR)
1588#define REG_I2C_SR REG8(I2C_SR)
1589#define REG_I2C_GR REG16(I2C_GR)
1590
1591/* I2C Control Register (I2C_CR) */
1592
1593#define I2C_CR_IEN (1 << 4)
1594#define I2C_CR_STA (1 << 3)
1595#define I2C_CR_STO (1 << 2)
1596#define I2C_CR_AC (1 << 1)
1597#define I2C_CR_I2CE (1 << 0)
1598
1599/* I2C Status Register (I2C_SR) */
1600
1601#define I2C_SR_STX (1 << 4)
1602#define I2C_SR_BUSY (1 << 3)
1603#define I2C_SR_TEND (1 << 2)
1604#define I2C_SR_DRF (1 << 1)
1605#define I2C_SR_ACKF (1 << 0)
1606
1607
1608/*************************************************************************
1609 * SSI (Synchronous Serial Interface)
1610 *************************************************************************/
1611/* n = 0, 1, 2 (SSI0, SSI1, SSI2) */
1612#define SSI_DR(n) (SSI##n##_BASE + 0x000)
1613#define SSI_CR0(n) (SSI##n##_BASE + 0x004)
1614#define SSI_CR1(n) (SSI##n##_BASE + 0x008)
1615#define SSI_SR(n) (SSI##n##_BASE + 0x00C)
1616#define SSI_ITR(n) (SSI##n##_BASE + 0x010)
1617#define SSI_ICR(n) (SSI##n##_BASE + 0x014)
1618#define SSI_GR(n) (SSI##n##_BASE + 0x018)
1619
1620#define REG_SSI_DR(n) REG32(SSI_DR(n))
1621#define REG_SSI_CR0(n) REG16(SSI_CR0(n))
1622#define REG_SSI_CR1(n) REG32(SSI_CR1(n))
1623#define REG_SSI_SR(n) REG32(SSI_SR(n))
1624#define REG_SSI_ITR(n) REG16(SSI_ITR(n))
1625#define REG_SSI_ICR(n) REG8(SSI_ICR(n))
1626#define REG_SSI_GR(n) REG16(SSI_GR(n))
1627
1628/* SSI Data Register (SSI_DR) */
1629
1630#define SSI_DR_GPC_BIT 0
1631#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1632
1633#define SSI_MAX_FIFO_ENTRIES 128 /* 128 txfifo and 128 rxfifo */
1634
1635/* SSI Control Register 0 (SSI_CR0) */
1636
1637#define SSI_CR0_SSIE (1 << 15)
1638#define SSI_CR0_TIE (1 << 14)
1639#define SSI_CR0_RIE (1 << 13)
1640#define SSI_CR0_TEIE (1 << 12)
1641#define SSI_CR0_REIE (1 << 11)
1642#define SSI_CR0_LOOP (1 << 10)
1643#define SSI_CR0_RFINE (1 << 9)
1644#define SSI_CR0_RFINC (1 << 8)
1645#define SSI_CR0_EACLRUN (1 << 7) /* hardware auto clear underrun when TxFifo no empty */
1646#define SSI_CR0_FSEL (1 << 6)
1647#define SSI_CR0_TFLUSH (1 << 2)
1648#define SSI_CR0_RFLUSH (1 << 1)
1649#define SSI_CR0_DISREV (1 << 0)
1650
1651/* SSI Control Register 1 (SSI_CR1) */
1652
1653#define SSI_CR1_FRMHL_BIT 30
1654#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1655  #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1656  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1657  #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1658  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1659#define SSI_CR1_TFVCK_BIT 28
1660#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1661  #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1662  #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1663  #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1664  #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1665#define SSI_CR1_TCKFI_BIT 26
1666#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1667  #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1668  #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1669  #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1670  #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1671#define SSI_CR1_LFST (1 << 25)
1672#define SSI_CR1_ITFRM (1 << 24)
1673#define SSI_CR1_UNFIN (1 << 23)
1674#define SSI_CR1_MULTS (1 << 22)
1675#define SSI_CR1_FMAT_BIT 20
1676#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1677  #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1678  #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1679  #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1680  #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1681#define SSI_CR1_TTRG_BIT 16 /* SSI1 TX trigger */
1682#define SSI_CR1_TTRG_MASK (0xf << SSI1_CR1_TTRG_BIT)
1683#define SSI_CR1_MCOM_BIT 12
1684#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1685  #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1686  #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1687  #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1688  #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1689  #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1690  #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1691  #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1692  #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1693  #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1694  #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1695  #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1696  #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1697  #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1698  #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1699  #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1700  #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1701#define SSI_CR1_RTRG_BIT 8 /* SSI RX trigger */
1702#define SSI_CR1_RTRG_MASK (0xf << SSI1_CR1_RTRG_BIT)
1703#define SSI_CR1_FLEN_BIT 4
1704#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1705  #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1706  #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1707  #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1708  #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1709  #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1710  #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1711  #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1712  #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1713  #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1714  #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1715  #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1716  #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1717  #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1718  #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1719  #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1720  #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1721#define SSI_CR1_PHA (1 << 1)
1722#define SSI_CR1_POL (1 << 0)
1723
1724/* SSI Status Register (SSI_SR) */
1725
1726#define SSI_SR_TFIFONUM_BIT 16
1727#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1728#define SSI_SR_RFIFONUM_BIT 8
1729#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1730#define SSI_SR_END (1 << 7)
1731#define SSI_SR_BUSY (1 << 6)
1732#define SSI_SR_TFF (1 << 5)
1733#define SSI_SR_RFE (1 << 4)
1734#define SSI_SR_TFHE (1 << 3)
1735#define SSI_SR_RFHF (1 << 2)
1736#define SSI_SR_UNDR (1 << 1)
1737#define SSI_SR_OVER (1 << 0)
1738
1739/* SSI Interval Time Control Register (SSI_ITR) */
1740
1741#define SSI_ITR_CNTCLK (1 << 15)
1742#define SSI_ITR_IVLTM_BIT 0
1743#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1744
1745
1746/*************************************************************************
1747 * MSC
1748 *************************************************************************/
1749#define MSC_STRPCL (MSC0_BASE + 0x000)
1750#define MSC_STAT (MSC0_BASE + 0x004)
1751#define MSC_CLKRT (MSC0_BASE + 0x008)
1752#define MSC_CMDAT (MSC0_BASE + 0x00C)
1753#define MSC_RESTO (MSC0_BASE + 0x010)
1754#define MSC_RDTO (MSC0_BASE + 0x014)
1755#define MSC_BLKLEN (MSC0_BASE + 0x018)
1756#define MSC_NOB (MSC0_BASE + 0x01C)
1757#define MSC_SNOB (MSC0_BASE + 0x020)
1758#define MSC_IMASK (MSC0_BASE + 0x024)
1759#define MSC_IREG (MSC0_BASE + 0x028)
1760#define MSC_CMD (MSC0_BASE + 0x02C)
1761#define MSC_ARG (MSC0_BASE + 0x030)
1762#define MSC_RES (MSC0_BASE + 0x034)
1763#define MSC_RXFIFO (MSC0_BASE + 0x038)
1764#define MSC_TXFIFO (MSC0_BASE + 0x03C)
1765
1766#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1767#define REG_MSC_STAT REG32(MSC_STAT)
1768#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1769#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1770#define REG_MSC_RESTO REG16(MSC_RESTO)
1771#define REG_MSC_RDTO REG16(MSC_RDTO)
1772#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1773#define REG_MSC_NOB REG16(MSC_NOB)
1774#define REG_MSC_SNOB REG16(MSC_SNOB)
1775#define REG_MSC_IMASK REG16(MSC_IMASK)
1776#define REG_MSC_IREG REG16(MSC_IREG)
1777#define REG_MSC_CMD REG8(MSC_CMD)
1778#define REG_MSC_ARG REG32(MSC_ARG)
1779#define REG_MSC_RES REG16(MSC_RES)
1780#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1781#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1782
1783/* MSC Clock and Control Register (MSC_STRPCL) */
1784
1785#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1786#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1787#define MSC_STRPCL_START_READWAIT (1 << 5)
1788#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1789#define MSC_STRPCL_RESET (1 << 3)
1790#define MSC_STRPCL_START_OP (1 << 2)
1791#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1792#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1793  #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1794  #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1795
1796/* MSC Status Register (MSC_STAT) */
1797
1798#define MSC_STAT_IS_RESETTING (1 << 15)
1799#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1800#define MSC_STAT_PRG_DONE (1 << 13)
1801#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1802#define MSC_STAT_END_CMD_RES (1 << 11)
1803#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1804#define MSC_STAT_IS_READWAIT (1 << 9)
1805#define MSC_STAT_CLK_EN (1 << 8)
1806#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1807#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1808#define MSC_STAT_CRC_RES_ERR (1 << 5)
1809#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1810#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1811#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1812  #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1813  #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1814  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1815#define MSC_STAT_TIME_OUT_RES (1 << 1)
1816#define MSC_STAT_TIME_OUT_READ (1 << 0)
1817
1818/* MSC Bus Clock Control Register (MSC_CLKRT) */
1819
1820#define MSC_CLKRT_CLK_RATE_BIT 0
1821#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1822  #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1823  #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1824  #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1825  #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1826  #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1827  #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1828  #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1829  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1830
1831/* MSC Command Sequence Control Register (MSC_CMDAT) */
1832
1833#define MSC_CMDAT_IO_ABORT (1 << 11)
1834#define MSC_CMDAT_BUS_WIDTH_BIT 9
1835#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1836  #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1837  #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1838  #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1839  #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1840#define MSC_CMDAT_DMA_EN (1 << 8)
1841#define MSC_CMDAT_INIT (1 << 7)
1842#define MSC_CMDAT_BUSY (1 << 6)
1843#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1844#define MSC_CMDAT_WRITE (1 << 4)
1845#define MSC_CMDAT_READ (0 << 4)
1846#define MSC_CMDAT_DATA_EN (1 << 3)
1847#define MSC_CMDAT_RESPONSE_BIT 0
1848#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1849  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1850  #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1851  #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1852  #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1853  #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1854  #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1855  #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1856
1857#define CMDAT_DMA_EN (1 << 8)
1858#define CMDAT_INIT (1 << 7)
1859#define CMDAT_BUSY (1 << 6)
1860#define CMDAT_STREAM (1 << 5)
1861#define CMDAT_WRITE (1 << 4)
1862#define CMDAT_DATA_EN (1 << 3)
1863
1864/* MSC Interrupts Mask Register (MSC_IMASK) */
1865
1866#define MSC_IMASK_SDIO (1 << 7)
1867#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1868#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1869#define MSC_IMASK_END_CMD_RES (1 << 2)
1870#define MSC_IMASK_PRG_DONE (1 << 1)
1871#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1872
1873
1874/* MSC Interrupts Status Register (MSC_IREG) */
1875
1876#define MSC_IREG_SDIO (1 << 7)
1877#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1878#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1879#define MSC_IREG_END_CMD_RES (1 << 2)
1880#define MSC_IREG_PRG_DONE (1 << 1)
1881#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1882
1883/*************************************************************************
1884 * EMC (External SDR Controller)
1885 *************************************************************************/
1886#define EMC_LOW_SDRAM_SPACE_SIZE 0x10000000 /* 256M */
1887#define EMC_MEM_PHY_BASE 0x20000000
1888#define EMC_MEM_PHY_BASE_SHIFT 24
1889
1890
1891#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
1892
1893#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1894#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1895#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1896#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1897
1898#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1899#define EMC_DMAR1 (EMC_BASE + 0x94) /* SDRAM Bank 1 Addr Config Register */
1900#define EMC_SDMR0 (EMC_BASE + 0x8000) /* Mode Register of SDRAM bank 0 */
1901
1902#define REG_EMC_BCR REG32(EMC_BCR)
1903
1904#define REG_EMC_DMCR REG32(EMC_DMCR)
1905#define REG_EMC_RTCSR REG16(EMC_RTCSR)
1906#define REG_EMC_RTCNT REG16(EMC_RTCNT)
1907#define REG_EMC_RTCOR REG16(EMC_RTCOR)
1908#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1909#define REG_EMC_DMAR1 REG32(EMC_DMAR1)
1910
1911#define EMC_PMEMPS0 (EMC_BASE + 0x6000)
1912#define EMC_PMEMPS1 (EMC_BASE + 0x6004)
1913#define EMC_PMEMPS2 (EMC_BASE + 0x6008)
1914#define EMC_PMEMPS3 (EMC_BASE + 0x600c)
1915
1916#define REG_EMC_PMEMPS0 REG32(EMC_PMEMPS0)
1917#define REG_EMC_PMEMPS1 REG32(EMC_PMEMPS1)
1918#define REG_EMC_PMEMPS2 REG32(EMC_PMEMPS2)
1919#define REG_EMC_PMEMPS3 REG32(EMC_PMEMPS3)
1920
1921/* DRAM Control Register */
1922#define EMC_DMCR_BW_BIT 31
1923#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1924#define EMC_DMCR_CA_BIT 26
1925#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1926  #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1927  #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1928  #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1929  #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1930  #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1931#define EMC_DMCR_RMODE (1 << 25)
1932#define EMC_DMCR_RFSH (1 << 24)
1933#define EMC_DMCR_MRSET (1 << 23)
1934#define EMC_DMCR_RA_BIT 20
1935#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1936  #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1937  #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1938  #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1939#define EMC_DMCR_BA_BIT 19
1940#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1941#define EMC_DMCR_PDM (1 << 18)
1942#define EMC_DMCR_EPIN (1 << 17)
1943#define EMC_DMCR_MBSEL_BIT 16
1944  #define EMC_DMCR_MBSEL_B0 (0 << 16)
1945  #define EMC_DMCR_MBSEL_B1 (1 << 16)
1946#define EMC_DMCR_TRAS_BIT 13
1947#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1948#define EMC_DMCR_RCD_BIT 11
1949#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1950#define EMC_DMCR_TPC_BIT 8
1951#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1952#define EMC_DMCR_TRWL_BIT 5
1953#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1954#define EMC_DMCR_TRC_BIT 2
1955#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1956#define EMC_DMCR_TCL_BIT 0
1957#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1958
1959/* Refresh Time Control/Status Register */
1960#define EMC_RTCSR_CMF (1 << 7)
1961#define EMC_RTCSR_CKS_BIT 0
1962#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1963  #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1964  #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1965  #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1966  #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1967  #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1968  #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1969  #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1970  #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1971
1972/* SDRAM Bank Address Configuration Register */
1973#define EMC_DMAR_BASE_BIT 8
1974#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1975#define EMC_DMAR_MASK_BIT 0
1976#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1977
1978/* Mode Register of SDRAM bank 0 */
1979#define EMC_SDMR_BM (1 << 9) /* Write Single Mode */
1980#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1981#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1982  #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1983#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1984#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1985  #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1986  #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1987  #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1988#define EMC_SDMR_BT_BIT 3 /* Burst Type */
1989#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1990  #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1991  #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1992#define EMC_SDMR_BL_BIT 0 /* Burst Length */
1993#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1994  #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1995  #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1996  #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1997  #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1998
1999#define EMC_SDMR_CAS2_16BIT \
2000  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
2001#define EMC_SDMR_CAS2_32BIT \
2002  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
2003#define EMC_SDMR_CAS3_16BIT \
2004  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
2005#define EMC_SDMR_CAS3_32BIT \
2006  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
2007
2008/* Extended Mode Register of Mobile SDRAM*/
2009#define EMC_SDMR_SET_BA1 (1 << 14) /*BA1*/
2010#define EMC_SDMR_SET_BA0 (1 << 13) /*BA0*/
2011
2012#define EMC_SDMR_DS_BIT 5 /* Driver strength */
2013#define EMC_SDMR_DS_MASK (3 << EMC_SDMR_DS_BIT)
2014  #define EMC_SDMR_DS_FULL (0 << EMC_SDMR_DS_BIT) /*Full*/
2015  #define EMC_SDMR_DS_HALF (1 << EMC_SDMR_DS_BIT) /*1/2 Strength*/
2016  #define EMC_SDMR_DS_QUTR (2 << EMC_SDMR_DS_BIT) /*1/4 Strength*/
2017
2018#define EMC_SDMR_PRSR_BIT 0 /* Partial Array Self Refresh */
2019#define EMC_SDMR_PRSR_MASK (7 << EMC_SDMR_PRSR_BIT)
2020  #define EMC_SDMR_PRSR_ALL (0 << EMC_SDMR_PRSR_BIT) /*All Banks*/
2021  #define EMC_SDMR_PRSR_HALF_TL (1 << EMC_SDMR_PRSR_BIT) /*Half of Total Bank*/
2022  #define EMC_SDMR_PRSR_QUTR_TL (2 << EMC_SDMR_PRSR_BIT) /*Quarter of Total Bank*/
2023  #define EMC_SDMR_PRSR_HALF_B0 (5 << EMC_SDMR_PRSR_BIT) /*Half of Bank0*/
2024  #define EMC_SDMR_PRSR_QUTR_B0 (6 << EMC_SDMR_PRSR_BIT) /*Quarter of Bank0*/
2025
2026#define EMC_DMAR_BASE_BIT 8
2027#define EMC_DMAR_MASK_BIT 0
2028
2029#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
2030#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
2031
2032#define EMC_DMAR0_BASE (0x20 << EMC_DMAR_BASE_BIT)
2033#define EMC_DMAR1_BASE_64M (0x24 << EMC_DMAR_BASE_BIT) /*when bank0 is 64M*/
2034#define EMC_DMAR1_BASE_128M (0x28 << EMC_DMAR_BASE_BIT) /*when bank0 is 128M*/
2035
2036#define EMC_DMAR_MASK_64_64 (0xfc << EMC_DMAR_MASK_BIT) /*mask for two 64M SDRAM*/
2037#define EMC_DMAR_MASK_128_128 (0xf8 << EMC_DMAR_MASK_BIT) /*mask for two 128M SDRAM*/
2038
2039
2040/*************************************************************************
2041 * NEMC (External Normal Memory Controller)
2042 *************************************************************************/
2043#define NEMC_BCR (NEMC_BASE + 0x0) /* BCR */
2044
2045#define NEMC_SMCR1 (NEMC_BASE + 0x14) /* Static Memory Control Register 1 */
2046#define NEMC_SMCR2 (NEMC_BASE + 0x18) /* Static Memory Control Register 2 */
2047#define NEMC_SMCR3 (NEMC_BASE + 0x1c) /* Static Memory Control Register 3 */
2048#define NEMC_SMCR4 (NEMC_BASE + 0x20) /* Static Memory Control Register 4 */
2049#define NEMC_SMCR5 (NEMC_BASE + 0x24) /* Static Memory Control Register 5 */
2050#define NEMC_SMCR6 (NEMC_BASE + 0x28) /* Static Memory Control Register 6 */
2051#define NEMC_SACR1 (NEMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
2052#define NEMC_SACR2 (NEMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
2053#define NEMC_SACR3 (NEMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
2054#define NEMC_SACR4 (NEMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
2055#define NEMC_SACR5 (NEMC_BASE + 0x44) /* Static Memory Bank 5 Addr Config Reg */
2056#define NEMC_SACR6 (NEMC_BASE + 0x48) /* Static Memory Bank 6 Addr Config Reg */
2057
2058#define NEMC_NFCSR (NEMC_BASE + 0x050) /* NAND Flash Control/Status Register */
2059
2060#define REG_NEMC_BCR REG32(NEMC_BCR)
2061#define REG_NEMC_SMCR1 REG32(NEMC_SMCR1)
2062#define REG_NEMC_SMCR2 REG32(NEMC_SMCR2)
2063#define REG_NEMC_SMCR3 REG32(NEMC_SMCR3)
2064#define REG_NEMC_SMCR4 REG32(NEMC_SMCR4)
2065#define REG_NEMC_SMCR5 REG32(NEMC_SMCR5)
2066#define REG_NEMC_SMCR6 REG32(NEMC_SMCR6)
2067#define REG_NEMC_SACR1 REG32(NEMC_SACR1)
2068#define REG_NEMC_SACR2 REG32(NEMC_SACR2)
2069#define REG_NEMC_SACR3 REG32(NEMC_SACR3)
2070#define REG_NEMC_SACR4 REG32(NEMC_SACR4)
2071#define REG_NEMC_SACR5 REG32(NEMC_SACR5)
2072#define REG_NEMC_SACR6 REG32(NEMC_SACR6)
2073
2074
2075#define REG_NEMC_NFCSR REG32(NEMC_NFCSR)
2076
2077
2078/* Bus Control Register */
2079#define NEMC_BCR_BT_SEL_BIT 30
2080#define NEMC_BCR_BT_SEL_MASK (0x3 << NEMC_BCR_BT_SEL_BIT)
2081#define NEMC_BCR_PK_SEL (1 << 24)
2082#define NEMC_BCR_BSR_MASK (1 << 2) /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */
2083  #define NEMC_BCR_BSR_SHARE (0 << 2)
2084  #define NEMC_BCR_BSR_UNSHARE (1 << 2)
2085#define NEMC_BCR_BRE (1 << 1)
2086#define NEMC_BCR_ENDIAN (1 << 0)
2087
2088/* Static Memory Control Register */
2089#define NEMC_SMCR_STRV_BIT 24
2090#define NEMC_SMCR_STRV_MASK (0x0f << NEMC_SMCR_STRV_BIT)
2091#define NEMC_SMCR_TAW_BIT 20
2092#define NEMC_SMCR_TAW_MASK (0x0f << NEMC_SMCR_TAW_BIT)
2093#define NEMC_SMCR_TBP_BIT 16
2094#define NEMC_SMCR_TBP_MASK (0x0f << NEMC_SMCR_TBP_BIT)
2095#define NEMC_SMCR_TAH_BIT 12
2096#define NEMC_SMCR_TAH_MASK (0x07 << NEMC_SMCR_TAH_BIT)
2097#define NEMC_SMCR_TAS_BIT 8
2098#define NEMC_SMCR_TAS_MASK (0x07 << NEMC_SMCR_TAS_BIT)
2099#define NEMC_SMCR_BW_BIT 6
2100#define NEMC_SMCR_BW_MASK (0x03 << NEMC_SMCR_BW_BIT)
2101  #define NEMC_SMCR_BW_8BIT (0 << NEMC_SMCR_BW_BIT)
2102  #define NEMC_SMCR_BW_16BIT (1 << NEMC_SMCR_BW_BIT)
2103  #define NEMC_SMCR_BW_32BIT (2 << NEMC_SMCR_BW_BIT)
2104#define NEMC_SMCR_BCM (1 << 3)
2105#define NEMC_SMCR_BL_BIT 1
2106#define NEMC_SMCR_BL_MASK (0x03 << NEMC_SMCR_BL_BIT)
2107  #define NEMC_SMCR_BL_4 (0 << NEMC_SMCR_BL_BIT)
2108  #define NEMC_SMCR_BL_8 (1 << NEMC_SMCR_BL_BIT)
2109  #define NEMC_SMCR_BL_16 (2 << NEMC_SMCR_BL_BIT)
2110  #define NEMC_SMCR_BL_32 (3 << NEMC_SMCR_BL_BIT)
2111#define NEMC_SMCR_SMT (1 << 0)
2112
2113/* Static Memory Bank Addr Config Reg */
2114#define NEMC_SACR_BASE_BIT 8
2115#define NEMC_SACR_BASE_MASK (0xff << NEMC_SACR_BASE_BIT)
2116#define NEMC_SACR_MASK_BIT 0
2117#define NEMC_SACR_MASK_MASK (0xff << NEMC_SACR_MASK_BIT)
2118
2119/* NAND Flash Control/Status Register */
2120#define NEMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
2121#define NEMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
2122#define NEMC_NFCSR_NFCE3 (1 << 5)
2123#define NEMC_NFCSR_NFE3 (1 << 4)
2124#define NEMC_NFCSR_NFCE2 (1 << 3)
2125#define NEMC_NFCSR_NFE2 (1 << 2)
2126#define NEMC_NFCSR_NFCE1 (1 << 1)
2127#define NEMC_NFCSR_NFE1 (1 << 0)
2128
2129/*************************************************************************
2130 * DDRC (DDR Controller)
2131 *************************************************************************/
2132#define DDR_MEM_PHY_BASE 0x20000000
2133
2134#define DDRC_ST (DDRC_BASE + 0x0) /* DDR Status Register */
2135#define DDRC_CFG (DDRC_BASE + 0x4) /* DDR Configure Register */
2136#define DDRC_CTRL (DDRC_BASE + 0x8) /* DDR Control Register */
2137#define DDRC_LMR (DDRC_BASE + 0xc) /* DDR Load-Mode-Register */
2138#define DDRC_TIMING1 (DDRC_BASE + 0x10) /* DDR Timing Config Register 1 */
2139#define DDRC_TIMING2 (DDRC_BASE + 0x14) /* DDR Timing Config Register 2 */
2140#define DDRC_REFCNT (DDRC_BASE + 0x18) /* DDR Auto-Refresh Counter */
2141#define DDRC_DQS (DDRC_BASE + 0x1c) /* DDR DQS Delay Control Register */
2142#define DDRC_DQS_ADJ (DDRC_BASE + 0x20) /* DDR DQS Delay Adjust Register */
2143#define DDRC_MMAP0 (DDRC_BASE + 0x24) /* DDR Memory Map Config Register */
2144#define DDRC_MMAP1 (DDRC_BASE + 0x28) /* DDR Memory Map Config Register */
2145#define DDRC_MDELAY (DDRC_BASE + 0x2c) /* DDR Memory Map Config Register */
2146
2147/* DDRC Register */
2148#define REG_DDRC_ST REG32(DDRC_ST)
2149#define REG_DDRC_CFG REG32(DDRC_CFG)
2150#define REG_DDRC_CTRL REG32(DDRC_CTRL)
2151#define REG_DDRC_LMR REG32(DDRC_LMR)
2152#define REG_DDRC_TIMING1 REG32(DDRC_TIMING1)
2153#define REG_DDRC_TIMING2 REG32(DDRC_TIMING2)
2154#define REG_DDRC_REFCNT REG32(DDRC_REFCNT)
2155#define REG_DDRC_DQS REG32(DDRC_DQS)
2156#define REG_DDRC_DQS_ADJ REG32(DDRC_DQS_ADJ)
2157#define REG_DDRC_MMAP0 REG32(DDRC_MMAP0)
2158#define REG_DDRC_MMAP1 REG32(DDRC_MMAP1)
2159#define REG_DDRC_MDELAY REG32(DDRC_MDELAY)
2160
2161/* DDRC Status Register */
2162#define DDRC_ST_ENDIAN (1 << 7) /* 0 Little data endian
2163                        1 Big data endian */
2164#define DDRC_ST_DPDN (1 << 5) /* 0 DDR memory is NOT in deep-power-down state
2165                        1 DDR memory is in deep-power-down state */
2166#define DDRC_ST_PDN (1 << 4) /* 0 DDR memory is NOT in power-down state
2167                        1 DDR memory is in power-down state */
2168#define DDRC_ST_AREF (1 << 3) /* 0 DDR memory is NOT in auto-refresh state
2169                        1 DDR memory is in auto-refresh state */
2170#define DDRC_ST_SREF (1 << 2) /* 0 DDR memory is NOT in self-refresh state
2171                        1 DDR memory is in self-refresh state */
2172#define DDRC_ST_CKE1 (1 << 1) /* 0 CKE1 Pin is low
2173                        1 CKE1 Pin is high */
2174#define DDRC_ST_CKE0 (1 << 0) /* 0 CKE0 Pin is low
2175                        1 CKE0 Pin is high */
2176
2177/* DDRC Configure Register */
2178#define DDRC_CFG_MSEL_BIT 16 /* Mask delay select */
2179#define DDRC_CFG_MSEL_MASK (0x3 << DDRC_CFG_MSEL_BIT)
2180  #define DDRC_CFG_MSEL_0 (0 << DDRC_CFG_MSEL_BIT) /* 00 No delay */
2181  #define DDRC_CFG_MSEL_1 (1 << DDRC_CFG_MSEL_BIT) /* 01 delay 1 tCK */
2182  #define DDRC_CFG_MSEL_2 (2 << DDRC_CFG_MSEL_BIT) /* 10 delay 2 tCK */
2183  #define DDRC_CFG_MSEL_3 (3 << DDRC_CFG_MSEL_BIT) /* 11 delay 3 tCK */
2184
2185#define DDRC_CFG_MPRT (1 << 15) /* mem protect */
2186
2187#define DDRC_CFG_ROW1_BIT 27 /* Row Address width. */
2188#define DDRC_CFG_COL1_BIT 25 /* Row Address width. */
2189#define DDRC_CFG_BA1 (1 << 24)
2190#define DDRC_CFG_IMBA (1 << 23)
2191#define DDRC_CFG_BTRUN (1 << 21)
2192
2193#define DDRC_CFG_TYPE_BIT 12
2194#define DDRC_CFG_TYPE_MASK (0x7 << DDRC_CFG_TYPE_BIT)
2195#define DDRC_CFG_TYPE_DDR1 (2 << DDRC_CFG_TYPE_BIT)
2196#define DDRC_CFG_TYPE_MDDR (3 << DDRC_CFG_TYPE_BIT)
2197#define DDRC_CFG_TYPE_DDR2 (4 << DDRC_CFG_TYPE_BIT)
2198
2199#define DDRC_CFG_ROW_BIT 10 /* Row Address width. */
2200#define DDRC_CFG_ROW_MASK (0x3 << DDRC_CFG_ROW_BIT)
2201  #define DDRC_CFG_ROW_13 (0 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */
2202  #define DDRC_CFG_ROW_14 (1 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */
2203
2204#define DDRC_CFG_COL_BIT 8 /* Column Address width.
2205                     Specify the Column address width of external DDR. */
2206#define DDRC_CFG_COL_MASK (0x3 << DDRC_CFG_COL_BIT)
2207  #define DDRC_CFG_COL_9 (0 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */
2208  #define DDRC_CFG_COL_10 (1 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */
2209
2210#define DDRC_CFG_CS1EN (1 << 7) /* 0 DDR Pin CS1 un-used
2211                        1 There're DDR memory connected to CS1 */
2212#define DDRC_CFG_CS0EN (1 << 6) /* 0 DDR Pin CS0 un-used
2213                        1 There're DDR memory connected to CS0 */
2214
2215#define DDRC_CFG_TSEL_BIT 18 /* Read delay select */
2216#define DDRC_CFG_TSEL_MASK (0x3 << DDRC_CFG_TSEL_BIT)
2217#define DDRC_CFG_TSEL_0 (0 << DDRC_CFG_TSEL_BIT) /* No delay */
2218#define DDRC_CFG_TSEL_1 (1 << DDRC_CFG_TSEL_BIT) /* delay 1 tCK */
2219#define DDRC_CFG_TSEL_2 (2 << DDRC_CFG_TSEL_BIT) /* delay 2 tCK */
2220#define DDRC_CFG_TSEL_3 (3 << DDRC_CFG_TSEL_BIT) /* delay 3 tCK */
2221
2222#define DDRC_CFG_CL_BIT 2 /* CAS Latency */
2223#define DDRC_CFG_CL_MASK (0xf << DDRC_CFG_CL_BIT)
2224#define DDRC_CFG_CL_3 (0 << DDRC_CFG_CL_BIT) /* CL = 3 tCK */
2225#define DDRC_CFG_CL_4 (1 << DDRC_CFG_CL_BIT) /* CL = 4 tCK */
2226#define DDRC_CFG_CL_5 (2 << DDRC_CFG_CL_BIT) /* CL = 5 tCK */
2227#define DDRC_CFG_CL_6 (3 << DDRC_CFG_CL_BIT) /* CL = 6 tCK */
2228
2229#define DDRC_CFG_BA (1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used
2230                        1 8 bank device, Pin ba[2:0] valid*/
2231#define DDRC_CFG_DW (1 << 0) /*0 External memory data width is 16-bit
2232                       1 External memory data width is 32-bit */
2233
2234/* DDRC Control Register */
2235#define DDRC_CTRL_ACTPD (1 << 15) /* 0 Precharge all banks before entering power-down
2236                         1 Do not precharge banks before entering power-down */
2237#define DDRC_CTRL_PDT_BIT 12 /* Power-Down Timer */
2238#define DDRC_CTRL_PDT_MASK (0x7 << DDRC_CTRL_PDT_BIT)
2239  #define DDRC_CTRL_PDT_DIS (0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
2240  #define DDRC_CTRL_PDT_8 (1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
2241  #define DDRC_CTRL_PDT_16 (2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
2242  #define DDRC_CTRL_PDT_32 (3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
2243  #define DDRC_CTRL_PDT_64 (4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
2244  #define DDRC_CTRL_PDT_128 (5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
2245
2246#define DDRC_CTRL_PRET_BIT 8 /* Precharge Timer */
2247#define DDRC_CTRL_PRET_MASK (0x7 << DDRC_CTRL_PRET_BIT) /* */
2248  #define DDRC_CTRL_PRET_DIS (0 << DDRC_CTRL_PRET_BIT) /* PRET function Disabled */
2249  #define DDRC_CTRL_PRET_8 (1 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 8 tCK idle */
2250  #define DDRC_CTRL_PRET_16 (2 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 16 tCK idle */
2251  #define DDRC_CTRL_PRET_32 (3 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 32 tCK idle */
2252  #define DDRC_CTRL_PRET_64 (4 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 64 tCK idle */
2253  #define DDRC_CTRL_PRET_128 (5 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 128 tCK idle */
2254
2255#define DDRC_CTRL_DPD (1 << 6) /* 1 Drive external DDR device entering self-refresh mode */
2256
2257#define DDRC_CTRL_SR (1 << 5) /* 1 Drive external DDR device entering self-refresh mode
2258                        0 Drive external DDR device exiting self-refresh mode */
2259#define DDRC_CTRL_UNALIGN (1 << 4) /* 0 Disable unaligned transfer on AXI BUS
2260                        1 Enable unaligned transfer on AXI BUS */
2261#define DDRC_CTRL_ALH (1 << 3) /* Advanced Latency Hiding:
2262                        0 Disable ALH
2263                        1 Enable ALH */
2264#define DDRC_CTRL_RDC (1 << 2) /* 0 dclk clock frequency is lower than 60MHz
2265                        1 dclk clock frequency is higher than 60MHz */
2266#define DDRC_CTRL_CKE (1 << 1) /* 0 Not set CKE Pin High
2267                        1 Set CKE Pin HIGH */
2268#define DDRC_CTRL_RESET (1 << 0) /* 0 End resetting ddrc_controller
2269                        1 Resetting ddrc_controller */
2270
2271/* DDRC Load-Mode-Register */
2272#define DDRC_LMR_DDR_ADDR_BIT 16 /* When performing a DDR command, DDRC_ADDR[13:0]
2273                          corresponding to external DDR address Pin A[13:0] */
2274#define DDRC_LMR_DDR_ADDR_MASK (0xff << DDRC_LMR_DDR_ADDR_BIT)
2275
2276#define DDRC_LMR_BA_BIT 8 /* When performing a DDR command, BA[2:0]
2277                     corresponding to external DDR address Pin BA[2:0]. */
2278#define DDRC_LMR_BA_MASK (0x7 << DDRC_LMR_BA_BIT)
2279  /* For DDR2 */
2280  #define DDRC_LMR_BA_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
2281  #define DDRC_LMR_BA_EMRS1 (1 << DDRC_LMR_BA_BIT) /* Extended Mode Register1 set */
2282  #define DDRC_LMR_BA_EMRS2 (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register2 set */
2283  #define DDRC_LMR_BA_EMRS3 (3 << DDRC_LMR_BA_BIT) /* Extended Mode Register3 set */
2284  /* For mobile DDR */
2285  #define DDRC_LMR_BA_M_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
2286  #define DDRC_LMR_BA_M_EMRS (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */
2287  #define DDRC_LMR_BA_M_SR (1 << DDRC_LMR_BA_BIT) /* Status Register set */
2288  /* For Normal DDR1 */
2289  #define DDRC_LMR_BA_N_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
2290  #define DDRC_LMR_BA_N_EMRS (1 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */
2291
2292#define DDRC_LMR_CMD_BIT 4
2293#define DDRC_LMR_CMD_MASK (0x3 << DDRC_LMR_CMD_BIT)
2294  #define DDRC_LMR_CMD_PREC (0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
2295  #define DDRC_LMR_CMD_AUREF (1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
2296  #define DDRC_LMR_CMD_LMR (2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
2297
2298#define DDRC_LMR_START (1 << 0) /* 0 No command is performed
2299                            1 On the posedge of START, perform a command
2300                            defined by CMD field */
2301
2302/* DDRC Mode Register Set */
2303#define DDR2_MRS_PD_BIT 10 /* Active power down exit time */
2304#define DDR2_MRS_PD_MASK (1 << DDR_MRS_PD_BIT)
2305  #define DDR2_MRS_PD_FAST_EXIT (0 << 10)
2306  #define DDR2_MRS_PD_SLOW_EXIT (1 << 10)
2307#define DDR2_MRS_WR_BIT 9 /* Write Recovery for autoprecharge */
2308#define DDR2_MRS_WR_MASK (7 << DDR_MRS_WR_BIT)
2309#define DDR2_MRS_DLL_RST (1 << 8) /* DLL Reset */
2310#define DDR2_MRS_TM_BIT 7 /* Operating Mode */
2311#define DDR2_MRS_TM_MASK (1 << DDR_MRS_TM_BIT)
2312  #define DDR2_MRS_TM_NORMAL (0 << DDR_MRS_TM_BIT)
2313  #define DDR2_MRS_TM_TEST (1 << DDR_MRS_TM_BIT)
2314#define DDR_MRS_CAS_BIT 4 /* CAS Latency */
2315#define DDR_MRS_CAS_MASK (7 << DDR_MRS_CAS_BIT)
2316#define DDR_MRS_BT_BIT 3 /* Burst Type */
2317#define DDR_MRS_BT_MASK (1 << DDR_MRS_BT_BIT)
2318  #define DDR_MRS_BT_SEQ (0 << DDR_MRS_BT_BIT) /* Sequential */
2319  #define DDR_MRS_BT_INT (1 << DDR_MRS_BT_BIT) /* Interleave */
2320#define DDR_MRS_BL_BIT 0 /* Burst Length */
2321#define DDR_MRS_BL_MASK (7 << DDR_MRS_BL_BIT)
2322  #define DDR_MRS_BL_4 (2 << DDR_MRS_BL_BIT)
2323  #define DDR_MRS_BL_8 (3 << DDR_MRS_BL_BIT)
2324
2325/* DDR2 Extended Mode Register1 Set */
2326#define DDR_EMRS1_QOFF (1<<12) /* 0 Output buffer enabled
2327                       1 Output buffer disabled */
2328#define DDR_EMRS1_RDQS_EN (1<<11) /* 0 Disable
2329                       1 Enable */
2330#define DDR_EMRS1_DQS_DIS (1<<10) /* 0 Enable
2331                       1 Disable */
2332#define DDR_EMRS1_OCD_BIT 7 /* Additive Latency 0 -> 6 */
2333#define DDR_EMRS1_OCD_MASK (0x7 << DDR_EMRS1_OCD_BIT)
2334  #define DDR_EMRS1_OCD_EXIT (0 << DDR_EMRS1_OCD_BIT)
2335  #define DDR_EMRS1_OCD_D0 (1 << DDR_EMRS1_OCD_BIT)
2336  #define DDR_EMRS1_OCD_D1 (2 << DDR_EMRS1_OCD_BIT)
2337  #define DDR_EMRS1_OCD_ADJ (4 << DDR_EMRS1_OCD_BIT)
2338  #define DDR_EMRS1_OCD_DFLT (7 << DDR_EMRS1_OCD_BIT)
2339#define DDR_EMRS1_AL_BIT 3 /* Additive Latency 0 -> 6 */
2340#define DDR_EMRS1_AL_MASK (7 << DDR_EMRS1_AL_BIT)
2341#define DDR_EMRS1_RTT_BIT 2 /* */
2342#define DDR_EMRS1_RTT_MASK (0x11 << DDR_EMRS1_DIC_BIT) /* Bit 6, Bit 2 */
2343#define DDR_EMRS1_DIC_BIT 1 /* Output Driver Impedence Control */
2344#define DDR_EMRS1_DIC_MASK (1 << DDR_EMRS1_DIC_BIT) /* 100% */
2345  #define DDR_EMRS1_DIC_NORMAL (0 << DDR_EMRS1_DIC_BIT) /* 60% */
2346  #define DDR_EMRS1_DIC_HALF (1 << DDR_EMRS1_DIC_BIT)
2347#define DDR_EMRS1_DLL_BIT 0 /* DLL Enable */
2348#define DDR_EMRS1_DLL_MASK (1 << DDR_EMRS1_DLL_BIT)
2349  #define DDR_EMRS1_DLL_EN (0 << DDR_EMRS1_DLL_BIT)
2350  #define DDR_EMRS1_DLL_DIS (1 << DDR_EMRS1_DLL_BIT)
2351
2352/* Mobile SDRAM Extended Mode Register */
2353#define DDR_EMRS_DS_BIT 5 /* Driver strength */
2354#define DDR_EMRS_DS_MASK (3 << DDR_EMRS_DS_BIT)
2355  #define DDR_EMRS_DS_FULL (0 << DDR_EMRS_DS_BIT) /*Full*/
2356  #define DDR_EMRS_DS_HALF (1 << DDR_EMRS_DS_BIT) /*1/2 Strength*/
2357  #define DDR_EMRS_DS_QUTR (2 << DDR_EMRS_DS_BIT) /*1/4 Strength*/
2358
2359#define DDR_EMRS_PRSR_BIT 0 /* Partial Array Self Refresh */
2360#define DDR_EMRS_PRSR_MASK (7 << DDR_EMRS_PRSR_BIT)
2361  #define DDR_EMRS_PRSR_ALL (0 << DDR_EMRS_PRSR_BIT) /*All Banks*/
2362  #define DDR_EMRS_PRSR_HALF_TL (1 << DDR_EMRS_PRSR_BIT) /*Half of Total Bank*/
2363  #define DDR_EMRS_PRSR_QUTR_TL (2 << DDR_EMRS_PRSR_BIT) /*Quarter of Total Bank*/
2364  #define DDR_EMRS_PRSR_HALF_B0 (5 << DDR_EMRS_PRSR_BIT) /*Half of Bank0*/
2365  #define DDR_EMRS_PRSR_QUTR_B0 (6 << DDR_EMRS_PRSR_BIT) /*Quarter of Bank0*/
2366
2367/* DDR1 Mode Register */
2368#define DDR1_MRS_OM_BIT 7 /* Operating Mode */
2369#define DDR1_MRS_OM_MASK (0x3f << DDR1_MRS_OM_BIT)
2370  #define DDR1_MRS_OM_NORMAL (0 << DDR1_MRS_OM_BIT)
2371  #define DDR1_MRS_OM_DLLRST (1 << DDR1_MRS_OM_BIT)
2372  #define DDR1_MRS_OM_TEST (1 << DDR1_MRS_OM_BIT)
2373#if 0
2374#define DDR1_MRS_CAS_BIT 4 /* CAS Latency */
2375#define DDR1_MRS_CAS_MASK (7 << DDR1_MRS_CAS_BIT)
2376#define DDR1_MRS_BT_BIT 3 /* Burst Type */
2377#define DDR1_MRS_BT_MASK (1 << DDR1_MRS_BT_BIT)
2378  #define DDR1_MRS_BT_SEQ (0 << DDR1_MRS_BT_BIT) /* Sequential */
2379  #define DDR1_MRS_BT_INT (1 << DDR1_MRS_BT_BIT) /* Interleave */
2380#define DDR1_MRS_BL_BIT 0 /* Burst Length */
2381#define DDR1_MRS_BL_MASK (7 << DDR1_MRS_BL_BIT)
2382  #define DDR1_MRS_BL_4 (2 << DDR1_MRS_BL_BIT)
2383  #define DDR1_MRS_BL_8 (3 << DDR1_MRS_BL_BIT)
2384#endif
2385/* DDR1 Extended Mode Register */
2386#define DDR1_EMRS_OM_BIT 2 /* Partial Array Self Refresh */
2387#define DDR1_EMRS_OM_MASK (0x3ff << DDR1_EMRS_OM_BIT)
2388  #define DDR1_EMRS_OM_NORMAL (0 << DDR1_EMRS_OM_BIT) /*All Banks*/
2389
2390#define DDR1_EMRS_DS_BIT 1 /* Driver strength */
2391#define DDR1_EMRS_DS_MASK (1 << DDR1_EMRS_DS_BIT)
2392  #define DDR1_EMRS_DS_FULL (0 << DDR1_EMRS_DS_BIT) /*Full*/
2393  #define DDR1_EMRS_DS_HALF (1 << DDR1_EMRS_DS_BIT) /*1/2 Strength*/
2394
2395#define DDR1_EMRS_DLL_BIT 0 /* Driver strength */
2396#define DDR1_EMRS_DLL_MASK (1 << DDR1_EMRS_DLL_BIT)
2397  #define DDR1_EMRS_DLL_EN (0 << DDR1_EMRS_DLL_BIT) /*Full*/
2398  #define DDR1_EMRS_DLL_DIS (1 << DDR1_EMRS_DLL_BIT) /*1/2 Strength*/
2399
2400/* DDRC Timing Config Register 1 */
2401#define DDRC_TIMING1_TRAS_BIT 28 /* ACTIVE to PRECHARGE command period (2 * tRAS + 1) */
2402#define DDRC_TIMING1_TRAS_MASK (0xf << DDRC_TIMING1_TRAS_BIT)
2403
2404#define DDRC_TIMING1_TRTP_BIT 24 /* READ to PRECHARGE command period. */
2405#define DDRC_TIMING1_TRTP_MASK (0x3 << DDRC_TIMING1_TRTP_BIT)
2406
2407#define DDRC_TIMING1_TRP_BIT 20 /* PRECHARGE command period. */
2408#define DDRC_TIMING1_TRP_MASK (0x7 << DDRC_TIMING1_TRP_BIT)
2409
2410#define DDRC_TIMING1_TRCD_BIT 16 /* ACTIVE to READ or WRITE command period. */
2411#define DDRC_TIMING1_TRCD_MASK (0x7 << DDRC_TIMING1_TRCD_BIT)
2412
2413#define DDRC_TIMING1_TRC_BIT 12 /* ACTIVE to ACTIVE command period. */
2414#define DDRC_TIMING1_TRC_MASK (0xf << DDRC_TIMING1_TRC_BIT)
2415
2416#define DDRC_TIMING1_TRRD_BIT 8 /* ACTIVE bank A to ACTIVE bank B command period. */
2417#define DDRC_TIMING1_TRRD_MASK (0x3 << DDRC_TIMING1_TRRD_BIT)
2418#define DDRC_TIMING1_TRRD_DISABLE (0 << DDRC_TIMING1_TRRD_BIT)
2419#define DDRC_TIMING1_TRRD_2 (1 << DDRC_TIMING1_TRRD_BIT)
2420#define DDRC_TIMING1_TRRD_3 (2 << DDRC_TIMING1_TRRD_BIT)
2421#define DDRC_TIMING1_TRRD_4 (3 << DDRC_TIMING1_TRRD_BIT)
2422
2423#define DDRC_TIMING1_TWR_BIT 4 /* WRITE Recovery Time defined by register MR of DDR2 memory */
2424#define DDRC_TIMING1_TWR_MASK (0x7 << DDRC_TIMING1_TWR_BIT)
2425  #define DDRC_TIMING1_TWR_1 (0 << DDRC_TIMING1_TWR_BIT)
2426  #define DDRC_TIMING1_TWR_2 (1 << DDRC_TIMING1_TWR_BIT)
2427  #define DDRC_TIMING1_TWR_3 (2 << DDRC_TIMING1_TWR_BIT)
2428  #define DDRC_TIMING1_TWR_4 (3 << DDRC_TIMING1_TWR_BIT)
2429  #define DDRC_TIMING1_TWR_5 (4 << DDRC_TIMING1_TWR_BIT)
2430  #define DDRC_TIMING1_TWR_6 (5 << DDRC_TIMING1_TWR_BIT)
2431
2432#define DDRC_TIMING1_TWTR_BIT 0 /* WRITE to READ command delay. */
2433#define DDRC_TIMING1_TWTR_MASK (0x3 << DDRC_TIMING1_TWTR_BIT)
2434  #define DDRC_TIMING1_TWTR_1 (0 << DDRC_TIMING1_TWTR_BIT)
2435  #define DDRC_TIMING1_TWTR_2 (1 << DDRC_TIMING1_TWTR_BIT)
2436  #define DDRC_TIMING1_TWTR_3 (2 << DDRC_TIMING1_TWTR_BIT)
2437  #define DDRC_TIMING1_TWTR_4 (3 << DDRC_TIMING1_TWTR_BIT)
2438
2439/* DDRC Timing Config Register 2 */
2440#define DDRC_TIMING2_TRFC_BIT 12 /* AUTO-REFRESH command period. */
2441#define DDRC_TIMING2_TRFC_MASK (0xf << DDRC_TIMING2_TRFC_BIT)
2442#define DDRC_TIMING2_TMINSR_BIT 8 /* Minimum Self-Refresh / Deep-Power-Down time */
2443#define DDRC_TIMING2_TMINSR_MASK (0xf << DDRC_TIMING2_TMINSR_BIT)
2444#define DDRC_TIMING2_TXP_BIT 4 /* EXIT-POWER-DOWN to next valid command period. */
2445#define DDRC_TIMING2_TXP_MASK (0x7 << DDRC_TIMING2_TXP_BIT)
2446#define DDRC_TIMING2_TMRD_BIT 0 /* Load-Mode-Register to next valid command period. */
2447#define DDRC_TIMING2_TMRD_MASK (0x3 << DDRC_TIMING2_TMRD_BIT)
2448
2449/* DDRC Auto-Refresh Counter */
2450#define DDRC_REFCNT_CON_BIT 16 /* Constant value used to compare with CNT value. */
2451#define DDRC_REFCNT_CON_MASK (0xff << DDRC_REFCNT_CON_BIT)
2452#define DDRC_REFCNT_CNT_BIT 8 /* 8-bit counter */
2453#define DDRC_REFCNT_CNT_MASK (0xff << DDRC_REFCNT_CNT_BIT)
2454#define DDRC_REFCNT_CLKDIV_BIT 1 /* Clock Divider for auto-refresh counter. */
2455#define DDRC_REFCNT_CLKDIV_MASK (0x7 << DDRC_REFCNT_CLKDIV_BIT)
2456#define DDRC_REFCNT_REF_EN (1 << 0) /* Enable Refresh Counter */
2457
2458/* DDRC DQS Delay Control Register */
2459#define DDRC_DQS_ERROR (1 << 29) /* ahb_clk Delay Detect ERROR, read-only. */
2460#define DDRC_DQS_READY (1 << 28) /* ahb_clk Delay Detect READY, read-only. */
2461#define DDRC_DQS_AUTO (1 << 23) /* Hardware auto-detect & set delay line */
2462#define DDRC_DQS_DET (1 << 24) /* Start delay detecting. */
2463#define DDRC_DQS_CLKD_BIT 16 /* CLKD is reference value for setting WDQS and RDQS.*/
2464#define DDRC_DQS_CLKD_MASK (0x7f << DDRC_DQS_CLKD_BIT)
2465#define DDRC_DQS_WDQS_BIT 8 /* Set delay element number to write DQS delay-line. */
2466#define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT)
2467#define DDRC_DQS_RDQS_BIT 0 /* Set delay element number to read DQS delay-line. */
2468#define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT)
2469
2470/* DDRC DQS Delay Adjust Register */
2471#define DDRC_DQS_ADJWDQS_BIT 8 /* The adjust value for WRITE DQS delay */
2472#define DDRC_DQS_ADJWDQS_MASK (0x1f << DDRC_DQS_ADJWDQS_BIT)
2473#define DDRC_DQS_ADJRDQS_BIT 0 /* The adjust value for READ DQS delay */
2474#define DDRC_DQS_ADJRDQS_MASK (0x1f << DDRC_DQS_ADJRDQS_BIT)
2475
2476/* DDRC Memory Map Config Register */
2477#define DDRC_MMAP_BASE_BIT 8 /* base address */
2478#define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT)
2479#define DDRC_MMAP_MASK_BIT 0 /* address mask */
2480#define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT)
2481
2482#define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT)
2483#define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
2484#define DDRC_MMAP1_BASE_128M (0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
2485#define DDRC_MMAP1_BASE_256M (0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
2486
2487#define DDRC_MMAP_MASK_64_64 (0xfc << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/
2488#define DDRC_MMAP_MASK_128_128 (0xf8 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/
2489#define DDRC_MMAP_MASK_256_256 (0xf0 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/
2490
2491/*************************************************************************
2492 * CIM
2493 *************************************************************************/
2494#define CIM_CFG (CIM_BASE + 0x0000)
2495#define CIM_CTRL (CIM_BASE + 0x0004)
2496#define CIM_STATE (CIM_BASE + 0x0008)
2497#define CIM_IID (CIM_BASE + 0x000C)
2498#define CIM_RXFIFO (CIM_BASE + 0x0010)
2499#define CIM_DA (CIM_BASE + 0x0020)
2500#define CIM_FA (CIM_BASE + 0x0024)
2501#define CIM_FID (CIM_BASE + 0x0028)
2502#define CIM_CMD (CIM_BASE + 0x002C)
2503
2504#define REG_CIM_CFG REG32(CIM_CFG)
2505#define REG_CIM_CTRL REG32(CIM_CTRL)
2506#define REG_CIM_STATE REG32(CIM_STATE)
2507#define REG_CIM_IID REG32(CIM_IID)
2508#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
2509#define REG_CIM_DA REG32(CIM_DA)
2510#define REG_CIM_FA REG32(CIM_FA)
2511#define REG_CIM_FID REG32(CIM_FID)
2512#define REG_CIM_CMD REG32(CIM_CMD)
2513
2514/* CIM Configuration Register (CIM_CFG) */
2515
2516#define CIM_CFG_INV_DAT (1 << 15)
2517#define CIM_CFG_VSP (1 << 14)
2518#define CIM_CFG_HSP (1 << 13)
2519#define CIM_CFG_PCP (1 << 12)
2520#define CIM_CFG_DUMMY_ZERO (1 << 9)
2521#define CIM_CFG_EXT_VSYNC (1 << 8)
2522#define CIM_CFG_PACK_BIT 4
2523#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
2524  #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
2525  #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
2526  #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
2527  #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
2528  #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
2529  #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
2530  #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
2531  #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
2532#define CIM_CFG_DSM_BIT 0
2533#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
2534  #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
2535  #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
2536  #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
2537  #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
2538
2539/* CIM Control Register (CIM_CTRL) */
2540
2541#define CIM_CTRL_MCLKDIV_BIT 24
2542#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
2543#define CIM_CTRL_FRC_BIT 16
2544#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
2545  #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
2546  #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
2547  #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
2548  #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
2549  #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
2550  #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
2551  #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
2552  #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
2553  #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
2554  #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
2555  #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
2556  #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
2557  #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
2558  #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
2559  #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
2560  #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
2561#define CIM_CTRL_VDDM (1 << 13)
2562#define CIM_CTRL_DMA_SOFM (1 << 12)
2563#define CIM_CTRL_DMA_EOFM (1 << 11)
2564#define CIM_CTRL_DMA_STOPM (1 << 10)
2565#define CIM_CTRL_RXF_TRIGM (1 << 9)
2566#define CIM_CTRL_RXF_OFM (1 << 8)
2567#define CIM_CTRL_RXF_TRIG_BIT 4
2568#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
2569  #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
2570  #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
2571  #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
2572  #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
2573  #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
2574  #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
2575  #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
2576  #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
2577#define CIM_CTRL_DMA_EN (1 << 2)
2578#define CIM_CTRL_RXF_RST (1 << 1)
2579#define CIM_CTRL_ENA (1 << 0)
2580
2581/* CIM State Register (CIM_STATE) */
2582
2583#define CIM_STATE_DMA_SOF (1 << 6)
2584#define CIM_STATE_DMA_EOF (1 << 5)
2585#define CIM_STATE_DMA_STOP (1 << 4)
2586#define CIM_STATE_RXF_OF (1 << 3)
2587#define CIM_STATE_RXF_TRIG (1 << 2)
2588#define CIM_STATE_RXF_EMPTY (1 << 1)
2589#define CIM_STATE_VDD (1 << 0)
2590
2591/* CIM DMA Command Register (CIM_CMD) */
2592
2593#define CIM_CMD_SOFINT (1 << 31)
2594#define CIM_CMD_EOFINT (1 << 30)
2595#define CIM_CMD_STOP (1 << 28)
2596#define CIM_CMD_LEN_BIT 0
2597#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
2598
2599
2600/*************************************************************************
2601 * SADC (Smart A/D Controller)
2602 *************************************************************************/
2603
2604#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
2605#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
2606#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
2607#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
2608#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
2609#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
2610#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
2611#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
2612#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
2613
2614#define REG_SADC_ENA REG8(SADC_ENA)
2615#define REG_SADC_CFG REG32(SADC_CFG)
2616#define REG_SADC_CTRL REG8(SADC_CTRL)
2617#define REG_SADC_STATE REG8(SADC_STATE)
2618#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
2619#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
2620#define REG_SADC_TSDAT REG32(SADC_TSDAT)
2621#define REG_SADC_BATDAT REG16(SADC_BATDAT)
2622#define REG_SADC_SADDAT REG16(SADC_SADDAT)
2623
2624/* ADC Enable Register */
2625#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
2626#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
2627#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
2628#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
2629
2630/* ADC Configure Register */
2631#define SADC_CFG_CLKOUT_NUM_BIT 16
2632#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
2633#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
2634#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
2635#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
2636  #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
2637  #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
2638  #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
2639#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
2640#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
2641  #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
2642  #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
2643  #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
2644  #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
2645  #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
2646  #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
2647  #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
2648  #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
2649#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
2650#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
2651#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
2652#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
2653#define SADC_CFG_CMD_BIT 0 /* ADC Command */
2654#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
2655  #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
2656  #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
2657  #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
2658  #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
2659  #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
2660  #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
2661  #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
2662  #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
2663  #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
2664  #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
2665  #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
2666  #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
2667  #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
2668
2669/* ADC Control Register */
2670#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
2671#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
2672#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
2673#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
2674#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
2675
2676/* ADC Status Register */
2677#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
2678#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
2679#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
2680#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
2681#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
2682#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
2683#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
2684#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
2685
2686/* ADC Touch Screen Data Register */
2687#define SADC_TSDAT_DATA0_BIT 0
2688#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
2689#define SADC_TSDAT_TYPE0 (1 << 15)
2690#define SADC_TSDAT_DATA1_BIT 16
2691#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
2692#define SADC_TSDAT_TYPE1 (1 << 31)
2693
2694
2695/*************************************************************************
2696 * SLCD (Smart LCD Controller)
2697 *************************************************************************/
2698
2699#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2700#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2701#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2702#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2703
2704#define REG_SLCD_CFG REG32(SLCD_CFG)
2705#define REG_SLCD_CTRL REG8(SLCD_CTRL)
2706#define REG_SLCD_STATE REG8(SLCD_STATE)
2707#define REG_SLCD_DATA REG32(SLCD_DATA)
2708
2709/* SLCD Configure Register */
2710#define SLCD_CFG_BURST_BIT 14
2711#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2712  #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2713  #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2714#define SLCD_CFG_DWIDTH_BIT 10
2715#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2716  #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2717  #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2718  #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2719  #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2720  #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
2721#define SLCD_CFG_CWIDTH_16BIT (0 << 8)
2722#define SLCD_CFG_CWIDTH_8BIT (1 << 8)
2723#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2724#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2725#define SLCD_CFG_RS_CMD_LOW (0 << 3)
2726#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2727#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2728#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2729#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2730#define SLCD_CFG_TYPE_SERIAL (1 << 0)
2731
2732/* SLCD Control Register */
2733#define SLCD_CTRL_DMA_EN (1 << 0)
2734
2735/* SLCD Status Register */
2736#define SLCD_STATE_BUSY (1 << 0)
2737
2738/* SLCD Data Register */
2739#define SLCD_DATA_RS_DATA (0 << 31)
2740#define SLCD_DATA_RS_COMMAND (1 << 31)
2741
2742/*************************************************************************
2743 * LCD (LCD Controller)
2744 *************************************************************************/
2745#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2746#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2747#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2748
2749#define LCD_OSDC (LCD_BASE + 0x100) /* LCD OSD Configure Register */
2750#define LCD_OSDCTRL (LCD_BASE + 0x104) /* LCD OSD Control Register */
2751#define LCD_OSDS (LCD_BASE + 0x108) /* LCD OSD Status Register */
2752#define LCD_BGC (LCD_BASE + 0x10C) /* LCD Background Color Register */
2753#define LCD_KEY0 (LCD_BASE + 0x110) /* LCD Foreground Color Key Register 0 */
2754#define LCD_KEY1 (LCD_BASE + 0x114) /* LCD Foreground Color Key Register 1 */
2755#define LCD_ALPHA (LCD_BASE + 0x118) /* LCD ALPHA Register */
2756#define LCD_IPUR (LCD_BASE + 0x11C) /* LCD IPU Restart Register */
2757
2758#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2759#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2760#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2761
2762#define LCD_XYP0 (LCD_BASE + 0x120) /* Foreground 0 XY Position Register */
2763#define LCD_XYP1 (LCD_BASE + 0x124) /* Foreground 1 XY Position Register */
2764#define LCD_SIZE0 (LCD_BASE + 0x128) /* Foreground 0 Size Register */
2765#define LCD_SIZE1 (LCD_BASE + 0x12C) /* Foreground 1 Size Register */
2766#define LCD_RGBC (LCD_BASE + 0x90) /* RGB Controll Register */
2767
2768#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2769#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2770#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2771#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2772#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2773#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2774#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2775#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2776#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2777#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2778#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2779#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2780#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2781#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2782#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2783
2784#define LCD_OFFS0 (LCD_BASE + 0x60) /* DMA Offsize Register 0 */
2785#define LCD_PW0 (LCD_BASE + 0x64) /* DMA Page Width Register 0 */
2786#define LCD_CNUM0 (LCD_BASE + 0x68) /* DMA Command Counter Register 0 */
2787#define LCD_DESSIZE0 (LCD_BASE + 0x6C) /* Foreground Size in Descriptor 0 Register*/
2788#define LCD_OFFS1 (LCD_BASE + 0x70) /* DMA Offsize Register 1 */
2789#define LCD_PW1 (LCD_BASE + 0x74) /* DMA Page Width Register 1 */
2790#define LCD_CNUM1 (LCD_BASE + 0x78) /* DMA Command Counter Register 1 */
2791#define LCD_DESSIZE1 (LCD_BASE + 0x7C) /* Foreground Size in Descriptor 1 Register*/
2792
2793#define REG_LCD_CFG REG32(LCD_CFG)
2794#define REG_LCD_CTRL REG32(LCD_CTRL)
2795#define REG_LCD_STATE REG32(LCD_STATE)
2796
2797#define REG_LCD_OSDC REG16(LCD_OSDC)
2798#define REG_LCD_OSDCTRL REG16(LCD_OSDCTRL)
2799#define REG_LCD_OSDS REG16(LCD_OSDS)
2800#define REG_LCD_BGC REG32(LCD_BGC)
2801#define REG_LCD_KEY0 REG32(LCD_KEY0)
2802#define REG_LCD_KEY1 REG32(LCD_KEY1)
2803#define REG_LCD_ALPHA REG8(LCD_ALPHA)
2804#define REG_LCD_IPUR REG32(LCD_IPUR)
2805
2806#define REG_LCD_VAT REG32(LCD_VAT)
2807#define REG_LCD_DAH REG32(LCD_DAH)
2808#define REG_LCD_DAV REG32(LCD_DAV)
2809
2810#define REG_LCD_XYP0 REG32(LCD_XYP0)
2811#define REG_LCD_XYP1 REG32(LCD_XYP1)
2812#define REG_LCD_SIZE0 REG32(LCD_SIZE0)
2813#define REG_LCD_SIZE1 REG32(LCD_SIZE1)
2814#define REG_LCD_RGBC REG16(LCD_RGBC)
2815
2816#define REG_LCD_VSYNC REG32(LCD_VSYNC)
2817#define REG_LCD_HSYNC REG32(LCD_HSYNC)
2818#define REG_LCD_PS REG32(LCD_PS)
2819#define REG_LCD_CLS REG32(LCD_CLS)
2820#define REG_LCD_SPL REG32(LCD_SPL)
2821#define REG_LCD_REV REG32(LCD_REV)
2822#define REG_LCD_IID REG32(LCD_IID)
2823#define REG_LCD_DA0 REG32(LCD_DA0)
2824#define REG_LCD_SA0 REG32(LCD_SA0)
2825#define REG_LCD_FID0 REG32(LCD_FID0)
2826#define REG_LCD_CMD0 REG32(LCD_CMD0)
2827#define REG_LCD_DA1 REG32(LCD_DA1)
2828#define REG_LCD_SA1 REG32(LCD_SA1)
2829#define REG_LCD_FID1 REG32(LCD_FID1)
2830#define REG_LCD_CMD1 REG32(LCD_CMD1)
2831
2832#define REG_LCD_OFFS0 REG32(LCD_OFFS0)
2833#define REG_LCD_PW0 REG32(LCD_PW0)
2834#define REG_LCD_CNUM0 REG32(LCD_CNUM0)
2835#define REG_LCD_DESSIZE0 REG32(LCD_DESSIZE0)
2836#define REG_LCD_OFFS1 REG32(LCD_OFFS1)
2837#define REG_LCD_PW1 REG32(LCD_PW1)
2838#define REG_LCD_CNUM1 REG32(LCD_CNUM1)
2839#define REG_LCD_DESSIZE1 REG32(LCD_DESSIZE1)
2840
2841/* LCD Configure Register */
2842#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2843#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2844  #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2845  #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2846#define LCD_CFG_TVEPEH (1 << 30) /* TVE PAL enable extra halfline signal */
2847#define LCD_CFG_FUHOLD (1 << 29) /* hold pixel clock when outFIFO underrun */
2848#define LCD_CFG_NEWDES (1 << 28) /* use new descripter. old: 4words, new:8words */
2849#define LCD_CFG_PALBP (1 << 27) /* bypass data format and alpha blending */
2850#define LCD_CFG_TVEN (1 << 26) /* indicate the terminal is lcd or tv */
2851#define LCD_CFG_RECOVER (1 << 25) /* Auto recover when output fifo underrun */
2852#define LCD_CFG_DITHER (1 << 24) /* Dither function */
2853#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2854#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2855#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2856#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2857#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2858#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2859#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2860#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2861#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2862#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2863#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2864#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2865#define LCD_CFG_HSP (1 << 11) /* HSYNC polarity:0-active high,1-active low */
2866#define LCD_CFG_PCP (1 << 10) /* PCLK polarity:0-rising,1-falling */
2867#define LCD_CFG_DEP (1 << 9) /* DE polarity:0-active high,1-active low */
2868#define LCD_CFG_VSP (1 << 8) /* VSYNC polarity:0-rising,1-falling */
2869#define LCD_CFG_MODE_TFT_18BIT (1 << 7) /* 18bit TFT */
2870#define LCD_CFG_MODE_TFT_16BIT (0 << 7) /* 16bit TFT */
2871#define LCD_CFG_MODE_TFT_24BIT (1 << 6) /* 24bit TFT */
2872#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2873#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2874#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2875  #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2876  #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2877  #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2878#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2879#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2880  #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2881  #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2882  #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2883  #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2884  #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2885  #define LCD_CFG_MODE_INTER_CCIR656 (6 << LCD_CFG_MODE_BIT)
2886  #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2887  #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2888  #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2889  #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2890  #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2891  #define LCD_CFG_MODE_LCM (13 << LCD_CFG_MODE_BIT)
2892  #define LCD_CFG_MODE_SLCD LCD_CFG_MODE_LCM
2893
2894/* LCD Control Register */
2895#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2896#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2897  #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2898  #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2899  #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2900  #define LCD_CTRL_BST_32 (3 << LCD_CTRL_BST_BIT) /* 32-word */
2901#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode(foreground 0 in OSD mode) */
2902#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode(foreground 0 in OSD mode) */
2903#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2904#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2905#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2906  #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2907  #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2908  #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2909#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2910#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2911#define LCD_CTRL_VGA (1 << 15) /* VGA interface enable */
2912#define LCD_CTRL_DACTE (1 << 14) /* DAC loop back test */
2913#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2914#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2915#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2916#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2917#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2918#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2919#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2920#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2921#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2922#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2923#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2924#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2925#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2926  #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2927  #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2928  #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2929  #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2930  #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2931  #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2932  #define LCD_CTRL_BPP_CMPS_24 (6 << LCD_CTRL_BPP_BIT) /* 24 compress bpp */
2933
2934/* LCD Status Register */
2935#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2936#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2937#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2938#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2939#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2940#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2941#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2942
2943/* OSD Configure Register */
2944#define LCD_OSDC_SOFM1 (1 << 15) /* Start of frame interrupt mask for foreground 1 */
2945#define LCD_OSDC_EOFM1 (1 << 14) /* End of frame interrupt mask for foreground 1 */
2946#define LCD_OSDC_SOFM0 (1 << 11) /* Start of frame interrupt mask for foreground 0 */
2947#define LCD_OSDC_EOFM0 (1 << 10) /* End of frame interrupt mask for foreground 0 */
2948#define LCD_OSDC_F1EN (1 << 4) /* enable foreground 1 */
2949#define LCD_OSDC_F0EN (1 << 3) /* enable foreground 0 */
2950#define LCD_OSDC_ALPHAEN (1 << 2) /* enable alpha blending */
2951#define LCD_OSDC_ALPHAMD (1 << 1) /* alpha blending mode */
2952#define LCD_OSDC_OSDEN (1 << 0) /* OSD mode enable */
2953
2954/* OSD Controll Register */
2955#define LCD_OSDCTRL_IPU (1 << 15) /* input data from IPU */
2956#define LCD_OSDCTRL_RGB565 (0 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
2957#define LCD_OSDCTRL_RGB555 (1 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
2958#define LCD_OSDCTRL_CHANGES (1 << 3) /* Change size flag */
2959#define LCD_OSDCTRL_OSDBPP_BIT 0 /* Bits Per Pixel of OSD Channel 1 */
2960#define LCD_OSDCTRL_OSDBPP_MASK (0x7<<LCD_OSDCTRL_OSDBPP_BIT) /* Bits Per Pixel of OSD Channel 1's MASK */
2961  #define LCD_OSDCTRL_OSDBPP_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
2962  #define LCD_OSDCTRL_OSDBPP_15_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
2963  #define LCD_OSDCTRL_OSDBPP_18_24 (5 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/
2964  #define LCD_OSDCTRL_OSDBPP_CMPS_24 (6 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/
2965
2966/* OSD State Register */
2967#define LCD_OSDS_SOF1 (1 << 15) /* Start of frame flag for foreground 1 */
2968#define LCD_OSDS_EOF1 (1 << 14) /* End of frame flag for foreground 1 */
2969#define LCD_OSDS_SOF0 (1 << 11) /* Start of frame flag for foreground 0 */
2970#define LCD_OSDS_EOF0 (1 << 10) /* End of frame flag for foreground 0 */
2971#define LCD_OSDS_READY (1 << 0) /* Read for accept the change */
2972
2973/* Background Color Register */
2974#define LCD_BGC_RED_OFFSET (1 << 16) /* Red color offset */
2975#define LCD_BGC_RED_MASK (0xFF<<LCD_BGC_RED_OFFSET)
2976#define LCD_BGC_GREEN_OFFSET (1 << 8) /* Green color offset */
2977#define LCD_BGC_GREEN_MASK (0xFF<<LCD_BGC_GREEN_OFFSET)
2978#define LCD_BGC_BLUE_OFFSET (1 << 0) /* Blue color offset */
2979#define LCD_BGC_BLUE_MASK (0xFF<<LCD_BGC_BLUE_OFFSET)
2980
2981/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */
2982#define LCD_KEY_KEYEN (1 << 31) /* enable color key */
2983#define LCD_KEY_KEYMD (1 << 30) /* color key mode */
2984#define LCD_KEY_RED_OFFSET 16 /* Red color offset */
2985#define LCD_KEY_RED_MASK (0xFF<<LCD_KEY_RED_OFFSET)
2986#define LCD_KEY_GREEN_OFFSET 8 /* Green color offset */
2987#define LCD_KEY_GREEN_MASK (0xFF<<LCD_KEY_GREEN_OFFSET)
2988#define LCD_KEY_BLUE_OFFSET 0 /* Blue color offset */
2989#define LCD_KEY_BLUE_MASK (0xFF<<LCD_KEY_BLUE_OFFSET)
2990#define LCD_KEY_MASK (LCD_KEY_RED_MASK|LCD_KEY_GREEN_MASK|LCD_KEY_BLUE_MASK)
2991
2992/* IPU Restart Register */
2993#define LCD_IPUR_IPUREN (1 << 31) /* IPU restart function enable*/
2994#define LCD_IPUR_IPURMASK (0xFFFFFF) /* IPU restart value mask*/
2995
2996/* RGB Control Register */
2997#define LCD_RGBC_RGBDM (1 << 15) /* enable RGB Dummy data */
2998#define LCD_RGBC_DMM (1 << 14) /* RGB Dummy mode */
2999#define LCD_RGBC_YCC (1 << 8) /* RGB to YCC */
3000#define LCD_RGBC_ODDRGB_BIT 4 /* odd line serial RGB data arrangement */
3001#define LCD_RGBC_ODDRGB_MASK (0x7<<LCD_RGBC_ODDRGB_BIT)
3002  #define LCD_RGBC_ODD_RGB 0
3003  #define LCD_RGBC_ODD_RBG 1
3004  #define LCD_RGBC_ODD_GRB 2
3005  #define LCD_RGBC_ODD_GBR 3
3006  #define LCD_RGBC_ODD_BRG 4
3007  #define LCD_RGBC_ODD_BGR 5
3008#define LCD_RGBC_EVENRGB_BIT 0 /* even line serial RGB data arrangement */
3009#define LCD_RGBC_EVENRGB_MASK (0x7<<LCD_RGBC_EVENRGB_BIT)
3010  #define LCD_RGBC_EVEN_RGB 0
3011  #define LCD_RGBC_EVEN_RBG 1
3012  #define LCD_RGBC_EVEN_GRB 2
3013  #define LCD_RGBC_EVEN_GBR 3
3014  #define LCD_RGBC_EVEN_BRG 4
3015  #define LCD_RGBC_EVEN_BGR 5
3016
3017/* Vertical Synchronize Register */
3018#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
3019#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
3020#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
3021#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
3022
3023/* Horizontal Synchronize Register */
3024#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
3025#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
3026#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
3027#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
3028
3029/* Virtual Area Setting Register */
3030#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
3031#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
3032#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
3033#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
3034
3035/* Display Area Horizontal Start/End Point Register */
3036#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
3037#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
3038#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
3039#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
3040
3041/* Display Area Vertical Start/End Point Register */
3042#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
3043#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
3044#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
3045#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
3046
3047/* Foreground XY Position Register */
3048#define LCD_XYP_YPOS_BIT 16 /* Y position bit of foreground 0 or 1 */
3049#define LCD_XYP_YPOS_MASK (0xffff << LCD_XYP_YPOS_BIT)
3050#define LCD_XYP_XPOS_BIT 0 /* X position bit of foreground 0 or 1 */
3051#define LCD_XYP_XPOS_MASK (0xffff << LCD_XYP_XPOS_BIT)
3052
3053/* PS Signal Setting */
3054#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
3055#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
3056#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
3057#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
3058
3059/* CLS Signal Setting */
3060#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
3061#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
3062#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
3063#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
3064
3065/* SPL Signal Setting */
3066#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
3067#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
3068#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
3069#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
3070
3071/* REV Signal Setting */
3072#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
3073#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
3074
3075/* DMA Command Register */
3076#define LCD_CMD_SOFINT (1 << 31)
3077#define LCD_CMD_EOFINT (1 << 30)
3078#define LCD_CMD_CMD (1 << 29) /* indicate command in slcd mode */
3079#define LCD_CMD_PAL (1 << 28)
3080#define LCD_CMD_LEN_BIT 0
3081#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
3082
3083/* DMA Offsize Register 0,1 */
3084
3085/* DMA Page Width Register 0,1 */
3086
3087/* DMA Command Counter Register 0,1 */
3088
3089/* Foreground 0,1 Size Register */
3090#define LCD_DESSIZE_HEIGHT_BIT 16 /* height of foreground 1 */
3091#define LCD_DESSIZE_HEIGHT_MASK (0xffff << LCD_DESSIZE_HEIGHT_BIT)
3092#define LCD_DESSIZE_WIDTH_BIT 0 /* width of foreground 1 */
3093#define LCD_DESSIZE_WIDTH_MASK (0xffff << LCD_DESSIZE_WIDTH_BIT)
3094
3095/*************************************************************************
3096 * TVE (TV Encoder Controller)
3097 *************************************************************************/
3098#define TVE_CTRL (TVE_BASE + 0x40) /* TV Encoder Control register */
3099#define TVE_FRCFG (TVE_BASE + 0x44) /* Frame configure register */
3100#define TVE_SLCFG1 (TVE_BASE + 0x50) /* TV signal level configure register 1 */
3101#define TVE_SLCFG2 (TVE_BASE + 0x54) /* TV signal level configure register 2*/
3102#define TVE_SLCFG3 (TVE_BASE + 0x58) /* TV signal level configure register 3*/
3103#define TVE_LTCFG1 (TVE_BASE + 0x60) /* Line timing configure register 1 */
3104#define TVE_LTCFG2 (TVE_BASE + 0x64) /* Line timing configure register 2 */
3105#define TVE_CFREQ (TVE_BASE + 0x70) /* Chrominance sub-carrier frequency configure register */
3106#define TVE_CPHASE (TVE_BASE + 0x74) /* Chrominance sub-carrier phase configure register */
3107#define TVE_CBCRCFG (TVE_BASE + 0x78) /* Chrominance filter configure register */
3108#define TVE_WSSCR (TVE_BASE + 0x80) /* Wide screen signal control register */
3109#define TVE_WSSCFG1 (TVE_BASE + 0x84) /* Wide screen signal configure register 1 */
3110#define TVE_WSSCFG2 (TVE_BASE + 0x88) /* Wide screen signal configure register 2 */
3111#define TVE_WSSCFG3 (TVE_BASE + 0x8c) /* Wide screen signal configure register 3 */
3112
3113#define REG_TVE_CTRL REG32(TVE_CTRL)
3114#define REG_TVE_FRCFG REG32(TVE_FRCFG)
3115#define REG_TVE_SLCFG1 REG32(TVE_SLCFG1)
3116#define REG_TVE_SLCFG2 REG32(TVE_SLCFG2)
3117#define REG_TVE_SLCFG3 REG32(TVE_SLCFG3)
3118#define REG_TVE_LTCFG1 REG32(TVE_LTCFG1)
3119#define REG_TVE_LTCFG2 REG32(TVE_LTCFG2)
3120#define REG_TVE_CFREQ REG32(TVE_CFREQ)
3121#define REG_TVE_CPHASE REG32(TVE_CPHASE)
3122#define REG_TVE_CBCRCFG REG32(TVE_CBCRCFG)
3123#define REG_TVE_WSSCR REG32(TVE_WSSCR)
3124#define REG_TVE_WSSCFG1 REG32(TVE_WSSCFG1)
3125#define REG_TVE_WSSCFG2 REG32(TVE_WSSCFG2)
3126#define REG_TVE_WSSCFG3 REG32(TVE_WSSCFG3)
3127
3128/* TV Encoder Control register */
3129#define TVE_CTRL_EYCBCR (1 << 25) /* YCbCr_enable */
3130#define TVE_CTRL_ECVBS (1 << 24) /* cvbs_enable */
3131#define TVE_CTRL_DAPD3 (1 << 23) /* DAC 3 power down */
3132#define TVE_CTRL_DAPD2 (1 << 22) /* DAC 2 power down */
3133#define TVE_CTRL_DAPD1 (1 << 21) /* DAC 1 power down */
3134#define TVE_CTRL_DAPD (1 << 20) /* power down all DACs */
3135#define TVE_CTRL_YCDLY_BIT 16
3136#define TVE_CTRL_YCDLY_MASK (0x7 << TVE_CTRL_YCDLY_BIT)
3137#define TVE_CTRL_CGAIN_BIT 14
3138#define TVE_CTRL_CGAIN_MASK (0x3 << TVE_CTRL_CGAIN_BIT)
3139  #define TVE_CTRL_CGAIN_FULL (0 << TVE_CTRL_CGAIN_BIT) /* gain = 1 */
3140  #define TVE_CTRL_CGAIN_QUTR (1 << TVE_CTRL_CGAIN_BIT) /* gain = 1/4 */
3141  #define TVE_CTRL_CGAIN_HALF (2 << TVE_CTRL_CGAIN_BIT) /* gain = 1/2 */
3142  #define TVE_CTRL_CGAIN_THREE_QURT (3 << TVE_CTRL_CGAIN_BIT) /* gain = 3/4 */
3143#define TVE_CTRL_CBW_BIT 12
3144#define TVE_CTRL_CBW_MASK (0x3 << TVE_CTRL_CBW_BIT)
3145  #define TVE_CTRL_CBW_NARROW (0 << TVE_CTRL_CBW_BIT) /* Narrow band */
3146  #define TVE_CTRL_CBW_WIDE (1 << TVE_CTRL_CBW_BIT) /* Wide band */
3147  #define TVE_CTRL_CBW_EXTRA (2 << TVE_CTRL_CBW_BIT) /* Extra wide band */
3148  #define TVE_CTRL_CBW_ULTRA (3 << TVE_CTRL_CBW_BIT) /* Ultra wide band */
3149#define TVE_CTRL_SYNCT (1 << 9)
3150#define TVE_CTRL_PAL (1 << 8)
3151#define TVE_CTRL_FINV (1 << 7) /* invert_top:1-invert top and bottom fields. */
3152#define TVE_CTRL_ZBLACK (1 << 6) /* bypass_yclamp:1-Black of luminance (Y) input is 0.*/
3153#define TVE_CTRL_CR1ST (1 << 5) /* uv_order:0-Cb before Cr,1-Cr before Cb */
3154#define TVE_CTRL_CLBAR (1 << 4) /* Color bar mode:0-Output input video to TV,1-Output color bar to TV */
3155#define TVE_CTRL_SWRST (1 << 0) /* Software reset:1-TVE is reset */
3156
3157/* Signal level configure register 1 */
3158#define TVE_SLCFG1_BLACKL_BIT 0
3159#define TVE_SLCFG1_BLACKL_MASK (0x3ff << TVE_SLCFG1_BLACKL_BIT)
3160#define TVE_SLCFG1_WHITEL_BIT 16
3161#define TVE_SLCFG1_WHITEL_MASK (0x3ff << TVE_SLCFG1_WHITEL_BIT)
3162
3163/* Signal level configure register 2 */
3164#define TVE_SLCFG2_BLANKL_BIT 0
3165#define TVE_SLCFG2_BLANKL_MASK (0x3ff << TVE_SLCFG2_BLANKL_BIT)
3166#define TVE_SLCFG2_VBLANKL_BIT 16
3167#define TVE_SLCFG2_VBLANKL_MASK (0x3ff << TVE_SLCFG2_VBLANKL_BIT)
3168
3169/* Signal level configure register 3 */
3170#define TVE_SLCFG3_SYNCL_BIT 0
3171#define TVE_SLCFG3_SYNCL_MASK (0xff << TVE_SLCFG3_SYNCL_BIT)
3172
3173/* Line timing configure register 1 */
3174#define TVE_LTCFG1_BACKP_BIT 0
3175#define TVE_LTCFG1_BACKP_MASK (0x7f << TVE_LTCFG1_BACKP_BIT)
3176#define TVE_LTCFG1_HSYNCW_BIT 8
3177#define TVE_LTCFG1_HSYNCW_MASK (0x7f << TVE_LTCFG1_HSYNCW_BIT)
3178#define TVE_LTCFG1_FRONTP_BIT 16
3179#define TVE_LTCFG1_FRONTP_MASK (0x1f << TVE_LTCFG1_FRONTP_BIT)
3180
3181/* Line timing configure register 2 */
3182#define TVE_LTCFG2_BURSTW_BIT 0
3183#define TVE_LTCFG2_BURSTW_MASK (0x3f << TVE_LTCFG2_BURSTW_BIT)
3184#define TVE_LTCFG2_PREBW_BIT 8
3185#define TVE_LTCFG2_PREBW_MASK (0x1f << TVE_LTCFG2_PREBW_BIT)
3186#define TVE_LTCFG2_ACTLIN_BIT 16
3187#define TVE_LTCFG2_ACTLIN_MASK (0x7ff << TVE_LTCFG2_ACTLIN_BIT)
3188
3189/* Chrominance sub-carrier phase configure register */
3190#define TVE_CPHASE_CCRSTP_BIT 0
3191#define TVE_CPHASE_CCRSTP_MASK (0x3 << TVE_CPHASE_CCRSTP_BIT)
3192  #define TVE_CPHASE_CCRSTP_8 (0 << TVE_CPHASE_CCRSTP_BIT) /* Every 8 field */
3193  #define TVE_CPHASE_CCRSTP_4 (1 << TVE_CPHASE_CCRSTP_BIT) /* Every 4 field */
3194  #define TVE_CPHASE_CCRSTP_2 (2 << TVE_CPHASE_CCRSTP_BIT) /* Every 2 lines */
3195  #define TVE_CPHASE_CCRSTP_0 (3 << TVE_CPHASE_CCRSTP_BIT) /* Never */
3196#define TVE_CPHASE_ACTPH_BIT 16
3197#define TVE_CPHASE_ACTPH_MASK (0xff << TVE_CPHASE_ACTPH_BIT)
3198#define TVE_CPHASE_INITPH_BIT 24
3199#define TVE_CPHASE_INITPH_MASK (0xff << TVE_CPHASE_INITPH_BIT)
3200
3201/* Chrominance filter configure register */
3202#define TVE_CBCRCFG_CRGAIN_BIT 0
3203#define TVE_CBCRCFG_CRGAIN_MASK (0xff << TVE_CBCRCFG_CRGAIN_BIT)
3204#define TVE_CBCRCFG_CBGAIN_BIT 8
3205#define TVE_CBCRCFG_CBGAIN_MASK (0xff << TVE_CBCRCFG_CBGAIN_BIT)
3206#define TVE_CBCRCFG_CRBA_BIT 16
3207#define TVE_CBCRCFG_CRBA_MASK (0xff << TVE_CBCRCFG_CRBA_BIT)
3208#define TVE_CBCRCFG_CBBA_BIT 24
3209#define TVE_CBCRCFG_CBBA_MASK (0xff << TVE_CBCRCFG_CBBA_BIT)
3210
3211/* Frame configure register */
3212#define TVE_FRCFG_NLINE_BIT 0
3213#define TVE_FRCFG_NLINE_MASK (0x3ff << TVE_FRCFG_NLINE_BIT)
3214#define TVE_FRCFG_L1ST_BIT 16
3215#define TVE_FRCFG_L1ST_MASK (0xff << TVE_FRCFG_L1ST_BIT)
3216
3217/* Wide screen signal control register */
3218#define TVE_WSSCR_EWSS0_BIT 0
3219#define TVE_WSSCR_EWSS1_BIT 1
3220#define TVE_WSSCR_WSSTP_BIT 2
3221#define TVE_WSSCR_WSSCKBP_BIT 3
3222#define TVE_WSSCR_WSSEDGE_BIT 4
3223#define TVE_WSSCR_WSSEDGE_MASK (0x7 << TVE_WSSCR_WSSEDGE_BIT)
3224#define TVE_WSSCR_ENCH_BIT 8
3225#define TVE_WSSCR_NCHW_BIT 9
3226#define TVE_WSSCR_NCHFREQ_BIT 12
3227#define TVE_WSSCR_NCHFREQ_MASK (0x7 << TVE_WSSCR_NCHFREQ_BIT)
3228
3229
3230/*************************************************************************
3231 * USB Device
3232 *************************************************************************/
3233#define USB_BASE UDC_BASE
3234
3235#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
3236#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
3237#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
3238#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
3239#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
3240#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
3241#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
3242#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
3243#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
3244#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
3245#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
3246
3247#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
3248#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
3249#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
3250#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
3251#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
3252#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
3253#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
3254#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
3255
3256#define USB_FIFO_EP0 (USB_BASE + 0x20)
3257#define USB_FIFO_EP1 (USB_BASE + 0x24)
3258#define USB_FIFO_EP2 (USB_BASE + 0x28)
3259
3260#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
3261#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
3262
3263#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
3264#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
3265#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
3266#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
3267#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
3268#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
3269#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
3270
3271
3272/* Power register bit masks */
3273#define USB_POWER_SUSPENDM 0x01
3274#define USB_POWER_RESUME 0x04
3275#define USB_POWER_HSMODE 0x10
3276#define USB_POWER_HSENAB 0x20
3277#define USB_POWER_SOFTCONN 0x40
3278
3279/* Interrupt register bit masks */
3280#define USB_INTR_SUSPEND 0x01
3281#define USB_INTR_RESUME 0x02
3282#define USB_INTR_RESET 0x04
3283
3284#define USB_INTR_EP0 0x0001
3285#define USB_INTR_INEP1 0x0002
3286#define USB_INTR_INEP2 0x0004
3287#define USB_INTR_OUTEP1 0x0002
3288
3289/* CSR0 bit masks */
3290#define USB_CSR0_OUTPKTRDY 0x01
3291#define USB_CSR0_INPKTRDY 0x02
3292#define USB_CSR0_SENTSTALL 0x04
3293#define USB_CSR0_DATAEND 0x08
3294#define USB_CSR0_SETUPEND 0x10
3295#define USB_CSR0_SENDSTALL 0x20
3296#define USB_CSR0_SVDOUTPKTRDY 0x40
3297#define USB_CSR0_SVDSETUPEND 0x80
3298
3299/* Endpoint CSR register bits */
3300#define USB_INCSRH_AUTOSET 0x80
3301#define USB_INCSRH_ISO 0x40
3302#define USB_INCSRH_MODE 0x20
3303#define USB_INCSRH_DMAREQENAB 0x10
3304#define USB_INCSRH_DMAREQMODE 0x04
3305#define USB_INCSR_CDT 0x40
3306#define USB_INCSR_SENTSTALL 0x20
3307#define USB_INCSR_SENDSTALL 0x10
3308#define USB_INCSR_FF 0x08
3309#define USB_INCSR_UNDERRUN 0x04
3310#define USB_INCSR_FFNOTEMPT 0x02
3311#define USB_INCSR_INPKTRDY 0x01
3312#define USB_OUTCSRH_AUTOCLR 0x80
3313#define USB_OUTCSRH_ISO 0x40
3314#define USB_OUTCSRH_DMAREQENAB 0x20
3315#define USB_OUTCSRH_DNYT 0x10
3316#define USB_OUTCSRH_DMAREQMODE 0x08
3317#define USB_OUTCSR_CDT 0x80
3318#define USB_OUTCSR_SENTSTALL 0x40
3319#define USB_OUTCSR_SENDSTALL 0x20
3320#define USB_OUTCSR_FF 0x10
3321#define USB_OUTCSR_DATAERR 0x08
3322#define USB_OUTCSR_OVERRUN 0x04
3323#define USB_OUTCSR_FFFULL 0x02
3324#define USB_OUTCSR_OUTPKTRDY 0x01
3325
3326/* Testmode register bits */
3327#define USB_TEST_SE0NAK 0x01
3328#define USB_TEST_J 0x02
3329#define USB_TEST_K 0x04
3330#define USB_TEST_PACKET 0x08
3331
3332/* DMA control bits */
3333#define USB_CNTL_ENA 0x01
3334#define USB_CNTL_DIR_IN 0x02
3335#define USB_CNTL_MODE_1 0x04
3336#define USB_CNTL_INTR_EN 0x08
3337#define USB_CNTL_EP(n) ((n) << 4)
3338#define USB_CNTL_BURST_0 (0 << 9)
3339#define USB_CNTL_BURST_4 (1 << 9)
3340#define USB_CNTL_BURST_8 (2 << 9)
3341#define USB_CNTL_BURST_16 (3 << 9)
3342
3343/*************************************************************************
3344 * BCH
3345 *************************************************************************/
3346#define BCH_CR (BCH_BASE + 0x00) /* BCH Control register */
3347#define BCH_CRS (BCH_BASE + 0x04) /* BCH Control Set register */
3348#define BCH_CRC (BCH_BASE + 0x08) /* BCH Control Clear register */
3349#define BCH_CNT (BCH_BASE + 0x0C) /* BCH ENC/DEC Count register */
3350#define BCH_DR (BCH_BASE + 0x10) /* BCH data register */
3351#define BCH_PAR0 (BCH_BASE + 0x14) /* BCH Parity 0 register */
3352#define BCH_PAR1 (BCH_BASE + 0x18) /* BCH Parity 1 register */
3353#define BCH_PAR2 (BCH_BASE + 0x1C) /* BCH Parity 2 register */
3354#define BCH_PAR3 (BCH_BASE + 0x20) /* BCH Parity 3 register */
3355#define BCH_PAR4 (BCH_BASE + 0x24) /* BCH Parity 4 register */
3356#define BCH_PAR5 (BCH_BASE + 0x28) /* BCH Parity 5 register */
3357#define BCH_PAR6 (BCH_BASE + 0x2C) /* BCH Parity 6 register */
3358#define BCH_PAR7 (BCH_BASE + 0x30) /* BCH Parity 7 register */
3359#define BCH_PAR8 (BCH_BASE + 0x34) /* BCH Parity 8 register */
3360#define BCH_PAR9 (BCH_BASE + 0x38) /* BCH Parity 9 register */
3361#define BCH_ERR0 (BCH_BASE + 0x3C) /* BCH Error Report 0 register */
3362#define BCH_ERR1 (BCH_BASE + 0x40) /* BCH Error Report 1 register */
3363#define BCH_ERR2 (BCH_BASE + 0x44) /* BCH Error Report 2 register */
3364#define BCH_ERR3 (BCH_BASE + 0x48) /* BCH Error Report 3 register */
3365#define BCH_ERR4 (BCH_BASE + 0x4C) /* BCH Error Report 4 register */
3366#define BCH_ERR5 (BCH_BASE + 0x50) /* BCH Error Report 5 register */
3367#define BCH_ERR6 (BCH_BASE + 0x54) /* BCH Error Report 6 register */
3368#define BCH_ERR7 (BCH_BASE + 0x58) /* BCH Error Report 7 register */
3369#define BCH_ERR8 (BCH_BASE + 0x5C) /* BCH Error Report 8 register */
3370#define BCH_ERR9 (BCH_BASE + 0x60) /* BCH Error Report 9 register */
3371#define BCH_ERR10 (BCH_BASE + 0x64) /* BCH Error Report 10 register */
3372#define BCH_ERR11 (BCH_BASE + 0x68) /* BCH Error Report 11 register */
3373#define BCH_INTS (BCH_BASE + 0x6C) /* BCH Interrupt Status register */
3374#define BCH_INTE (BCH_BASE + 0x70) /* BCH Interrupt Enable register */
3375#define BCH_INTES (BCH_BASE + 0x74) /* BCH Interrupt Set register */
3376#define BCH_INTEC (BCH_BASE + 0x78) /* BCH Interrupt Clear register */
3377
3378#define REG_BCH_CR REG32(BCH_CR)
3379#define REG_BCH_CRS REG32(BCH_CRS)
3380#define REG_BCH_CRC REG32(BCH_CRC)
3381#define REG_BCH_CNT REG32(BCH_CNT)
3382#define REG_BCH_DR REG8(BCH_DR)
3383#define REG_BCH_PAR0 REG32(BCH_PAR0)
3384#define REG_BCH_PAR1 REG32(BCH_PAR1)
3385#define REG_BCH_PAR2 REG32(BCH_PAR2)
3386#define REG_BCH_PAR3 REG32(BCH_PAR3)
3387#define REG_BCH_PAR4 REG32(BCH_PAR4)
3388#define REG_BCH_PAR5 REG32(BCH_PAR5)
3389#define REG_BCH_PAR6 REG32(BCH_PAR6)
3390#define REG_BCH_PAR7 REG32(BCH_PAR7)
3391#define REG_BCH_PAR8 REG32(BCH_PAR8)
3392#define REG_BCH_PAR9 REG32(BCH_PAR9)
3393#define REG_BCH_ERR0 REG32(BCH_ERR0)
3394#define REG_BCH_ERR1 REG32(BCH_ERR1)
3395#define REG_BCH_ERR2 REG32(BCH_ERR2)
3396#define REG_BCH_ERR3 REG32(BCH_ERR3)
3397#define REG_BCH_ERR4 REG32(BCH_ERR4)
3398#define REG_BCH_ERR5 REG32(BCH_ERR5)
3399#define REG_BCH_ERR6 REG32(BCH_ERR6)
3400#define REG_BCH_ERR7 REG32(BCH_ERR7)
3401#define REG_BCH_ERR8 REG32(BCH_ERR8)
3402#define REG_BCH_ERR9 REG32(BCH_ERR9)
3403#define REG_BCH_ERR10 REG32(BCH_ERR10)
3404#define REG_BCH_ERR11 REG32(BCH_ERR11)
3405#define REG_BCH_INTS REG32(BCH_INTS)
3406#define REG_BCH_INTE REG32(BCH_INTE)
3407#define REG_BCH_INTEC REG32(BCH_INTEC)
3408#define REG_BCH_INTES REG32(BCH_INTES)
3409
3410/* BCH Control Register*/
3411#define BCH_CR_DMAE (1 << 7) /* BCH DMA Enable */
3412#define BCH_CR_BSEL_BIT 3
3413#define BCH_CR_BSEL_MASK (0x3 << BCH_CR_BSEL_BIT)
3414  #define BCH_CR_BSEL_4 (0x0 << BCH_CR_BSEL_BIT) /* 4 Bit BCH Select */
3415  #define BCH_CR_BSEL_8 (0x1 << BCH_CR_BSEL_BIT) /* 8 Bit BCH Select */
3416  #define BCH_CR_BSEL_12 (0x2 << BCH_CR_BSEL_BIT) /* 12 Bit BCH Select */
3417  #define BCH_CR_BSEL_16 (0x3 << BCH_CR_BSEL_BIT) /* 16 Bit BCH Select */
3418  #define BCH_CR_BSEL_20 (0x4 << BCH_CR_BSEL_BIT) /* 20 Bit BCH Select */
3419  #define BCH_CR_BSEL_24 (0x5 << BCH_CR_BSEL_BIT) /* 24 Bit BCH Select */
3420#define BCH_CR_ENCE (1 << 2) /* BCH Encoding Select */
3421#define BCH_CR_DECE (0 << 2) /* BCH Decoding Select */
3422#define BCH_CR_BRST (1 << 1) /* BCH Reset */
3423#define BCH_CR_BCHE (1 << 0) /* BCH Enable */
3424
3425/* BCH Interrupt Status Register */
3426#define BCH_INTS_ERRC_BIT 27
3427#define BCH_INTS_ERRC_MASK (0x1f << BCH_INTS_ERRC_BIT)
3428#define BCH_INTS_ALLf (1 << 4)
3429#define BCH_INTS_DECF (1 << 3)
3430#define BCH_INTS_ENCF (1 << 2)
3431#define BCH_INTS_UNCOR (1 << 1)
3432#define BCH_INTS_ERR (1 << 0)
3433
3434/* BCH ENC/DEC Count Register */
3435#define BCH_CNT_DEC_BIT 16
3436#define BCH_CNT_DEC_MASK (0x7ff << BCH_CNT_DEC_BIT)
3437#define BCH_CNT_ENC_BIT 0
3438#define BCH_CNT_ENC_MASK (0x7ff << BCH_CNT_ENC_BIT)
3439
3440/* BCH Error Report Register */
3441#define BCH_ERR_INDEX_ODD_BIT 16
3442#define BCH_ERR_INDEX_ODD_MASK (0x1fff << BCH_ERR_INDEX_ODD_BIT)
3443#define BCH_ERR_INDEX_EVEN_BIT 0
3444#define BCH_ERR_INDEX_EVEN_MASK (0x1fff << BCH_ERR_INDEX_EVEN_BIT)
3445
3446//----------------------------------------------------------------------
3447//
3448// Module Operation Definitions
3449//
3450//----------------------------------------------------------------------
3451#ifndef __ASSEMBLY__
3452
3453#define is_share_mode() (1)
3454
3455/***************************************************************************
3456 * GPIO
3457 ***************************************************************************/
3458
3459//------------------------------------------------------
3460// GPIO Pins Description
3461//
3462// PORT 0:
3463//
3464// PIN/BIT N FUNC0 FUNC1 FUNC2 NOTE
3465// 0 SD0 - -
3466// 1 SD1 - -
3467// 2 SD2 - -
3468// 3 SD3 - -
3469// 4 SD4 - -
3470// 5 SD5 - -
3471// 6 SD6 - -
3472// 7 SD7 - -
3473// 8 SD8 - -
3474// 9 SD9 - -
3475// 10 SD10 - -
3476// 11 SD11 - -
3477// 12 SD12 - -
3478// 13 SD13 - -
3479// 14 SD14 - -
3480// 15 SD15 - -
3481// 16 RD_ - -
3482// 17 WE_ - -
3483// 18 FRE_ MSC0_CLK SSI0_CLK
3484// 19 FWE_ MSC0_CMD SSI0_CE0_
3485// 20 MSC0_D0 SSI0_DR - 1
3486// 21 CS1_ MSC0_D1 SSI0_DT
3487// 22 CS2_ MSC0_D2 -
3488// 23 CS3_ - -
3489// 24 CS4_ - -
3490// 25 CS5_ - -
3491// 26 CS6_ - -
3492// 27 WAIT_ - -
3493// 28 DREQ0 - -
3494// 29 DACK0 OWI -
3495// 30 - - - 6
3496// 31 - - - 7
3497
3498//Note1. PA20: GPIO group A bit 20. If NAND flash is used, this pin must be used as NAND FRB. (NAND flash ready/busy)
3499//Note6. PA30: GPIO group A bit 30 can only be used as input and interrupt, no pull-up and pull-down.
3500//Note7. PA31: GPIO group A bit 31. No corresponding pin exists for this GPIO. It is only used to select the function between UART and JTAG, which share the same set of pins, by using register PASEL [31]
3501// When PASEL [31]=0, select JTAG function.
3502// When PASEL [31]=1, select UART function
3503
3504//------------------------------------------------------
3505// PORT 1:
3506//
3507// PIN/BIT N FUNC0 FUNC1 FUNC2 NOTE
3508// 0 SA0 - -
3509// 1 SA1 - -
3510// 2 SA2 - - CL
3511// 3 SA3 - - AL
3512// 4 SA4 - -
3513// 5 SA5 - -
3514// 6 CIM_PCLK TSCLK -
3515// 7 CIM_HSYN TSFRM -
3516// 8 CIM_VSYN TSSTR -
3517// 9 CIM_MCLK TSFAIL -
3518// 10 CIM_D0 TSDI0 -
3519// 11 CIM_D1 TSDI1 -
3520// 12 CIM_D2 TSDI2 -
3521// 13 CIM_D3 TSDI3 -
3522// 14 CIM_D4 TSDI4 -
3523// 15 CIM_D5 TSDI5 -
3524// 16 CIM_D6 TSDI6 -
3525// 17 CIM_D7 TSDI7 -
3526// 18 - - -
3527// 19 - - -
3528// 20 MSC2_D0 SSI2_DR TSDI0
3529// 21 MSC2_D1 SSI2_DT TSDI1
3530// 22 TSDI2 - -
3531// 23 TSDI3 - -
3532// 24 TSDI4 - -
3533// 25 TSDI5 - -
3534// 26 TSDI6 - -
3535// 27 TSDI7 - -
3536// 28 MSC2_CLK SSI2_CLK TSCLK
3537// 29 MSC2_CMD SSI2_CE0_ TSSTR
3538// 30 MSC2_D2 SSI2_GPC TSFAIL
3539// 31 MSC2_D3 SSI2_CE1_ TSFRM
3540
3541//------------------------------------------------------
3542// PORT 2:
3543// PIN/BIT N FUNC0 FUNC1 FUNC2 FUNC3 NOTE
3544// 0 LCD_B0 (O) LCD_REV (O) - -
3545// 1 LCD_B1 (O) LCD_PS (O) - -
3546// 2 LCD_B2 (O) - - -
3547// 3 LCD_B3 (O) - - -
3548// 4 LCD_B4 (O) - - -
3549// 5 LCD_B5 (O) - - -
3550// 6 LCD_B6 (O) - - -
3551// 7 LCD_B7 (O) - - -
3552// 8 LCD_PCLK (O) - - -
3553// 9 LCD_DE (O) - - -
3554// 10 LCD_G0 (O) LCD_SPL (O) - -
3555// 11 LCD_G1 (O) - - -
3556// 12 LCD_G2 (O) - - -
3557// 13 LCD_G3 (O) - - -
3558// 14 LCD_G4 (O) - - -
3559// 15 LCD_G5 (O) - - -
3560// 16 LCD_G6 (O) - - -
3561// 17 LCD_G7 (O) - - -
3562// 18 LCD_HSYN (IO) - - -
3563// 19 LCD_VSYN (IO) - - -
3564// 20 LCD_R0 (O) LCD_CLS (O) - -
3565// 21 LCD_R1 (O) - - -
3566// 22 LCD_R2 (O) - - -
3567// 23 LCD_R3 (O) - - -
3568// 24 LCD_R4 (O) - - -
3569// 25 LCD_R5 (O) - - -
3570// 26 LCD_R6 (O) - - -
3571// 27 LCD_R7 (O) - - -
3572// 28 UART2_RxD (I) - - -
3573// 29 UART2_CTS_ (I) - - -
3574// 30 UART2_TxD (O) - - -
3575// 31 UART2_RTS_ (O) - - -
3576
3577//------------------------------------------------------
3578// PORT 3:
3579//
3580// PIN/BIT N FUNC0 FUNC1 FUNC2 FUNC3 NOTE
3581// 0 MII_TXD0 - - -
3582// 1 MII_TXD1 - - -
3583// 2 MII_TXD2 - - -
3584// 3 MII_TXD3 - - -
3585// 4 MII_TXEN - - -
3586// 5 MII_TXCLK(RMII_CLK) - - -
3587// 6 MII_COL - - -
3588// 7 MII_RXER - - -
3589// 8 MII_RXDV - - -
3590// 9 MII_RXCLK - - -
3591// 10 MII_RXD0 - - -
3592// 11 MII_RXD1 - - -
3593// 12 MII_RXD2 - - -
3594// 13 MII_RXD3 - - -
3595// 14 MII_CRS - - -
3596// 15 MII_MDC - - -
3597// 16 MII_MDIO - - -
3598// 17 BOOT_SEL0 - - - Note2,5
3599// 18 BOOT_SEL1 - - - Note3,5
3600// 19 BOOT_SEL2 - - - Note4,5
3601// 20 MSC1_D0 SSI1_DR - -
3602// 21 MSC1_D1 SSI1_DT - -
3603// 22 MSC1_D2 SSI1_GPC - -
3604// 23 MSC1_D3 SSI1_CE1_ - -
3605// 24 MSC1_CLK SSI1_CLK - -
3606// 25 MSC1_CMD SSI1_CE0_ - -
3607// 26 UART1_RxD - - -
3608// 27 UART1_CTS_ - - -
3609// 28 UART1_TxD - - -
3610// 29 UART1_RTS_ - - -
3611// 30 I2C0_SDA - - -
3612// 31 I2C0_SCK - - -
3613//
3614// Note2. PD17: GPIO group D bit 17 is used as BOOT_SEL0 input during boot.
3615// Note3. PD18: GPIO group D bit 18 is used as BOOT_SEL1 input during boot.
3616// Note4. PD19: GPIO group D bit 19 is used as BOOT_SEL2 input during boot.
3617// Note5. BOOT_SEL2, BOOT_SEL1, BOOT_SEL0 are used to select boot source and function during the processor boot.
3618//
3619//------------------------------------------------------
3620// PORT 4:
3621//
3622// PIN/BIT N FUNC0 FUNC1 FUNC2 FUNC3 NOTE
3623// 0 PWM0 - - -
3624// 1 PWM1 - - -
3625// 2 PWM2 SYNC - -
3626// 3 PWM3 UART3_RxD BCLK -
3627// 4 PWM4 - - -
3628// 5 PWM5 UART3_TxD SCLK_RSTN -
3629// 6 SDATI - - -
3630// 7 SDATO - - -
3631// 8 UART3_CTS_ - - -
3632// 9 UART3_RTS_ - - -
3633// 10 - - - -
3634// 11 SDATO1 - - -
3635// 12 SDATO2 - - -
3636// 13 SDATO3 - - -
3637// 14 SSI0_DR SSI1_DR SSI2_DR -
3638// 15 SSI0_CLK SI1_CLK SSI2_CLK -
3639// 16 SSI0_CE0_ SI1_CE0_ SSI2_CE0_ -
3640// 17 SSI0_DT SSI1_DT SSI2_DT -
3641// 18 SSI0_CE1_ SSI1_CE1_ SSI2_CE1_ -
3642// 19 SSI0_GPC SSI1_GPC SSI2_GPC -
3643// 20 MSC0_D0 MSC1_D0 MSC2_D0 -
3644// 21 MSC0_D1 MSC1_D1 MSC2_D1 -
3645// 22 MSC0_D2 MSC1_D2 MSC2_D2 -
3646// 23 MSC0_D3 MSC1_D3 MSC2_D3 -
3647// 24 MSC0_CLK MSC1_CLK MSC2_CLK -
3648// 25 MSC0_CMD MSC1_CMD MSC2_CMD -
3649// 26 MSC0_D4 MSC0_D4 MSC0_D4 PS2_MCLK
3650// 27 MSC0_D5 MSC0_D5 MSC0_D5 PS2_MDATA
3651// 28 MSC0_D6 MSC0_D6 MSC0_D6 PS2_KCLK
3652// 29 MSC0_D7 MSC0_D7 MSC0_D7 PS2_KDATA
3653// 30 I2C1_SDA SCC_DATA - -
3654// 31 I2C1_SCK SCC_CLK - -
3655//
3656//------------------------------------------------------
3657// PORT 5:
3658//
3659// PIN/BIT N FUNC0 FUNC1 FUNC2 FUNC3 NOTE
3660// 0 UART0_RxD GPS_CLK - -
3661// 1 UART0_CTS_ GPS_MAG - -
3662// 2 UART0_TxD GPS_SIG - -
3663// 3 UART0_RTS_ - - -
3664//
3665//////////////////////////////////////////////////////////
3666
3667/*----------------------------------------------------------------
3668 * p is the port number (0,1,2,3,4,5)
3669 * o is the pin offset (0-31) inside the port
3670 * n is the absolute number of a pin (0-127), regardless of the port
3671 */
3672
3673//----------------------------------------------------------------
3674// Function Pins Mode
3675
3676#define __gpio_as_func0(n) \
3677do { \
3678    unsigned int p, o; \
3679    p = (n) / 32; \
3680    o = (n) % 32; \
3681    REG_GPIO_PXFUNS(p) = (1 << o); \
3682    REG_GPIO_PXTRGC(p) = (1 << o); \
3683    REG_GPIO_PXSELC(p) = (1 << o); \
3684} while (0)
3685
3686#define __gpio_as_func1(n) \
3687do { \
3688    unsigned int p, o; \
3689    p = (n) / 32; \
3690    o = (n) % 32; \
3691    REG_GPIO_PXFUNS(p) = (1 << o); \
3692    REG_GPIO_PXTRGC(p) = (1 << o); \
3693    REG_GPIO_PXSELS(p) = (1 << o); \
3694} while (0)
3695
3696#define __gpio_as_func2(n) \
3697do { \
3698    unsigned int p, o; \
3699    p = (n) / 32; \
3700    o = (n) % 32; \
3701    REG_GPIO_PXFUNS(p) = (1 << o); \
3702    REG_GPIO_PXTRGS(p) = (1 << o); \
3703    REG_GPIO_PXSELC(p) = (1 << o); \
3704} while (0)
3705
3706#define __gpio_as_func3(n) \
3707do { \
3708    unsigned int p, o; \
3709    p = (n) / 32; \
3710    o = (n) % 32; \
3711    REG_GPIO_PXFUNS(p) = (1 << o); \
3712    REG_GPIO_PXTRGS(p) = (1 << o); \
3713    REG_GPIO_PXSELS(p) = (1 << o); \
3714} while (0)
3715
3716
3717/*
3718 * MII_TXD0- D3 MII_TXEN MII_TXCLK MII_COL
3719 * MII_RXER MII_RXDV MII_RXCLK MII_RXD0 - D3
3720 * MII_CRS MII_MDC MII_MDIO
3721 */
3722
3723#define __gpio_as_eth() \
3724do { \
3725    REG_GPIO_PXFUNS(3) = 0x0001ffff; \
3726    REG_GPIO_PXTRGC(3) = 0x0001ffff; \
3727    REG_GPIO_PXSELC(3) = 0x0001ffff; \
3728    REG_GPIO_PXPES(3) = 0x0001ffff; \
3729} while (0)
3730
3731/*
3732 * UART0_TxD, UART0_RxD
3733 */
3734#define __gpio_as_uart0() \
3735do { \
3736    REG_GPIO_PXFUNS(5) = 0x00000005; \
3737    REG_GPIO_PXTRGC(5) = 0x00000005; \
3738    REG_GPIO_PXSELC(5) = 0x00000005; \
3739    REG_GPIO_PXPES(5) = 0x00000005; \
3740} while (0)
3741
3742
3743/*
3744 * UART0_TxD, UART0_RxD, UART0_CTS, UART0_RTS
3745 */
3746#define __gpio_as_uart0_ctsrts() \
3747do { \
3748    REG_GPIO_PXFUNS(5) = 0x0000000f; \
3749    REG_GPIO_PXTRGC(5) = 0x0000000f; \
3750    REG_GPIO_PXSELC(5) = 0x0000000f; \
3751    REG_GPIO_PXPES(5) = 0x0000000f; \
3752} while (0)
3753/*
3754 * GPS_CLK GPS_MAG GPS_SIG
3755 */
3756#define __gpio_as_gps() \
3757do { \
3758    REG_GPIO_PXFUNS(5) = 0x00000007; \
3759    REG_GPIO_PXTRGC(5) = 0x00000007; \
3760    REG_GPIO_PXSELS(5) = 0x00000007; \
3761    REG_GPIO_PXPES(5) = 0x00000007; \
3762} while (0)
3763
3764/*
3765 * UART1_TxD, UART1_RxD
3766 */
3767#define __gpio_as_uart1() \
3768do { \
3769    REG_GPIO_PXFUNS(3) = 0x14000000; \
3770    REG_GPIO_PXTRGC(3) = 0x14000000; \
3771    REG_GPIO_PXSELC(3) = 0x14000000; \
3772    REG_GPIO_PXPES(3) = 0x14000000; \
3773} while (0)
3774
3775/*
3776 * UART1_TxD, UART1_RxD, UART1_CTS, UART1_RTS
3777 */
3778#define __gpio_as_uart1_ctsrts() \
3779do { \
3780    REG_GPIO_PXFUNS(3) = 0x3c000000; \
3781    REG_GPIO_PXTRGC(3) = 0x3c000000; \
3782    REG_GPIO_PXSELC(3) = 0x3c000000; \
3783    REG_GPIO_PXPES(3) = 0x3c000000; \
3784} while (0)
3785
3786
3787/*
3788 * UART2_TxD, UART2_RxD
3789 */
3790#define __gpio_as_uart2() \
3791do { \
3792    REG_GPIO_PXFUNS(2) = 0x50000000; \
3793    REG_GPIO_PXTRGC(2) = 0x50000000; \
3794    REG_GPIO_PXSELC(2) = 0x50000000; \
3795    REG_GPIO_PXPES(2) = 0x50000000; \
3796} while (0)
3797
3798/*
3799 * UART2_TxD, UART2_RxD, UART2_CTS, UART2_RTS
3800 */
3801#define __gpio_as_uart2_ctsrts() \
3802do { \
3803    REG_GPIO_PXFUNS(2) = 0xf0000000; \
3804    REG_GPIO_PXTRGC(2) = 0xf0000000; \
3805    REG_GPIO_PXSELC(2) = 0xf0000000; \
3806    REG_GPIO_PXPES(2) = 0xf0000000; \
3807} while (0)
3808
3809/*
3810 * UART3_TxD, UART3_RxD
3811 */
3812#define __gpio_as_uart3() \
3813do { \
3814    REG_GPIO_PXFUNS(4) = 0x00000028; \
3815    REG_GPIO_PXTRGC(4) = 0x00000028; \
3816    REG_GPIO_PXSELS(4) = 0x00000028; \
3817    REG_GPIO_PXPES(4) = 0x00000028; \
3818} while (0)
3819
3820/*
3821 * UART3_TxD, UART3_RxD, UART3_CTS, UART3_RTS
3822 */
3823#define __gpio_as_uart3_ctsrts() \
3824do { \
3825    REG_GPIO_PXFUNS(4) = 0x00000028; \
3826    REG_GPIO_PXTRGC(4) = 0x00000028; \
3827    REG_GPIO_PXSELS(4) = 0x00000028; \
3828    REG_GPIO_PXFUNS(4) = 0x00000300; \
3829    REG_GPIO_PXTRGC(4) = 0x00000300; \
3830    REG_GPIO_PXSELC(4) = 0x00000300; \
3831    REG_GPIO_PXPES(4) = 0x00000328; \
3832}
3833
3834/*
3835 * SD0 ~ SD7, CS1#, CLE, ALE, FRE#, FWE#, FRB#
3836 * @n: chip select number(1 ~ 6)
3837 */
3838#define __gpio_as_nand_8bit(n) \
3839do { \
3840                                    \
3841    REG_GPIO_PXFUNS(0) = 0x002c00ff; /* SD0 ~ SD7, CS1#, FRE#, FWE# */ \
3842    REG_GPIO_PXSELC(0) = 0x002c00ff; \
3843    REG_GPIO_PXPES(0) = 0x002c00ff; \
3844    REG_GPIO_PXFUNS(1) = 0x0000000c; /* CLE(SA2), ALE(SA3) */ \
3845    REG_GPIO_PXSELC(1) = 0x0000000c; \
3846    REG_GPIO_PXPES(1) = 0x0000000c; \
3847                                    \
3848    REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */ \
3849    REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1); \
3850    REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1); \
3851                                    \
3852     REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */ \
3853    REG_GPIO_PXSELC(0) = 0x00100000; \
3854    REG_GPIO_PXDIRC(0) = 0x00100000; \
3855    REG_GPIO_PXPES(0) = 0x00100000; \
3856} while (0)
3857
3858/*
3859 * SD0 ~ SD15, CS1#, CLE, ALE, FRE#, FWE#, FRB#
3860 * @n: chip select number(1 ~ 6)
3861 */
3862#define __gpio_as_nand_16bit(n) \
3863do { \
3864                                    \
3865    REG_GPIO_PXFUNS(0) = 0x002cffff; /* SD0 ~ SD15, CS1#, FRE#, FWE# */ \
3866    REG_GPIO_PXSELC(0) = 0x002cffff; \
3867    REG_GPIO_PXPES(0) = 0x002cffff; \
3868    REG_GPIO_PXFUNS(1) = 0x0000000c; /* CLE(SA2), ALE(SA3) */ \
3869    REG_GPIO_PXSELC(1) = 0x0000000c; \
3870    REG_GPIO_PXPES(1) = 0x0000000c; \
3871                                    \
3872    REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */ \
3873    REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1); \
3874    REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1); \
3875                                    \
3876     REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */ \
3877    REG_GPIO_PXSELC(0) = 0x00100000; \
3878    REG_GPIO_PXDIRC(0) = 0x00100000; \
3879    REG_GPIO_PXPES(0) = 0x00100000; \
3880} while (0)
3881
3882/*
3883 * SD0 ~ SD7, SA0 ~ SA5, CS2#, RD#, WR#, WAIT#
3884 */
3885#define __gpio_as_nor() \
3886do { \
3887    /* SD0 ~ SD7, RD#, WR#, CS2#, WAIT# */ \
3888    REG_GPIO_PXFUNS(0) = 0x084300ff; \
3889    REG_GPIO_PXTRGC(0) = 0x084300ff; \
3890    REG_GPIO_PXSELC(0) = 0x084300ff; \
3891    REG_GPIO_PXPES(0) = 0x084300ff; \
3892    /* SA0 ~ SA5 */ \
3893    REG_GPIO_PXFUNS(1) = 0x0000003f; \
3894    REG_GPIO_PXTRGC(1) = 0x0000003f; \
3895    REG_GPIO_PXSELC(1) = 0x0000003f; \
3896    REG_GPIO_PXPES(1) = 0x0000003f; \
3897} while (0)
3898
3899/*
3900 * LCD_D0~LCD_D7, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
3901 */
3902#define __gpio_as_lcd_8bit() \
3903do { \
3904    REG_GPIO_PXFUNS(2) = 0x000c03ff; \
3905    REG_GPIO_PXTRGC(2) = 0x000c03ff; \
3906    REG_GPIO_PXSELC(2) = 0x000c03ff; \
3907    REG_GPIO_PXPES(2) = 0x000c03ff; \
3908} while (0)
3909
3910/*
3911 * LCD_R3~LCD_R7, LCD_G2~LCD_G7, LCD_B3~LCD_B7,
3912 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
3913 */
3914#define __gpio_as_lcd_16bit() \
3915do { \
3916    REG_GPIO_PXFUNS(2) = 0x0f8ff3f8; \
3917    REG_GPIO_PXTRGC(2) = 0x0f8ff3f8; \
3918    REG_GPIO_PXSELC(2) = 0x0f8ff3f8; \
3919    REG_GPIO_PXPES(2) = 0x0f8ff3f8; \
3920} while (0)
3921
3922/*
3923 * LCD_R2~LCD_R7, LCD_G2~LCD_G7, LCD_B2~LCD_B7,
3924 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
3925 */
3926#define __gpio_as_lcd_18bit() \
3927do { \
3928    REG_GPIO_PXFUNS(2) = 0x0fcff3fc; \
3929    REG_GPIO_PXTRGC(2) = 0x0fcff3fc; \
3930    REG_GPIO_PXSELC(2) = 0x0fcff3fc; \
3931    REG_GPIO_PXPES(2) = 0x0fcff3fc; \
3932} while (0)
3933
3934/*
3935 * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7,
3936 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
3937 */
3938#define __gpio_as_lcd_24bit() \
3939do { \
3940    REG_GPIO_PXFUNS(2) = 0x0fffffff; \
3941    REG_GPIO_PXTRGC(2) = 0x0fffffff; \
3942    REG_GPIO_PXSELC(2) = 0x0fffffff; \
3943    REG_GPIO_PXPES(2) = 0x0fffffff; \
3944} while (0)
3945
3946/*
3947 * LCD_CLS, LCD_SPL, LCD_PS, LCD_REV
3948 */
3949#define __gpio_as_lcd_special() \
3950do { \
3951    REG_GPIO_PXFUNS(2) = 0x0fffffff; \
3952    REG_GPIO_PXTRGC(2) = 0x0fffffff; \
3953    REG_GPIO_PXSELC(2) = 0x0feffbfc; \
3954    REG_GPIO_PXSELS(2) = 0x00100403; \
3955    REG_GPIO_PXPES(2) = 0x0fffffff; \
3956} while (0)
3957
3958/*
3959 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
3960 */
3961#define __gpio_as_cim() \
3962do { \
3963    REG_GPIO_PXFUNS(1) = 0x0003ffc0; \
3964    REG_GPIO_PXTRGC(1) = 0x0003ffc0; \
3965    REG_GPIO_PXSELC(1) = 0x0003ffc0; \
3966    REG_GPIO_PXPES(1) = 0x0003ffc0; \
3967} while (0)
3968
3969/*
3970 * SDATO, SDATI, BCLK, SYNC, SCLK_RSTN(gpio sepc) or
3971 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET(aic spec)
3972 */
3973#define __gpio_as_aic() \
3974do { \
3975    REG_GPIO_PXFUNS(4) = 0x16c00000; \
3976    REG_GPIO_PXTRGC(4) = 0x02c00000; \
3977    REG_GPIO_PXTRGS(4) = 0x14000000; \
3978    REG_GPIO_PXSELC(4) = 0x14c00000; \
3979    REG_GPIO_PXSELS(4) = 0x02000000; \
3980    REG_GPIO_PXPES(4) = 0x16c00000; \
3981} while (0)
3982
3983/*
3984 * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3
3985 */
3986#define __gpio_as_msc0_4bit() \
3987do { \
3988    REG_GPIO_PXFUNS(2) = 0x38400300; \
3989    REG_GPIO_PXTRGC(2) = 0x38400300; \
3990    REG_GPIO_PXSELS(2) = 0x30400300; \
3991    REG_GPIO_PXSELC(2) = 0x08000000; \
3992    REG_GPIO_PXPES(2) = 0x38400300; \
3993} while (0)
3994
3995/*
3996 * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3
3997 */
3998#define __gpio_as_msc1_4bit() \
3999do { \
4000    REG_GPIO_PXFUNS(1) = 0xfc000000; \
4001    REG_GPIO_PXTRGC(1) = 0xfc000000; \
4002    REG_GPIO_PXSELC(1) = 0xfc000000; \
4003    REG_GPIO_PXPES(1) = 0xfc000000; \
4004} while (0)
4005
4006/* Port B
4007 * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3
4008 */
4009#define __gpio_as_msc2_4bit_1() \
4010do { \
4011    REG_GPIO_PXFUNS(1) = 0xf0300000; \
4012    REG_GPIO_PXTRGC(1) = 0xf0300000; \
4013    REG_GPIO_PXSELC(1) = 0xf0300000; \
4014    REG_GPIO_PXPES(1) = 0xf0300000; \
4015} while (0)
4016
4017#define __gpio_as_msc __gpio_as_msc0_4bit /* default as msc0 4bit */
4018#define __gpio_as_msc0 __gpio_as_msc0_4bit /* msc0 default as 4bit */
4019#define __gpio_as_msc1 __gpio_as_msc1_4bit /* msc1 only support 4bit */
4020
4021/*
4022 * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7
4023 */
4024#define __gpio_as_tssi_1() \
4025do { \
4026    REG_GPIO_PXFUNS(1) = 0x0003ffc0; \
4027    REG_GPIO_PXTRGC(1) = 0x0003ffc0; \
4028    REG_GPIO_PXSELS(1) = 0x0003ffc0; \
4029    REG_GPIO_PXPES(1) = 0x0003ffc0; \
4030} while (0)
4031
4032/*
4033 * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7
4034 */
4035#define __gpio_as_tssi_2() \
4036do { \
4037    REG_GPIO_PXFUNS(1) = 0xfff00000; \
4038    REG_GPIO_PXTRGC(1) = 0x0fc00000; \
4039    REG_GPIO_PXTRGS(1) = 0xf0300000; \
4040    REG_GPIO_PXSELC(1) = 0xfff00000; \
4041    REG_GPIO_PXPES(1) = 0xfff00000; \
4042} while (0)
4043
4044/*
4045 * SSI_CE0, SSI_CE1, SSI_GPC, SSI_CLK, SSI_DT, SSI_DR
4046 */
4047#define __gpio_as_ssi() \
4048do { \
4049    REG_GPIO_PXFUNS(0) = 0x002c0000; /* SSI0_CE0, SSI0_CLK, SSI0_DT */ \
4050    REG_GPIO_PXTRGS(0) = 0x002c0000; \
4051    REG_GPIO_PXSELC(0) = 0x002c0000; \
4052    REG_GPIO_PXPES(0) = 0x002c0000; \
4053                        \
4054    REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0_DR */ \
4055    REG_GPIO_PXTRGC(0) = 0x00100000; \
4056    REG_GPIO_PXSELS(0) = 0x00100000; \
4057    REG_GPIO_PXPES(0) = 0x00100000; \
4058} while (0)
4059
4060/*
4061 * SSI_CE0, SSI_CE2, SSI_GPC, SSI_CLK, SSI_DT, SSI1_DR
4062 */
4063#define __gpio_as_ssi_1() \
4064do { \
4065    REG_GPIO_PXFUNS(5) = 0x0000fc00; \
4066    REG_GPIO_PXTRGC(5) = 0x0000fc00; \
4067    REG_GPIO_PXSELC(5) = 0x0000fc00; \
4068    REG_GPIO_PXPES(5) = 0x0000fc00; \
4069} while (0)
4070
4071/* Port B
4072 * SSI2_CE0, SSI2_CE2, SSI2_GPC, SSI2_CLK, SSI2_DT, SSI12_DR
4073 */
4074#define __gpio_as_ssi2_1() \
4075do { \
4076    REG_GPIO_PXFUNS(5) = 0xf0300000; \
4077    REG_GPIO_PXTRGC(5) = 0xf0300000; \
4078    REG_GPIO_PXSELS(5) = 0xf0300000; \
4079    REG_GPIO_PXPES(5) = 0xf0300000; \
4080} while (0)
4081
4082/*
4083 * I2C_SCK, I2C_SDA
4084 */
4085#define __gpio_as_i2c() \
4086do { \
4087    REG_GPIO_PXFUNS(4) = 0x00003000; \
4088    REG_GPIO_PXSELC(4) = 0x00003000; \
4089    REG_GPIO_PXPES(4) = 0x00003000; \
4090} while (0)
4091
4092/*
4093 * PWM0
4094 */
4095#define __gpio_as_pwm0() \
4096do { \
4097    REG_GPIO_PXFUNS(4) = 0x00100000; \
4098    REG_GPIO_PXSELC(4) = 0x00100000; \
4099    REG_GPIO_PXPES(4) = 0x00100000; \
4100} while (0)
4101
4102/*
4103 * PWM1
4104 */
4105#define __gpio_as_pwm1() \
4106do { \
4107    REG_GPIO_PXFUNS(5) = 0x00000800; \
4108    REG_GPIO_PXSELC(5) = 0x00000800; \
4109    REG_GPIO_PXPES(5) = 0x00000800; \
4110} while (0)
4111
4112/*
4113 * PWM2
4114 */
4115#define __gpio_as_pwm2() \
4116do { \
4117    REG_GPIO_PXFUNS(4) = 0x00400000; \
4118    REG_GPIO_PXSELC(4) = 0x00400000; \
4119    REG_GPIO_PXPES(4) = 0x00400000; \
4120} while (0)
4121
4122/*
4123 * PWM3
4124 */
4125#define __gpio_as_pwm3() \
4126do { \
4127    REG_GPIO_PXFUNS(4) = 0x00800000; \
4128    REG_GPIO_PXSELC(4) = 0x00800000; \
4129    REG_GPIO_PXPES(4) = 0x00800000; \
4130} while (0)
4131
4132/*
4133 * PWM4
4134 */
4135#define __gpio_as_pwm4() \
4136do { \
4137    REG_GPIO_PXFUNS(4) = 0x01000000; \
4138    REG_GPIO_PXSELC(4) = 0x01000000; \
4139    REG_GPIO_PXPES(4) = 0x01000000; \
4140} while (0)
4141
4142/*
4143 * PWM5
4144 */
4145#define __gpio_as_pwm5() \
4146do { \
4147    REG_GPIO_PXFUNS(4) = 0x02000000; \
4148    REG_GPIO_PXSELC(4) = 0x02000000; \
4149    REG_GPIO_PXPES(4) = 0x02000000; \
4150} while (0)
4151
4152/*
4153 * n = 0 ~ 5
4154 */
4155#define __gpio_as_pwm(n) __gpio_as_pwm##n()
4156
4157
4158//-------------------------------------------
4159// GPIO or Interrupt Mode
4160
4161#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
4162
4163#define __gpio_port_as_output(p, o) \
4164do { \
4165    REG_GPIO_PXFUNC(p) = (1 << (o)); \
4166    REG_GPIO_PXSELC(p) = (1 << (o)); \
4167    REG_GPIO_PXDIRS(p) = (1 << (o)); \
4168} while (0)
4169
4170#define __gpio_port_as_input(p, o) \
4171do { \
4172    REG_GPIO_PXFUNC(p) = (1 << (o)); \
4173    REG_GPIO_PXSELC(p) = (1 << (o)); \
4174    REG_GPIO_PXDIRC(p) = (1 << (o)); \
4175} while (0)
4176
4177#define __gpio_as_output(n) \
4178do { \
4179    unsigned int p, o; \
4180    p = (n) / 32; \
4181    o = (n) % 32; \
4182    __gpio_port_as_output(p, o); \
4183} while (0)
4184
4185#define __gpio_as_input(n) \
4186do { \
4187    unsigned int p, o; \
4188    p = (n) / 32; \
4189    o = (n) % 32; \
4190    __gpio_port_as_input(p, o); \
4191} while (0)
4192
4193#define __gpio_set_pin(n) \
4194do { \
4195    unsigned int p, o; \
4196    p = (n) / 32; \
4197    o = (n) % 32; \
4198    REG_GPIO_PXDATS(p) = (1 << o); \
4199} while (0)
4200
4201#define __gpio_clear_pin(n) \
4202do { \
4203    unsigned int p, o; \
4204    p = (n) / 32; \
4205    o = (n) % 32; \
4206    REG_GPIO_PXDATC(p) = (1 << o); \
4207} while (0)
4208
4209#define __gpio_get_pin(n) \
4210({ \
4211    unsigned int p, o, v; \
4212    p = (n) / 32; \
4213    o = (n) % 32; \
4214    if (__gpio_get_port(p) & (1 << o)) \
4215        v = 1; \
4216    else \
4217        v = 0; \
4218    v; \
4219})
4220
4221#define __gpio_as_irq_high_level(n) \
4222do { \
4223    unsigned int p, o; \
4224    p = (n) / 32; \
4225    o = (n) % 32; \
4226    REG_GPIO_PXIMS(p) = (1 << o); \
4227    REG_GPIO_PXTRGC(p) = (1 << o); \
4228    REG_GPIO_PXFUNC(p) = (1 << o); \
4229    REG_GPIO_PXSELS(p) = (1 << o); \
4230    REG_GPIO_PXDIRS(p) = (1 << o); \
4231    REG_GPIO_PXFLGC(p) = (1 << o); \
4232    REG_GPIO_PXIMC(p) = (1 << o); \
4233} while (0)
4234
4235#define __gpio_as_irq_low_level(n) \
4236do { \
4237    unsigned int p, o; \
4238    p = (n) / 32; \
4239    o = (n) % 32; \
4240    REG_GPIO_PXIMS(p) = (1 << o); \
4241    REG_GPIO_PXTRGC(p) = (1 << o); \
4242    REG_GPIO_PXFUNC(p) = (1 << o); \
4243    REG_GPIO_PXSELS(p) = (1 << o); \
4244    REG_GPIO_PXDIRC(p) = (1 << o); \
4245    REG_GPIO_PXFLGC(p) = (1 << o); \
4246    REG_GPIO_PXIMC(p) = (1 << o); \
4247} while (0)
4248
4249#define __gpio_as_irq_rise_edge(n) \
4250do { \
4251    unsigned int p, o; \
4252    p = (n) / 32; \
4253    o = (n) % 32; \
4254    REG_GPIO_PXIMS(p) = (1 << o); \
4255    REG_GPIO_PXTRGS(p) = (1 << o); \
4256    REG_GPIO_PXFUNC(p) = (1 << o); \
4257    REG_GPIO_PXSELS(p) = (1 << o); \
4258    REG_GPIO_PXDIRS(p) = (1 << o); \
4259    REG_GPIO_PXFLGC(p) = (1 << o); \
4260    REG_GPIO_PXIMC(p) = (1 << o); \
4261} while (0)
4262
4263#define __gpio_as_irq_fall_edge(n) \
4264do { \
4265    unsigned int p, o; \
4266    p = (n) / 32; \
4267    o = (n) % 32; \
4268    REG_GPIO_PXIMS(p) = (1 << o); \
4269    REG_GPIO_PXTRGS(p) = (1 << o); \
4270    REG_GPIO_PXFUNC(p) = (1 << o); \
4271    REG_GPIO_PXSELS(p) = (1 << o); \
4272    REG_GPIO_PXDIRC(p) = (1 << o); \
4273    REG_GPIO_PXFLGC(p) = (1 << o); \
4274    REG_GPIO_PXIMC(p) = (1 << o); \
4275} while (0)
4276
4277#define __gpio_mask_irq(n) \
4278do { \
4279    unsigned int p, o; \
4280    p = (n) / 32; \
4281    o = (n) % 32; \
4282    REG_GPIO_PXIMS(p) = (1 << o); \
4283} while (0)
4284
4285#define __gpio_unmask_irq(n) \
4286do { \
4287    unsigned int p, o; \
4288    p = (n) / 32; \
4289    o = (n) % 32; \
4290    REG_GPIO_PXIMC(p) = (1 << o); \
4291} while (0)
4292
4293#define __gpio_ack_irq(n) \
4294do { \
4295    unsigned int p, o; \
4296    p = (n) / 32; \
4297    o = (n) % 32; \
4298    REG_GPIO_PXFLGC(p) = (1 << o); \
4299} while (0)
4300
4301#define __gpio_get_irq() \
4302({ \
4303    unsigned int p, i, tmp, v = 0; \
4304    for (p = 3; p >= 0; p--) { \
4305        tmp = REG_GPIO_PXFLG(p); \
4306        for (i = 0; i < 32; i++) \
4307            if (tmp & (1 << i)) \
4308                v = (32*p + i); \
4309    } \
4310    v; \
4311})
4312
4313#define __gpio_group_irq(n) \
4314({ \
4315    register int tmp, i; \
4316    tmp = REG_GPIO_PXFLG((n)); \
4317    for (i=31;i>=0;i--) \
4318        if (tmp & (1 << i)) \
4319            break; \
4320    i; \
4321})
4322
4323#define __gpio_enable_pull(n) \
4324do { \
4325    unsigned int p, o; \
4326    p = (n) / 32; \
4327    o = (n) % 32; \
4328    REG_GPIO_PXPEC(p) = (1 << o); \
4329} while (0)
4330
4331#define __gpio_disable_pull(n) \
4332do { \
4333    unsigned int p, o; \
4334    p = (n) / 32; \
4335    o = (n) % 32; \
4336    REG_GPIO_PXPES(p) = (1 << o); \
4337} while (0)
4338
4339
4340/***************************************************************************
4341 * CPM
4342 ***************************************************************************/
4343#define __cpm_get_pllm() \
4344    ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
4345#define __cpm_get_plln() \
4346    ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
4347#define __cpm_get_pllod() \
4348    ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
4349
4350#define __cpm_get_pll1m() \
4351    ((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1M_MASK) >> CPM_CPPCR1_PLL1M_BIT)
4352#define __cpm_get_pll1n() \
4353    ((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1N_MASK) >> CPM_CPPCR1_PLL1N_BIT)
4354#define __cpm_get_pll1od() \
4355    ((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1OD_MASK) >> CPM_CPPCR1_PLL1OD_BIT)
4356
4357#define __cpm_get_cdiv() \
4358    ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
4359#define __cpm_get_hdiv() \
4360    ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
4361#define __cpm_get_h2div() \
4362    ((REG_CPM_CPCCR & CPM_CPCCR_H2DIV_MASK) >> CPM_CPCCR_H2DIV_BIT)
4363#define __cpm_get_pdiv() \
4364    ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
4365#define __cpm_get_mdiv() \
4366    ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
4367#define __cpm_get_sdiv() \
4368    ((REG_CPM_CPCCR & CPM_CPCCR_SDIV_MASK) >> CPM_CPCCR_SDIV_BIT)
4369#define __cpm_get_i2sdiv() \
4370    ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
4371#define __cpm_get_pixdiv() \
4372    ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
4373#define __cpm_get_mscdiv(n) \
4374    ((REG_CPM_MSCCDR(n) & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
4375#define __cpm_get_ssidiv() \
4376    ((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
4377#define __cpm_get_pcmdiv() \
4378    ((REG_CPM_PCMCDR & CPM_PCMCDR_PCMCD_MASK) >> CPM_PCMCDR_PCMCD_BIT)
4379#define __cpm_get_pll1div() \
4380    ((REG_CPM_CPPCR1 & CPM_CPCCR1_P1SDIV_MASK) >> CPM_CPCCR1_P1SDIV_BIT)
4381
4382#define __cpm_set_cdiv(v) \
4383    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
4384#define __cpm_set_hdiv(v) \
4385    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
4386#define __cpm_set_pdiv(v) \
4387    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
4388#define __cpm_set_mdiv(v) \
4389    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
4390#define __cpm_set_h1div(v) \
4391    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_H1DIV_MASK) | ((v) << (CPM_CPCCR_H1DIV_BIT)))
4392#define __cpm_set_udiv(v) \
4393    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
4394#define __cpm_set_i2sdiv(v) \
4395    (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
4396#define __cpm_set_pixdiv(v) \
4397    (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
4398#define __cpm_set_mscdiv(v) \
4399    (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
4400#define __cpm_set_ssidiv(v) \
4401    (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))
4402#define __cpm_set_pcmdiv(v) \
4403    (REG_CPM_PCMCDR = (REG_CPM_PCMCDR & ~CPM_PCMCDR_PCMCD_MASK) | ((v) << (CPM_PCMCDR_PCMCD_BIT)))
4404#define __cpm_set_pll1div(v) \
4405    (REG_CPM_CPPCR1 = (REG_CPM_CPPCR1 & ~CPM_CPCCR1_P1SDIV_MASK) | ((v) << (CPM_CPCCR1_P1SDIV_BIT)))
4406
4407#define __cpm_select_i2sclk_pll1() (REG_CPM_I2SCDR |= CPM_I2SCDR_I2PCS)
4408#define __cpm_select_i2sclk_pll0() (REG_CPM_I2SCDR &= ~CPM_I2SCDR_I2PCS)
4409#define __cpm_select_otgclk_pll1() (REG_CPM_USBCDR |= CPM_USBCDR_UPCS)
4410#define __cpm_select_otgclk_pll0() (REG_CPM_USBCDR &= ~CPM_USBCDR_UPCS)
4411#define __cpm_select_lcdpclk_pll1() (REG_CPM_LPCDR |= CPM_LPCDR_LPCS)
4412#define __cpm_select_lcdpclk_pll0() (REG_CPM_LPCDR &= ~CPM_LPCDR_LPCS)
4413#define __cpm_select_uhcclk_pll1() (REG_CPM_UHCCDR |= CPM_UHCCDR_UHPCS)
4414#define __cpm_select_uhcclk_pll0() (REG_CPM_UHCCDR &= ~CPM_UHCCDR_UHPCS)
4415#define __cpm_select_gpsclk_pll1() (REG_CPM_GPSCDR |= CPM_GPSCDR_GPCS)
4416#define __cpm_select_gpsclk_pll0() (REG_CPM_GPSCDR &= ~CPM_GPSCDR_GPCS)
4417#define __cpm_select_pcmclk_pll1() (REG_CPM_PCMCDR |= CPM_PCMCDR_PCMPCS)
4418#define __cpm_select_pcmclk_pll0() (REG_CPM_PCMCDR &= ~CPM_PCMCDR_PCMPCS)
4419#define __cpm_select_gpuclk_pll1() (REG_CPM_GPUCDR |= CPM_GPUCDR_GPCS)
4420#define __cpm_select_gpuclk_pll0() (REG_CPM_GPUCDR &= ~CPM_GPUCDR_GPCS)
4421#define __cpm_select_clk_pll1() (REG_CPM_CDR |= CPM_CDR_PCS)
4422#define __cpm_select_clk_pll0() (REG_CPM_CDR &= ~CPM_CDR_PCS)
4423
4424
4425#define __cpm_select_pcmclk_pll() (REG_CPM_PCMCDR |= CPM_PCMCDR_PCMS)
4426#define __cpm_select_pcmclk_exclk() (REG_CPM_PCMCDR &= ~CPM_PCMCDR_PCMS)
4427#define __cpm_select_pixclk_ext() (REG_CPM_LPCDR |= CPM_LPCDR_LPCS)
4428#define __cpm_select_pixclk_pll() (REG_CPM_LPCDR &= ~CPM_LPCDR_LPCS)
4429#define __cpm_select_tveclk_exclk() (REG_CPM_LPCDR |= CPM_CPCCR_LSCS)
4430#define __cpm_select_tveclk_pll() (REG_CPM_LPCDR &= ~CPM_LPCDR_LSCS)
4431#define __cpm_select_pixclk_lcd() (REG_CPM_LPCDR &= ~CPM_LPCDR_LTCS)
4432#define __cpm_select_pixclk_tve() (REG_CPM_LPCDR |= CPM_LPCDR_LTCS)
4433#define __cpm_select_i2sclk_exclk() (REG_CPM_I2SCDR &= ~CPM_I2SCDR_I2CS)
4434#define __cpm_select_i2sclk_pll() (REG_CPM_I2SCDR |= CPM_I2SCDR_I2CS)
4435//#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
4436//#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
4437
4438#define __cpm_enable_cko()
4439#define __cpm_exclk_direct() (REG_CPM_CPCCR &= ~CPM_CPCCR_ECS)
4440#define __cpm_exclk_div2() (REG_CPM_CPCCR |= CPM_CPCCR_ECS)
4441#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
4442
4443#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
4444#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
4445
4446#define __cpm_pll1_enable() (REG_CPM_CPPCR1 |= CPM_CPPCR1_PLL1EN)
4447
4448#define __cpm_pll_is_off() (REG_CPM_CPPSR & CPM_CPPSR_PLLOFF)
4449#define __cpm_pll_is_on() (REG_CPM_CPPSR & CPM_CPPSR_PLLON)
4450#define __cpm_pll_bypass() (REG_CPM_CPPSR |= CPM_CPPSR_PLLBP)
4451
4452#define __cpm_get_cclk_doze_duty() \
4453    ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
4454#define __cpm_set_cclk_doze_duty(v) \
4455    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
4456
4457#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
4458#define __cpm_idle_mode() \
4459    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
4460#define __cpm_sleep_mode() \
4461    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
4462
4463#define __cpm_stop_all() \
4464    do {\
4465        (REG_CPM_CLKGR0 = 0xffffffff);\
4466        (REG_CPM_CLKGR1 = 0x3ff);\
4467    }while(0)
4468#define __cpm_stop_emc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_EMC)
4469#define __cpm_stop_ddr() (REG_CPM_CLKGR0 |= CPM_CLKGR0_DDR)
4470#define __cpm_stop_ipu() (REG_CPM_CLKGR0 |= CPM_CLKGR0_IPU)
4471#define __cpm_stop_lcd() (REG_CPM_CLKGR0 |= CPM_CLKGR0_LCD)
4472#define __cpm_stop_tve() (REG_CPM_CLKGR0 |= CPM_CLKGR0_TVE)
4473#define __cpm_stop_Cim() (REG_CPM_CLKGR0 |= CPM_CLKGR0_CIM)
4474#define __cpm_stop_mdma() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MDMA)
4475#define __cpm_stop_uhc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UHC)
4476#define __cpm_stop_mac() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MAC)
4477#define __cpm_stop_gps() (REG_CPM_CLKGR0 |= CPM_CLKGR0_GPS)
4478#define __cpm_stop_dmac() (REG_CPM_CLKGR0 |= CPM_CLKGR0_DMAC)
4479#define __cpm_stop_ssi2() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI2)
4480#define __cpm_stop_ssi1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI1)
4481#define __cpm_stop_uart3() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART3)
4482#define __cpm_stop_uart2() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART2)
4483#define __cpm_stop_uart1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART1)
4484#define __cpm_stop_uart0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART0)
4485#define __cpm_stop_sadc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SADC)
4486#define __cpm_stop_kbc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_KBC)
4487#define __cpm_stop_msc2() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC2)
4488#define __cpm_stop_msc1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC1)
4489#define __cpm_stop_owi() (REG_CPM_CLKGR0 |= CPM_CLKGR0_OWI)
4490#define __cpm_stop_tssi() (REG_CPM_CLKGR0 |= CPM_CLKGR0_TSSI)
4491#define __cpm_stop_aic() (REG_CPM_CLKGR0 |= CPM_CLKGR0_AIC)
4492#define __cpm_stop_scc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SCC)
4493#define __cpm_stop_i2c0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_I2C1)
4494#define __cpm_stop_i2c1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_I2C0)
4495#define __cpm_stop_ssi0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI0)
4496#define __cpm_stop_msc0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC0)
4497#define __cpm_stop_otg() (REG_CPM_CLKGR0 |= CPM_CLKGR0_OTG)
4498#define __cpm_stop_bch() (REG_CPM_CLKGR0 |= CPM_CLKGR0_BCH)
4499#define __cpm_stop_nemc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_NEMC)
4500#define __cpm_stop_gpu() (REG_CPM_CLKGR1 |= CPM_CLKGR0_GPU)
4501#define __cpm_stop_pcm() (REG_CPM_CLKGR1 |= CPM_CLKGR0_PCM)
4502#define __cpm_stop_ahb1() (REG_CPM_CLKGR1 |= CPM_CLKGR0_AHB1)
4503#define __cpm_stop_cabac() (REG_CPM_CLKGR1 |= CPM_CLKGR0_CABAC)
4504#define __cpm_stop_sram() (REG_CPM_CLKGR1 |= CPM_CLKGR0_SRAM)
4505#define __cpm_stop_dct() (REG_CPM_CLKGR1 |= CPM_CLKGR0_DCT)
4506#define __cpm_stop_me() (REG_CPM_CLKGR1 |= CPM_CLKGR0_ME)
4507#define __cpm_stop_dblk() (REG_CPM_CLKGR1 |= CPM_CLKGR0_DBLK)
4508#define __cpm_stop_mc() (REG_CPM_CLKGR1 |= CPM_CLKGR0_MC)
4509#define __cpm_stop_bdma() (REG_CPM_CLKGR1 |= CPM_CLKGR0_BDMA)
4510
4511#define __cpm_start_all() \
4512    do {\
4513        REG_CPM_CLKGR0 = 0x0;\
4514        REG_CPM_CLKGR1 = 0x0;\
4515    } while(0)
4516#define __cpm_start_emc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_EMC)
4517#define __cpm_start_ddr() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_DDR)
4518#define __cpm_start_ipu() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_IPU)
4519#define __cpm_start_lcd() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_LCD)
4520#define __cpm_start_tve() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_TVE)
4521#define __cpm_start_Cim() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_CIM)
4522#define __cpm_start_mdma() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MDMA)
4523#define __cpm_start_uhc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UHC)
4524#define __cpm_start_mac() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MAC)
4525#define __cpm_start_gps() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_GPS)
4526#define __cpm_start_dmac() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_DMAC)
4527#define __cpm_start_ssi2() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI2)
4528#define __cpm_start_ssi1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI1)
4529#define __cpm_start_uart3() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART3)
4530#define __cpm_start_uart2() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART2)
4531#define __cpm_start_uart1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART1)
4532#define __cpm_start_uart0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART0)
4533#define __cpm_start_sadc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SADC)
4534#define __cpm_start_kbc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_KBC)
4535#define __cpm_start_msc2() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC2)
4536#define __cpm_start_msc1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC1)
4537#define __cpm_start_owi() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_OWI)
4538#define __cpm_start_tssi() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_TSSI)
4539#define __cpm_start_aic() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_AIC)
4540#define __cpm_start_scc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SCC)
4541#define __cpm_start_i2c0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_I2C1)
4542#define __cpm_start_i2c1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_I2C0)
4543#define __cpm_start_ssi0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI0)
4544#define __cpm_start_msc0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC0)
4545#define __cpm_start_otg() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_OTG)
4546#define __cpm_start_bch() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_BCH)
4547#define __cpm_start_nemc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_NEMC)
4548#define __cpm_start_gpu() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_GPU)
4549#define __cpm_start_pcm() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_PCM)
4550#define __cpm_start_ahb1() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_AHB1)
4551#define __cpm_start_cabac() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_CABAC)
4552#define __cpm_start_sram() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_SRAM)
4553#define __cpm_start_dct() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_DCT)
4554#define __cpm_start_me() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_ME)
4555#define __cpm_start_dblk() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_DBLK)
4556#define __cpm_start_mc() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_MC)
4557#define __cpm_start_bdma() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_BDMA)
4558
4559#define __cpm_get_o1st() \
4560    ((REG_CPM_OPCR & CPM_OPCR_O1ST_MASK) >> CPM_OPCR_O1ST_BIT)
4561#define __cpm_set_o1st(v) \
4562    (REG_CPM_OPCR = (REG_CPM_OPCR & ~CPM_OPCR_O1ST_MASK) | ((v) << (CPM_OPCR_O1ST_BIT)))
4563#define __cpm_suspend_udcphy() (REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE)
4564#define __cpm_enable_osc_in_sleep() (REG_CPM_OPCR |= CPM_OPCR_OSC_ENABLE)
4565#define __cpm_select_rtcclk_rtc() (REG_CPM_OPCR |= CPM_OPCR_ERCS)
4566#define __cpm_select_rtcclk_exclk() (REG_CPM_OPCR &= ~CPM_OPCR_ERCS)
4567
4568
4569#ifdef CFG_EXTAL
4570#define JZ_EXTAL CFG_EXTAL
4571#else
4572#define JZ_EXTAL 3686400
4573#endif
4574#define JZ_EXTAL2 32768 /* RTC clock */
4575
4576/* PLL output frequency */
4577static __inline__ unsigned int __cpm_get_pllout(void)
4578{
4579    unsigned long m, n, no, pllout;
4580    unsigned long cppcr = REG_CPM_CPPCR;
4581    unsigned long od[4] = {1, 2, 4, 8};
4582    if ((cppcr & CPM_CPPCR_PLLEN) && (!(cppcr & CPM_CPPCR_PLLBP))) {
4583        m = __cpm_get_pllm() * 2;
4584        n = __cpm_get_plln();
4585        no = od[__cpm_get_pllod()];
4586        pllout = ((JZ_EXTAL) * m / (n * no));
4587    } else
4588        pllout = JZ_EXTAL;
4589    return pllout;
4590}
4591
4592/* PLL output frequency */
4593static __inline__ unsigned int __cpm_get_pll1out(void)
4594{
4595    unsigned long m, n, no, pllout;
4596    unsigned long cppcr1 = REG_CPM_CPPCR1;
4597    unsigned long od[4] = {1, 2, 4, 8};
4598    if (cppcr1 & CPM_CPPCR1_PLL1EN)
4599    {
4600        m = __cpm_get_pll1m() * 2;
4601        n = __cpm_get_pll1n();
4602        no = od[__cpm_get_pll1od()];
4603        if (cppcr1 & CPM_CPPCR1_P1SCS)
4604            pllout = ((__cpm_get_pllout()) * m / (n * no));
4605        else
4606            pllout = ((JZ_EXTAL) * m / (n * no));
4607            
4608    } else
4609        pllout = JZ_EXTAL;
4610    return pllout;
4611}
4612
4613/* PLL output frequency for MSC/I2S/LCD/USB */
4614static __inline__ unsigned int __cpm_get_pllout2(void)
4615{
4616    if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
4617        return __cpm_get_pllout();
4618    else
4619        return __cpm_get_pllout()/2;
4620}
4621
4622/* CPU core clock */
4623static __inline__ unsigned int __cpm_get_cclk(void)
4624{
4625    int div[] = {1, 2, 3, 4, 6, 8};
4626
4627    return __cpm_get_pllout() / div[__cpm_get_cdiv()];
4628}
4629
4630/* AHB system bus clock */
4631static __inline__ unsigned int __cpm_get_hclk(void)
4632{
4633    int div[] = {1, 2, 3, 4, 6, 8};
4634
4635    return __cpm_get_pllout() / div[__cpm_get_hdiv()];
4636}
4637
4638/* Memory bus clock */
4639static __inline__ unsigned int __cpm_get_mclk(void)
4640{
4641    int div[] = {1, 2, 3, 4, 6, 8};
4642
4643    return __cpm_get_pllout() / div[__cpm_get_mdiv()];
4644}
4645
4646/* APB peripheral bus clock */
4647static __inline__ unsigned int __cpm_get_pclk(void)
4648{
4649    int div[] = {1, 2, 3, 4, 6, 8};
4650
4651    return __cpm_get_pllout() / div[__cpm_get_pdiv()];
4652}
4653
4654/* AHB1 module clock */
4655static __inline__ unsigned int __cpm_get_h2clk(void)
4656{
4657    int div[] = {1, 2, 3, 4, 6, 8};
4658
4659    return __cpm_get_pllout() / div[__cpm_get_h2div()];
4660}
4661
4662/* LCD pixel clock */
4663static __inline__ unsigned int __cpm_get_pixclk(void)
4664{
4665    return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
4666}
4667
4668/* I2S clock */
4669static __inline__ unsigned int __cpm_get_i2sclk(void)
4670{
4671    if (REG_CPM_I2SCDR & CPM_I2SCDR_I2CS) {
4672        return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
4673    }
4674    else {
4675        return JZ_EXTAL;
4676    }
4677}
4678
4679/* USB clock */
4680/*
4681static __inline__ unsigned int __cpm_get_usbclk(void)
4682{
4683    if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
4684        return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
4685    }
4686    else {
4687        return JZ_EXTAL;
4688    }
4689}
4690*/
4691/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
4692static __inline__ unsigned int __cpm_get_extalclk(void)
4693{
4694    return JZ_EXTAL;
4695}
4696
4697/* RTC clock for CPM,INTC,RTC,TCU,WDT */
4698static __inline__ unsigned int __cpm_get_rtcclk(void)
4699{
4700    return JZ_EXTAL2;
4701}
4702
4703/*
4704 * Output 24MHz for SD and 16MHz for MMC.
4705 */
4706#if 1
4707static inline void __cpm_select_msc_clk(int n, int sd)
4708{
4709    unsigned int pllout2 = __cpm_get_pllout2();
4710    unsigned int div = 0;
4711
4712    if (sd) {
4713        div = pllout2 / 24000000;
4714    }
4715    else {
4716        div = pllout2 / 16000000;
4717    }
4718
4719    REG_CPM_MSCCDR = div - 1;
4720    REG_CPM_CPCCR |= CPM_CPCCR_CE;
4721}
4722#endif
4723/***************************************************************************
4724 * TCU
4725 ***************************************************************************/
4726// where 'n' is the TCU channel
4727#define __tcu_select_extalclk(n) \
4728    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
4729#define __tcu_select_rtcclk(n) \
4730    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
4731#define __tcu_select_pclk(n) \
4732    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
4733
4734#define __tcu_select_clk_div1(n) \
4735    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
4736#define __tcu_select_clk_div4(n) \
4737    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
4738#define __tcu_select_clk_div16(n) \
4739    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
4740#define __tcu_select_clk_div64(n) \
4741    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
4742#define __tcu_select_clk_div256(n) \
4743    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
4744#define __tcu_select_clk_div1024(n) \
4745    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
4746
4747#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
4748#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
4749
4750#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
4751#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
4752
4753#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
4754#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
4755
4756#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
4757#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
4758
4759#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
4760#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
4761#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
4762#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
4763#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
4764#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
4765#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
4766#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
4767#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
4768#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
4769
4770#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
4771#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
4772
4773#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
4774#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
4775
4776#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
4777#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
4778
4779#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
4780#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
4781#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
4782#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
4783
4784
4785/***************************************************************************
4786 * WDT
4787 ***************************************************************************/
4788#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
4789#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
4790#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
4791#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
4792
4793#define __wdt_select_extalclk() \
4794    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
4795#define __wdt_select_rtcclk() \
4796    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
4797#define __wdt_select_pclk() \
4798    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
4799
4800#define __wdt_select_clk_div1() \
4801    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
4802#define __wdt_select_clk_div4() \
4803    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
4804#define __wdt_select_clk_div16() \
4805    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
4806#define __wdt_select_clk_div64() \
4807    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
4808#define __wdt_select_clk_div256() \
4809    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
4810#define __wdt_select_clk_div1024() \
4811    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
4812
4813
4814/***************************************************************************
4815 * UART
4816 ***************************************************************************/
4817
4818#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
4819#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
4820
4821#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
4822#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
4823
4824#define __uart_enable_receive_irq() \
4825  ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
4826#define __uart_disable_receive_irq() \
4827  ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
4828
4829#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
4830#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
4831
4832#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
4833
4834#define __uart_set_baud(devclk, baud) \
4835  do { \
4836    REG8(UART0_LCR) |= UARTLCR_DLAB; \
4837    REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
4838    REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
4839    REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
4840  } while (0)
4841
4842#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
4843#define __uart_clear_errors() \
4844  ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
4845
4846#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
4847#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
4848#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
4849#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
4850#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
4851#define __uart_receive_char() REG8(UART0_RDR)
4852#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
4853#define __uart_enable_irda() \
4854  /* Tx high pulse as 0, Rx low pulse as 0 */ \
4855  ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
4856
4857/***************************************************************************
4858 * Mem Copy DMAC
4859 ***************************************************************************/
4860
4861/* n is the DMA channel index (0 - 3) */
4862
4863#define __mdmac_enable_module \
4864    ( REG_MDMAC_DMACR |= DMAC_MDMACR_DMAE | DMAC_MDMACR_PR_012345 )
4865#define __mdmac_disable_module \
4866    ( REG_MDMAC_DMACR &= ~DMAC_MDMACR_DMAE )
4867
4868/* p=0,1,2,3 */
4869#define __mdmac_set_priority(p) \
4870do { \
4871    REG_MDMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
4872    REG_MDMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
4873} while (0)
4874
4875#define __mdmac_test_halt_error ( REG_MDMAC_DMACR & DMAC_MDMACR_HLT )
4876#define __mdmac_test_addr_error ( REG_MDMAC_DMACR & DMAC_MDMACR_AR )
4877
4878#define __mdmac_channel_enable_clk \
4879    REG_MDMAC_DMACKE |= 1 << (n);
4880
4881#define __mdmac_enable_descriptor(n) \
4882  ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
4883#define __mdmac_disable_descriptor(n) \
4884  ( REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
4885
4886#define __mdmac_enable_channel(n) \
4887do { \
4888    REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_EN; \
4889} while (0)
4890#define __mdmac_disable_channel(n) \
4891do { \
4892    REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN; \
4893} while (0)
4894#define __mdmac_channel_enabled(n) \
4895  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_EN )
4896
4897#define __mdmac_channel_enable_irq(n) \
4898  ( REG_MDMAC_DCMD((n)) |= DMAC_DCMD_TIE )
4899#define __mdmac_channel_disable_irq(n) \
4900  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
4901
4902#define __mdmac_channel_transmit_halt_detected(n) \
4903  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
4904#define __mdmac_channel_transmit_end_detected(n) \
4905  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_TT )
4906#define __mdmac_channel_address_error_detected(n) \
4907  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
4908#define __mdmac_channel_count_terminated_detected(n) \
4909  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_CT )
4910#define __mdmac_channel_descriptor_invalid_detected(n) \
4911  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_INV )
4912
4913#define __mdmac_channel_clear_transmit_halt(n) \
4914    do { \
4915        /* clear both channel halt error and globle halt error */ \
4916        REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT; \
4917        REG_MDMAC_DMACR &= ~DMAC_DMACR_HLT; \
4918    } while (0)
4919#define __mdmac_channel_clear_transmit_end(n) \
4920  ( REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
4921#define __mdmac_channel_clear_address_error(n) \
4922    do { \
4923        REG_MDMAC_DDA(n) = 0; /* clear descriptor address register */ \
4924        REG_MDMAC_DSAR(n) = 0; /* clear source address register */ \
4925        REG_MDMAC_DTAR(n) = 0; /* clear target address register */ \
4926        /* clear both channel addr error and globle address error */ \
4927        REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_AR; \
4928        REG_MDMAC_DMACR &= ~DMAC_DMACR_AR; \
4929    } while (0)
4930#define __mdmac_channel_clear_count_terminated(n) \
4931  ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
4932#define __mdmac_channel_clear_descriptor_invalid(n) \
4933  ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
4934
4935#define __mdmac_channel_set_transfer_unit_32bit(n) \
4936do { \
4937    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
4938    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
4939} while (0)
4940
4941#define __mdmac_channel_set_transfer_unit_16bit(n) \
4942do { \
4943    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
4944    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
4945} while (0)
4946
4947#define __mdmac_channel_set_transfer_unit_8bit(n) \
4948do { \
4949    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
4950    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
4951} while (0)
4952
4953#define __mdmac_channel_set_transfer_unit_16byte(n) \
4954do { \
4955    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
4956    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
4957} while (0)
4958
4959#define __mdmac_channel_set_transfer_unit_32byte(n) \
4960do { \
4961    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
4962    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
4963} while (0)
4964
4965/* w=8,16,32 */
4966#define __mdmac_channel_set_dest_port_width(n,w) \
4967do { \
4968    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
4969    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
4970} while (0)
4971
4972/* w=8,16,32 */
4973#define __mdmac_channel_set_src_port_width(n,w) \
4974do { \
4975    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
4976    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
4977} while (0)
4978
4979/* v=0-15 */
4980#define __mdmac_channel_set_rdil(n,v) \
4981do { \
4982    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
4983    REG_MDMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
4984} while (0)
4985
4986#define __mdmac_channel_dest_addr_fixed(n) \
4987    (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DAI)
4988#define __mdmac_channel_dest_addr_increment(n) \
4989    (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DAI)
4990
4991#define __mdmac_channel_src_addr_fixed(n) \
4992    (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SAI)
4993#define __mdmac_channel_src_addr_increment(n) \
4994    (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SAI)
4995
4996#define __mdmac_channel_set_doorbell(n) \
4997    (REG_MDMAC_DMADBSR = (1 << (n)))
4998
4999#define __mdmac_channel_irq_detected(n) (REG_MDMAC_DMAIPR & (1 << (n)))
5000#define __mdmac_channel_ack_irq(n) (REG_MDMAC_DMAIPR &= ~(1 <<(n)))
5001
5002static __inline__ int __mdmac_get_irq(void)
5003{
5004    int i;
5005    for (i = 0; i < MAX_MDMA_NUM; i++)
5006        if (__mdmac_channel_irq_detected(i))
5007            return i;
5008    return -1;
5009}
5010
5011
5012
5013/***************************************************************************
5014 * DMAC
5015 ***************************************************************************/
5016
5017/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
5018
5019#define __dmac_enable_module(m) \
5020    ( REG_DMAC_DMACR(m) |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_012345 )
5021#define __dmac_disable_module(m) \
5022    ( REG_DMAC_DMACR(m) &= ~DMAC_DMACR_DMAE )
5023
5024/* p=0,1,2,3 */
5025#define __dmac_set_priority(m,p) \
5026do { \
5027    REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK; \
5028    REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT); \
5029} while (0)
5030
5031#define __dmac_test_halt_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_HLT )
5032#define __dmac_test_addr_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_AR )
5033
5034#define __dmac_enable_descriptor(n) \
5035  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
5036#define __dmac_disable_descriptor(n) \
5037  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
5038
5039#define __dmac_enable_channel(n) \
5040  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
5041#define __dmac_disable_channel(n) \
5042  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
5043#define __dmac_channel_enabled(n) \
5044  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
5045
5046#define __dmac_channel_enable_irq(n) \
5047  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
5048#define __dmac_channel_disable_irq(n) \
5049  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
5050
5051#define __dmac_channel_transmit_halt_detected(n) \
5052  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
5053#define __dmac_channel_transmit_end_detected(n) \
5054  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
5055#define __dmac_channel_address_error_detected(n) \
5056  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
5057#define __dmac_channel_count_terminated_detected(n) \
5058  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
5059#define __dmac_channel_descriptor_invalid_detected(n) \
5060  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
5061
5062#define __dmac_channel_clear_transmit_halt(n) \
5063  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
5064#define __dmac_channel_clear_transmit_end(n) \
5065  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
5066#define __dmac_channel_clear_address_error(n) \
5067  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
5068#define __dmac_channel_clear_count_terminated(n) \
5069  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
5070#define __dmac_channel_clear_descriptor_invalid(n) \
5071  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
5072
5073#define __dmac_channel_set_transfer_unit_32bit(n) \
5074do { \
5075    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5076    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
5077} while (0)
5078
5079#define __dmac_channel_set_transfer_unit_16bit(n) \
5080do { \
5081    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5082    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
5083} while (0)
5084
5085#define __dmac_channel_set_transfer_unit_8bit(n) \
5086do { \
5087    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5088    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
5089} while (0)
5090
5091#define __dmac_channel_set_transfer_unit_16byte(n) \
5092do { \
5093    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5094    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
5095} while (0)
5096
5097#define __dmac_channel_set_transfer_unit_32byte(n) \
5098do { \
5099    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5100    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
5101} while (0)
5102
5103/* w=8,16,32 */
5104#define __dmac_channel_set_dest_port_width(n,w) \
5105do { \
5106    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
5107    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
5108} while (0)
5109
5110/* w=8,16,32 */
5111#define __dmac_channel_set_src_port_width(n,w) \
5112do { \
5113    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
5114    REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
5115} while (0)
5116
5117/* v=0-15 */
5118#define __dmac_channel_set_rdil(n,v) \
5119do { \
5120    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
5121    REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
5122} while (0)
5123
5124#define __dmac_channel_dest_addr_fixed(n) \
5125  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
5126#define __dmac_channel_dest_addr_increment(n) \
5127  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
5128
5129#define __dmac_channel_src_addr_fixed(n) \
5130  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
5131#define __dmac_channel_src_addr_increment(n) \
5132  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
5133
5134#define __dmac_channel_set_doorbell(m,n) \
5135    ( REG_DMAC_DMADBSR(m) = (1 << (n)) )
5136
5137#define __dmac_channel_irq_detected(m,n) ( REG_DMAC_DMAIPR(m) & (1 << (n)) )
5138#define __dmac_channel_ack_irq(m,n) ( REG_DMAC_DMAIPR(m) &= ~(1 << (n)) )
5139
5140static __inline__ int __dmac_get_irq(void)
5141{
5142    int i;
5143    for (i = 0; i < MAX_DMA_NUM; i++)
5144        if (__dmac_channel_irq_detected(i/HALF_DMA_NUM, i-i/HALF_DMA_NUM*HALF_DMA_NUM))
5145            return i;
5146    return -1;
5147}
5148
5149
5150/***************************************************************************
5151 * AIC (AC'97 & I2S Controller)
5152 ***************************************************************************/
5153
5154#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
5155#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
5156
5157#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
5158#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
5159
5160#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
5161#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
5162#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
5163
5164#define __aic_reset() \
5165do { \
5166        REG_AIC_FR |= AIC_FR_RST; \
5167} while(0)
5168
5169
5170#define __aic_set_transmit_trigger(n) \
5171do { \
5172    REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
5173    REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
5174} while(0)
5175
5176#define __aic_set_receive_trigger(n) \
5177do { \
5178    REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
5179    REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
5180} while(0)
5181
5182#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
5183#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
5184#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
5185#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
5186#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
5187#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
5188
5189#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
5190#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
5191
5192#define __aic_enable_transmit_intr() \
5193  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
5194#define __aic_disable_transmit_intr() \
5195  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
5196#define __aic_enable_receive_intr() \
5197  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
5198#define __aic_disable_receive_intr() \
5199  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
5200
5201#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
5202#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
5203#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
5204#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
5205
5206#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
5207#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
5208#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
5209#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
5210#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
5211#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
5212
5213#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
5214#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
5215#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
5216#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
5217#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
5218#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
5219
5220#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
5221#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
5222#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
5223#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
5224#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
5225#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
5226
5227#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
5228#define __ac97_set_xs_mono() \
5229do { \
5230    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
5231    REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
5232} while(0)
5233#define __ac97_set_xs_stereo() \
5234do { \
5235    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
5236    REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
5237} while(0)
5238
5239/* In fact, only stereo is support now. */
5240#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
5241#define __ac97_set_rs_mono() \
5242do { \
5243    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
5244    REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
5245} while(0)
5246#define __ac97_set_rs_stereo() \
5247do { \
5248    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
5249    REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
5250} while(0)
5251
5252#define __ac97_warm_reset_codec() \
5253 do { \
5254    REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
5255    REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
5256    udelay(2); \
5257    REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
5258    REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
5259 } while (0)
5260
5261#define __ac97_cold_reset_codec() \
5262 do { \
5263    REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
5264    udelay(2); \
5265    REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
5266 } while (0)
5267
5268/* n=8,16,18,20 */
5269#define __ac97_set_iass(n) \
5270 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
5271#define __ac97_set_oass(n) \
5272 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
5273
5274#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
5275#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
5276
5277/* n=8,16,18,20,24 */
5278/*#define __i2s_set_sample_size(n) \
5279 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
5280
5281#define __i2s_set_oss_sample_size(n) \
5282 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
5283#define __i2s_set_iss_sample_size(n) \
5284 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
5285
5286#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
5287#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
5288
5289#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
5290#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
5291#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
5292#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
5293
5294#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
5295
5296#define __aic_get_transmit_resident() \
5297  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
5298#define __aic_get_receive_count() \
5299  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
5300
5301#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
5302#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
5303#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
5304#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
5305#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
5306#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
5307#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
5308
5309#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
5310
5311#define CODEC_READ_CMD (1 << 19)
5312#define CODEC_WRITE_CMD (0 << 19)
5313#define CODEC_REG_INDEX_BIT 12
5314#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
5315#define CODEC_REG_DATA_BIT 4
5316#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
5317
5318#define __ac97_out_rcmd_addr(reg) \
5319do { \
5320    REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
5321} while (0)
5322
5323#define __ac97_out_wcmd_addr(reg) \
5324do { \
5325    REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
5326} while (0)
5327
5328#define __ac97_out_data(value) \
5329do { \
5330    REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
5331} while (0)
5332
5333#define __ac97_in_data() \
5334 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
5335
5336#define __ac97_in_status_addr() \
5337 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
5338
5339#define __i2s_set_sample_rate(i2sclk, sync) \
5340  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
5341
5342#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
5343#define __aic_read_rfifo() ( REG_AIC_DR )
5344
5345#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
5346#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
5347
5348//
5349// Define next ops for AC97 compatible
5350//
5351
5352#define AC97_ACSR AIC_ACSR
5353
5354#define __ac97_enable() __aic_enable(); __aic_select_ac97()
5355#define __ac97_disable() __aic_disable()
5356#define __ac97_reset() __aic_reset()
5357
5358#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
5359#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
5360
5361#define __ac97_enable_record() __aic_enable_record()
5362#define __ac97_disable_record() __aic_disable_record()
5363#define __ac97_enable_replay() __aic_enable_replay()
5364#define __ac97_disable_replay() __aic_disable_replay()
5365#define __ac97_enable_loopback() __aic_enable_loopback()
5366#define __ac97_disable_loopback() __aic_disable_loopback()
5367
5368#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
5369#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
5370#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
5371#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
5372
5373#define __ac97_transmit_request() __aic_transmit_request()
5374#define __ac97_receive_request() __aic_receive_request()
5375#define __ac97_transmit_underrun() __aic_transmit_underrun()
5376#define __ac97_receive_overrun() __aic_receive_overrun()
5377
5378#define __ac97_clear_errors() __aic_clear_errors()
5379
5380#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
5381#define __ac97_get_receive_count() __aic_get_receive_count()
5382
5383#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
5384#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
5385#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
5386#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
5387
5388#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
5389#define __ac97_read_rfifo() __aic_read_rfifo()
5390
5391//
5392// Define next ops for I2S compatible
5393//
5394
5395#define I2S_ACSR AIC_I2SSR
5396
5397#define __i2s_enable() __aic_enable(); __aic_select_i2s()
5398#define __i2s_disable() __aic_disable()
5399#define __i2s_reset() __aic_reset()
5400
5401#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
5402#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
5403
5404#define __i2s_enable_record() __aic_enable_record()
5405#define __i2s_disable_record() __aic_disable_record()
5406#define __i2s_enable_replay() __aic_enable_replay()
5407#define __i2s_disable_replay() __aic_disable_replay()
5408#define __i2s_enable_loopback() __aic_enable_loopback()
5409#define __i2s_disable_loopback() __aic_disable_loopback()
5410
5411#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
5412#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
5413#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
5414#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
5415
5416#define __i2s_transmit_request() __aic_transmit_request()
5417#define __i2s_receive_request() __aic_receive_request()
5418#define __i2s_transmit_underrun() __aic_transmit_underrun()
5419#define __i2s_receive_overrun() __aic_receive_overrun()
5420
5421#define __i2s_clear_errors() __aic_clear_errors()
5422
5423#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
5424#define __i2s_get_receive_count() __aic_get_receive_count()
5425
5426#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
5427#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
5428#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
5429#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
5430
5431#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
5432#define __i2s_read_rfifo() __aic_read_rfifo()
5433
5434#define __i2s_reset_codec() \
5435 do { \
5436 } while (0)
5437
5438
5439/***************************************************************************
5440 * ICDC
5441 ***************************************************************************/
5442#define __i2s_internal_codec() __aic_internal_codec()
5443#define __i2s_external_codec() __aic_external_codec()
5444
5445/***************************************************************************
5446 * INTC
5447 ***************************************************************************/
5448#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
5449#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
5450#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
5451
5452/***************************************************************************
5453 * I2C
5454 ***************************************************************************/
5455
5456#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
5457#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
5458
5459#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
5460#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
5461#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
5462#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
5463
5464#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
5465#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
5466#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
5467
5468#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
5469#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
5470#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
5471
5472#define __i2c_set_clk(dev_clk, i2c_clk) \
5473  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
5474
5475#define __i2c_read() ( REG_I2C_DR )
5476#define __i2c_write(val) ( REG_I2C_DR = (val) )
5477
5478
5479/***************************************************************************
5480 * MSC
5481 ***************************************************************************/
5482
5483#define __msc_start_op() \
5484  ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
5485
5486#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
5487#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
5488#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
5489#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
5490#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
5491#define __msc_get_nob() ( REG_MSC_NOB )
5492#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
5493#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
5494#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
5495#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
5496
5497#define __msc_set_cmdat_bus_width1() \
5498do { \
5499    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
5500    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
5501} while(0)
5502
5503#define __msc_set_cmdat_bus_width4() \
5504do { \
5505    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
5506    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
5507} while(0)
5508
5509#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
5510#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
5511#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
5512#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
5513#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
5514#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
5515#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
5516#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
5517
5518/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
5519#define __msc_set_cmdat_res_format(r) \
5520do { \
5521    REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
5522    REG_MSC_CMDAT |= (r); \
5523} while(0)
5524
5525#define __msc_clear_cmdat() \
5526  REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
5527  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
5528  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
5529
5530#define __msc_get_imask() ( REG_MSC_IMASK )
5531#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
5532#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
5533#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
5534#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
5535#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
5536#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
5537#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
5538#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
5539#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
5540#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
5541#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
5542#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
5543
5544/* n=0,1,2,3,4,5,6,7 */
5545#define __msc_set_clkrt(n) \
5546do { \
5547    REG_MSC_CLKRT = n; \
5548} while(0)
5549
5550#define __msc_get_ireg() ( REG_MSC_IREG )
5551#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
5552#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
5553#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
5554#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
5555#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
5556#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
5557#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
5558#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
5559
5560#define __msc_get_stat() ( REG_MSC_STAT )
5561#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
5562#define __msc_stat_crc_err() \
5563  ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
5564#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
5565#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
5566#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
5567#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
5568#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
5569
5570#define __msc_rd_resfifo() ( REG_MSC_RES )
5571#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
5572#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
5573
5574#define __msc_reset() \
5575do { \
5576    REG_MSC_STRPCL = MSC_STRPCL_RESET; \
5577     while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
5578} while (0)
5579
5580#define __msc_start_clk() \
5581do { \
5582    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
5583} while (0)
5584
5585#define __msc_stop_clk() \
5586do { \
5587    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
5588} while (0)
5589
5590#define MMC_CLK 19169200
5591#define SD_CLK 24576000
5592
5593/* msc_clk should little than pclk and little than clk retrieve from card */
5594#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
5595do { \
5596    unsigned int rate, pclk, i; \
5597    pclk = dev_clk; \
5598    rate = type?SD_CLK:MMC_CLK; \
5599      if (msc_clk && msc_clk < pclk) \
5600            pclk = msc_clk; \
5601    i = 0; \
5602      while (pclk < rate) \
5603        { \
5604              i ++; \
5605              rate >>= 1; \
5606        } \
5607      lv = i; \
5608} while(0)
5609
5610/* divide rate to little than or equal to 400kHz */
5611#define __msc_calc_slow_clk_divisor(type, lv) \
5612do { \
5613    unsigned int rate, i; \
5614    rate = (type?SD_CLK:MMC_CLK)/1000/400; \
5615    i = 0; \
5616    while (rate > 0) \
5617        { \
5618              rate >>= 1; \
5619              i ++; \
5620        } \
5621      lv = i; \
5622} while(0)
5623
5624
5625/***************************************************************************
5626 * SSI (Synchronous Serial Interface)
5627 ***************************************************************************/
5628/* n = 0, 1 (SSI0, SSI1) */
5629#define __ssi_enable(n) ( REG_SSI_CR0(n) |= SSI_CR0_SSIE )
5630#define __ssi_disable(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_SSIE )
5631#define __ssi_select_ce(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_FSEL )
5632
5633#define __ssi_normal_mode(n) ( REG_SSI_ITR(n) &= ~SSI_ITR_IVLTM_MASK )
5634
5635#define __ssi_select_ce2(n) \
5636do { \
5637    REG_SSI_CR0(n) |= SSI_CR0_FSEL; \
5638    REG_SSI_CR1(n) &= ~SSI_CR1_MULTS; \
5639} while (0)
5640
5641#define __ssi_select_gpc(n) \
5642do { \
5643    REG_SSI_CR0(n) &= ~SSI_CR0_FSEL; \
5644    REG_SSI_CR1(n) |= SSI_CR1_MULTS; \
5645} while (0)
5646
5647#define __ssi_underrun_auto_clear(n) \
5648do { \
5649    REG_SSI_CR0(n) |= SSI_CR0_EACLRUN; \
5650} while (0)
5651
5652#define __ssi_underrun_clear_manually(n) \
5653do { \
5654    REG_SSI_CR0(n) &= ~SSI_CR0_EACLRUN; \
5655} while (0)
5656
5657#define __ssi_enable_tx_intr(n) \
5658    ( REG_SSI_CR0(n) |= SSI_CR0_TIE | SSI_CR0_TEIE )
5659
5660#define __ssi_disable_tx_intr(n) \
5661    ( REG_SSI_CR0(n) &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
5662
5663#define __ssi_enable_rx_intr(n) \
5664    ( REG_SSI_CR0(n) |= SSI_CR0_RIE | SSI_CR0_REIE )
5665
5666#define __ssi_disable_rx_intr(n) \
5667    ( REG_SSI_CR0(n) &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
5668
5669#define __ssi_enable_txfifo_half_empty_intr(n) \
5670    ( REG_SSI_CR0(n) |= SSI_CR0_TIE )
5671#define __ssi_disable_txfifo_half_empty_intr(n) \
5672    ( REG_SSI_CR0(n) &= ~SSI_CR0_TIE )
5673#define __ssi_enable_tx_error_intr(n) \
5674    ( REG_SSI_CR0(n) |= SSI_CR0_TEIE )
5675#define __ssi_disable_tx_error_intr(n) \
5676    ( REG_SSI_CR0(n) &= ~SSI_CR0_TEIE )
5677#define __ssi_enable_rxfifo_half_full_intr(n) \
5678    ( REG_SSI_CR0(n) |= SSI_CR0_RIE )
5679#define __ssi_disable_rxfifo_half_full_intr(n) \
5680    ( REG_SSI_CR0(n) &= ~SSI_CR0_RIE )
5681#define __ssi_enable_rx_error_intr(n) \
5682    ( REG_SSI_CR0(n) |= SSI_CR0_REIE )
5683#define __ssi_disable_rx_error_intr(n) \
5684    ( REG_SSI_CR0(n) &= ~SSI_CR0_REIE )
5685
5686#define __ssi_enable_loopback(n) ( REG_SSI_CR0(n) |= SSI_CR0_LOOP )
5687#define __ssi_disable_loopback(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_LOOP )
5688
5689#define __ssi_enable_receive(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_DISREV )
5690#define __ssi_disable_receive(n) ( REG_SSI_CR0(n) |= SSI_CR0_DISREV )
5691
5692#define __ssi_finish_receive(n) \
5693    ( REG_SSI_CR0(n) |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
5694
5695#define __ssi_disable_recvfinish(n) \
5696    ( REG_SSI_CR0(n) &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
5697
5698#define __ssi_flush_txfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH )
5699#define __ssi_flush_rxfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_RFLUSH )
5700
5701#define __ssi_flush_fifo(n) \
5702    ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
5703
5704#define __ssi_finish_transmit(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_UNFIN )
5705#define __ssi_wait_transmit(n) ( REG_SSI_CR1(n) |= SSI_CR1_UNFIN )
5706#define __ssi_use_busy_wait_mode(n) __ssi_wait_transmit(n)
5707#define __ssi_unset_busy_wait_mode(n) __ssi_finish_transmit(n)
5708
5709#define __ssi_spi_format(n) \
5710    do { \
5711        REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \
5712        REG_SSI_CR1(n) |= SSI_CR1_FMAT_SPI; \
5713        REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
5714        REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
5715    } while (0)
5716
5717/* TI's SSP format, must clear SSI_CR1.UNFIN */
5718#define __ssi_ssp_format(n) \
5719    do { \
5720        REG_SSI_CR1(n) &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
5721        REG_SSI_CR1(n) |= SSI_CR1_FMAT_SSP; \
5722    } while (0)
5723
5724/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
5725#define __ssi_microwire_format(n) \
5726    do { \
5727        REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \
5728        REG_SSI_CR1(n) |= SSI_CR1_FMAT_MW1; \
5729        REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
5730        REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
5731        REG_SSI_CR0(n) &= ~SSI_CR0_RFINE; \
5732    } while (0)
5733
5734/* CE# level (FRMHL), CE# in interval time (ITFRM),
5735   clock phase and polarity (PHA POL),
5736   interval time (SSIITR), interval characters/frame (SSIICR) */
5737
5738/* frmhl,endian,mcom,flen,pha,pol MASK */
5739#define SSICR1_MISC_MASK \
5740    ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
5741      | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )
5742
5743#define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol) \
5744    do { \
5745        REG_SSI_CR1(n) &= ~SSICR1_MISC_MASK; \
5746        REG_SSI_CR1(n) |= ((frmhl) << 30) | ((endian) << 25) | \
5747            (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
5748            ((pha) << 1) | (pol); \
5749    } while(0)
5750
5751/* Transfer with MSB or LSB first */
5752#define __ssi_set_msb(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_LFST )
5753#define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST )
5754
5755#define __ssi_set_frame_length(n, m) \
5756    REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4)
5757
5758/* m = 1 - 16 */
5759#define __ssi_set_microwire_command_length(n,m) \
5760    ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##m##BIT) )
5761
5762/* Set the clock phase for SPI */
5763#define __ssi_set_spi_clock_phase(n, m) \
5764    ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_PHA) | (((m)&0x1)<< 1)))
5765
5766/* Set the clock polarity for SPI */
5767#define __ssi_set_spi_clock_polarity(n, p) \
5768    ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_POL) | ((p)&0x1)) )
5769
5770/* SSI tx trigger, m = i x 8 */
5771#define __ssi_set_tx_trigger(n, m) \
5772    do { \
5773        REG_SSI_CR1(n) &= ~SSI_CR1_TTRG_MASK; \
5774        REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_TTRG_BIT; \
5775    } while (0)
5776
5777/* SSI rx trigger, m = i x 8 */
5778#define __ssi_set_rx_trigger(n, m) \
5779    do { \
5780        REG_SSI_CR1(n) &= ~SSI_CR1_RTRG_MASK; \
5781        REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_RTRG_BIT; \
5782    } while (0)
5783
5784#define __ssi_get_txfifo_count(n) \
5785    ( (REG_SSI_SR(n) & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
5786
5787#define __ssi_get_rxfifo_count(n) \
5788    ( (REG_SSI_SR(n) & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
5789
5790#define __ssi_transfer_end(n) ( REG_SSI_SR(n) & SSI_SR_END )
5791#define __ssi_is_busy(n) ( REG_SSI_SR(n) & SSI_SR_BUSY )
5792
5793#define __ssi_txfifo_full(n) ( REG_SSI_SR(n) & SSI_SR_TFF )
5794#define __ssi_rxfifo_empty(n) ( REG_SSI_SR(n) & SSI_SR_RFE )
5795#define __ssi_rxfifo_half_full(n) ( REG_SSI_SR(n) & SSI_SR_RFHF )
5796#define __ssi_txfifo_half_empty(n) ( REG_SSI_SR(n) & SSI_SR_TFHE )
5797#define __ssi_underrun(n) ( REG_SSI_SR(n) & SSI_SR_UNDR )
5798#define __ssi_overrun(n) ( REG_SSI_SR(n) & SSI_SR_OVER )
5799#define __ssi_clear_underrun(n) ( REG_SSI_SR(n) = ~SSI_SR_UNDR )
5800#define __ssi_clear_overrun(n) ( REG_SSI_SR(n) = ~SSI_SR_OVER )
5801#define __ssi_clear_errors(n) ( REG_SSI_SR(n) &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
5802
5803#define __ssi_set_clk(n, dev_clk, ssi_clk) \
5804    ( REG_SSI_GR(n) = (dev_clk) / (2*(ssi_clk)) - 1 )
5805
5806#define __ssi_receive_data(n) REG_SSI_DR(n)
5807#define __ssi_transmit_data(n, v) (REG_SSI_DR(n) = (v))
5808
5809
5810/***************************************************************************
5811 * CIM
5812 ***************************************************************************/
5813
5814#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
5815#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
5816
5817#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
5818#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
5819
5820#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
5821#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
5822
5823#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
5824#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
5825
5826#define __cim_sample_data_at_pclk_falling_edge() \
5827  ( REG_CIM_CFG |= CIM_CFG_PCP )
5828#define __cim_sample_data_at_pclk_rising_edge() \
5829  ( REG_CIM_CFG &= ~CIM_CFG_PCP )
5830
5831#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
5832#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
5833
5834#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
5835#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
5836
5837/* n=0-7 */
5838#define __cim_set_data_packing_mode(n) \
5839do { \
5840    REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
5841    REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
5842} while (0)
5843
5844#define __cim_enable_ccir656_progressive_mode() \
5845do { \
5846    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
5847    REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
5848} while (0)
5849
5850#define __cim_enable_ccir656_interlace_mode() \
5851do { \
5852    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
5853    REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
5854} while (0)
5855
5856#define __cim_enable_gated_clock_mode() \
5857do { \
5858    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
5859    REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
5860} while (0)
5861
5862#define __cim_enable_nongated_clock_mode() \
5863do { \
5864    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
5865    REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
5866} while (0)
5867
5868/* sclk:system bus clock
5869 * mclk: CIM master clock
5870 */
5871#define __cim_set_master_clk(sclk, mclk) \
5872do { \
5873    REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
5874    REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
5875} while (0)
5876
5877#define __cim_enable_sof_intr() \
5878  ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
5879#define __cim_disable_sof_intr() \
5880  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
5881
5882#define __cim_enable_eof_intr() \
5883  ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
5884#define __cim_disable_eof_intr() \
5885  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
5886
5887#define __cim_enable_stop_intr() \
5888  ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
5889#define __cim_disable_stop_intr() \
5890  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
5891
5892#define __cim_enable_trig_intr() \
5893  ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
5894#define __cim_disable_trig_intr() \
5895  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
5896
5897#define __cim_enable_rxfifo_overflow_intr() \
5898  ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
5899#define __cim_disable_rxfifo_overflow_intr() \
5900  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
5901
5902/* n=1-16 */
5903#define __cim_set_frame_rate(n) \
5904do { \
5905    REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
5906    REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
5907} while (0)
5908
5909#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
5910#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
5911
5912#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
5913#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
5914
5915/* n=4,8,12,16,20,24,28,32 */
5916#define __cim_set_rxfifo_trigger(n) \
5917do { \
5918    REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
5919    REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
5920} while (0)
5921
5922#define __cim_clear_state() ( REG_CIM_STATE = 0 )
5923
5924#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
5925#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
5926#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
5927#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
5928#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
5929#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
5930#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
5931#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
5932
5933#define __cim_get_iid() ( REG_CIM_IID )
5934#define __cim_get_image_data() ( REG_CIM_RXFIFO )
5935#define __cim_get_dam_cmd() ( REG_CIM_CMD )
5936
5937#define __cim_set_da(a) ( REG_CIM_DA = (a) )
5938
5939/***************************************************************************
5940 * LCD
5941 ***************************************************************************/
5942#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
5943#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
5944
5945#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
5946#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
5947
5948#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
5949#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
5950
5951/* n=1,2,4,8,16 */
5952#define __lcd_set_bpp(n) \
5953  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
5954
5955/* n=4,8,16 */
5956#define __lcd_set_burst_length(n) \
5957do { \
5958    REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
5959    REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
5960} while (0)
5961
5962#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
5963#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
5964
5965#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
5966#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
5967
5968/* n=2,4,16 */
5969#define __lcd_set_stn_frc(n) \
5970do { \
5971    REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
5972    REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
5973} while (0)
5974
5975
5976#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
5977#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
5978
5979#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
5980#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
5981
5982#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
5983#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
5984
5985#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
5986#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
5987
5988#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
5989#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
5990
5991#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
5992#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
5993
5994#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
5995#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
5996
5997#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
5998#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
5999
6000#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
6001#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
6002
6003
6004/* LCD status register indication */
6005
6006#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
6007#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
6008#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
6009#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
6010#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
6011#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
6012#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
6013
6014#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
6015#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
6016#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
6017
6018#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
6019#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
6020
6021/* n=1,2,4,8 for single mono-STN
6022 * n=4,8 for dual mono-STN
6023 */
6024#define __lcd_set_panel_datawidth(n) \
6025do { \
6026    REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
6027    REG_LCD_CFG |= LCD_CFG_PDW_n##; \
6028} while (0)
6029
6030/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
6031#define __lcd_set_panel_mode(m) \
6032do { \
6033    REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
6034    REG_LCD_CFG |= (m); \
6035} while(0)
6036
6037/* n = 0-255 */
6038#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
6039#define __lcd_set_ac_bias(n) \
6040do { \
6041    REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
6042    REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
6043} while(0)
6044
6045#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
6046#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
6047
6048#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
6049#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
6050
6051#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
6052#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
6053
6054#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
6055#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
6056
6057#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
6058#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
6059
6060#define __lcd_vsync_get_vps() \
6061  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
6062
6063#define __lcd_vsync_get_vpe() \
6064  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
6065#define __lcd_vsync_set_vpe(n) \
6066do { \
6067    REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
6068    REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
6069} while (0)
6070
6071#define __lcd_hsync_get_hps() \
6072  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
6073#define __lcd_hsync_set_hps(n) \
6074do { \
6075    REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
6076    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
6077} while (0)
6078
6079#define __lcd_hsync_get_hpe() \
6080  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
6081#define __lcd_hsync_set_hpe(n) \
6082do { \
6083    REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
6084    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
6085} while (0)
6086
6087#define __lcd_vat_get_ht() \
6088  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
6089#define __lcd_vat_set_ht(n) \
6090do { \
6091    REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
6092    REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
6093} while (0)
6094
6095#define __lcd_vat_get_vt() \
6096  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
6097#define __lcd_vat_set_vt(n) \
6098do { \
6099    REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
6100    REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
6101} while (0)
6102
6103#define __lcd_dah_get_hds() \
6104  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
6105#define __lcd_dah_set_hds(n) \
6106do { \
6107    REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
6108    REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
6109} while (0)
6110
6111#define __lcd_dah_get_hde() \
6112  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
6113#define __lcd_dah_set_hde(n) \
6114do { \
6115    REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
6116    REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
6117} while (0)
6118
6119#define __lcd_dav_get_vds() \
6120  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
6121#define __lcd_dav_set_vds(n) \
6122do { \
6123    REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
6124    REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
6125} while (0)
6126
6127#define __lcd_dav_get_vde() \
6128  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
6129#define __lcd_dav_set_vde(n) \
6130do { \
6131    REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
6132    REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
6133} while (0)
6134
6135#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
6136#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
6137#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
6138#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
6139
6140#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
6141#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
6142#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
6143#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
6144
6145#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
6146#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
6147
6148#define __lcd_cmd0_get_len() \
6149  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
6150#define __lcd_cmd1_get_len() \
6151  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
6152
6153/***************************************************************************
6154 * RTC ops
6155 ***************************************************************************/
6156
6157#define __rtc_write_ready() (REG_RTC_RCR & RTC_RCR_WRDY)
6158#define __rtc_write_enabled() (REG_RTC_WENR & RTC_WENR_WEN)
6159#define __rtc_write_enable() (REG_RTC_WENR |= (0xA55A << RTC_WENR_WENPAT_BIT))
6160#define __rtc_write_disable() (REG_RTC_WENR &= ~RTC_WENR_WENPAT_MASK)
6161
6162#define __rtc_enabled() \
6163do{ \
6164      while(!__rtc_write_ready()); \
6165      REG_RTC_RCR |= RTC_RCR_RTCE ; \
6166}while(0) \
6167
6168#define __rtc_disabled() \
6169do{ \
6170      while(!__rtc_write_ready()); \
6171      REG_RTC_RCR &= ~RTC_RCR_RTCE; \
6172}while(0)
6173#define __rtc_enable_alarm() \
6174do{ \
6175      while(!__rtc_write_ready()); \
6176      REG_RTC_RCR |= RTC_RCR_AE; \
6177}while(0)
6178
6179#define __rtc_disable_alarm() \
6180do{ \
6181      while(!__rtc_write_ready()); \
6182      REG_RTC_RCR &= ~RTC_RCR_AE; \
6183}while(0)
6184
6185#define __rtc_enable_alarm_irq() \
6186do{ \
6187      while(!__rtc_write_ready()); \
6188      REG_RTC_RCR |= RTC_RCR_AIE; \
6189}while(0)
6190
6191#define __rtc_disable_alarm_irq() \
6192do{ \
6193      while(!__rtc_write_ready()); \
6194      REG_RTC_RCR &= ~RTC_RCR_AIE; \
6195}while(0)
6196#define __rtc_enable_Hz_irq() \
6197do{ \
6198      while(!__rtc_write_ready()); \
6199      REG_RTC_RCR |= RTC_RCR_HZIE; \
6200}while(0)
6201
6202#define __rtc_disable_Hz_irq() \
6203do{ \
6204      while(!__rtc_write_ready()); \
6205      REG_RTC_RCR &= ~RTC_RCR_HZIE; \
6206}while(0)
6207#define __rtc_get_1Hz_flag() \
6208do{ \
6209      while(!__rtc_write_ready()); \
6210      ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
6211}while(0)
6212#define __rtc_clear_1Hz_flag() \
6213do{ \
6214      while(!__rtc_write_ready()); \
6215      REG_RTC_RCR &= ~RTC_RCR_HZ; \
6216}while(0)
6217#define __rtc_get_alarm_flag() \
6218do{ \
6219       while(!__rtc_write_ready()); \
6220      ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \
6221while(0)
6222#define __rtc_clear_alarm_flag() \
6223do{ \
6224      while(!__rtc_write_ready()); \
6225      REG_RTC_RCR &= ~RTC_RCR_AF; \
6226}while(0)
6227#define __rtc_get_second() \
6228do{ \
6229       while(!__rtc_write_ready());\
6230       REG_RTC_RSR; \
6231}while(0)
6232 
6233#define __rtc_set_second(v) \
6234do{ \
6235      while(!__rtc_write_ready()); \
6236      REG_RTC_RSR = v; \
6237}while(0)
6238
6239#define __rtc_get_alarm_second() \
6240do{ \
6241      while(!__rtc_write_ready()); \
6242      REG_RTC_RSAR; \
6243}while(0)
6244
6245      
6246#define __rtc_set_alarm_second(v) \
6247do{ \
6248      while(!__rtc_write_ready()); \
6249      REG_RTC_RSAR = v; \
6250}while(0)
6251
6252#define __rtc_RGR_is_locked() \
6253do{ \
6254      while(!__rtc_write_ready()); \
6255      REG_RTC_RGR >> RTC_RGR_LOCK; \
6256}while(0)
6257#define __rtc_lock_RGR() \
6258do{ \
6259      while(!__rtc_write_ready()); \
6260      REG_RTC_RGR |= RTC_RGR_LOCK; \
6261}while(0)
6262
6263#define __rtc_unlock_RGR() \
6264do{ \
6265      while(!__rtc_write_ready()); \
6266      REG_RTC_RGR &= ~RTC_RGR_LOCK; \
6267}while(0)
6268
6269#define __rtc_get_adjc_val() \
6270do{ \
6271      while(!__rtc_write_ready()); \
6272      ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
6273}while(0)
6274#define __rtc_set_adjc_val(v) \
6275do{ \
6276      while(!__rtc_write_ready()); \
6277      ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \
6278}while(0)
6279
6280#define __rtc_get_nc1Hz_val() \
6281      while(!__rtc_write_ready()); \
6282      ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
6283      
6284#define __rtc_set_nc1Hz_val(v) \
6285do{ \
6286      while(!__rtc_write_ready()); \
6287      ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \
6288}while(0)
6289#define __rtc_power_down() \
6290do{ \
6291      while(!__rtc_write_ready()); \
6292      REG_RTC_HCR |= RTC_HCR_PD; \
6293}while(0)
6294
6295#define __rtc_get_hwfcr_val() \
6296do{ \
6297      while(!__rtc_write_ready()); \
6298      REG_RTC_HWFCR & RTC_HWFCR_MASK; \
6299}while(0)
6300#define __rtc_set_hwfcr_val(v) \
6301do{ \
6302      while(!__rtc_write_ready()); \
6303      REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \
6304}while(0)
6305
6306#define __rtc_get_hrcr_val() \
6307do{ \
6308      while(!__rtc_write_ready()); \
6309      ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
6310}while(0)
6311#define __rtc_set_hrcr_val(v) \
6312do{ \
6313      while(!__rtc_write_ready()); \
6314      ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \
6315}while(0)
6316
6317#define __rtc_enable_alarm_wakeup() \
6318do{ \
6319      while(!__rtc_write_ready()); \
6320      ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \
6321}while(0)
6322
6323#define __rtc_disable_alarm_wakeup() \
6324do{ \
6325      while(!__rtc_write_ready()); \
6326      ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \
6327}while(0)
6328
6329#define __rtc_status_hib_reset_occur() \
6330do{ \
6331      while(!__rtc_write_ready()); \
6332    ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \
6333}while(0)
6334#define __rtc_status_ppr_reset_occur() \
6335do{ \
6336      while(!__rtc_write_ready()); \
6337   ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \
6338}while(0)
6339#define __rtc_status_wakeup_pin_waken_up() \
6340do{ \
6341      while(!__rtc_write_ready()); \
6342   ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
6343}while(0)
6344#define __rtc_status_alarm_waken_up() \
6345do{ \
6346      while(!__rtc_write_ready()); \
6347  ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
6348}while(0)
6349#define __rtc_clear_hib_stat_all() \
6350do{ \
6351      while(!__rtc_write_ready()); \
6352      ( REG_RTC_HWRSR = 0 ); \
6353}while(0)
6354
6355#define __rtc_get_scratch_pattern() \
6356      while(!__rtc_write_ready()); \
6357          (REG_RTC_HSPR)
6358#define __rtc_set_scratch_pattern(n) \
6359do{ \
6360      while(!__rtc_write_ready()); \
6361      (REG_RTC_HSPR = n ); \
6362}while(0)
6363
6364/*************************************************************************
6365 * BCH
6366 *************************************************************************/
6367#define __ecc_encoding_4bit() \
6368do { \
6369    REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6370    REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6371} while(0)
6372#define __ecc_decoding_4bit() \
6373do { \
6374    REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6375    REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6376} while(0)
6377#define __ecc_encoding_8bit() \
6378do { \
6379    REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6380    REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6381} while(0)
6382#define __ecc_decoding_8bit() \
6383do { \
6384    REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6385    REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6386} while(0)
6387#define __ecc_encoding_12bit() \
6388do { \
6389    REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6390    REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6391} while(0)
6392#define __ecc_decoding_12bit() \
6393do { \
6394    REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6395    REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6396} while(0)
6397#define __ecc_encoding_16bit() \
6398do { \
6399    REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6400    REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6401} while(0)
6402#define __ecc_decoding_16bit() \
6403do { \
6404    REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6405    REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6406} while(0)
6407#define __ecc_encoding_20bit() \
6408do { \
6409    REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6410    REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6411} while(0)
6412#define __ecc_decoding_20bit() \
6413do { \
6414    REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6415    REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6416} while(0)
6417#define __ecc_encoding_24bit() \
6418do { \
6419    REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6420    REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6421} while(0)
6422#define __ecc_decoding_24bit() \
6423do { \
6424    REG_BCH_CRS = BCH_CR_BSEL_24