Root/xbboot/target-stage1/board-jz4740.c

1//
2// Authors: Xiangfu Liu <xiangfu@sharism.cc>
3//
4// This program is free software; you can redistribute it and/or
5// modify it under the terms of the GNU General Public License
6// as published by the Free Software Foundation; either version
7// 3 of the License, or (at your option) any later version.
8//
9
10#include "jz4740.h"
11
12void gpio_init_4740()
13{
14    __gpio_as_nand();
15    __gpio_as_sdram_32bit();
16        /* enable the TP4, TP5 as UART0 */
17        REG_GPIO_PXSELS(2) = 0x80000000;
18    __gpio_as_uart0();
19    __gpio_as_lcd_18bit();
20    __gpio_as_msc();
21
22#define GPIO_LCD_CS (2 * 32 + 21)
23#define GPIO_KEYOUT_BASE (2 * 32 + 10)
24#define GPIO_KEYIN_BASE (3 * 32 + 18)
25
26    unsigned int i;
27    for (i = 0; i < 7; i++){
28        __gpio_as_input(GPIO_KEYIN_BASE + i);
29        __gpio_enable_pull(GPIO_KEYIN_BASE + i);
30    }
31
32    for (i = 0; i < 8; i++) {
33        __gpio_as_output(GPIO_KEYOUT_BASE + i);
34        __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
35    }
36
37    __gpio_as_output(GPIO_LCD_CS);
38    __gpio_clear_pin(GPIO_LCD_CS);
39}
40
41void pll_init_4740()
42{
43    register unsigned int cfcr, plcr1;
44    int n2FR[33] = {
45        0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
46        7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
47        9
48    };
49    /* int div[5] = {1, 4, 4, 4, 4}; */ /* divisors of I:S:P:L:M */
50    int nf, pllout2;
51
52    cfcr = CPM_CPCCR_CLKOEN |
53        (n2FR[1] << CPM_CPCCR_CDIV_BIT) |
54        (n2FR[ARG_PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
55        (n2FR[ARG_PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
56        (n2FR[ARG_PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
57        (n2FR[ARG_PHM_DIV] << CPM_CPCCR_LDIV_BIT);
58
59    pllout2 = (cfcr & CPM_CPCCR_PCS) ? ARG_CPU_SPEED : (ARG_CPU_SPEED / 2);
60
61    /* Init UHC clock */
62    REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
63
64    nf = ARG_CPU_SPEED * 2 / ARG_EXTAL;
65    plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
66        (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
67        (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
68        (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
69        CPM_CPPCR_PLLEN; /* enable PLL */
70
71    /* init PLL */
72    REG_CPM_CPCCR = cfcr;
73    REG_CPM_CPPCR = plcr1;
74}
75
76static void serial_setbaud()
77{
78    volatile u8* uart_lcr = (volatile u8*)(UART_BASE + OFF_LCR);
79    volatile u8* uart_dlhr = (volatile u8*)(UART_BASE + OFF_DLHR);
80    volatile u8* uart_dllr = (volatile u8*)(UART_BASE + OFF_DLLR);
81    u32 baud_div, tmp;
82
83    baud_div = ARG_EXTAL / 16 / ARG_UART_BAUD;
84    tmp = *uart_lcr;
85    tmp |= UART_LCR_DLAB;
86    *uart_lcr = tmp;
87
88    *uart_dlhr = (baud_div >> 8) & 0xff;
89    *uart_dllr = baud_div & 0xff;
90
91    tmp &= ~UART_LCR_DLAB;
92    *uart_lcr = tmp;
93}
94
95void serial_init_4740(int uart)
96{
97    UART_BASE = UART0_BASE + uart * UART_OFF;
98
99    volatile u8* uart_fcr = (volatile u8*)(UART_BASE + OFF_FCR);
100    volatile u8* uart_lcr = (volatile u8*)(UART_BASE + OFF_LCR);
101    volatile u8* uart_ier = (volatile u8*)(UART_BASE + OFF_IER);
102    volatile u8* uart_sircr = (volatile u8*)(UART_BASE + OFF_SIRCR);
103
104    /* Disable port interrupts while changing hardware */
105    *uart_ier = 0;
106
107    /* Disable UART unit function */
108    *uart_fcr = ~UART_FCR_UUE;
109
110    /* Set both receiver and transmitter in UART mode (not SIR) */
111    *uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
112
113    /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
114    *uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
115
116    /* Set baud rate */
117    serial_setbaud();
118
119    /* Enable UART unit, enable and clear FIFO */
120    *uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
121}
122
123#define SDRAM_CASL 3 /* CAS latency: 2 or 3 */
124// SDRAM Timings, unit: ns
125#define SDRAM_TRAS 45 /* RAS# Active Time */
126#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
127#define SDRAM_TPC 20 /* RAS# Precharge Time */
128#define SDRAM_TRWL 7 /* Write Latency Time */
129#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
130
131void sdram_init_4740()
132{
133    register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
134
135    unsigned int cas_latency_sdmr[2] = {
136        EMC_SDMR_CAS_2,
137        EMC_SDMR_CAS_3,
138    };
139    unsigned int cas_latency_dmcr[2] = {
140        1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
141        2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
142    };
143
144    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
145
146    if (ARG_BUS_WIDTH_16 == 0xff)
147        return;
148    else
149        ARG_BUS_WIDTH_16 = 1;
150
151    cpu_clk = ARG_CPU_SPEED;
152    mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
153
154    REG_EMC_BCR = 0; /* Disable bus release */
155    REG_EMC_RTCSR = 0; /* Disable clock for counting */
156
157    /* Fault DMCR value for mode register setting*/
158#define SDRAM_ROW0 11
159#define SDRAM_COL0 8
160#define SDRAM_BANK40 0
161#define SDRAM_BW16 1
162    dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
163        ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
164        (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
165        (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
166        EMC_DMCR_EPIN |
167        cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
168
169    /* Basic DMCR value */
170    dmcr = ((ARG_ROW_ADDR-11)<<EMC_DMCR_RA_BIT) |
171        ((ARG_COL_ADDR-8)<<EMC_DMCR_CA_BIT) |
172        (ARG_BANK_ADDR_2BIT<<EMC_DMCR_BA_BIT) |
173        (ARG_BUS_WIDTH_16<<EMC_DMCR_BW_BIT) |
174        EMC_DMCR_EPIN |
175        cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
176
177    /* SDRAM timimg */
178    ns = 1000000000 / mem_clk;
179    tmp = SDRAM_TRAS/ns;
180    if (tmp < 4) tmp = 4;
181    if (tmp > 11) tmp = 11;
182    dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
183    tmp = SDRAM_RCD/ns;
184    if (tmp > 3) tmp = 3;
185    dmcr |= (tmp << EMC_DMCR_RCD_BIT);
186    tmp = SDRAM_TPC/ns;
187    if (tmp > 7) tmp = 7;
188    dmcr |= (tmp << EMC_DMCR_TPC_BIT);
189    tmp = SDRAM_TRWL/ns;
190    if (tmp > 3) tmp = 3;
191    dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
192    tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
193    if (tmp > 14) tmp = 14;
194    dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
195
196    /* SDRAM mode value */
197    sdmode = EMC_SDMR_BT_SEQ |
198         EMC_SDMR_OM_NORMAL |
199         EMC_SDMR_BL_4 |
200         cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
201
202    /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
203    REG_EMC_DMCR = dmcr;
204    REG8(EMC_SDMR0|sdmode) = 0;
205
206    /* Wait for precharge, > 200us */
207    tmp = (cpu_clk / 1000000) * 1000;
208    while (tmp--);
209
210    /* Stage 2. Enable auto-refresh */
211    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
212
213    tmp = SDRAM_TREF/ns;
214    tmp = tmp/64 + 1;
215    if (tmp > 0xff) tmp = 0xff;
216    REG_EMC_RTCOR = tmp;
217    REG_EMC_RTCNT = 0;
218    REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
219
220    /* Wait for number of auto-refresh cycles */
221    tmp = (cpu_clk / 1000000) * 1000;
222    while (tmp--);
223
224     /* Stage 3. Mode Register Set */
225    REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
226    REG8(EMC_SDMR0|sdmode) = 0;
227
228        /* Set back to basic DMCR value */
229    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
230
231    /* everything is ok now */
232}
233
234void nand_init_4740()
235{
236    REG_EMC_SMCR1 = 0x094c4400;
237    REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1; //__nand_enable()
238}
239

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