1 | /* |
2 | * JZ4760 board definitions. |
3 | * |
4 | * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. |
5 | */ |
6 | #ifndef __BOARD_JZ4760_H__ |
7 | #define __BOARD_JZ4760_H__ |
8 | |
9 | //#define DEBUG |
10 | //#define CONFIG_FPGA |
11 | //#define CFG_DIV 2 /* for FPGA */ |
12 | |
13 | #define CFG_EXTAL 12000000 |
14 | #define CFG_CPU_SPEED 144000000 /* CPU clock */ |
15 | |
16 | #define CONFIG_DDRC |
17 | #define CONFIG_SDRAM_DDR2 |
18 | //#define CONFIG_SDRAM_MDDR |
19 | //#define CONFIG_SDRAM_DDR1 |
20 | //#define CONFIG_MOBILE_SDRAM |
21 | |
22 | #if (!defined(CONFIG_SDRAM_MDDR) && !defined(CONFIG_SDRAM_DDR1) && !defined(CONFIG_SDRAM_DDR2)) |
23 | /*----------------------------------------------------------------------- |
24 | * SDRAM Info. |
25 | */ |
26 | #define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/ |
27 | |
28 | #ifndef CONFIG_MOBILE_SDRAM |
29 | // SDRAM paramters |
30 | #define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ |
31 | #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ |
32 | #define SDRAM_ROW 13 /* Row address: 11 to 13 */ |
33 | #define SDRAM_COL 9 /* Column address: 8 to 12 */ |
34 | #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ |
35 | |
36 | // SDRAM Timings, unit: ns |
37 | #define SDRAM_TRAS 45 /* RAS# Active Time */ |
38 | #define SDRAM_RCD 20 /* RAS# to CAS# Delay */ |
39 | #define SDRAM_TPC 20 /* RAS# Precharge Time */ |
40 | #define SDRAM_TRWL 7 /* Write Latency Time */ |
41 | #define SDRAM_TREF 7812 /* Refresh period: 4096 refresh cycles/64ms */ |
42 | |
43 | #else /* Mobile SDRAM */ |
44 | // SDRAM paramters |
45 | #define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ |
46 | #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ |
47 | #define SDRAM_ROW 13 /* Row address: 11 to 13 */ |
48 | #define SDRAM_COL 9 /* Column address: 8 to 12 */ |
49 | #define SDRAM_CASL 3 /* CAS latency: 2 or 3 */ |
50 | |
51 | // SDRAM Timings, unit: ns |
52 | #define SDRAM_TRAS 50 /* RAS# Active Time */ |
53 | #define SDRAM_RCD 18 /* RAS# to CAS# Delay */ |
54 | #define SDRAM_TPC 20 /* RAS# Precharge Time */ |
55 | #define SDRAM_TRWL 7 /* Write Latency Time */ |
56 | #define SDRAM_TREF 7812 /* Refresh period: 4096 refresh cycles/64ms */ |
57 | #endif /* CONFIG_MOBILE_SDRAM */ |
58 | |
59 | #else /* CONFIG_DDRC */ |
60 | |
61 | /*-------------------------------------------------------------------------------- |
62 | * DDR2 info |
63 | */ |
64 | /* Chip Select */ |
65 | #define DDR_CS1EN 0 // CSEN : whether a ddr chip exists 0 - un-used, 1 - used |
66 | #define DDR_CS0EN 1 |
67 | #define DDR_DW32 1 /* 0 - 16-bit data width, 1 - 32-bit data width */ |
68 | |
69 | /* SDRAM paramters */ |
70 | #if defined(CONFIG_SDRAM_DDR2) // ddr2 |
71 | #define DDR_ROW 13 /* ROW : 12 to 14 row address */ |
72 | #define DDR_COL 10 /* COL : 8 to 10 column address */ |
73 | #define DDR_BANK8 1 /* Banks each chip: 0-4bank, 1-8bank */ |
74 | #define DDR_CL 3 /* CAS latency: 1 to 7 */ |
75 | |
76 | /* |
77 | * ddr2 controller timing1 register |
78 | */ |
79 | #define DDR_tRAS 45 /*tRAS: ACTIVE to PRECHARGE command period to the same bank. */ |
80 | #define DDR_tRTP 8 /* 7.5ns READ to PRECHARGE command period. */ |
81 | #define DDR_tRP 42 /* tRP: PRECHARGE command period to the same bank */ |
82 | #define DDR_tRCD 42 /* ACTIVE to READ or WRITE command period to the same bank. */ |
83 | #define DDR_tRC 60 /* ACTIVE to ACTIVE command period to the same bank.*/ |
84 | #define DDR_tRRD 8 /* ACTIVE bank A to ACTIVE bank B command period. */ |
85 | #define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory */ |
86 | #define DDR_tWTR 2 /* unit: tCK. WRITE to READ command delay. */ |
87 | |
88 | /* |
89 | * ddr2 controller timing2 register |
90 | */ |
91 | #define DDR_tRFC 128 /* ns, AUTO-REFRESH command period. */ |
92 | #define DDR_tMINSR 6 /* Minimum Self-Refresh / Deep-Power-Down */ |
93 | #define DDR_tXP 2 /* EXIT-POWER-DOWN to next valid command period: 1 to 8 tCK. */ |
94 | #define DDR_tMRD 2 /* unit: tCK. Load-Mode-Register to next valid command period: 1 to 4 tCK */ |
95 | |
96 | /* |
97 | * ddr2 controller refcnt register |
98 | */ |
99 | #define DDR_tREFI 7800 /* Refresh period: ns */ |
100 | |
101 | #elif defined(CONFIG_SDRAM_MDDR) // ddr1 and mddr |
102 | #define DDR_ROW 14 /* ROW : 12 to 14 row address */ |
103 | #define DDR_COL 10 /* COL : 8 to 10 column address */ |
104 | #define DDR_BANK8 0 /* Banks each chip: 0-4bank, 1-8bank */ |
105 | #define DDR_CL 3 /* CAS latency: 1 to 7 */ |
106 | /* |
107 | * ddr2 controller timing1 register |
108 | */ |
109 | #define DDR_tRAS 40 /*tRAS: ACTIVE to PRECHARGE command period to the same bank. */ |
110 | #define DDR_tRTP 12 /* 7.5ns READ to PRECHARGE command period. */ |
111 | #define DDR_tRP 15 /* tRP: PRECHARGE command period to the same bank */ |
112 | #define DDR_tRCD 20 /* ACTIVE to READ or WRITE command period to the same bank. */ |
113 | #define DDR_tRC 55 /* ACTIVE to ACTIVE command period to the same bank.*/ |
114 | #define DDR_tRRD 10 /* ACTIVE bank A to ACTIVE bank B command period. */ |
115 | #define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory */ |
116 | #define DDR_tWTR 2 /* WRITE to READ command delay. */ |
117 | /* |
118 | * ddr2 controller timing2 register |
119 | */ |
120 | #define DDR_tRFC 90 /* ns, AUTO-REFRESH command period. */ |
121 | #define DDR_tMINSR 6 /* Minimum Self-Refresh / Deep-Power-Down */ |
122 | #define DDR_tXP 1 /* EXIT-POWER-DOWN to next valid command period: 1 to 8 tCK. */ |
123 | #define DDR_tMRD 2 /* unit: tCK Load-Mode-Register to next valid command period: 1 to 4 tCK */ |
124 | /* |
125 | * ddr2 controller refcnt register |
126 | */ |
127 | #define DDR_tREFI 7800 /* Refresh period: 4096 refresh cycles/64ms */ |
128 | |
129 | #elif defined(CONFIG_SDRAM_DDR1) // ddr1 and mddr |
130 | #define DDR_ROW 13 /* ROW : 12 to 14 row address */ |
131 | #define DDR_COL 10 /* COL : 8 to 10 column address */ |
132 | #define DDR_BANK8 0 /* Banks each chip: 0-4bank, 1-8bank */ |
133 | #define DDR_CL 3 /* CAS latency: 1 to 7 */ |
134 | #define DDR_CL_HALF 0 /*Only for DDR1, Half CAS latency: 0 or 1 */ |
135 | /* |
136 | * ddr2 controller timing1 register |
137 | */ |
138 | #define DDR_tRAS 40 /*tRAS: ACTIVE to PRECHARGE command period to the same bank. */ |
139 | #define DDR_tRTP 12 /* 7.5ns READ to PRECHARGE command period. */ |
140 | #define DDR_tRP 15 /* tRP: PRECHARGE command period to the same bank */ |
141 | #define DDR_tRCD 15 /* ACTIVE to READ or WRITE command period to the same bank. */ |
142 | #define DDR_tRC 55 /* ACTIVE to ACTIVE command period to the same bank.*/ |
143 | #define DDR_tRRD 10 /* ACTIVE bank A to ACTIVE bank B command period. */ |
144 | #define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory */ |
145 | #define DDR_tWTR 2 /* WRITE to READ command delay 2*tCK */ |
146 | /* |
147 | * ddr2 controller timing2 register |
148 | */ |
149 | #define DDR_tRFC 70 /* ns, AUTO-REFRESH command period. */ |
150 | #define DDR_tMINSR 6 /* Minimum Self-Refresh / Deep-Power-Down */ |
151 | #define DDR_tXP 2 /* EXIT-POWER-DOWN to next valid command period: 1 to 8 tCK. */ |
152 | #define DDR_tMRD 2 /* unit: tCK. Load-Mode-Register to next valid command period: 1 to 4 tCK */ |
153 | /* |
154 | * ddr2 controller refcnt register |
155 | */ |
156 | #define DDR_tREFI 7800 /* Refresh period: 4096 refresh cycles/64ms */ |
157 | |
158 | #endif |
159 | |
160 | #define DDR_CLK_DIV 1 /* Clock Divider. auto refresh |
161 | * cnt_clk = memclk/(16*(2^DDR_CLK_DIV)) |
162 | */ |
163 | #endif /* CONFIG_DDRC */ |
164 | |
165 | #endif /* __BOARD_JZ4760_H__ */ |
166 | |