1 | /* |
2 | * device board |
3 | * |
4 | * Copyright 2009 (C) Qi Hardware Inc., |
5 | * Author: Xiangfu Liu <xiangfu@sharism.cc> |
6 | * |
7 | * This program is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License |
9 | * version 3 as published by the Free Software Foundation. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
19 | * Boston, MA 02110-1301, USA |
20 | */ |
21 | |
22 | #include "target/jz4740.h" |
23 | #include "target/configs.h" |
24 | |
25 | void gpio_init_4740(void) |
26 | { |
27 | /* |
28 | * Initialize SDRAM pins |
29 | */ |
30 | #if 0 |
31 | /* PORT A: D0 ~ D31 */ |
32 | REG_GPIO_PXFUNS(0) = 0xffffffff; |
33 | REG_GPIO_PXSELC(0) = 0xffffffff; |
34 | |
35 | /* PORT B: A0 ~ A16, DCS#, RAS#, CAS#, CKE#, RDWE#, CKO#, WE0# */ |
36 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; |
37 | REG_GPIO_PXSELC(1) = 0x81f9ffff; |
38 | |
39 | /* PORT C: WE1#, WE2#, WE3# */ |
40 | REG_GPIO_PXFUNS(2) = 0x07000000; |
41 | REG_GPIO_PXSELC(2) = 0x07000000; |
42 | |
43 | /* |
44 | * Initialize Static Memory Pins |
45 | */ |
46 | |
47 | /* CS4# */ |
48 | REG_GPIO_PXFUNS(1) = 0x10000000; |
49 | REG_GPIO_PXSELC(1) = 0x10000000; |
50 | |
51 | /* |
52 | * Initialize UART0 pins |
53 | */ |
54 | |
55 | /* PORT D: TXD/RXD */ |
56 | REG_GPIO_PXFUNS(3) = 0x06000000; |
57 | REG_GPIO_PXSELS(3) = 0x06000000; |
58 | #endif |
59 | |
60 | __gpio_as_nand(); |
61 | /* |
62 | * Initialize SDRAM pins |
63 | */ |
64 | __gpio_as_sdram_32bit(); |
65 | |
66 | /* |
67 | * Initialize UART0 pins |
68 | */ |
69 | __gpio_as_uart0(); |
70 | __gpio_as_uart1(); |
71 | } |
72 | |
73 | void pll_init_4740(void) |
74 | { |
75 | register unsigned int cfcr, plcr1; |
76 | int n2FR[33] = { |
77 | 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, |
78 | 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, |
79 | 9 |
80 | }; |
81 | /* int div[5] = {1, 4, 4, 4, 4}; */ /* divisors of I:S:P:L:M */ |
82 | int nf, pllout2; |
83 | |
84 | cfcr = CPM_CPCCR_CLKOEN | |
85 | (n2FR[1] << CPM_CPCCR_CDIV_BIT) | |
86 | (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | |
87 | (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | |
88 | (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | |
89 | (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); |
90 | |
91 | pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); |
92 | |
93 | /* Init UHC clock */ |
94 | REG_CPM_UHCCDR = pllout2 / 48000000 - 1; |
95 | |
96 | nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; |
97 | plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ |
98 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
99 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
100 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ |
101 | CPM_CPPCR_PLLEN; /* enable PLL */ |
102 | |
103 | /* init PLL */ |
104 | REG_CPM_CPCCR = cfcr; |
105 | REG_CPM_CPPCR = plcr1; |
106 | } |
107 | |
108 | void sdram_init_4740(void) |
109 | { |
110 | register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; |
111 | |
112 | unsigned int cas_latency_sdmr[2] = { |
113 | EMC_SDMR_CAS_2, |
114 | EMC_SDMR_CAS_3, |
115 | }; |
116 | |
117 | unsigned int cas_latency_dmcr[2] = { |
118 | 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ |
119 | 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ |
120 | }; |
121 | |
122 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
123 | |
124 | if (SDRAM_BW16 == 0xff) |
125 | return; |
126 | |
127 | cpu_clk = CFG_CPU_SPEED; |
128 | mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; |
129 | |
130 | REG_EMC_BCR = 0; /* Disable bus release */ |
131 | REG_EMC_RTCSR = 0; /* Disable clock for counting */ |
132 | |
133 | /* Fault DMCR value for mode register setting*/ |
134 | #define SDRAM_ROW0 11 |
135 | #define SDRAM_COL0 8 |
136 | #define SDRAM_BANK40 0 |
137 | |
138 | dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | |
139 | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | |
140 | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | |
141 | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
142 | EMC_DMCR_EPIN | |
143 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
144 | |
145 | /* Basic DMCR value */ |
146 | dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | |
147 | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | |
148 | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | |
149 | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
150 | EMC_DMCR_EPIN | |
151 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
152 | |
153 | /* SDRAM timimg */ |
154 | ns = 1000000000 / mem_clk; |
155 | tmp = SDRAM_TRAS/ns; |
156 | if (tmp < 4) tmp = 4; |
157 | if (tmp > 11) tmp = 11; |
158 | dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); |
159 | tmp = SDRAM_RCD/ns; |
160 | if (tmp > 3) tmp = 3; |
161 | dmcr |= (tmp << EMC_DMCR_RCD_BIT); |
162 | tmp = SDRAM_TPC/ns; |
163 | if (tmp > 7) tmp = 7; |
164 | dmcr |= (tmp << EMC_DMCR_TPC_BIT); |
165 | tmp = SDRAM_TRWL/ns; |
166 | if (tmp > 3) tmp = 3; |
167 | dmcr |= (tmp << EMC_DMCR_TRWL_BIT); |
168 | tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; |
169 | if (tmp > 14) tmp = 14; |
170 | dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); |
171 | |
172 | /* SDRAM mode value */ |
173 | sdmode = EMC_SDMR_BT_SEQ | |
174 | EMC_SDMR_OM_NORMAL | |
175 | EMC_SDMR_BL_4 | |
176 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; |
177 | |
178 | /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ |
179 | REG_EMC_DMCR = dmcr; |
180 | REG8(EMC_SDMR0|sdmode) = 0; |
181 | |
182 | /* Wait for precharge, > 200us */ |
183 | tmp = (cpu_clk / 1000000) * 1000; |
184 | while (tmp--); |
185 | |
186 | /* Stage 2. Enable auto-refresh */ |
187 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; |
188 | |
189 | tmp = SDRAM_TREF/ns; |
190 | tmp = tmp/64 + 1; |
191 | if (tmp > 0xff) tmp = 0xff; |
192 | REG_EMC_RTCOR = tmp; |
193 | REG_EMC_RTCNT = 0; |
194 | REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ |
195 | |
196 | /* Wait for number of auto-refresh cycles */ |
197 | tmp = (cpu_clk / 1000000) * 1000; |
198 | while (tmp--); |
199 | |
200 | /* Stage 3. Mode Register Set */ |
201 | REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
202 | REG8(EMC_SDMR0|sdmode) = 0; |
203 | |
204 | /* Set back to basic DMCR value */ |
205 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
206 | |
207 | /* everything is ok now */ |
208 | } |
209 | |
210 | void serial_setbrg_4740(void) |
211 | { |
212 | volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR); |
213 | volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR); |
214 | volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR); |
215 | u32 baud_div, tmp; |
216 | |
217 | baud_div = CFG_EXTAL / 16 / CONFIG_BAUDRATE; |
218 | tmp = *uart_lcr; |
219 | tmp |= UART_LCR_DLAB; |
220 | *uart_lcr = tmp; |
221 | |
222 | *uart_dlhr = (baud_div >> 8) & 0xff; |
223 | *uart_dllr = baud_div & 0xff; |
224 | |
225 | tmp &= ~UART_LCR_DLAB; |
226 | *uart_lcr = tmp; |
227 | } |
228 | |