1 | /* |
2 | * board.c |
3 | * |
4 | * Board init routines. |
5 | * |
6 | * Copyright (C) 2006 Ingenic Semiconductor Inc. |
7 | * |
8 | */ |
9 | #include "target/xburst_types.h" |
10 | #include "target/jz4760.h" |
11 | #include "board-jz4760.h" |
12 | |
13 | extern volatile u32 UART_BASE; |
14 | |
15 | void nand_init_4760() |
16 | { |
17 | REG_NEMC_NFCSR |= NEMC_NFCSR_NFE1 | NEMC_NFCSR_NFCE1; |
18 | } |
19 | |
20 | void cpm_start_all_4760() |
21 | { |
22 | __cpm_start_all(); |
23 | } |
24 | |
25 | /* |
26 | * SD0 ~ SD7, SA0 ~ SA5, CS2#, RD#, WR#, WAIT# |
27 | */ |
28 | #define __gpio_as_nor() \ |
29 | do { \ |
30 | /* SD0 ~ SD7, RD#, WR#, CS2#, WAIT# */ \ |
31 | REG_GPIO_PXFUNS(0) = 0x084300ff; \ |
32 | REG_GPIO_PXTRGC(0) = 0x084300ff; \ |
33 | REG_GPIO_PXSELC(0) = 0x084300ff; \ |
34 | REG_GPIO_PXPES(0) = 0x084300ff; \ |
35 | /* SA0 ~ SA5 */ \ |
36 | REG_GPIO_PXFUNS(1) = 0x0000003f; \ |
37 | REG_GPIO_PXTRGC(1) = 0x0000003f; \ |
38 | REG_GPIO_PXSELC(1) = 0x0000003f; \ |
39 | REG_GPIO_PXPES(1) = 0x0000003f; \ |
40 | } while (0) |
41 | |
42 | void gpio_init_4760() |
43 | { |
44 | __gpio_as_uart0(); |
45 | __gpio_as_uart1(); |
46 | __gpio_as_uart2(); |
47 | __gpio_as_uart3(); |
48 | |
49 | #ifdef CONFIG_FPGA // if the delay isn't added on FPGA, the first line that uart to print will not be normal. |
50 | __gpio_as_nor(); |
51 | { |
52 | volatile int i=1000; |
53 | while(i--); |
54 | } |
55 | #endif |
56 | __gpio_as_nand_8bit(1); |
57 | } |
58 | |
59 | #define MHZ (1000 * 1000) |
60 | static inline unsigned int pll_calc_m_n_od(unsigned int speed, unsigned int xtal) |
61 | { |
62 | const int pll_m_max = 0x7f, pll_m_min = 4; |
63 | const int pll_n_max = 0x0f, pll_n_min = 2; |
64 | |
65 | int od[] = {1, 2, 4, 8}; |
66 | int min_od = 0; |
67 | |
68 | unsigned int plcr_m_n_od = 0; |
69 | unsigned int distance; |
70 | unsigned int tmp, raw; |
71 | |
72 | int i, j, k; |
73 | int m, n; |
74 | |
75 | distance = 0xFFFFFFFF; |
76 | |
77 | for (i = 0; i < sizeof (od) / sizeof(int); i++) { |
78 | /* Limit: 500MHZ <= CLK_OUT * OD <= 1500MHZ */ |
79 | // if (min_od != 0) |
80 | // break; |
81 | if ((speed * od[i]) < 500 * MHZ || (speed * od[i]) > 1500 * MHZ) |
82 | continue; |
83 | for (k = pll_n_min; k <= pll_n_max; k++) { |
84 | n = k; |
85 | |
86 | /* Limit: 1MHZ <= XIN/N <= 50MHZ */ |
87 | if ((xtal / n) < (1 * MHZ)) |
88 | break; |
89 | if ((xtal / n) > (15 * MHZ)) |
90 | continue; |
91 | |
92 | for (j = pll_m_min; j <= pll_m_max; j++) { |
93 | m = j*2; |
94 | |
95 | raw = xtal * m / n; |
96 | tmp = raw / od[i]; |
97 | |
98 | tmp = (tmp > speed) ? (tmp - speed) : (speed - tmp); |
99 | |
100 | if (tmp < distance) { |
101 | distance = tmp; |
102 | |
103 | plcr_m_n_od = (j << CPM_CPPCR_PLLM_BIT) |
104 | | (k << CPM_CPPCR_PLLN_BIT) |
105 | | (i << CPM_CPPCR_PLLOD_BIT); |
106 | |
107 | if (!distance) { /* Match. */ |
108 | // serial_puts("right value"); |
109 | return plcr_m_n_od; |
110 | } |
111 | } |
112 | } |
113 | min_od = od[i]; |
114 | } |
115 | } |
116 | return plcr_m_n_od; |
117 | } |
118 | |
119 | /* TODO: pll_init() need modification. */ |
120 | void pll_init_4760() |
121 | { |
122 | register unsigned int cfcr, plcr1; |
123 | int n2FR[9] = { |
124 | 0, 0, 1, 2, 3, 0, 4, 0, 5 |
125 | }; |
126 | |
127 | /** divisors, |
128 | * for jz4760 ,I:H:H2:P:M:S. |
129 | * DIV should be one of [1, 2, 3, 4, 6, 8] like: |
130 | * div[6] = {1, 2, 2, 2, 2, 2}; |
131 | * div[6] = {1, 3, 6, 6, 6, 6}; |
132 | */ |
133 | int div[6] = {1, 2, 4, 4, 4, 4}; |
134 | |
135 | cfcr = CPM_CPCCR_PCS | |
136 | (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | |
137 | (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | |
138 | (n2FR[div[2]] << CPM_CPCCR_H2DIV_BIT) | |
139 | (n2FR[div[3]] << CPM_CPCCR_PDIV_BIT) | |
140 | (n2FR[div[4]] << CPM_CPCCR_MDIV_BIT) | |
141 | (n2FR[div[5]] << CPM_CPCCR_SDIV_BIT); |
142 | |
143 | if (CFG_EXTAL > 16000000) |
144 | cfcr |= CPM_CPCCR_ECS; |
145 | else |
146 | cfcr &= ~CPM_CPCCR_ECS; |
147 | |
148 | /* set CPM_CPCCR_MEM only for ddr1 or ddr2 */ |
149 | #if defined(CONFIG_DDRC) && (defined(CONFIG_SDRAM_DDR1) || defined(CONFIG_SDRAM_DDR2)) |
150 | cfcr |= CPM_CPCCR_MEM; |
151 | #else |
152 | cfcr &= ~CPM_CPCCR_MEM; |
153 | #endif |
154 | cfcr |= CPM_CPCCR_CE; |
155 | |
156 | plcr1 = pll_calc_m_n_od(CFG_CPU_SPEED, CFG_EXTAL); |
157 | plcr1 |= (0x20 << CPM_CPPCR_PLLST_BIT) /* PLL stable time */ |
158 | | CPM_CPPCR_PLLEN; /* enable PLL */ |
159 | |
160 | /* init PLL */ |
161 | REG_CPM_CPCCR = cfcr; |
162 | REG_CPM_CPPCR = plcr1; |
163 | |
164 | while(!(REG_CPM_CPPSR & (1 << 29))); |
165 | |
166 | #ifdef DEBUG |
167 | serial_puts("REG_CPM_CPCCR = "); |
168 | serial_put_hex(REG_CPM_CPCCR); |
169 | serial_puts("REG_CPM_CPPCR = "); |
170 | serial_put_hex(REG_CPM_CPPCR); |
171 | #endif |
172 | } |
173 | |
174 | #if (defined(CONFIG_SDRAM_MDDR)||defined(CONFIG_SDRAM_DDR1)||defined(CONFIG_SDRAM_DDR2)) |
175 | void jzmemset(void *dest,int ch,int len) |
176 | { |
177 | unsigned int *d = (unsigned int *)dest; |
178 | int i; |
179 | int wd; |
180 | |
181 | wd = (ch << 24) | (ch << 16) | (ch << 8) | ch; |
182 | |
183 | for(i = 0;i < len / 32;i++) |
184 | { |
185 | *d++ = wd; |
186 | *d++ = wd; |
187 | *d++ = wd; |
188 | *d++ = wd; |
189 | *d++ = wd; |
190 | *d++ = wd; |
191 | *d++ = wd; |
192 | *d++ = wd; |
193 | } |
194 | } |
195 | |
196 | unsigned int gen_verify_data(unsigned int i) |
197 | { |
198 | i = i/4*0x11111111; |
199 | return i; |
200 | //return 0xffffffff; |
201 | } |
202 | |
203 | int initdram(int board_type) |
204 | { |
205 | u32 ddr_cfg; |
206 | u32 rows, cols, dw, banks; |
207 | unsigned long size; |
208 | ddr_cfg = REG_DDRC_CFG; |
209 | rows = 12 + ((ddr_cfg & DDRC_CFG_ROW_MASK) >> DDRC_CFG_ROW_BIT); |
210 | cols = 8 + ((ddr_cfg & DDRC_CFG_COL_MASK) >> DDRC_CFG_COL_BIT); |
211 | |
212 | dw = (ddr_cfg & DDRC_CFG_DW) ? 4 : 2; |
213 | banks = (ddr_cfg & DDRC_CFG_BA) ? 8 : 4; |
214 | |
215 | size = (1 << (rows + cols)) * dw * banks; |
216 | size *= (DDR_CS1EN + DDR_CS0EN); |
217 | |
218 | return size; |
219 | } |
220 | static int dma_check_result(void *src, void *dst, int size,int print_flag) |
221 | { |
222 | unsigned int addr1, addr2, i, err = 0; |
223 | unsigned int data_expect,dsrc,ddst; |
224 | |
225 | addr1 = (unsigned int)src; |
226 | addr2 = (unsigned int)dst; |
227 | |
228 | for (i = 0; i < size; i += 4) { |
229 | data_expect = gen_verify_data(i); |
230 | dsrc = REG32(addr1); |
231 | ddst = REG32(addr2); |
232 | if ((dsrc != data_expect) || (ddst != data_expect)) { |
233 | #if DEBUG |
234 | serial_put_hex(addr2); |
235 | serial_puts("data:"); |
236 | serial_put_hex(data_expect); |
237 | serial_puts("src"); |
238 | serial_put_hex(dsrc); |
239 | serial_puts("dst"); |
240 | serial_put_hex(ddst); |
241 | #endif |
242 | err = 1; |
243 | if(!print_flag) |
244 | return 1; |
245 | } |
246 | |
247 | addr1 += 4; |
248 | addr2 += 4; |
249 | } |
250 | return err; |
251 | } |
252 | |
253 | #if DEBUG |
254 | void dump_jz_dma_channel(unsigned int dmanr) |
255 | { |
256 | |
257 | if (dmanr > MAX_DMA_NUM) |
258 | return; |
259 | serial_puts("REG_DDRC_ST \t\t="); |
260 | serial_put_hex(REG_DDRC_ST); |
261 | |
262 | serial_puts("DMA Registers, Channel "); |
263 | serial_put_hex(dmanr); |
264 | |
265 | serial_puts(" DMACR = "); |
266 | serial_put_hex(REG_DMAC_DMACR(dmanr/HALF_DMA_NUM)); |
267 | serial_puts(" DSAR = "); |
268 | serial_put_hex(REG_DMAC_DSAR(dmanr)); |
269 | serial_puts(" DTAR = "); |
270 | serial_put_hex(REG_DMAC_DTAR(dmanr)); |
271 | serial_puts(" DTCR = "); |
272 | serial_put_hex(REG_DMAC_DTCR(dmanr)); |
273 | serial_puts(" DRSR = "); |
274 | serial_put_hex(REG_DMAC_DRSR(dmanr)); |
275 | serial_puts(" DCCSR = "); |
276 | serial_put_hex(REG_DMAC_DCCSR(dmanr)); |
277 | serial_puts(" DCMD = "); |
278 | serial_put_hex(REG_DMAC_DCMD(dmanr)); |
279 | serial_puts(" DDA = "); |
280 | serial_put_hex(REG_DMAC_DDA(dmanr)); |
281 | serial_puts(" DMADBR = "); |
282 | serial_put_hex(REG_DMAC_DMADBR(dmanr/HALF_DMA_NUM)); |
283 | } |
284 | |
285 | void dma_nodesc_test_single(int dma_chan, int dma_src_addr, int dma_dst_addr, int size) |
286 | { |
287 | int dma_src_phys_addr, dma_dst_phys_addr; |
288 | |
289 | /* Allocate DMA buffers */ |
290 | dma_src_phys_addr = dma_src_addr & (~0xa0000000); |
291 | dma_dst_phys_addr = dma_dst_addr & (~0xa0000000); |
292 | |
293 | /* Init DMA module */ |
294 | REG_DMAC_DCCSR(dma_chan) = 0; |
295 | REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO; |
296 | REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr; |
297 | REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr; |
298 | REG_DMAC_DTCR(dma_chan) = size; |
299 | REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT; |
300 | REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; |
301 | } |
302 | |
303 | static void ddrc_regs_print(void) |
304 | { |
305 | serial_puts("\nDDRC REGS:\n"); |
306 | serial_puts("REG_DDRC_ST \t\t="); |
307 | serial_put_hex(REG_DDRC_ST); |
308 | serial_puts("REG_DDRC_CFG \t\t="); |
309 | serial_put_hex( REG_DDRC_CFG); |
310 | serial_puts("REG_DDRC_CTRL \t\t="); |
311 | serial_put_hex(REG_DDRC_CTRL); |
312 | serial_puts("REG_DDRC_LMR \t\t="); |
313 | serial_put_hex(REG_DDRC_LMR); |
314 | serial_puts("REG_DDRC_TIMING1 \t="); |
315 | serial_put_hex(REG_DDRC_TIMING1); |
316 | serial_puts("REG_DDRC_TIMING2 \t="); |
317 | serial_put_hex(REG_DDRC_TIMING2); |
318 | serial_puts("REG_DDRC_REFCNT \t\t="); |
319 | serial_put_hex(REG_DDRC_REFCNT); |
320 | serial_puts("REG_DDRC_DQS \t\t="); |
321 | serial_put_hex(REG_DDRC_DQS); |
322 | serial_puts("REG_DDRC_DQS_ADJ \t="); |
323 | serial_put_hex(REG_DDRC_DQS_ADJ); |
324 | serial_puts("REG_DDRC_MMAP0 \t\t="); |
325 | serial_put_hex(REG_DDRC_MMAP0); |
326 | serial_puts("REG_DDRC_MMAP1 \t\t="); |
327 | serial_put_hex(REG_DDRC_MMAP1); |
328 | serial_puts("REG_DDRC_MDELAY \t\t="); |
329 | serial_put_hex(REG_DDRC_MDELAY); |
330 | serial_puts("REG_EMC_PMEMPS2 \t\t="); |
331 | serial_put_hex(REG_EMC_PMEMPS2); |
332 | } |
333 | |
334 | static int dma_memcpy_test(int channle_0, int channle_1) { |
335 | int i, err = 0, banks; |
336 | unsigned int addr, DDR_DMA0_SRC, DDR_DMA0_DST, DDR_DMA1_SRC, DDR_DMA1_DST; |
337 | volatile unsigned int tmp; |
338 | register unsigned int cpu_clk; |
339 | long int memsize, banksize, testsize; |
340 | int channel; |
341 | |
342 | #ifndef CONFIG_DDRC |
343 | banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS); |
344 | #else |
345 | banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN); |
346 | #endif |
347 | memsize = initdram(0); |
348 | |
349 | banksize = memsize/banks; |
350 | testsize = 4096; |
351 | |
352 | DDR_DMA0_SRC = DDR_DMA_BASE + banksize*0; |
353 | DDR_DMA0_DST = DDR_DMA_BASE + banksize*0 + testsize; |
354 | DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2; |
355 | DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3; |
356 | |
357 | cpu_clk = CFG_CPU_SPEED; |
358 | |
359 | // for(channel = 0; channel < MAX_DMA_NUM; channel++) { |
360 | |
361 | // MDMA |
362 | REG_MDMAC_DMACR = DMAC_DMACR_DMAE; |
363 | // COMMON DMA |
364 | //REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */ |
365 | //REG_DMAC_DMACR(1) = DMAC_DMACR_DMAE; /* global DMA enable bit */ |
366 | |
367 | // Write A0 |
368 | addr = DDR_DMA0_SRC; |
369 | |
370 | for (i = 0; i < testsize; i += 4) { |
371 | *(volatile unsigned int *)addr = (i/4*0x11111111); |
372 | //*(volatile unsigned int *)addr = addr; |
373 | addr += 4; |
374 | } |
375 | |
376 | // Write A2 |
377 | addr = DDR_DMA1_SRC; |
378 | for (i = 0; i < testsize; i += 4) { |
379 | *(volatile unsigned int *)addr = (i/4*0x11111111); |
380 | //*(volatile unsigned int *)addr = addr; |
381 | addr += 4; |
382 | } |
383 | |
384 | |
385 | // MDMA |
386 | REG_MDMAC_DMACR = 0; |
387 | // COMMON DMA |
388 | //REG_DMAC_DMACR(0) = 0; |
389 | //REG_DMAC_DMACR(1) = 0; |
390 | |
391 | /* Init target buffer */ |
392 | jzmemset((void *)DDR_DMA0_DST, 0, testsize); |
393 | jzmemset((void *)DDR_DMA1_DST, 0, testsize); |
394 | |
395 | // Set DMA1 for moving data from A0 -> A1 |
396 | dma_data_move(channle_0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize, DMAC_DCMD_DS_32BYTE); |
397 | // Set DMA2 for moving data from A2 -> A3 |
398 | dma_data_move(channle_1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize, DMAC_DCMD_DS_64BYTE); |
399 | |
400 | // Start DMA0 |
401 | REG_DMAC_DCCSR(0) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; |
402 | // Wait for DMA0 finishing |
403 | while(REG_DMAC_DTCR(0)); |
404 | |
405 | // Start DMA1 |
406 | REG_DMAC_DCCSR(1) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; |
407 | |
408 | // Read from A1 & check |
409 | err = check_result((void *)DDR_DMA0_SRC, (void *)DDR_DMA0_DST, testsize); |
410 | REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */ |
411 | if (err != 0) { |
412 | serial_puts("DMA0: err!\n"); |
413 | //return err; |
414 | } |
415 | |
416 | // Wait for DMA1 finishing |
417 | while(REG_DMAC_DTCR(1)); |
418 | |
419 | // Read from A3 & check |
420 | err = check_result((void *)DDR_DMA1_SRC, (void *)DDR_DMA1_DST, testsize); |
421 | REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */ |
422 | if (err != 0) { |
423 | serial_puts("DMA1: err!\n"); |
424 | //return err; |
425 | } |
426 | |
427 | serial_puts("TEST PASSED\n\n"); |
428 | |
429 | tmp = (cpu_clk / 1000000) * 1; |
430 | while (tmp--); |
431 | // } |
432 | return err; |
433 | } |
434 | |
435 | #endif |
436 | |
437 | |
438 | void dma_nodesc_test(int dma_chan, int dma_src_addr, int dma_dst_addr, int size) |
439 | { |
440 | int dma_src_phys_addr, dma_dst_phys_addr; |
441 | |
442 | /* Allocate DMA buffers */ |
443 | dma_src_phys_addr = dma_src_addr & (~0xa0000000); |
444 | dma_dst_phys_addr = dma_dst_addr & (~0xa0000000); |
445 | |
446 | /* Init DMA module */ |
447 | REG_DMAC_DCCSR(dma_chan) = 0; |
448 | REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO; |
449 | REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr; |
450 | REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr; |
451 | REG_DMAC_DTCR(dma_chan) = size / 32; |
452 | REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE; |
453 | REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; |
454 | } |
455 | |
456 | #define DDR_DMA_BASE (0xa0000000) /*un-cached*/ |
457 | #define DMA_CHANNEL0_EN |
458 | //#define DMA_CHANNEL1_EN |
459 | static int ddr_dma_test(int print_flag) { |
460 | int i, err = 0, banks; |
461 | int times; |
462 | unsigned int addr, DDR_DMA0_SRC, DDR_DMA0_DST, DDR_DMA1_SRC, DDR_DMA1_DST; |
463 | volatile unsigned int tmp; |
464 | register unsigned int cpu_clk; |
465 | long int memsize, banksize, testsize; |
466 | REG_DMAC_DMACKE(0) = 0x3f; |
467 | REG_DMAC_DMACKE(1) = 0x3f; |
468 | |
469 | #ifndef CONFIG_DDRC |
470 | banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS); |
471 | #else |
472 | banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN); |
473 | #endif |
474 | memsize = initdram(0); |
475 | |
476 | banksize = memsize/banks; |
477 | testsize = 4096; |
478 | |
479 | for(times = 0; times < banks; times++) { |
480 | #if 0 |
481 | DDR_DMA0_SRC = DDR_DMA_BASE + banksize*0; |
482 | DDR_DMA0_DST = DDR_DMA_BASE + banksize*(banks - 2) + testsize; |
483 | DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize; |
484 | DDR_DMA1_DST = DDR_DMA_BASE + banksize*1; |
485 | #else |
486 | DDR_DMA0_SRC = DDR_DMA_BASE + banksize*times; |
487 | DDR_DMA0_DST = DDR_DMA_BASE + banksize*(times+1) - testsize; |
488 | DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2; |
489 | DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3; |
490 | #endif |
491 | |
492 | cpu_clk = CFG_CPU_SPEED; |
493 | |
494 | #ifdef DMA_CHANNEL0_EN |
495 | addr = DDR_DMA0_SRC; |
496 | |
497 | for (i = 0; i < testsize; i += 4) { |
498 | *(volatile unsigned int *)(addr + i) = gen_verify_data(i); |
499 | } |
500 | #endif |
501 | #ifdef DMA_CHANNEL1_EN |
502 | addr = DDR_DMA1_SRC; |
503 | for (i = 0; i < testsize; i += 4) { |
504 | |
505 | *(volatile unsigned int *)addr = gen_verify_data(i); |
506 | |
507 | addr += 4; |
508 | } |
509 | #endif |
510 | |
511 | REG_DMAC_DMACR(0) = 0; |
512 | // REG_DMAC_DMACR(1) = 0; |
513 | /* Init target buffer */ |
514 | #ifdef DMA_CHANNEL0_EN |
515 | jzmemset((void *)DDR_DMA0_DST, 0, testsize); |
516 | dma_nodesc_test(0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize); |
517 | #endif |
518 | #ifdef DMA_CHANNEL1_EN |
519 | jzmemset((void *)DDR_DMA1_DST, 0, testsize); |
520 | dma_nodesc_test(1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize); |
521 | #endif |
522 | |
523 | REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */ |
524 | // REG_DMAC_DMACR(1) = DMAC_DMACR_DMAE; /* global DMA enable bit */ |
525 | // while(REG_DMAC_DTCR(0) || REG_DMAC_DTCR(1)); |
526 | while(REG_DMAC_DTCR(0)); |
527 | tmp = (cpu_clk / 1000000) * 1; |
528 | while (tmp--); |
529 | |
530 | #ifdef DMA_CHANNEL0_EN |
531 | err = dma_check_result((void *)DDR_DMA0_SRC, (void *)DDR_DMA0_DST, testsize,print_flag); |
532 | |
533 | REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */ |
534 | |
535 | if(err == 0) { |
536 | serial_puts("passed:"); |
537 | serial_put_hex(times); |
538 | } else { |
539 | serial_put_hex(times); |
540 | } |
541 | |
542 | if (err != 0) { |
543 | #ifdef DMA_CHANNEL1_EN |
544 | REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */ |
545 | #endif |
546 | return err; |
547 | } |
548 | |
549 | #endif |
550 | |
551 | #ifdef DMA_CHANNEL1_EN |
552 | //err += dma_check_result((void *)DDR_DMA1_SRC, (void *)DDR_DMA1_DST, testsize); |
553 | //REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */ |
554 | #endif |
555 | } |
556 | return err; |
557 | } |
558 | |
559 | void ddr_mem_init(int msel, int hl, int tsel, int arg) |
560 | { |
561 | volatile int tmp_cnt; |
562 | register unsigned int cpu_clk, ddr_twr; |
563 | register unsigned int ddrc_cfg_reg=0, init_ddrc_mdelay=0; |
564 | |
565 | cpu_clk = CFG_CPU_SPEED; |
566 | |
567 | #if defined(CONFIG_SDRAM_DDR2) // ddr2 |
568 | ddrc_cfg_reg = DDRC_CFG_TYPE_DDR2 | (DDR_ROW-12)<<10 |
569 | | (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6 |
570 | | ((DDR_CL-1) | 0x8)<<2 | DDR_BANK8<<1 | DDR_DW32; |
571 | #elif defined(CONFIG_SDRAM_DDR1) // ddr1 |
572 | ddrc_cfg_reg = DDRC_CFG_BTRUN |DDRC_CFG_TYPE_DDR1 |
573 | | (DDR_ROW-12)<<10 | (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6 |
574 | | ((DDR_CL_HALF?(DDR_CL&~0x8):((DDR_CL-1)|0x8))<<2) |
575 | | DDR_BANK8<<1 | DDR_DW32; |
576 | #else // mobile ddr |
577 | ddrc_cfg_reg = DDRC_CFG_TYPE_MDDR |
578 | | (DDR_ROW-12)<<10 | (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6 |
579 | | ((DDR_CL-1) | 0x8)<<2 | DDR_BANK8<<1 | DDR_DW32; |
580 | #endif |
581 | |
582 | ddrc_cfg_reg |= DDRC_CFG_MPRT; |
583 | |
584 | #if defined(CONFIG_FPGA) |
585 | init_ddrc_mdelay= tsel<<18 | msel<<16 | hl<<15; |
586 | #else |
587 | init_ddrc_mdelay= tsel<<18 | msel<<16 | hl<<15 | arg << 14; |
588 | #endif |
589 | ddr_twr = ((REG_DDRC_TIMING1 & DDRC_TIMING1_TWR_MASK) >> DDRC_TIMING1_TWR_BIT) + 1; |
590 | REG_DDRC_CFG = ddrc_cfg_reg; |
591 | |
592 | REG_DDRC_MDELAY = init_ddrc_mdelay | 1 << 6; |
593 | /***** init ddrc registers & ddr memory regs ****/ |
594 | /* AR: auto refresh */ |
595 | REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; |
596 | /* Wait for DDR_tRP */ |
597 | tmp_cnt = (cpu_clk / 1000000) * 1; |
598 | while (tmp_cnt--); |
599 | |
600 | /* Wait for number of auto-refresh cycles */ |
601 | tmp_cnt = (cpu_clk / 1000000) * 10; |
602 | while (tmp_cnt--); |
603 | |
604 | #if defined(CONFIG_SDRAM_DDR2) // ddr1 and mddr |
605 | |
606 | /* Set CKE High */ |
607 | REG_DDRC_CTRL = DDRC_CTRL_CKE; // ? |
608 | |
609 | /* Wait for number of auto-refresh cycles */ |
610 | tmp_cnt = (cpu_clk / 1000000) * 1; |
611 | while (tmp_cnt--); |
612 | |
613 | /* PREA */ |
614 | REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; |
615 | |
616 | /* Wait for DDR_tRP */ |
617 | tmp_cnt = (cpu_clk / 1000000) * 1; |
618 | while (tmp_cnt--); |
619 | |
620 | /* EMR2: extend mode register2 */ |
621 | REG_DDRC_LMR = DDRC_LMR_BA_EMRS2 | DDRC_LMR_CMD_LMR | DDRC_LMR_START;//0x221; |
622 | |
623 | /* EMR3: extend mode register3 */ |
624 | REG_DDRC_LMR = DDRC_LMR_BA_EMRS3 | DDRC_LMR_CMD_LMR | DDRC_LMR_START;//0x321; |
625 | |
626 | /* EMR1: extend mode register1 */ |
627 | REG_DDRC_LMR = (DDR_EMRS1_DQS_DIS << 16) | DDRC_LMR_BA_EMRS1 | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
628 | |
629 | /* wait DDR_tMRD */ |
630 | tmp_cnt = (cpu_clk / 1000000) * 1; |
631 | while (tmp_cnt--); |
632 | |
633 | /* MR - DLL Reset A1A0 burst 2 */ |
634 | REG_DDRC_LMR = ((ddr_twr-1)<<9 | DDR2_MRS_DLL_RST | DDR_CL<<4 | DDR_MRS_BL_4)<< 16 |
635 | | DDRC_LMR_BA_MRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
636 | |
637 | /* wait DDR_tMRD */ |
638 | tmp_cnt = (cpu_clk / 1000000) * 1; |
639 | while (tmp_cnt--); |
640 | |
641 | /* PREA */ |
642 | REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; |
643 | |
644 | /* Wait for DDR_tRP */ |
645 | tmp_cnt = (cpu_clk / 1000000) * 1; |
646 | while (tmp_cnt--); |
647 | |
648 | /* AR: auto refresh */ |
649 | REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; |
650 | /* Wait for DDR_tRP */ |
651 | tmp_cnt = (cpu_clk / 1000000) * 1; |
652 | while (tmp_cnt--); |
653 | |
654 | REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; |
655 | |
656 | /* Wait for DDR_tRP */ |
657 | tmp_cnt = (cpu_clk / 1000000) * 1; |
658 | while (tmp_cnt--); |
659 | |
660 | /* MR - DLL Reset End */ |
661 | REG_DDRC_LMR = ((ddr_twr-1)<<9 | DDR_CL<<4 | DDR_MRS_BL_4)<< 16 |
662 | | DDRC_LMR_BA_MRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
663 | |
664 | /* wait 200 tCK */ |
665 | tmp_cnt = (cpu_clk / 1000000) * 2; |
666 | while (tmp_cnt--); |
667 | |
668 | /* EMR1 - OCD Default */ |
669 | REG_DDRC_LMR = (DDR_EMRS1_DQS_DIS | DDR_EMRS1_OCD_DFLT) << 16 |
670 | | DDRC_LMR_BA_EMRS1 | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
671 | |
672 | /* EMR1 - OCD Exit */ |
673 | REG_DDRC_LMR = (DDR_EMRS1_DQS_DIS << 16) | DDRC_LMR_BA_EMRS1 | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
674 | |
675 | /* wait DDR_tMRD */ |
676 | tmp_cnt = (cpu_clk / 1000000) * 1; |
677 | while (tmp_cnt--); |
678 | |
679 | #elif defined(CONFIG_SDRAM_DDR1) // ddr1 and mddr |
680 | /* set cke high */ |
681 | REG_DDRC_CTRL = DDRC_CTRL_CKE; // ? |
682 | |
683 | /* Nop command */ |
684 | tmp_cnt = (cpu_clk / 1000000) * 1; |
685 | while (tmp_cnt--); |
686 | |
687 | /* PREA all */ |
688 | // REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; |
689 | |
690 | /* Wait for DDR_tRP */ |
691 | tmp_cnt = (cpu_clk / 1000000) * 1; |
692 | while (tmp_cnt--); |
693 | |
694 | /* EMR: extend mode register: enable DLL */ |
695 | REG_DDRC_LMR = (DDR1_EMRS_OM_NORMAL | DDR1_EMRS_DS_FULL | DDR1_EMRS_DLL_EN) << 16 |
696 | | DDRC_LMR_BA_N_EMRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
697 | |
698 | /* MR DLL reset */ |
699 | REG_DDRC_LMR = (DDR1_MRS_OM_DLLRST | (DDR_CL_HALF?(DDR_CL|0x4):DDR_CL)<<4 | DDR_MRS_BL_4)<< 16 |
700 | | DDRC_LMR_BA_N_MRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
701 | |
702 | /* wait DDR_tXSRD, 200 tCK */ |
703 | tmp_cnt = (cpu_clk / 1000000) * 2; |
704 | while (tmp_cnt--); |
705 | /* PREA all */ |
706 | REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; |
707 | REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; |
708 | REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; |
709 | tmp_cnt = (cpu_clk / 1000000) * 15; |
710 | while (tmp_cnt--); |
711 | /* EMR: extend mode register, clear dll en */ |
712 | REG_DDRC_LMR = (DDR1_EMRS_OM_NORMAL | DDR1_EMRS_DS_FULL) << 16 |
713 | | DDRC_LMR_BA_N_EMRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
714 | /* wait DDR_tMRD */ |
715 | tmp_cnt = (cpu_clk / 1000000) * 1; |
716 | while (tmp_cnt--); |
717 | |
718 | #elif defined(CONFIG_SDRAM_MDDR) // ddr1 and mddr |
719 | REG_DDRC_CTRL = DDRC_CTRL_CKE; // ? |
720 | |
721 | /* Wait for number of auto-refresh cycles */ |
722 | tmp_cnt = (cpu_clk / 1000000) * 20; |
723 | while (tmp_cnt--); |
724 | |
725 | /* PREA */ |
726 | REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; |
727 | |
728 | /* Wait for DDR_tRP */ |
729 | tmp_cnt = (cpu_clk / 1000000) * 1; |
730 | while (tmp_cnt--); |
731 | |
732 | /* AR: auto refresh */ |
733 | REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; |
734 | |
735 | /* wait DDR_tRFC */ |
736 | tmp_cnt = (cpu_clk / 1000000) * 1; |
737 | while (tmp_cnt--); |
738 | |
739 | /* AR: auto refresh */ |
740 | REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; |
741 | /* wait DDR_tRFC */ |
742 | tmp_cnt = (cpu_clk / 1000000) * 1; |
743 | while (tmp_cnt--); |
744 | |
745 | /* MR */ |
746 | REG_DDRC_LMR = (DDR_CL<<4 | DDR_MRS_BL_4)<< 16 |
747 | | DDRC_LMR_BA_M_MRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
748 | |
749 | /* wait DDR_tMRD */ |
750 | tmp_cnt = (cpu_clk / 1000000) * 1; |
751 | while (tmp_cnt--); |
752 | |
753 | /* EMR: extend mode register */ |
754 | REG_DDRC_LMR = (DDR_EMRS_DS_HALF | DDR_EMRS_PRSR_ALL) << 16 |
755 | | DDRC_LMR_BA_M_EMRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; |
756 | |
757 | /* wait DDR_tMRD */ |
758 | tmp_cnt = (cpu_clk / 1000000) * 1; |
759 | while (tmp_cnt--); |
760 | |
761 | #endif |
762 | } |
763 | void testallmem() |
764 | { |
765 | unsigned int i,d; |
766 | unsigned int *dat; |
767 | dat = (unsigned int *)0xa0000000; |
768 | for(i = 0; i < 64*1024*1024;i+=4) |
769 | { |
770 | *dat = i; |
771 | dat++; |
772 | } |
773 | |
774 | dat = (unsigned int *)0xa0000000; |
775 | for(i = 0; i < 64*1024*1024;i+=4) |
776 | { |
777 | d = *dat; |
778 | if(d != i) |
779 | { |
780 | serial_puts("errdata:\n"); |
781 | serial_puts("expect:\n"); |
782 | serial_put_hex(i); |
783 | serial_put_hex(d); |
784 | } |
785 | dat++; |
786 | } |
787 | |
788 | } |
789 | |
790 | #define DDR_DMA_BASE (0xa0000000) /*un-cached*/ |
791 | |
792 | void dma_data_move(int dma_chan, int dma_src_addr, int dma_dst_addr, int size, int burst) |
793 | { |
794 | int dma_src_phys_addr, dma_dst_phys_addr; |
795 | |
796 | /* set addr to uncached */ |
797 | dma_src_phys_addr = dma_src_addr & ~0xa0000000; |
798 | dma_dst_phys_addr = dma_dst_addr & ~0xa0000000; |
799 | |
800 | /* Init DMA module */ |
801 | |
802 | REG_DMAC_DCCSR(dma_chan) = 0; |
803 | REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO; |
804 | REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr; |
805 | REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr; |
806 | REG_DMAC_DTCR(dma_chan) = size / 32; |
807 | REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | burst; |
808 | // REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; |
809 | } |
810 | |
811 | static int check_result(void *src, void *dst, int size) |
812 | { |
813 | unsigned int addr1, addr2, i, err = 0; |
814 | |
815 | addr1 = (unsigned int)src; |
816 | addr2 = (unsigned int)dst; |
817 | |
818 | for (i = 0; i < size; i += 4) { |
819 | if ((*(volatile unsigned int *)addr1 != *(volatile unsigned int *)addr2) |
820 | || (*(volatile unsigned int *)addr1 != (i/4*0x11111111))) { |
821 | #ifdef DEBUG |
822 | err++; |
823 | if (err < 10){ |
824 | serial_puts("wrong data at");serial_put_hex(addr2); |
825 | serial_puts("data");serial_put_hex(i/4*0x11111111); |
826 | serial_puts("src");serial_put_hex(*(volatile unsigned int *)addr1); |
827 | serial_puts("dst");serial_put_hex(*(volatile unsigned int *)addr2); |
828 | } |
829 | #else |
830 | return 1; |
831 | #endif |
832 | } |
833 | |
834 | addr1 += 4; |
835 | addr2 += 4; |
836 | } |
837 | return err; |
838 | } |
839 | |
840 | #endif |
841 | |
842 | #if (defined(CONFIG_SDRAM_MDDR) || defined(CONFIG_SDRAM_DDR1) || defined(CONFIG_SDRAM_DDR2)) |
843 | #define DEF_DDR_CVT 0 |
844 | #define DDR_USE_FIRST_ARGS 0 |
845 | unsigned int testall = 0; |
846 | /* DDR sdram init */ |
847 | void sdram_init_4760(void) |
848 | { |
849 | //add driver power |
850 | REG_EMC_PMEMPS2 |= (3 << 18); |
851 | |
852 | REG_DMAC_DMACKE(0) = 0x3f; |
853 | REG_DMAC_DMACKE(1) = 0x3f; |
854 | int i, num = 0, tsel = 0, msel, hl; |
855 | volatile unsigned int tmp_cnt; |
856 | register unsigned int tmp, cpu_clk, mem_clk, ddr_twr, ns, ns_int; |
857 | register unsigned int ddrc_timing1_reg=0, ddrc_timing2_reg=0; |
858 | register unsigned int init_ddrc_refcnt=0, init_ddrc_dqs=0, init_ddrc_ctrl=0; |
859 | |
860 | register unsigned int memsize, ddrc_mmap0_reg, ddrc_mmap1_reg; |
861 | register unsigned int mem_base0, mem_base1, mem_mask0, mem_mask1; |
862 | |
863 | #if defined(CONFIG_FPGA) |
864 | int cvt = DEF_DDR_CVT, cvt_cnt0 = 0, cvt_cnt1 = 1; |
865 | int max = 0, max0 = 0, max1 = 0, min0 = 0, min1 = 0; |
866 | int tsel0 = 0, tsel1 = 0; |
867 | struct ddr_delay_sel_t ddr_delay_sel[] = { |
868 | {0, 1}, {0, 0}, {1, 1}, {1, 0}, |
869 | {2, 1}, {2, 0}, {3, 1}, {3, 0} |
870 | }; |
871 | #endif |
872 | |
873 | testall = 0; |
874 | cpu_clk = CFG_CPU_SPEED; |
875 | |
876 | #ifdef DEBUG |
877 | ddrc_regs_print(); |
878 | #endif |
879 | |
880 | #if defined(CONFIG_FPGA) |
881 | mem_clk = CFG_EXTAL / CFG_DIV; |
882 | ns = 7; |
883 | #else |
884 | mem_clk = __cpm_get_mclk(); |
885 | ns = 1000000000 / mem_clk; /* ns per tck ns <= real value */ |
886 | #endif |
887 | |
888 | #ifdef DEBUG |
889 | serial_puts("mem_clk = "); |
890 | serial_put_hex(mem_clk); |
891 | #endif |
892 | |
893 | /* ACTIVE to PRECHARGE command period */ |
894 | tmp = (DDR_tRAS%ns == 0) ? (DDR_tRAS/ns) : (DDR_tRAS/ns+1); |
895 | if (tmp < 1) tmp = 1; |
896 | if (tmp > 31) tmp = 31; |
897 | ddrc_timing1_reg = ((tmp/2) << DDRC_TIMING1_TRAS_BIT); |
898 | |
899 | /* READ to PRECHARGE command period. */ |
900 | tmp = (DDR_tRTP%ns == 0) ? (DDR_tRTP/ns) : (DDR_tRTP/ns+1); |
901 | if (tmp < 1) tmp = 1; |
902 | if (tmp > 4) tmp = 4; |
903 | ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TRTP_BIT); |
904 | |
905 | /* PRECHARGE command period. */ |
906 | tmp = (DDR_tRP%ns == 0) ? DDR_tRP/ns : (DDR_tRP/ns+1); |
907 | if (tmp < 1) tmp = 1; |
908 | if (tmp > 8) tmp = 8; |
909 | ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TRP_BIT); |
910 | |
911 | /* ACTIVE to READ or WRITE command period. */ |
912 | tmp = (DDR_tRCD%ns == 0) ? DDR_tRCD/ns : (DDR_tRCD/ns+1); |
913 | if (tmp < 1) tmp = 1; |
914 | if (tmp > 8) tmp = 8; |
915 | ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TRCD_BIT); |
916 | |
917 | /* ACTIVE to ACTIVE command period. */ |
918 | tmp = (DDR_tRC%ns == 0) ? DDR_tRC/ns : (DDR_tRC/ns+1); |
919 | if (tmp < 3) tmp = 3; |
920 | if (tmp > 31) tmp = 31; |
921 | ddrc_timing1_reg |= ((tmp/2) << DDRC_TIMING1_TRC_BIT); |
922 | |
923 | /* ACTIVE bank A to ACTIVE bank B command period. */ |
924 | tmp = (DDR_tRRD%ns == 0) ? DDR_tRRD/ns : (DDR_tRRD/ns+1); |
925 | if (tmp < 2) tmp = 2; |
926 | if (tmp > 4) tmp = 4; |
927 | ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TRRD_BIT); |
928 | |
929 | |
930 | /* WRITE Recovery Time defined by register MR of DDR2 memory */ |
931 | tmp = (DDR_tWR%ns == 0) ? DDR_tWR/ns : (DDR_tWR/ns+1); |
932 | tmp = (tmp < 1) ? 1 : tmp; |
933 | tmp = (tmp < 2) ? 2 : tmp; |
934 | tmp = (tmp > 6) ? 6 : tmp; |
935 | ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TWR_BIT); |
936 | ddr_twr = tmp; |
937 | |
938 | /* WRITE to READ command delay. */ |
939 | tmp = (DDR_tWTR%ns == 0) ? DDR_tWTR/ns : (DDR_tWTR/ns+1); |
940 | if (tmp > 4) tmp = 4; |
941 | ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TWTR_BIT); |
942 | |
943 | |
944 | /* WRITE to READ command delay. */ |
945 | tmp = DDR_tWTR/ns; |
946 | if (tmp < 1) tmp = 1; |
947 | if (tmp > 4) tmp = 4; |
948 | ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TWTR_BIT); |
949 | |
950 | /* AUTO-REFRESH command period. */ |
951 | tmp = (DDR_tRFC%ns == 0) ? DDR_tRFC/ns : (DDR_tRFC/ns+1); |
952 | if (tmp > 31) tmp = 31; |
953 | ddrc_timing2_reg = ((tmp/2) << DDRC_TIMING2_TRFC_BIT); |
954 | |
955 | /* Minimum Self-Refresh / Deep-Power-Down time */ |
956 | tmp = DDR_tMINSR/ns; |
957 | if (tmp < 9) tmp = 9; |
958 | if (tmp > 129) tmp = 129; |
959 | ddrc_timing2_reg |= (((tmp-1)/8-1) << DDRC_TIMING2_TMINSR_BIT); |
960 | ddrc_timing2_reg |= (DDR_tXP-1)<<4 | (DDR_tMRD-1); |
961 | |
962 | init_ddrc_refcnt = DDR_CLK_DIV << 1 | DDRC_REFCNT_REF_EN; |
963 | |
964 | ns_int = (1000000000%mem_clk == 0) ? |
965 | (1000000000/mem_clk) : (1000000000/mem_clk+1); |
966 | tmp = DDR_tREFI/ns_int; |
967 | tmp = tmp / (16 * (1 << DDR_CLK_DIV)) - 1; |
968 | if (tmp > 0xfff) |
969 | tmp = 0xfff; |
970 | if (tmp < 1) |
971 | tmp = 1; |
972 | |
973 | init_ddrc_refcnt |= tmp << DDRC_REFCNT_CON_BIT; |
974 | init_ddrc_dqs = DDRC_DQS_AUTO | DDRC_DQS_DET; |
975 | |
976 | /* precharge power down, disable power down */ |
977 | /* precharge power down, if set active power down, |= DDRC_CTRL_ACTPD */ |
978 | init_ddrc_ctrl = DDRC_CTRL_PDT_DIS | DDRC_CTRL_PRET_8 | DDRC_CTRL_UNALIGN | DDRC_CTRL_CKE; |
979 | /* Add Jz4760 chip here. Jz4760 chip have no cvt */ |
980 | #define MAX_TSEL_VALUE 4 |
981 | #define MAX_DELAY_VALUES 16 /* quars (2) * hls (2) * msels (4) */ |
982 | int j, index, quar; |
983 | int mem_index[MAX_DELAY_VALUES]; |
984 | #if 0 // probe |
985 | jzmemset(mem_index, 0, MAX_DELAY_VALUES); |
986 | for (i = 1; i < MAX_TSEL_VALUE; i ++) { |
987 | tsel = i; |
988 | for (j = 0; j < MAX_DELAY_VALUES; j++) { |
989 | msel = j/4; |
990 | hl = ((j/2)&1)^1; |
991 | quar = j&1; |
992 | |
993 | /* reset ddrc_controller */ |
994 | REG_DDRC_CTRL = DDRC_CTRL_RESET; |
995 | |
996 | /* Wait for precharge, > 200us */ |
997 | tmp_cnt = (cpu_clk / 1000000) * 200; |
998 | while (tmp_cnt--); |
999 | |
1000 | REG_DDRC_CTRL = 0x0; |
1001 | REG_DDRC_TIMING1 = ddrc_timing1_reg; |
1002 | REG_DDRC_TIMING2 = ddrc_timing2_reg; |
1003 | |
1004 | ddr_mem_init(msel, hl, tsel, quar); |
1005 | |
1006 | memsize = initdram(0); |
1007 | mem_base0 = DDR_MEM_PHY_BASE >> 24; |
1008 | mem_base1 = (DDR_MEM_PHY_BASE + memsize / (DDR_CS1EN + DDR_CS0EN)) >> 24; |
1009 | mem_mask1 = mem_mask0 = 0xff & |
1010 | ~(((memsize/(DDR_CS1EN+DDR_CS0EN) >> 24) |
1011 | - 1) & DDRC_MMAP_MASK_MASK); |
1012 | |
1013 | ddrc_mmap0_reg = mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0; |
1014 | ddrc_mmap1_reg = mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1; |
1015 | |
1016 | REG_DDRC_MMAP0 = ddrc_mmap0_reg; |
1017 | REG_DDRC_MMAP1 = ddrc_mmap1_reg; |
1018 | |
1019 | REG_DDRC_REFCNT = init_ddrc_refcnt; |
1020 | |
1021 | /* Enable DLL Detect */ |
1022 | REG_DDRC_DQS = init_ddrc_dqs; |
1023 | |
1024 | while(!(REG_DDRC_DQS &( DDRC_DQS_ERROR | DDRC_DQS_READY))); |
1025 | /* Set CKE High */ |
1026 | REG_DDRC_CTRL = init_ddrc_ctrl; |
1027 | |
1028 | /* Wait for number of auto-refresh cycles */ |
1029 | tmp_cnt = (cpu_clk / 1000000) * 10; |
1030 | while (tmp_cnt--); |
1031 | |
1032 | /* Auto Refresh */ |
1033 | REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; |
1034 | |
1035 | /* Wait for number of auto-refresh cycles */ |
1036 | tmp_cnt = (cpu_clk / 1000000) * 10; |
1037 | while (tmp_cnt--); |
1038 | |
1039 | tmp_cnt = (cpu_clk / 1000000) * 10; |
1040 | while (tmp_cnt--); |
1041 | |
1042 | { |
1043 | int result = 0; |
1044 | result = ddr_dma_test(0); |
1045 | if(result != 0) |
1046 | serial_puts("FAIL!\n"); |
1047 | #if DEBUG |
1048 | serial_puts("result:"); |
1049 | serial_put_hex(result); |
1050 | serial_put_hex(num); |
1051 | #endif |
1052 | |
1053 | if(result != 0) { |
1054 | if (num > 0) |
1055 | break; |
1056 | else |
1057 | continue; |
1058 | } else { /* test pass */ |
1059 | |
1060 | mem_index[num] = j; |
1061 | num++; |
1062 | } |
1063 | } |
1064 | } |
1065 | |
1066 | if (num > 0) |
1067 | break; |
1068 | } |
1069 | if (tsel == 3 && num == 0) |
1070 | serial_puts("DDR INIT ERROR\n"); /* can't find a suitable mask delay. */ |
1071 | index = 0; |
1072 | for (i = 0; i < num; i++) { |
1073 | index += mem_index[i]; |
1074 | serial_put_hex(mem_index[i]); |
1075 | } |
1076 | |
1077 | #ifdef DEBUG |
1078 | serial_puts("index-1:"); |
1079 | serial_put_hex(index); |
1080 | #endif |
1081 | |
1082 | if (num) |
1083 | index /= num; |
1084 | #endif |
1085 | |
1086 | msel = index/4; |
1087 | hl = ((index/2)&1)^1; |
1088 | quar = index&1; |
1089 | |
1090 | #ifdef DEBUG |
1091 | serial_puts("tsel"); |
1092 | serial_put_hex(tsel); |
1093 | serial_puts("num"); |
1094 | serial_put_hex(num); |
1095 | serial_puts("index-2:"); |
1096 | serial_put_hex(index); |
1097 | #endif |
1098 | |
1099 | /* reset ddrc_controller */ |
1100 | REG_DDRC_CTRL = DDRC_CTRL_RESET; |
1101 | |
1102 | /* Wait for precharge, > 200us */ |
1103 | tmp_cnt = (cpu_clk / 1000000) * 200; |
1104 | while (tmp_cnt--); |
1105 | |
1106 | REG_DDRC_CTRL = 0x0; |
1107 | REG_DDRC_TIMING1 = ddrc_timing1_reg; |
1108 | REG_DDRC_TIMING2 = ddrc_timing2_reg; |
1109 | |
1110 | ddr_mem_init(msel, hl, tsel, quar); |
1111 | |
1112 | memsize = initdram(0); |
1113 | mem_base0 = DDR_MEM_PHY_BASE >> 24; |
1114 | mem_base1 = (DDR_MEM_PHY_BASE + memsize / (DDR_CS1EN + DDR_CS0EN)) >> 24; |
1115 | mem_mask1 = mem_mask0 = 0xff & |
1116 | ~(((memsize/(DDR_CS1EN+DDR_CS0EN) >> 24) |
1117 | - 1) & DDRC_MMAP_MASK_MASK); |
1118 | |
1119 | ddrc_mmap0_reg = mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0; |
1120 | ddrc_mmap1_reg = mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1; |
1121 | |
1122 | REG_DDRC_MMAP0 = ddrc_mmap0_reg; |
1123 | REG_DDRC_MMAP1 = ddrc_mmap1_reg; |
1124 | REG_DDRC_REFCNT = init_ddrc_refcnt; |
1125 | |
1126 | /* Enable DLL Detect */ |
1127 | REG_DDRC_DQS = init_ddrc_dqs; |
1128 | |
1129 | /* Set CKE High */ |
1130 | REG_DDRC_CTRL = init_ddrc_ctrl; |
1131 | |
1132 | /* Wait for number of auto-refresh cycles */ |
1133 | tmp_cnt = (cpu_clk / 1000000) * 10; |
1134 | while (tmp_cnt--); |
1135 | |
1136 | /* Auto Refresh */ |
1137 | REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; |
1138 | |
1139 | /* Wait for number of auto-refresh cycles */ |
1140 | tmp_cnt = (cpu_clk / 1000000) * 10; |
1141 | while (tmp_cnt--); |
1142 | if(testall) |
1143 | testallmem(); |
1144 | } |
1145 | #else |
1146 | void sdram_init_4760(void) |
1147 | { |
1148 | register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; |
1149 | |
1150 | unsigned int cas_latency_sdmr[2] = { |
1151 | EMC_SDMR_CAS_2, |
1152 | EMC_SDMR_CAS_3, |
1153 | }; |
1154 | |
1155 | unsigned int cas_latency_dmcr[2] = { |
1156 | 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ |
1157 | 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ |
1158 | }; |
1159 | |
1160 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
1161 | |
1162 | cpu_clk = CFG_CPU_SPEED; |
1163 | mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; |
1164 | |
1165 | REG_EMC_BCR = 0; /* Disable bus release */ |
1166 | REG_EMC_RTCSR = 0; /* Disable clock for counting */ |
1167 | |
1168 | /* Fault DMCR value for mode register setting*/ |
1169 | #define SDRAM_ROW0 11 |
1170 | #define SDRAM_COL0 8 |
1171 | #define SDRAM_BANK40 0 |
1172 | |
1173 | dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | |
1174 | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | |
1175 | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | |
1176 | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
1177 | EMC_DMCR_EPIN | |
1178 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
1179 | |
1180 | /* Basic DMCR value */ |
1181 | dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | |
1182 | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | |
1183 | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | |
1184 | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
1185 | EMC_DMCR_EPIN | |
1186 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
1187 | |
1188 | /* SDRAM timimg */ |
1189 | ns = 1000000000 / mem_clk; |
1190 | tmp = SDRAM_TRAS/ns; |
1191 | if (tmp < 4) tmp = 4; |
1192 | if (tmp > 11) tmp = 11; |
1193 | dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); |
1194 | tmp = SDRAM_RCD/ns; |
1195 | if (tmp > 3) tmp = 3; |
1196 | dmcr |= (tmp << EMC_DMCR_RCD_BIT); |
1197 | tmp = SDRAM_TPC/ns; |
1198 | if (tmp > 7) tmp = 7; |
1199 | dmcr |= (tmp << EMC_DMCR_TPC_BIT); |
1200 | tmp = SDRAM_TRWL/ns; |
1201 | if (tmp > 3) tmp = 3; |
1202 | dmcr |= (tmp << EMC_DMCR_TRWL_BIT); |
1203 | tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; |
1204 | if (tmp > 14) tmp = 14; |
1205 | dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); |
1206 | |
1207 | /* SDRAM mode value */ |
1208 | sdmode = EMC_SDMR_BT_SEQ | |
1209 | EMC_SDMR_OM_NORMAL | |
1210 | EMC_SDMR_BL_4 | |
1211 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; |
1212 | |
1213 | /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ |
1214 | REG_EMC_DMCR = dmcr; |
1215 | REG8(EMC_SDMR0|sdmode) = 0; |
1216 | |
1217 | /* Wait for precharge, > 200us */ |
1218 | tmp = (cpu_clk / 1000000) * 1000; |
1219 | while (tmp--); |
1220 | |
1221 | /* Stage 2. Enable auto-refresh */ |
1222 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; |
1223 | |
1224 | tmp = SDRAM_TREF/ns; |
1225 | tmp = tmp/64 + 1; |
1226 | if (tmp > 0xff) tmp = 0xff; |
1227 | REG_EMC_RTCOR = tmp; |
1228 | REG_EMC_RTCNT = 0; |
1229 | REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ |
1230 | |
1231 | /* Wait for number of auto-refresh cycles */ |
1232 | tmp = (cpu_clk / 1000000) * 1000; |
1233 | while (tmp--); |
1234 | |
1235 | /* Stage 3. Mode Register Set */ |
1236 | REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
1237 | REG8(EMC_SDMR0|sdmode) = 0; |
1238 | |
1239 | /* Set back to basic DMCR value */ |
1240 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
1241 | |
1242 | /* everything is ok now */ |
1243 | } |
1244 | #endif |
1245 | |
1246 | void serial_setbrg_4760(void) |
1247 | { |
1248 | volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR); |
1249 | volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR); |
1250 | volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR); |
1251 | u32 baud_div, tmp; |
1252 | |
1253 | baud_div = (CFG_EXTAL / 16 / 57600); |
1254 | tmp = *uart_lcr; |
1255 | tmp |= UART_LCR_DLAB; |
1256 | *uart_lcr = tmp; |
1257 | |
1258 | *uart_dlhr = (baud_div >> 8) & 0xff; |
1259 | *uart_dllr = baud_div & 0xff; |
1260 | |
1261 | tmp &= ~UART_LCR_DLAB; |
1262 | *uart_lcr = tmp; |
1263 | } |
1264 | |